M21463 6.25 Gbps Twelve-Channel Backplane Equalizer and Driver with 12x12 Crosspoint Switch and Integrated Clock and Data Recovery The M21463 is a twelve channel device designed to enable the transmission of multi-gigabit serial data through the most challenging environments. The device features twelve independent, programmable equalizers that equalize data at rates up to 6.25 Gbps. Each input channel also includes an integrated clock and data recovery device to retime the input data and reduce residual jitter on the signal. Control of the M21463 is provided through an I2C compatible software control interface. The M21463 can also self-configure from an external EEPROM without the need for a host processor. For compatibility with PCI-Express and S-ATA/SAS systems, the M21463 is designed with an electrical idle pass-through function to drive the differential output to the common mode level during OOB signaling. Boundary scan is provided for high-speed input and output pins, and the device is available in a 12x12 mm, 88 pin QFN package. Applications Features * Integrated CDRs on each input channel * Programmable Equalization for up to 40" of FR-4 PCB trace at 6.25 Gbps * Supports electrical idle signaling for PCIe and OOB signaling for S-ATA/SAS * Independently programmable output drive and de-emphasis levels * Low power dissipation: Approximately 210 mW per channel, 2.5 W total power at 1.2 V * Automatic Rate Detection (ARD) to support multiple generations of various protocols 3.125 Gbps 6.25 Gbps -- S-ATA/SAS 1.5 Gbps 3.0 Gbps 6.0 Gbps PCIe 2.5 Gbps 5.0 Gbps -- 1.0625 Gbps 2.125 Gbps 4.25 Gbps 2.5 Gbps 5.0 Gbps -- XAUI Fibre Channel InfiniBand * Up to 23 dB of input equalization and 6 dB of output de-emphasis * 12x12 mm, 88 pin QFN package * Extended operating case temperature range * Integrated 12x12 Crosspoint Switch Matrix Typical Application Diagram Open eye after signal conditioning Closed eye after long PCB trace M21463 Up to 40" of FR-4 trace at 6.25 Gbps M21463 Equalizer and Driver With CDR Equalizer and Driver With CDR One of twelve channels shown Programmable Input Equalizers 21463-DSH-001-E Output Drivers with Programmable De-emphasis Programmable Input Equalizers Mindspeed Technologies(R) Mindspeed Proprietary and Confidential Output Drivers with Programmable De-emphasis January 2012 Ordering Information Part Number Package Operating Case Temperature M21463G-15* 12x12 mm, 88-pin QFN package -40 to 85 C *The M21463 is RoHS compliant. Refer to http://www.mindspeed.com/web/support/environment/index.html for additional information. Mindspeed RoHS compliant devices are backwards compatible with 225 C reflow profiles. Revision History Revision Level Date E Released January 2012 Description Updated for production release. Removed "P" designator from part number for production release. Updated specification limits in tables Table 1-3, Table 1-4, and Table 1-5. Inserted Figures 2-5, 2-6, 2-7, 2-8, 2-9, 2-10, 2-12, and 2-13. Added text in Section 4.9 stating that the LOL alarm registers in addresses 5Eh, 5Fh, 7Dh, 7Eh, 9Ch, and 9Dh are not reliable and should not be used for data rates above 5.5 Gbps. D Preliminary August 2011 Changed typical value of unbounded random jitter (CDR enabled) in Table 1-4 from 3 mUI RMS to 10 mUI RMS. Deleted specification for SONET jitter peaking, SSC jitter peaking, SSC modulation frequency, and SSC frequency shift from Table 1-5. Changed maximum device operating case temperature from 90 C to 85 C. Changed typical loop bandwidth specification in Table 1-5 from Fbaud/1738 to Fbaud/3000. Changed minimum refclk frequency in Table 1-5 from 60 MHz to 100 MHz. Changed pin type in Table 3-1 for REFCLK P and REFCLK N from CMOS to PCML (typo error in previous data sheet, no change to refclk input circuit). Modified register description for CDR General Configuration registers (addresses 4Dh, 6Ch, and 8Bh) so that preset settings that were previously used for SSC applications and for refclk frequencies lower than 100 MHz are now reserved settings. Changed the settings for ADDR2 for Memory Interface Mode in Table 4-2 from 'X' to 'H or L'. Added to the description of the PRBS generator in Section 4.10. Automatic Rate Detection must be disabled when using the internal PRBBS generator. Added additional description of boundary scan functionality in Section 4.13 to state that only the pside of high-speed output pins supports boundary scan, and that a wait time of 2 sec and minimum swing of 1.5 V is required for proper scan results. C Advance April 2011 Update part number to M21463-15P Updated control pin type definitions to define inputs and outputs in Table 3-1. Change maximum data rate from 6.5 Gbps to 6.25 Gbps Add note stating that -40 C minimum case temperature applies for data rates up to 5.5 Gbps. Minimum case temperature for other data rates is TBD. Inserted Figures 2-1, 2-2, 2-3, 2-4, 2-11, and 2-14. B Advance July 2010 Complete document revision. A Advance July 2008 Initial Release. 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 2 M21463 Marking Diagram M21463 G-15 XXXX .X YYWW CC e 21463-DSH-001-E Part Number Lot Number Date and Country Code RoHS Symbol Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 3 1.0 Electrical Characteristics Table 1-1. Absolute Maximum Ratings Symbol Minimum Maximum Unit Analog I/O power supply voltage -0.5 2.1 V Core power supply voltage -0.5 1.4 V DVDDIO Digital I/O power supply voltage -0.5 4 V TSTORE Storage Temperature -65 150 C AVDDIO AVDDCORE/ DVDDCORE Parameter VESD, HBM Electrostatic discharge voltage (HBM) -2000 2000 V VESD, CDM Electrostatic discharge voltage (CDM) -500 500 V NOTES: Exposure of the device beyond the minimum/maximum limits may cause permanent damage. Limits listed in the above table are stress limits only, and do not imply functional operation within these limits. Exposure to absolute maximum ratings for extended periods of time may degrade device reliability. Table 1-2. Symbol AVDDIO AVDDCORE/ DVDDCORE DVDDIO TCASE 21463-DSH-001-E Recommended Operating Conditions Parameter Minimum Typical Maximum Unit Analog I/O power supply voltage 1.14 1.2, 1.8 1.89 V Core power supply voltage 1.14 1.2 1.26 V Digital I/O power supply voltage 2.37 2.5, 3.3 3.47 V Operating Case Temperature -40 -- 85 C Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 4 Electrical Characteristics Table 1-3. Power Consumption Specifications Symbol Parameter Note Minimum Typical Maximum Unit AIDDIO Analog I/O power supply current (AVDDIO = 1.2 V) 1 -- 210 260 mA AIDDIO Analog I/O power supply current (AVDDIO = 1.8 V) 2 -- 390 490 mA AIDDCORE Analog core power supply current (AVDDIO = 1.2 V) 1 -- 1.7 2.1 A AIDDCORE Analog core power supply current (AVDDIO = 1.8 V) 2 -- 1.8 2.2 A DIDDIO Digital I/O power supply current -- -- 2 10 mA DIDDCORE Digital core power supply current -- -- 180 250 mA PTOTAL Total power dissipation (AVDDIO=1.2 V) 1, 3 -- 2.5 3.3 W PTOTAL Total power dissipation (AVDDIO=1.8 V) 2, 3 -- 3.1 4.05 W NOTES: 1. Valid with nominal (800 mVPPD) output swing for all channels. 2. Valid with maximum (1500 mVPPD) output swing for all channels. 3. Typical calculated with nominal current and voltage. Maximum calculated with maximum current and 5% over voltage. Unless noted otherwise, specifications in this section are valid with AVDDIO = 1.8 V, 25 C case temperature, 800 mV differential input data swing, nominal (800 mVPPD) output data swing, PRBS 215 - 1 test pattern at 6.25 Gbps, RLOAD = 50 , short cables and/or traces with all CDRs enabled. Table 1-4. Input/Output Electrical Characteristics (1 of 2) Symbol Parameter Note Minimum Typical Maximum Unit DR NRZ Data Rate -- 103.125 -- 6250 Mbps VIN Input differential voltage swing (AC-Coupled), voltage measured at the device input -- 200 -- 2000 mV VIN Input launch amplitude (Voltage used to drive a signal across 40" of FR-4 trace) -- 500 -- -- mVPPD RTERM PCML differential input impedance termination -- 80 100 120 VOH PCML single ended output logic-high -- AVDDIO - 0.05 -- AVDDIO V VOUT PCML p-p differential output swing 1,2,3,6 350 -- 1750 mV tR/tF PCML output rise/fall time (20-80%) 6 -- 60 -- ps tDJ Deterministic jitter, CDR enabled 4, 8 -- 0.15 0.25 UI tDJ Deterministic output jitter, CDR bypassed 4 -- 0.1 0.24 UI URJ Unbounded Random jitter, CDR enabled 4, 8 -- 10 14 mUI RMS URJ Unbounded Random output jitter, CDR bypassed 4 -- 6 9 mUI RMS tPD Propagation delay 7 -- 1 -- ns Channel to channel skew -- -- 300 -- ps VIH CMOS Input logic high (three state inputs) -- 0.85 x DVDDIO -- -- V VIF CMOS input logic floating state (three state inputs) -- 0.3 x DVDDIO -- 0.7 x DVDDIO V VIL CMOS input logic low (three state inputs) -- -- -- 0.15 x DVDDIO V VIH CMOS input logic high (two state inputs) -- 0.75 x DVDDIO -- -- V tSKEW, CH 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 5 Electrical Characteristics Table 1-4. Input/Output Electrical Characteristics (2 of 2) Symbol Parameter Note Minimum Typical Maximum Unit VIL CMOS input logic low (two state inputs) -- -- -- 0.25 x DVDDIO V VOH CMOS output logic high, IOH = 2 mA 5 0.90 x DVDDIO -- -- V VOL CMOS output logic low, IOL = 2 mA 5 -- -- 0.10 x DVDDIO V NOTES: 1. AVDDIO must be 1.8 V to achieve higher than 800 mV output swing. 2. Output swing is specified with output de-emphasis disabled. 3. Six output swing levels can be selected. Output swing increases by approximately 200 mV with each setting. See Figure 2-7 for typical swing levels. 4. Additive output jitter with minimal media length 5. Two-wire serial interface can drive 400 pF at 100 kHz and 100 pF at 400 kHz. 6. Measured using a CID pattern with a minimum CID length of 10 bits with CDR bypassed. 7. With CDR bypassed. Propagation delay increases by 1 UI with CDR enabled. 8. HP 83712B is used as reference clock. Table 1-5. CDR Performance Specifications Symbol Parameter Notes Minimum Typical Maximum Unit FBAUD Input Data Rate -- 103.125 -- 6250 Mbps JTOL Jitter Tolerance (5 MHz jitter modulation frequency) 1 0.35 0.5 -- UI Jitter Peaking (Nominal) 2 -- 0.5 0.7 dB CDR loop bandwidth 3 -- FBAUD/3000 -- Hz REFFREQ Reference Clock Frequency (for data rates of 5.5 Gbps and below) 4 100 125 311 MHz REFFREQ Reference Clock Frequency (for data rates above 5.5 Gbps) 4 125 -- 311 MHz REFACC Reference Clock Accuracy -- -- 20 100 ppm REFAMPL Reference Clock Amplitude -- 200 800 1200 mVPPD JPK, NOM LBW NOTES: 1. Measured with 5 MHz sinusoidal jitter added until greater than 1E-9 BER detected. 2. Measured with 150 mUI input jitter, 50% transition density, and nominal register settings, prescale value set to 1. 3. Measured with 150 mUI input jitter, 50% transition density, and default register settings. 4. HP 83712B is used as reference clock. 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 6 2.0 Typical Performance Characteristics Unless noted otherwise, test conditions in this section are: AVDDIO = 1.8 V, 25 C case temperature, 800 mVPPD input data swing, nominal (800 mVPPD) output data swing PRBS 215 - 1 test pattern at 6.25 Gbps, RL = 50 , short traces and/or cables with all CDRs enabled. Differential Eye Diagram at 3.0 Gbps Figure 2-3. 50 ps/div 30 ps/div Differential Eye Diagram at 6.25 Gbps Figure 2-4. 27 ps/div 21463-DSH-001-E On-Chip PRBS Generator Differential Eye Diagram at 6.25 Gbps (See Section 4.10 for details on PRBS Generator) 150 mV/div 150 mV/div Figure 2-2. Differential Eye Diagram at 5.0 Gbps 150 mV/div 150 mV/div Figure 2-1. 27 ps/div Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 7 Typical Performance Characteristics Figure 2-5. Signal after 40" FR4 Trace at 6.25 Gbps (No Equalization) Figure 2-7. Differential Output Swing vs. OutctrlN[7:5] Setting as a Function of AVDDIO A V DDIO = 1.2V A V DDIO = 1.8V 1600 1400 Output Swing (m Vppd) 1200 1000 800 600 400 200 0 010 Figure 2-6. 21463-DSH-001-E Eye Diagram after Equalizing 40" FR4 Trace at 6.25 Gbps (CDR Bypassed) Figure 2-8. Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 011 100 101 O u tctrlN[7:5] 110 111 Eye Diagram after Equalizing 40" FR4 Trace at 6.25 Gbps (CDR Enabled) 8 Typical Performance Characteristics Figure 2-9. Output Waveform With COMWAKE OOB Signal Figure 2-11. Deterministic Jitter vs. Launch Amplitude after Equalizing a Signal across 40" FR4 Trace COMWAKE IDLE Time = 106.2 ns Figure 2-10. Deterministic Jitter vs. Data Rate as a Function of FR4 Trace Length (CDR Enabled and Bypassed) 21463-DSH-001-E Figure 2-12. Random Jitter vs. Data Rate as a Function of FR4 Trace Length (CDR Enabled and Bypassed) Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 9 Typical Performance Characteristics Figure 2-13. Typical LOS Assert/De-Assert Behavior Figure 2-14. Bathtub Curve Asserted LOS Hysteresis LOS can be asserted or de asserted De-asserted 50 100 150 200 250 Input voltage swing (mVppd) Figure 2-15. Input Equalization Test Setup Test Backplane (Used to Generate Figure 2-5, 2-6, 2-8, 2-10, 2-12) Pattern Generator Data Out P Data Out N Error Detector/ M21463 Evaluation Module M21463 Evaluation Module Digital Communications Analyzer Test Backplane with SMAHm-Zd adapter cards 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 10 3.0 Package Outline Drawing, Pinout Diagram, and Pin Descriptions The M21463 is assembled in 12x12 mm, 88-pin QFN packages. The exposed pad on the bottom of the package should be soldered to the ground plane to provide a GND connection and a thermal path for the device. Figure 3-1. 21463-DSH-001-E Package Outline Drawing Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 11 Package Outline Drawing, Pinout Diagram, and Pin Descriptions REFCLK P REFCLK N AVDDCORE DOUT8P DOUT8N DOUT9P AVDDIO DOUT10P AVDDCORE DOUT9N DOUT10N AVDDIO DOUT11P DOUT11N AVDDCORE AVDDCORE DIN0P DIN0N DIN1P AVDDCORE 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 DIN1N Pinout Diagram - Top View ADDR0 Figure 3-2. 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential xALARM ADDR1 DIN11N DIN11P AVDDCORE DIN10N DIN10P AVDDCORE DIN9N DIN9P AVDDCORE DIN8N DIN8P AVDDCORE AVDDCORE DOUT7N DOUT7P AVDDIO DOUT6N DOUT6P AVDDCORE DVDDCORE DOUT5N ADDR2 AVDDIO DVDDCORE SCL DOUT5P xSEL DOUT4N DOUT3N DOUT4P DOUT3P AVDDCORE AVDDIO DIN7P DOUT2P DOUT2N DIN7N AVDDCORE DOUT1N AVDDCORE 12x12 mm QFN (0.5 mm pitch) DIN6N AVDDCORE AVDDIO DOUT1P M21463 AVDDCORE DIN6P DOUT0P DOUT0N DIN5N AVDDCORE DIN5P AVDDCORE AVDDCORE DIN3N DIN4N DIN3P DIN4P DIN2N AVDDCORE AVDDCORE DIN2P 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 AVDDCORE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SDA DVDDIO 12 Package Outline Drawing, Pinout Diagram, and Pin Descriptions Table 3-1. M21463 Pin Descriptions (1 of 2) Pin Name Pin Number(s) Type Description AVDDIO 12,18,41, 49, 72, 78, Power Analog IO Voltage Supply DVDDIO 1 Power Digital IO Voltage Supply AVDDCORE 2, 5, 8, 9, 15, 25, 28, 31, 34, 37, 38, 46, 52, 53, 56, 59, 62, 69, 75, 81, 82, 85 Power Analog Core Voltage Supply DVDDCORE 23, 45 Power Digital Core Voltage Supply GND Exposed pad on bottom of package Ground Device ground xSEL 21 CMOS input Hardware Strobe Pin SCL 22 CMOS input/output 2 wire interface SCL pin SDA 24 CMOS input/output 2 wire interface SDA pin ADDR2 44 CMOS input 2 wire interface address select pin ADDR1 65 CMOS input 2 wire interface address select pin ADDR0 88 CMOS input 2 wire interface address select pin 66 Open drain Alarm output pin (1) REFCLKP 67 PCML input Reference clock input P REFCLKN 68 PCML input Reference clock input N DIN0P 83 PCML input Channel 0 Input P DIN0N 84 PCML input Channel 0 Input N DIN1P 86 PCML input Channel 1 Input P DIN1N 87 PCML input Channel 1 Input N DIN2P 3 PCML input Channel 2 Input P DIN2N 4 PCML input Channel 2 Input N DIN3P 6 PCML input Channel 3 Input P DIN3N 7 PCML input Channel 3 Input N DIN4P 26 PCML input Channel 4 Input P DIN4N 27 PCML input Channel 4 Input N DIN5P 29 PCML input Channel 5 Input P DIN5N 30 PCML input Channel 5 Input N DIN6P 32 PCML input Channel 6 Input P DIN6N 33 PCML input Channel 6 Input N DIN7P 35 PCML input Channel 7 Input P DIN7N 36 PCML input Channel 7 Input N DIN8P 54 PCML input Channel 8 Input P DIN8N 55 PCML input Channel 8 Input N DIN9P 57 PCML input Channel 9 Input P DIN9N 58 PCML input Channel 9 Input N DIN10P 60 PCML input Channel 10 Input P xALARM (1) 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 13 Package Outline Drawing, Pinout Diagram, and Pin Descriptions Table 3-1. M21463 Pin Descriptions (2 of 2) Pin Name Pin Number(s) Type Description DIN10N 61 PCML input Channel 10 Input N DIN11P 63 PCML input Channel 11 Input P DIN11N 64 PCML input Channel 11 Input N DOUT0P 10 PCML output Channel 0 Output P DOUT0N 11 PCML output Channel 0 Output N DOUT1P 13 PCML output Channel 1 Output P DOUT1N 14 PCML output Channel 1 Output N DOUT2P 16 PCML output Channel 2 Output P DOUT2N 17 PCML output Channel 2 Output N DOUT3P 19 PCML output Channel 3 Output P DOUT3N 20 PCML output Channel 3 Output N DOUT4P 39 PCML output Channel 4 Output P DOUT4N 40 PCML output Channel 4 Output N DOUT5P 42 PCML output Channel 5 Output P DOUT5N 43 PCML output Channel 5 Output N DOUT6P 47 PCML output Channel 6 Output P DOUT6N 48 PCML output Channel 6 Output N DOUT7P 50 PCML output Channel 7 Output P DOUT7N 51 PCML output Channel 7 Output N DOUT8P 70 PCML output Channel 8 Output P DOUT8N 71 PCML output Channel 8 Output N DOUT9P 73 PCML output Channel 9 Output P DOUT9N 74 PCML output Channel 9 Output N DOUT10P 76 PCML output Channel 10 Output P DOUT10N 77 PCML output Channel 10 Output N DOUT11P 79 PCML output Channel 11 Output P DOUT11N 80 PCML output Channel 11 Output N NOTE: 1. xALARM is an open-drain output, and should be connected to an external 10 k pull-up resistor in system designs. 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 14 4.0 Functional Description The M21463 is a twelve channel device with programmable input equalization, programmable output de-emphasis, and an embedded 12x12 crosspoint switch matrix. Details on various functionality and features are described in the following sections. Figure 4-1. Din 0 P Din 0 N Din 1 P Din 1 N Din 11 P Din 11 N Functional Block Diagram Input Buffer with Programmable Equalization Programmable CDR Output Buffer with Programmable De-Emphasis Dout 0 P Input Buffer with Programmable Equalization Programmable CDR Output Buffer with Programmable De-Emphasis Dout 1 P Output Buffer with Programmable De-Emphasis Dout 11 P Input Buffer with Programmable Equalization Control Interface and Registers 21463-DSH-001-E Programmable CDR Multifunction Control Pins 12 x 12 Crosspoint Switch Dout 0 N Dout 1 N Dout 11 N JTAG Controller Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 15 Functional Description 4.1 Power Supply The M21463 includes four distinct power supply domains: AVDDCORE, DVDDCORE, AVDDIO, and DVDDIO. AVDDCORE powers the analog core circuitry in the device, and must be set to 1.2 V. DVDDCORE powers the digital core circuitry in the device, and must be set to 1.2 V. AVDDIO powers the input/output circuits in the device, and can be set to either 1.2 V or 1.8 V. Note that to achieve output swing levels higher than 800 mVPPD, AVDDIO must be set to 1.8 V. DVDDIO powers the digital circuitry within the device, and can be set to 2.5 V or 3.3 V to allow for interface with various external digital devices. It is recommended that DVDDIO is connected to the same voltage level as any digital devices that are used to control the M21463. There are no power supply sequencing requirements for AVDDCORE, DVDDCORE, AVDDIO, or DVDDIO in the M21463. When the M21463 is operated in memory interface control (MIC) mode, the EEPROM must be powered up and stable within 50 ms of DVDDCORE reaching approximately 0.8 V to ensure that the register download from the EEPROM is robust. The device will issue a power on reset (POR) when DVDDCORE reaches approximately 0.8 V during the power supply ramp. After the POR is complete, the device will poll the ADDR pins to determine which control mode the device is configured for. If the device is configured for MIC operation, it will attempt to communicate with the on-board EEPROM for register download immediately after the POR is complete. If the EEPROM does not respond within approximately 50 ms after the POR, the M21463 will stop trying to communicate with the EEPROM and the MIC download will fail. See below for the recommended power supply ramp up timing in MIC mode. Figure 4-2. Recommended Power Supply Ramp-up in MIC Mode DVDDIO (EEPROM supply) Voltage (V) 2.5/3.3 1.2 DVDDCORE 0.8 <50 ms Time 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 16 Functional Description 4.2 Input and Output Buffers The input buffers in the M21463 are designed to work with AC coupled input signals, and support operation with a wide range of AC coupling capacitor values. Applications that use PRBS and/or 8b/10b encoded data will typically use AC coupling capacitors with a value of 0.1 F. The output buffers are designed with PCML logic, and can operate with either AC coupled or DC coupled systems. The input and output buffers include internal 50 terminations and support boundary scan. The high-speed outputs are powered-down by default, and should be set to the desired output swing level using registers 41h-4Ch. 4.3 LOS Alarm There is a signal detect circuit that will assert an alarm if the signal level at the input of the device is lower than the assert threshold level of the LOS circuit of the squelch is forced on for an input. Once asserted, the alarm will remain asserted until the signal is above the de-assert threshold level of the LOS circuit or the force squelch on an input channel has been removed. There is hysteresis between the assert and de-assert levels to prevent chattering of the LOS alarm. Please refer to Figure 2-13 for an illustration of the typical LOS assert/de-assert behavior. The LOS circuit should be disabled when used with strings of 1010 data that last for more than approximately 3 s to avoid false LOS alarms. The LOS alarm status register (address C3h, C4h), will latch when the LOS alarm for a channel is asserted, and will remain latched until it is cleared by setting bit 4 of address 03h to '1', and then back to '0'. When the LOS alarm is asserted and register 00h[3]=0b, the xALARM pin will send one interrupt pulse with a pulse width of approximately 35 ns as shown in Figure 4-3 below. Figure 4-3. Timing of xAlarm Interrupt Signal DVDDIO 35 ns GND 4.4 Input Equalization Each input channel of the M21463 includes an input equalizer, designed to compensate for bandwidth limitations of PCB traces. The equalizer operates in a programmable mode, where a fixed equalization setting is selected. There are 16 equalization settings available, which are programmed through register addresses 1Dh-28h when the device is used in lane switching mode. When the device is used in group switching mode (default mode), the input equalization setting is configured for the entire group using register addresses 26h, 27h, and 28h. Addresses 1Dh25h are not used when the device is in group switching mode. See the register description table for details on how to select each equalization level. It is recommended that each channel of the system is characterized once to optimize the equalization for each system channel. 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 17 Functional Description 4.5 Output De-emphasis Each output buffer of the M21463 includes a de-emphasis circuit that is configured by the user. There is approximately 6 dB of de-emphasis available, and the de-emphasis levels are selectable through registers 41h4Ch. Note that when the device is used in group switching (default) mode, the output de-emphasis is set for each group using registers 4Ah, 4Bh, and 4Ch. 4.6 Electrical Idle Pass-through Some protocols, such as SATA/SAS and PCIe, define a third logic state at the common mode for transmission of an electrical idle (EI) level. In SAS/SATA systems, OOB signals such as COMRESET, COMWAKE, and COMSAS utilize burst and idle levels for communication. The M21463 is designed to pass the electrical idle through the device to support SATA/SAS and PCIe protocol requirements. When the EI feature of the M21463 is enabled, the device will detect and pass EI signals with minimal distortion of the signal. A minimum eye opening of 150 mVPPD is required for the EI circuit to function properly when enabled.The EI circuit is controlled through registers 35h-40h. 4.7 Squelch To avoid random chattering of the output due to noise when there is no signal present at the inputs, the M21463 includes a squelch feature to automatically inhibit the output when there is an LOS alarm. There is an option to inhibit to either logic H, logic L, or the EI common mode level on squelch. In addition to the automatic squelch feature, a manual squelch can be forced through a register setting. When an input channel is squelched, any output configured to be connected to the squelched input will be H, L, or F depending on the selected squelch level. LOS should either be disabled or set to "never squelch" when the EI circuit is enabled to allow the device to detect data bursts quickly after electrical idle periods that last longer than approximately 5 s. The squelch circuit is controlled through register 03h, and also through registers 35h-40h. 4.8 Crosspoint Switch Core The 12x12 crosspoint switch core is configured through the Active Switch Configuration, Intermediate Switch Configuration #1, and Intermediate Switch Configuration #2 registers. The switch supports multicast and broadcast modes. The current switch configuration is stored in the "Active Switch Configuration" (ASC) registers, addresses 08h-0Dh. The switch configuration is updated immediately when a write operation to these registers takes place. One ASC register controls two output channels, so two crosspoint switch paths can be updated at a time by writing directly to the ASC registers. To configure a crosspoint switch path, the input channel is used as the register data value, and the output channel is the register address that is used. For example, to configure the crosspoint core so that input channel 2 is routed to output channel 0, write data = '0010' into register 0Dh[3:0]. Register 0Dh contains the active switch configuration for outputs 0 and 1, so the data for the desired input channel for output channel 1 would also need to be written into register 0Dh[7:4]. To allow for immediate reconfiguration of one to all crosspoint switch paths, there are two "Intermediate Switch Configuration" (ISC#1 and ISC#2) registers located in addresses 0Eh-19h. These registers allow for a new crosspoint switch configuration to be loaded into the registers in advance. When a "strobe" event occurs, the ASC registers will be updated with the contents from the appropriate "ISC" register, and the entire switch core configuration is updated. The switch core can be updated through either a software "strobe" in register 05h, or a hardware strobe by toggling the xSEL hardware pin. When a software strobe is being used, bit 7 of register address 05h is used to select which ISC register is used when the ASC is updated. When the M21463 is 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 18 Functional Description configured for hardware strobe mode by setting bit 3 of register address 03h to "1", the xSEL hardware pin is used to update the ASC contents. The device can be configured in two different hardware strobe modes with bit 6 of register address 05h. With this bit set to "0", ISC #1 is the active switch configuration after an L-to-H transition on xSEL, and ISC #2 is the active switch configuration after an H-to-L transition on xSEL. With this bit set to "1", an H-to-L transition on the xSEL pin will update the active switch configuration register with ISC #1 or ISC #2 as determined by bit 7 of register address 05h. The switch core can be programmed in two modes, group switch mode or lane switch mode. In group switch mode, four high-speed channels are treated as one group and switched together. Group 0 includes Input/Output channels 0,1, 2, and 3; Group 1 includes Input/Output channels 4, 5, 6, and 7; Group 2 includes Input/Output channels 8, 9, 10, and 11. In lane switch mode, each high speed channel is independent and switched individually. By default, the device is in group switch mode with the following switch core configuration: Input group 0 ---> Output group 1 Input group 1 ---> Output group 0 Input group 2 ---> Output group 2 The group switch configuration can be updated by writing to the group switch ASC, ISC #1, and ISC #2 registers, addresses 08h-19h. If the M21463 is being used in a protection switching application, two alternate switch states can be stored in each ISC register, and the HW strobe can be used to select between the two switch settings. This mode is enabled by default. Figures 4-4 and 4-5 show how the M21463 can be used in a protection switching application using the default group switch mode settings. Figure 4-4. M21463 Default ASC/ISC # 1 in Group Switch Mode M21463 Input /Output Group 0 Input/Output Group 1 Card 1 Card 0 Input/Output Group 2 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential Card 2 19 Functional Description Figure 4-5. M21463 Default ISC # 2 in Group Switch Mode M21463 Input /Output Group 0 Input/Output Group 1 Card 1 Card 0 Input/Output Group 2 4.9 Card 2 Clock and Data Recovery Operation The M21463 includes integrated CDRs for each input channel. There are three banks of four CDRs, and each bank of CDRs can be programmed independently to lock to data rates from 103 Mbps to 6.25 Gbps. The CDRs can be configured by selecting the protocol type and reference frequency from the list of options in the PLL General Configuration registers, addresses 4D, 6Ch and 8Bh. Once this register has been programmed, the CDR will be configured to lock to the data rates for the protocol type selected. By default, once enabled, the CDR is configured to lock to SATA/SAS data with a 150 MHz refclk. In this configuration, the CDR can lock to data that is at 1.5 Gbps, 3.0 Gbps, or 6.0 Gbps. The CDRs in the M21463 support spread spectrum clocking (SSC) in source synchronous applications. If the CDRs need to be configured to lock to a protocol type/reference combination that is not available in the list of preset values in registers 4Dh, 6Ch, and 8Bh, each CDR parameter (PLL reference multiplier, PLL tuning range, PLL Loop Bandwidth, CDR prescale value, CDR Loop Bandwidth, and CDR peaking) can be set manually using the individual configuration registers. Additionally, if only minor changes are required, a protocol can be selected, and then only the appropriate parameters can be changed away from the defaults. To program the CDR for manual operation, it is important to understand that the CDR consists of two primary components. The first component is a phase-locked loop (PLL) that multiplies the reference clock up to a rate between 3.3 GHz and 6.25 GHz. The PLL is shared across 4 channels in a bank of CDRs. The second component is the actual CDR, which exists per channel inside a bank. The M21463 contains three PLLs and 12 CDRs, with each PLL connected to a bank of four CDRs as described in Table 4-1. Table 4-1. CDR Bank Details CDR Bank A CDR Bank B CDR Bank C Input 0 Input 4 Input 8 Input 1 Input 5 Input 9 Input 2 Input 6 Input 10 Input 3 Input 7 Input 11 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 20 Functional Description To set the PLL and CDR for the correct data rate, use these formulas: FPLL = FREF * N FBAUD = FPLL / M 3.3 GHz FPLL 6.25 GHz 103.125 MHz < Fbaud < 6.25 GHz 16 N 127 M = 1, 2, 4, 8, 16 or 32 where FBAUD is the bit rate of the incoming data, FREF is the reference clock frequency, N is the PLL multiplier, and M is the CDR prescale. The value of N is set by the PLL reference multiplier register (4E, 6Dh or 8Ch). The value of M is set via the Data Rate Select registers (53h, 56h, 59h, 5Ch, 72h, 75h, 78h, 7Bh, 91h, 94h, 97h, and 9Ah). Since the M value is set per channel, it is clear that each channel within a Bank can independently lock to power-oftwo multipliers of the base rate. For instance, a Bank of CDRs that is set up for Fibre Channel can have individual channels running at 1X, 2X, or 4X rates. When running with the CDR manually configured, Mindspeed recommends disabling the Automatic Rate Detection algorithm, and manually setting the M value. In cases where channels are not related by a power of 2 (for instance PCI-Express and FibreChannel in the same bank), only one type of data can have the CDR enabled, and the other type should be set for bypass operation. As an example of how to set N and M, consider locking to 1X FibreChannel (1.0625 Gbps) with a 106.25 MHz Reference Clock. Since 1.0625 GHz is not within the PLL range, we need to determine the correct value of M. We see that with M=4, we get 1.0625 GHz * 4 = 4.25 GHz, which is within the range of the PLLs ability to lock. So, we now have FBAUD, FREF, and M, and we can solve for N, to get N=40. As a second example, consider PCI-Express at 2.5 Gbps with a 100 MHz reference clock. In this case, we see that we need M=2 to get the PLL in the correct range (5.00 GHz), which then implies N=50. In addition to setting the dividers correctly, the PLL needs to be configured to the correct frequency of operation, and to have the correct PLL Loop Bandwidth. For values of FREF * N between 3.3 GHz and 4.7 GHz, the PLL should be set to the lower frequency range. For values of FREF * N between 4.7 GHz and 6.25 GHz, the PLL should be set to the upper frequency range. The frequency range is set via the PLL Range Select register (4Fh, 6Eh, or 8Dh). Finally, the PLL Loop Bandwidth should be selected via registers 50h, 6Fh, or 8Eh. The loop bandwidth of the PLL should be set to minimize jitter from the PLL; however, the function of the LBW control on jitter is dependent on many variables. Below is a table with the default values for the PLL LBW, to give an estimate for where the PLL LBW value should be set. For applications that are much different than what is listed below, please contact a Mindspeed customer representative. Protocol PLL Output Frequency (GHz) Reference Clock (MHz) PLL LBW Setting XAUI 6.25 312.5 4 250 4 156.25 5 125 5 250 4 150 5 125 5 100 5 SATA/SAS 21463-DSH-001-E 6.00 Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 21 Functional Description Protocol PLL Output Frequency (GHz) Reference Clock (MHz) PLL LBW Setting Gigabit Ethernet / 5.00 250 6 200 6 156.25 6 125 7 100 7 311.04 6 155.52 6 250 5 212.5 5 125 6 106.25 6 PCI-Express SONET FibreChannel 4.97664 4.25 As a final configuration setting, the CDR loop bandwidth and peaking can be modified via the LBW and Peaking registers (54h, 57h, 5Ah, 5Dh, 73h, 76h, 79h, 7Ch, 92h, 95h, 98h, and 9Bh). Due to how the CDR works, increasing the Loop Bandwidth will increase the output jitter. Decreasing the Loop Bandwidth may lower output jitter, but the effect will be small. For these reasons, Mindspeed recommends the following settings, based on the value of M: For M = 1, 2, 4, or 8, CDR LBW should be set to 00 (automatic) or 01 (Nominal) For M = 16, CDR LBW should be set to 00 (automatic) or 02 (2X Nominal) For M = 32, CDR LBW should be set to 00 (automatic) or 04 (4X Nominal) For peaking, Mindspeed recommends a value of 05'h for most data protocols, as this setting provides a good balance between lock time and peaking. For SONET, where low peaking may be required, Mindspeed recommends a setting of 01, which provides the lowest peaking, at the expense of longer lock times. There is also the ability to disable the second order loop, which will provide no peaking. With the second order loop disabled, the frequency tracking of the CDR is limited, so this mode is not recommended for general applications. To check the operational status of the PLL and CDR, look at registers 5Eh, 7Dh, and 9Ch. These registers indicate whether or not the PLL is receiving a reference clock, the PLL lock status, and the lock status of each individual CDR. In each bit, a "1" indicates an error condition, and "0" indicates no error. In addition to the status registers, there are also status latch registers at 5Fh, 7Eh, and 9Dh. Whenever a status bit is asserted, the corresponding bit inside status latch register will be set to a 1. Writing to the status change register will set all bits to "0". For data rates above 5.5 Gbps, the LOL alarm registers in addresses 5Eh, 5Fh, 7Dh, 7Eh, 9Ch, and 9Dh are not reliable and should not be used. The CDRs are normally configured to find the correct prescale (M) value based on looking at the incoming data. The algorithm can become confused with certain patterns. For automatic rate detection to work correctly, the input data must have single-bit transitions (010 or 101) patterns occur relatively often. Automatic rate detection also only searches available rates within a protocol. For instance, SATA and SAS are only defined for 1.5 Gbps, 3.0 Gbps, and 6.0 Gbps, so when configured for SATA/SAS operation, 750 MHz is not considered a candidate. For more information on Automatic Rate Detection, please see your Mindspeed customer representative. 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 22 Functional Description 4.10 PRBS Generation Inside the receive section, there is the ability to generate PRBS data instead of the re-generated data stream. This ability can be used during system debug and bring-up. Registers 61h, 63h, 65h, 67h, 80h, 82h, 84h, 86h, 9Fh, A1h, A3h, and A5h control the PRBS generation on a per-channel basis. To enable the PRBS generator, set bit 4 to a 1, and then select the desired PRBS or Clock pattern via bits [3:0]. Automatic rate detection (ARD) must be disabled when using the internal PRBS generator. ARD is disabled using the Data Rate Select register, located at addresses 53h, 56h, 59h, 5Ch, 72h, 75h, 78h, 7Bh, 91h, 94h, 97h, and 9Ah. Since the PRBS generation is done at the receiver, the crosspoint core must be programmed to route the PRBS generator to the desired output. It is also of note that the PRBS generator can be run either with the CDR tracking the input data, or off of the PLL clock. To have the PRBS generator clocked off the PLL, set the Loop BW/Peaking register for the appropriate CDR to FFh. To have the PRBS generator run off the CDR's recovered clock, leave the Loop BW/Peaking register with its default value. The PRBS Generator can be used at the same time as the PRBS detector. In this case, it is recommended that the PRBS generator run off the CDR's recovered clock, or the PRBS detector will not work correctly. 4.11 PRBS Detection In conjunction with the PRBS generator, the M21463 has the ability to detect PRBS pattern errors on its inputs. Registers 62h, 64h, 66h, 68h, 81h, 83h, 85h, 87h, A0h, A2h, A4h, and A6h control the PRBS detectors (one per input channel), and also report the status of the error detection. Note that the PRBS Detector can be enabled at the same time as the PRBS generator discussed above. To enable PRBS detection on an input channel, set bit 4 of the appropriate PRBS Detector Control/Status register to 1, and set the desired pattern to be detected in bits [3:0]. Note that the normal and inverted clock patterns are exactly the same, and the M21463 cannot tell the difference between the two (that is, it will treat a 0011 clock and a 1100 clock identically). After PRBS detection has been enabled, the PRBS Detector Control/Status register can be read to get the status of the PRBS error detector. Bit 5 reports if the PRBS detector is currently detecting an error. Since this bit is updated every 16 input data cycles, it is a poor indicator of whether a link is good or not. A better indicator is found in Bit 6, which reports if any errors have been observed since the last time the PRBS Detector Control/Status register was written. Note that when enabling PRBS detection or changing the pattern, there will be some initial bits that are seen as errors. Thus, when enabling or changing the PRBS detector, the PRBS Detector Control/Status register should be written twice before reading Bit 6. 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 23 Functional Description 4.12 Control Options There are two control modes available for the M21463. To control using a two wire, I2C compatible programming interface, the device can be configured for Software Interface Control (SIC). The M21463 can also self configure from an external EEPROM when the Memory Interface Control (MIC) mode is selected. In addition to the two control modes, the M21463 also supports boundary scan through a JTAG port. The boundary scan mode is enabled by setting the ADDR2 and ADDR1 pins to the logic floating level. To configure the device for Boundary Scan or Memory Interface Control Mode, configure the ADDR2, ADDR1, and ADDR0 pins as shown: Table 4-2. Control Mode Operating Mode Memory Interface Control (EEPROM) Boundary Scan ADDR2 ADDR1 ADDR0 H or L F H F F X Software Interface Control (SIC) 4.13 Refer to Table 4-4 for two wire device settings. Boundary Scan Operation In order to test external connections to and from the M21463, the device includes support for boundary scan through a JTAG port when configured for boundary scan mode. Boundary scan is supported on control pins and high-speed input/output pins (only the p-side of high-speed output pins support boundary scan). A wait time of 2 sec and minimum swing of 1.5 V is required for proper scan results. To configure the M21463 for boundary scan test mode, the ADDR2 and ADDR1 pins must be set to the floating logic level. When the M21463 is in boundary scan test mode, the following pins are used for JTAG signals: Table 4-3. Boundary Scan Mode Functionality Pin Name Pin Number Functionality in Boundary Scan Mode SDA 24 TMS SCL 22 TCLK ADDR0 88 TDI xSEL 21 TDO 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 24 Functional Description 4.14 Software Interface Control Mode Operation The functionality of the M21463 is controlled through register settings. Refer to Sections 5.1 and 5.2 for a full description of the registers available within the M21463. To access the registers, an I2C compatible, two-wire programming interface is available in the device. The two-wire device address is determined by the status of the pins ADDR [2:0]. The table below shows the address for each combination of settings for ADDR [2:0]. Table 4-4. Two Wire Serial Device Address ADDR2 ADDR1 ADDR0 M21463 Device Address Mode F x x None Reserved H or L F H 0100000 MIC mode H or L F L 0100000 SIC mode L L L 0100001 SIC mode L L H 0100010 SIC mode L H L 0100011 SIC mode L H H 0100100 SIC mode H L L 0100101 SIC mode H L H 0100110 SIC mode H H L 0100111 SIC mode H H H 0101000 SIC mode L L F 0101001 SIC mode L H F 0101010 SIC mode H L F 0101011 SIC mode H H F 0101100 SIC mode The two wire programming interface is designed to drive 400 pF at 100 kHz and 100 pF at 400 kHz. During a write operation, data is latched into the M21463 registers on the rising edge of SCL during the acknowledge phase (ACK) of communication. Refer to the I2C bus specification standard for timing information that is applicable to the two-wire programming interface. 4.15 Memory Interface Control Mode Operation With the M21463 configured for Memory Interface Control (MIC) operation, a single M21463 device or an array of M21463 devices can self configure from a single EEPROM with a two wire serial programming interface upon device power up. If the M21463 is configured for MIC operation at power up, the M21463 interface operates as a temporary two wire quasi-master operating at 100 kHz when downloading from external memory and 400 kHz when configuring other M21463 devices. After powering up in MIC mode, the M21463 will attempt to communicate with the on-board EEPROM through the two wire programming bus. If the M21463 does not receive an ACK response from the onboard EEPROM, it will repeat the attempt to communicate through the two wire programming bus. If the M21463 does not receive an ACK from the on board EEPROM within approximately 50 ms, it will stop trying to communicate with the EEPROM and no device registers will get configured. In an array of M21463 devices, only one device should be configured for MIC operation, and subsequent devices in the array should be configured for SIC operation. All devices in an array will receive the same configuration. When the M21463 device begins to self 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 25 Functional Description configure, it will read the contents of an external EEPROM and configure its registers accordingly. The expected EEPROM device address is 1010000b, and the M21463 quasi master device address should be set to 0100000b. The device will issue a power on reset (POR) when DVDDCORE reaches approximately 0.8 V during the power supply ramp. After the POR is complete, the device will poll the ADDR pins to determine which control mode the device is configured for. If the device is configured for MIC operation, it will attempt to communicate with the onboard EEPROM for register download immediately after the POR is complete. If there is no response from the EEPROM within approximately 50 ms after the POR is complete, the M21463 will stop trying to communicate with the EEPROM and the register download will fail. Please refer to Figure 4-2 for the recommended power supply ramp up timing in MIC mode. Figure 4-6 below illustrates the connections necessary to self-configure three M21463 devices using MIC mode. The first M21463 device (quasi master) is configured for operation in MIC mode, and the other two devices (Slave #1 and Slave #2) are configured for SIC operation with consecutive programming addresses. GND GND GND SDA ADDR2 ADDR1 ADDR0 DVDDIO SCL SCL M21463 Slave #2 SDA SDA SCL ADDR2 ADDR1 ADDR0 M21463 Slave #1 SCL M21463 Quasi Master SDA ADDR2 ADDR1 ADDR0 GND GND DVDDIO M21463 MIC System Diagram DVDDIO or GND FLOAT DVDDIO Figure 4-6. EEPROM When the M21463 is operated in MIC mode, the EEPROM must be powered up and stable within 50 ms of DVDDCORE ramping up to ensure that the register download from the EEPROM is robust. If the MIC download fails due to no response from the external EEPROM, all M21463 devices will retain their default register configurations and the M21463 device that was configured for MIC operation will revert to SIC operation. In MIC mode, the M21463 will automatically download settings for all register bits for register addresses 00h-4Ch. Note that some of the register addresses within this space are not defined. The EEPROM should be configured such that the undefined registers are loaded with the default values. Also, MSPD reserved register bits should be loaded with the default values as indicated in Section 5.0 of the M21463 data sheet. Register 01h is used to load the checksum seed value. The checksum seed value should be selected such that the 8 LSB of the sum of the register values from address 00h through 4Ch is equal to 2Eh. After the download from the EEPROM, the checksum value is computed and written into register address FCh. If the checksum value is equal to 2Eh, then this is recognized as a valid checksum and the quasi-master device will continue to program other device on the interface bus. If the checksum value is not equal to 2Eh, the quasi master device will repeat the download process and look for the correct checksum value up to 512 times before timing out. If the correct 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 26 Functional Description checksum value is not detected, the quasi-master device will not configure any additional devices on the interface bus. Register address 02h is used to identify the number of M21463 devices that will be self configured by the quasi master in MIC mode. When multiple M21463 devices are self configured in an array, the quasi master M21463 device will copy its register contents into other devices in the array sequentially using a 400 kHz interface bus. The devices in the array must have sequential programming addresses, starting with 0100000b for the quasi master device. After the last device in the M21463 array has been configured, the device will revert to normal two-wire serial programmed operation. If the MIC mode is used in conjunction with an external host controller, the two wire interface on the host controller must not interrupt the programming bus while self configuration is taking place. This can be ensured by timing out the host controller for N x 0.8 seconds (N= number of M21463 devices in the self configure array), or by monitoring the SDA/SCL bus for activity. 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 27 5.0 Control Registers Map and Descriptions 5.1 Control Registers Map Table 5-1. M21463 Register Summary Table (1 of 9) Address Register Name D7 (MSB) D6 D5 D4 00h Alarm Mode MSPD 01h Checksum 02h MIC Control 03h Gen Config 04h Reserved 05h Strobe 06h Polarity Invert 07h Polarity Invert 08h* Active Switch Config Configuration for Output 11 09h* Active Switch Config 0Ah* D3 D2 xALARM mode control D1 D0 MSPD Seed value for MIC checksum MSPD Standby MSPD Group Switch Identifies number of devices in MIC mode Clear Alarm Strobe Mode MSPD Set Squelch Level MSPD ICL Select xSEL Mode Software Strobe 00h/00h R/W 55h/55h R/W 00h/00h R/W 0Bh/2Bh R/W 00h/00h R/W 00h/00h R/W Input 11 Polarity Input 10 Polarity Input 9 Polarity Input 8 Polarity 00h/00h R/W Input 3 Polarity Input 2 Polarity Input 1 Polarity Input 0 Polarity 00h/00h R/W Configuration for Output 10 BAh/00h R/W Configuration for Output 9 Configuration for Output 8 98h/00h R/W Active Switch Config Configuration for Output 7 Configuration for Output 6 32h/00h R/W 0Bh* Active Switch Config Configuration for Output 5 Configuration for Output 4 10h/00h R/W 0Ch Active Switch Config Configuration for Output 3 Configuration for Output 2/Group 2 76h/02h R/W 0Dh Active Switch Config Configuration for Output 1/Group 1 Configuration for Output 0/Group 0 54h/01h R/W 0Eh* Intermediate Switch Config #1 Configuration for Output 11 Configuration for Output 10 BAh/00h R/W 0Fh* Intermediate Switch Config #1 Configuration for Output 9 Configuration for Output 8 98h/00h R/W 10h* Intermediate Switch Config #1 Configuration for Output 7 Configuration for Output 6 32h/00h R/W 21463-DSH-001-E MSPD Default (Lane/ R/W Group mode) Input 7 Polarity Input 6 Polarity Input 5 Polarity Input 4 Polarity Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 28 Control Registers Map and Descriptions Table 5-1. M21463 Register Summary Table (2 of 9) Address Register Name D7 (MSB) D6 D5 D4 D3 D2 D1 D0 Default (Lane/ R/W Group mode) 11h* Intermediate Switch Config #1 Configuration for Output 5 Configuration for Output 4 10h/00h R/W 12h Intermediate Switch Config #1 Configuration for Output 3 Configuration for Output 2/Group 2 76h/02h R/W 13h Intermediate Switch Config #1 Configuration for Output 1/Group 1 Configuration for Output 0/Group 0 54h/01h R/W 14h* Intermediate Switch Config #2 Configuration for Output 11 Configuration for Output 10 32h/00h R/W 15h* Intermediate Switch Config #2 Configuration for Output 9 Configuration for Output 8 10h/00h R/W 16h* Intermediate Switch Config #2 Configuration for Output 7 Configuration for Output 6 76h/00h R/W 17h* Intermediate Switch Config #2 Configuration for Output 5 Configuration for Output 4 54h/00h R/W 18h Intermediate Switch Config #2 Configuration for Output 3 Configuration for Output 2/Group 2 BAh/00h R/W 19h Intermediate Switch Config #2 Configuration for Output 1/Group 1 Configuration for Output 0/Group 0 98h/12h R/W 1Ah* Input Config A Input 11 Configuration Input 10 Configuration Input 9 Configuration Input 8 Configuration FFh/00h R/W 1Bh* Input Config A Input 7 Configuration Input 6 Configuration Input 5 Configuration Input 4 Configuration FFh/00h R/W 1Ch Input Config A Input 3 Configuration Input 2/Group 2 Configuration Input 1/Group 1 Configuration Input 0/Group 0 Configuration FFh/3Fh R/W 1Dh* Input 11 Equalization Input 11 Equalization 37h/00h R/W 1Eh* Input 10 Equalization Input 10 Equalization 37h/00h R/W 1Fh* Input 9 Equalization Input 9 Equalization 37h/00h R/W 20h* Input 8 Equalization Input 8 Equalization 37h/00h R/W 21h* Input 7 Equalization Input 7 Equalization 37h/00h R/W 22h* Input 6 Equalization Input 6 Equalization 37h/00h R/W 23h* Input 5 Equalization Input 5 Equalization 37h/00h R/W 24h* Input 4 Equalization Input 4 Equalization 37h/00h R/W 25h* Input 3 Equalization Input 3 Equalization 37h/00h R/W 26h Input 2 Equalization Input/Group 2 Equalization 37h/37h R/W 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 29 Control Registers Map and Descriptions Table 5-1. M21463 Register Summary Table (3 of 9) Address Register Name D7 (MSB) D6 D5 D4 D3 D2 D1 D0 Default (Lane/ R/W Group mode) 27h Input 1 Equalization Input/Group 1 Equalization 37h/37h R/W 28h Input 0 Equalization Input/Group 0 Equalization 37h/37h R/W 29h-34h Reserved MSPD 00h/00h R/W 35h* Input 11 Config B MSPD In11 LOS Enable MSPD Input11 Squelch MSPD Input11 EI Enable C0h/00h R/W 36h* Input 10 Config B MSPD In10 LOS Enable MSPD Input10 Squelch MSPD Input10 EI Enable C0h/00h R/W 37h* Input 9 Config B MSPD In9 LOS Enable MSPD Input9 Squelch MSPD Input9 EI Enable C0h/00h R/W 38h* Input 8 Config B MSPD In8 LOS Enable MSPD Input8 Squelch MSPD Input8 EI Enable C0h/00h R/W 39h* Input 7 Config B MSPD In7 LOS Enable MSPD Input7 Squelch MSPD Input7 EI Enable C0h/00h R/W 3Ah* Input 6 Config B MSPD In6 LOS Enable MSPD Input6 Squelch MSPD Input6 EI Enable C0h/00h R/W 3Bh* Input 5 Config B MSPD In5 LOS Enable MSPD Input5 Squelch MSPD Input5 EI Enable C0h/00h R/W 3Ch* Input 4 Config B MSPD In4 LOS Enable MSPD Input4 Squelch MSPD Input4 EI Enable C0h/00h R/W 3Dh* Input 3 Config B MSPD In3 LOS Enable MSPD Input3 Squelch MSPD Input3 EI Enable C0h/00h R/W 3Eh Input 2 Config B MSPD In/ Group2 L OS Enable MSPD Input/Group2 Squelch MSPD Input2 EI Enable C0h/C0h R/W 3Fh Input 1 Config B MSPD In/ Group1 L OS Enable MSPD Input/Group1 Squelch MSPD Input1 EI Enable C0h/C0h R/W 40h Input 0 Config B MSPD In/ Group0 L OS Enable MSPD Input/Group0 Squelch MSPD Input0 EI Enable C0h/C0h R/W 41h* Output 11 Config Output 11 Swing MSPD Output 11 De-Emphasis MSPD 00h/00h R/W 42h* Output 10 Config Output 10 Swing MSPD Output 10 De-Emphasis MSPD 00h/00h R/W 43h* Output 9 Config Output 9 Swing MSPD Output 9 De-Emphasis MSPD 00h/00h R/W 44h* Output 8 Config Output 8 Swing MSPD Output 8 De-Emphasis MSPD 00h/00h R/W 45h* Output 7 Config Output 7 Swing MSPD Output 7 De-Emphasis MSPD 00h/00h R/W 46h* Output 6 Config Output 6 Swing MSPD Output 6 De-Emphasis MSPD 00h/00h R/W 47h* Output 5 Config Output 5 Swing MSPD Output 5 De-Emphasis MSPD 00h/00h R/W 48h* Output 4 Config Output 4 Swing MSPD Output 4 De-Emphasis MSPD 00h/00h R/W 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 30 Control Registers Map and Descriptions Table 5-1. M21463 Register Summary Table (4 of 9) Address Register Name D7 (MSB) D6 D5 D4 D3 D2 D1 D0 Default (Lane/ R/W Group mode) 49h* Output 3 Config Output 3 Swing MSPD Output 3 De-Emphasis MSPD 00h/00h R/W 4Ah Output 2 Config Output/Group 2 Swing MSPD Output/Group 2 De-Emphasis MSPD 00h/00h R/W 4Bh Output 1 Config Output/Group 1 Swing MSPD Output/Group 1 De-Emphasis MSPD 00h/00h R/W 4Ch Output 0 Config Output/Group 0 Swing MSPD Output/Group 0 De-Emphasis MSPD 00h/00h R/W 4Dh General Config, CDR 0-3 00h R/W 4Eh PLL Reference Multiplier, CDR 0-3 00h R/W 4Fh PLL Range Select, CDR 0-3 00h R/W 50h PLL LBW, CDR 0-3 00h R/W 51h Reserved 00h/00h R/W 52h CDR Config, CDR 0 MSPD 00h R/W 53h Data Rate Select, CDR 0 MSPD CDR 0 Prescale 00h R/W 54h Loop BW/Peaking, CDR 0 CDR 0 Peaking Select 00h R/W 55h CDR Config, CDR 1 MSPD 00h R/W 56h Data Rate Select, CDR 1 MSPD CDR 1 Prescale 00h R/W 57h Loop BW/Peaking, CDR 1 CDR 1 Peaking Select 00h R/W 58h CDR Config, CDR 2 MSPD 00h R/W 59h Data Rate Select, CDR 2 MSPD CDR 2 Prescale 00h R/W 5Ah Loop BW/Peaking, CDR2 CDR 2 Peaking Select 00h R/W 5Bh CDR Config, CDR 3 MSPD 00h R/W 5Ch Data Rate Select, CDR 3 MSPD CDR 3 Prescale 00h R/W 5Dh Loop BW/Peaking, CDR 3 CDR 3 Peaking Select 00h R/W 5Eh PLL/CDR Status, CDR 0-3 N/A R 21463-DSH-001-E MSPD Protocol Selection Value for Bank A Bank A Reference Multiplication Value Bank A Powerdown Unused Unused Bank A PLL Range Override Bank A PLL Range Select Bank A PLL Loop Bandwidth Bank A PLL LBW Override MSPD MSPD CDR 0 power up/down MSPD CDR 0 Loop Bandwidth CDR 1 power up/down MSPD CDR 1 ARD enable CDR 1 Loop Bandwidth CDR 2 power up/down MSPD Unused CDR 0 ARD enable CDR 2 ARD enable CDR 2 Loop Bandwidth CDR 3 power up/down NOREF CDR 3 ARD enable CDR 3 Loop Bandwidth PLL_LOL LOL CDR 3 Mindspeed Technologies(R) Mindspeed Proprietary and Confidential LOL CDR 2 LOL CDR 1 LOL CDR 0 31 Control Registers Map and Descriptions Table 5-1. M21463 Register Summary Table (5 of 9) Address Register Name 5Fh PLL/CDR Status Latch, CDR 0-3 60h Reserved 61h PRBS Generator Control, CDR 0 62h PRBS Detector Control/Status, CDR 0 63h PRBS Generator Control, CDR 1 64h PRBS Detector Control/Status, CDR 1 65h PRBS Generator Control, CDR 2 66h PRBS Detector Control/Status, CDR 2 67h PRBS Generator Control, CDR 3 68h PRBS Detector Control/Status, CDR 3 69h-6Bh Reserved 6Ch General Config, CDR 4-7 6Dh PLL Reference Multiplier, CDR 4-7 6Eh PLL Range Select, CDR 4-7 6Fh PLL LBW, CDR 4-7 70h Reserved 21463-DSH-001-E D7 (MSB) D6 Unused D5 D4 D3 D2 D1 D0 NOREF Latch PLL_LOL Latch LOL CDR 3 Latch LOL CDR 2 Latch LOL CDR 1 Latch LOL CDR 0 Latch MSPD Unused Unused CDR 0 PRBS Error Latch Unused Unused CDR 1 PRBS Error Latch Unused Unused CDR 2 PRBS Error Latch Unused Unused CDR 3 PRBS Error Latch R/W N/A R CDR 0 PRBS gen Enable CDR 0 PRBS Generator Pattern Select 00h R/W CDR 0 PRBS Error Status CDR 0 PRBS detect Enable CDR 0 PRBS Detector Pattern Select 00h R/W MSPD CDR 1 PRBS gen Enable CDR 1 PRBS Generator Pattern Select 00h R/W CDR 1 PRBS Error Status CDR 1 PRBS detect Enable CDR 1 PRBS Detector Pattern Select 00h R/W MSPD CDR 2 PRBS gen Enable CDR 2 PRBS Generator Pattern Select 00h R/W CDR 2 PRBS Error Status CDR 2 PRBS detect Enable CDR 2 PRBS Detector Pattern Select 00h R/W MSPD CDR 3 PRBS gen Enable CDR 3 PRBS Generator Pattern Select 00h R/W CDR 3 PRBS Error Status CDR 3 PRBS detect Enable CDR 3 PRBS Detector Pattern Select 00h R/W 00h/00h R/W 00h R/W 00h R/W 00h R/W 00h R/W 00h/00h R/W MSPD Protocol Selection Value for Bank B Bank B Reference Multiplication Value Unused Unused N/A MSPD MSPD Bank B Powerdown Default (Lane/ R/W Group mode) Bank B PLL Range Override Bank B PLL Loop Bandwidth Bank B PLL LBW Override MSPD Mindspeed Technologies(R) Mindspeed Proprietary and Confidential Bank B PLL Range Select 32 Control Registers Map and Descriptions Table 5-1. M21463 Register Summary Table (6 of 9) Address Register Name D7 (MSB) D6 D5 D3 D2 CDR4 power up/down D1 71h CDR Config, CDR 4 72h Data Rate Select, CDR 4 MSPD 73h Loop BW/Peaking, CDR 4 CDR 4 Peaking Select 74h CDR Config, CDR 5 75h Data Rate Select, CDR 5 MSPD 76h Loop BW/Peaking, CDR 5 CDR 5 Peaking Select 77h CDR Config, CDR 6 78h Data Rate Select, CDR 6 MSPD 79h Loop BW/Peaking, CDR 6 CDR 6 Peaking Select 7Ah CDR Config, CDR 7 7Bh Data Rate Select, CDR 7 MSPD 7Ch Loop BW/Peaking, CDR 7 CDR 7 Peaking Select 7Dh PLL/CDR Status, CDR 4-7 Unused NOREF PLL_LOL LOL CDR 7 LOL CDR 6 LOL CDR 5 7Eh PLL/CDR Status Latch, CDR 4-7 Unused NOREF Latch PLL_LOL Latch LOL CDR 7 Latch LOL CDR 6 Latch LOL CDR 5 Latch 7Fh Reserved 80h PRBS Generator Control, CDR 4 81h PRBS Detector Control/Status, CDR 4 82h PRBS Generator Control, CDR 5 83h PRBS Detector Control/Status, CDR 5 21463-DSH-001-E MSPD D4 MSPD CDR 4 ARD enable CDR 5 ARD enable 00h R/W CDR 4 Prescale 00h R/W 00h R/W MSPD 00h R/W CDR 5 Prescale 00h R/W 00h R/W MSPD 00h R/W CDR 6 Prescale 00h R/W 00h R/W MSPD 00h R/W CDR 7 Prescale 00h R/W 00h R/W LOL CDR 4 N/A R LOL CDR 4 Latch N/A R/W N/A R CDR 5 Loop Bandwidth CDR 6 power up/down MSPD MSPD CDR 4 Loop Bandwidth CDR 5 power up/down MSPD CDR 6 ARD enable CDR 6 Loop Bandwidth CDR 7 power up/down CDR 7 ARD enable CDR 7 Loop Bandwidth MSPD Unused Unused CDR 4 PRBS Error Latch Unused Unused CDR 5 PRBS Error Latch D0 Default (Lane/ R/W Group mode) MSPD CDR 4 PRBS gen Enable CDR 4 PRBS Generator Pattern Select 00h R/W CDR 4 PRBS Error Status CDR 4 PRBS detect Enable CDR 4 PRBS Detector Pattern Select 00h R/W MSPD CDR 5 PRBS gen Enable CDR 5 PRBS Generator Pattern Select 00h R/W CDR 5 PRBS Error Status CDR 5 PRBS detect Enable CDR 5 PRBS Detector Pattern Select 00h R/W Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 33 Control Registers Map and Descriptions Table 5-1. M21463 Register Summary Table (7 of 9) Address Register Name D7 (MSB) D6 D4 MSPD CDR 6 PRBS gen Enable CDR 6 PRBS Generator Pattern Select 00h R/W CDR 6 PRBS Error Status CDR 6 PRBS detect Enable CDR 6 PRBS Detector Pattern Select 00h R/W MSPD CDR 7 PRBS gen Enable CDR 7 PRBS Generator Pattern Select 00h R/W CDR 7 PRBS Error Status CDR 7 PRBS detect Enable CDR 7 PRBS Detector Pattern Select 00h R/W 00h/00h R/W 00h R/W 00h R/W 00h R/W 00h R/W 00h/00h R/W MSPD 00h R/W CDR 8 Prescale 00h R/W 00h R/W MSPD 00h R/W CDR 9 Prescale 00h R/W 00h R/W MSPD 00h R/W CDR 10 Prescale 00h R/W PRBS Generator Control, CDR 6 85h PRBS Detector Control/Status, CDR 6 86h PRBS Generator Control, CDR 7 87h PRBS Detector Control/Status, CDR 7 88h-8Ah Reserved 8Bh General Config, CDR 8-11 8Ch PLL Reference Multiplier, CDR 8-11 8Dh PLL Range Select, CDR 8-11 8Eh PLL LBW, CDR 8-11 8Fh Reserved 90h Gen Config, CDR 8 91h Data Rate Select, CDR 8 MSPD 92h Loop BW/Peaking, CDR 8 CDR 8 Peaking Select 93h Gen Config, CDR 9 94h Data Rate Select, CDR 9 MSPD 95h Loop BW/Peaking, CDR 9 CDR 9 Peaking Select 96h Gen Config, CDR 10 97h Data Rate Select, CDR 10 21463-DSH-001-E Unused D5 84h Unused CDR 6 PRBS Error Latch Unused Unused CDR 7 PRBS Error Latch D3 D2 D1 D0 Default (Lane/ R/W Group mode) MSPD MSPD Protocol Selection Value for Bank C Bank C Reference Multiplication Value Bank C Powerdown Unused Unused Bank C PLL Range Override Bank C PLL Loop Bandwidth Bank C PLL LBW Override MSPD MSPD CDR 8 power up/down MSPD CDR 8 ARD enable CDR 8 Loop Bandwidth CDR 9 power up/down MSPD CDR 9 ARD enable CDR 9 Loop Bandwidth CDR 10 power up/down MSPD CDR 10 ARD enable Mindspeed Technologies(R) Mindspeed Proprietary and Confidential Bank C PLL Range Select 34 Control Registers Map and Descriptions Table 5-1. M21463 Register Summary Table (8 of 9) Address Register Name D7 (MSB) D6 D5 D4 D3 D2 98h Loop BW/Peaking, CDR 10 99h Gen Config, CDR 11 9Ah Data Rate Select, CDR 11 MSPD 9Bh Loop BW/Peaking, CDR 11 CDR 11 Peaking Select 9Ch PLL/CDR Status, CDR 8-11 Unused NOREF PLL_LOL LOL CDR11 LOL CDR10 LOL CDR9 9Dh PLL/CDR Status Latch CDR 8-11 Unused NOREF Latch PLL_LOL Latch LOL CDR11 Latch LOL CDR10 Latch LOL CDR9 Latch 9Eh Reserved 9Fh PRBS Generator Control, CDR 8 A0h PRBS Detector Control/Status, CDR 8 A1h PRBS Generator Control, CDR 9 A2h PRBS Detector Control/Status, CDR 9 A3h PRBS Generator Control, CDR 10 A4h PRBS Detector Control/Status, CDR 10 A5h PRBS Generator Control, CDR 11 A6h PRBS Detector Control/Status, CDR 11 A7h-C2h Reserved C3h LOS Alarm 21463-DSH-001-E CDR 10 Peaking Select D1 MSPD D0 CDR 10 Loop Bandwidth 00h R/W MSPD 00h R/W CDR 11 Prescale 00h R/W 00h R/W LOL CDR8 N/A R LOL CDR8 Latch N/A R/W N/A R CDR 11 power up/down CDR 11 ARD enable CDR 11 Loop Bandwidth MSPD Unused Unused CDR 8 PRBS Error Latch Unused Unused CDR 9 PRBS Error Latch Unused Unused CDR 10 PRBS Error Latch Unused Unused CDR 11 PRBS Error Latch Default (Lane/ R/W Group mode) MSPD CDR 8 PRBS gen Enable CDR 8 PRBS Generator Pattern Select 00h R/W CDR 8 PRBS Error Status CDR 8 PRBS detect Enable CDR 8 PRBS Detector Pattern Select 00h R/W MSPD CDR 9 PRBS gen Enable CDR 9 PRBS Generator Pattern Select 00h R/W CDR 9 PRBS Error Status CDR 9 PRBS detect Enable CDR 9 PRBS Detector Pattern Select 00h R/W MSPD CDR 10 PRBS gen Enable CDR 10 PRBS Generator Pattern Select 00h R/W CDR 10 PRBS Error Status CDR 10 PRBS detect Enable CDR 10 PRBS Detector Pattern Select 00h R/W MSPD CDR 11 PRBS gen Enable CDR 11 PRBS Generator Pattern Select 00h R/W CDR 11 PRBS Error Status CDR 11 PRBS detect Enable CDR 11 PRBS Detector Pattern Select 00h R/W 00h/00h R/W N/A R MSPD MSPD Input11 LOS Mindspeed Technologies(R) Mindspeed Proprietary and Confidential Input10 LOS Input9 LO S Input8 LO S 35 Control Registers Map and Descriptions Table 5-1. M21463 Register Summary Table (9 of 9) D7 (MSB) Address Register Name C4h LOS Alarm C5h-F9h Reserved FAh Global CDR Control FCh MIC Checksum FDh D6 D5 D4 Input7 LO Input6 LOS Input5 LO Input4 LOS S S D3 D2 D1 D0 Input 3 LOS Input 2 LOS Input 1 LOS Input 0 LOS Default (Lane/ R/W Group mode) N/A R 00h/00h R/W 04h R/W Computed Checksum Value 00h R Chip Code M21463 Chip Code 60h R FEh Chip Revision M21463 Revision Number ---** R FFh Master Reset Chip Reset 00h R/W MSPD MSPD All CDR Powerdown and Bypass MSPD * Registers noted with a * are only used when the device is in Lane Switch Mode, which is enabled by setting address 03h[5] to 0b. ** See register description for details on the contents of the chip revision register (register address FEh). NOTE: Reserved register bits in R/W registers must be set to their default values. 5.2 Control Registers Descriptions Register Address: 00h Register Name: Alarm Mode Description: Controls the behavior of the xAlarm pin when an alarm is asserted. Bit 7:4 3 2:0 Bit Description Reserved, set to 0000b 1: xALARM is static high or low depending on Alarm condition 0: xALARM toggles once with an interrupt pulse when asserted Reserved, set to 000b Default R/W 0000b R/W 0b R/W 000b R/W Register Address: 01h Register Name: Checksum Description: Used with MIC mode. The sum of the value of registers from 00h-4Ch must be equal to 2Eh for to compute a valid checksum after the EEPROM download. Bit 7:0 Bit Description Checksum seed value Default R/W 55h R/W Default R/W Register Address: 02h Register Name: MIC Control Description: Identifies the number of devices on the serial bus when MIC programming mode is used. Bit Bit Description 7:4 Reserved, set to 0000b 0000b R/W 3:0 0000: No other devices on the serial bus 0001: 1 other device on the serial bus : * 1101: 13 other devices on the serial bus (maximum number supported) 0000b R/W 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 36 Control Registers Map and Descriptions Register Address: 03h Register Name: General Config Description: Used to power up/power down device circuitry, configure crosspoint switching modes, clear alarms, and select squelch mode. Bit Bit Description Default R/W 7 0: Power up mode, normal operation 1: Power down mode 0b R/W 6 Reserved, set to 0b 0b R/W 5 0: Lane Switch Mode 1: Group Switch Mode 1b R/W 4 0: Normal operation 1: Clear global alarms 0b R/W 3 0: Switch setting updated with software strobe (address 05h) 1: Switch setting updated with hardware xSEL pin 1b R/W 2 Reserved, set to 0b 0b R/W 00: Do not squelch 01: Output logic high on squelch 10: Output logic low on squelch 11: Output electrical idle level (common-mode) on squelch (recommended for AC coupled outputs) 11b R/W Default R/W 1:0 Register Address: 05h Register Name: Strobe Description: Configures the switch core setting changes. Bit Bit Description 7 0: Selects ISC#1 as the active switch state upon a HW/SW strobe 1: Selects ISC#2 as the active switch state upon a HW/SW strobe 0b R/W 6 0: When the device is configured for HW strobe mode (address 03h, bit 3), ISC#1 becomes the active switch setting after a L to H transition on the xSEL pin, and ISC#2 becomes the active switch setting after a H to L transition on the xSEL pin. After power up, ISC#1 will be the active switch setting if the xSEL pin is held L. An H to L transition on the xSEL pin is required for ISC#2 to become the active switch setting in this mode. 0b R/W 000000b R/W 1: When the device is configured for HW strobe mode (address 03h, bit 3), A transition from H to L on xSEL pin updates the active switch setting (ISC#1 or ISC#2 as determined by bit 7 of address 05h). 5:0 000000: Normal operation 010101: When the device is configured for SW strobe mode (address 03h, bit 3), Software strobe to update the active switch setting (ISC#1 or ISC#2 as determined by bit 7 of address 05h) 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 37 Control Registers Map and Descriptions Register Address: 06h, 07h Register Name: Polarity Invert Description: Inverts the polarity of the high-speed inputs. Bit Bit Description Default R/W 7 0: Reserved, set to 0b (address 06h), normal polarity for input 7 (address 07h) 1: Not Used (address 06h), inverted polarity for input 7 (address 07h) 0b R/W 6 0: Reserved, set to 0b (address 06h), normal polarity for input 6 (address 07h) 1: Not Used (address 06h), inverted polarity for input 6 (address 07h) 0b R/W 5 0: Reserved, set to 0b (address 06h), normal polarity for input 5 (address 07h) 1: Not Used (address 06h), inverted polarity for input 5 (address 07h) 0b R/W 4 0: Reserved, set to 0b (address 06h), normal polarity for input 4 (address 07h) 1: Not Used (address 06h), inverted polarity for input 4 (address 07h) 0b R/W 3 0: Normal polarity for input 11 (address 06h), input 3 (address 07h) 1: Inverted polarity for input 11 (address 06h), input 3 (address 07h) 0b R/W 2 0: Normal polarity for input 10 (address 06h), input 2 (address 07h) 1: Inverted polarity for input 10 (address 06h), input 2 (address 07h) 0b R/W 1 0: Normal polarity for input 9 (address 06h), input 1 (address 07h) 1: Inverted polarity for input 9 (address 06h), input 1 (address 07h) 0b R/W 0 0: Normal polarity for input 8 (address 06h), input 0 (address 07h) 1: Inverted polarity for input 8 (address 06h), input 0 (address 07h) 0b R/W Register Address: 08h, 09h, 0Ah, 0Bh, 0Ch, 0Dh Register Name: Active Switch Configuration (ASC) Description: Contains the active crosspoint switch configuration for output channels. In group switch mode, only addresses 0Ch and 0Dh are used. Bit Bit Description Default (Group Switch Mode) Default (Lane Switch Mode) R/W 7:4 Address 08h - Selects the input for output 11 (lane switch mode) Address 09h - Selects the input for output 9 (lane switch mode) Address 0Ah - Selects the input for output 7 (lane switch mode) Address 0Bh - Selects the input for output 5 (lane switch mode) Address 0Ch - Selects the input for output 3 (lane switch mode) Address 0Dh - Selects the input for output 1 (lane switch mode) or group 1 (group switch mode) Address 08h - 0000 Address 09h - 0000 Address 0Ah - 0000 Address 0Bh - 0000 Address 0Ch - 0000 Address 0Dh - 0000 (Input group 0) Address 08h - 1011 (Input 11) Address 09h - 1001 (Input 9) Address 0Ah - 0011 (Input 3) Address 0Bh - 0001 (Input 1) Address 0Ch - 0111 (Input 7) Address 0Dh - 0101 (Input 5) R/W 3:0 Address 08h - Selects the input for output 10 (lane switch mode) Address 09h - Selects the input for output 8 (lane switch mode) Address 0Ah - Selects the input for output 6 (lane switch mode) Address 0Bh - Selects the input for output 4 (lane switch mode) Address 0Ch - Selects the input for output 2 (lane switch mode) or group 2 (group switch mode) Address 0Dh - Selects the input for output 0 (lane switch mode) or group 0 (group switch mode) Address 08h - 0000 Address 09h - 0000 Address 0Ah - 0000 Address 0Bh - 0000 Address 0Ch - 0010 (Input group 2) Address 0Dh - 0001 (Input group 1) Address 08h - 1010 (Input 10) Address 09h - 1000 (Input 8) Address 0Ah - 0010 (Input 2) Address 0Bh - 0000 (Input 0) Address 0Ch - 0110 (Input 6) Address 0Dh - 0100 (Input 4) R/W 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 38 Control Registers Map and Descriptions Register Address: 0Eh, 0Fh, 10h, 11h, 12h, 13h Register Name: Intermediate Switch Configuration #1 (ISC #1) Description: Contains ISC #1 for output channels. In group switch mode, only addresses 12h and 13h are used. Bit Bit Description Default (Group Switch Mode) Default (Lane Switch Mode) R/W 7:4 Address 0Eh - Selects the input for output 11 (lane switch mode) Address 0Fh - Selects the input for output 9 (lane switch mode) Address 10h - Selects the input for output 7 (lane switch mode) Address 11h - Selects the input for output 5 (lane switch mode) Address 12h - Selects the input for output 3 (lane switch mode) Address 13h - Selects the input for output 1 (lane switch mode) or group 1 (group switch mode) Address 0Eh - 0000 Address 0Fh - 0000 Address 10h - 0000 Address 11h - 0000 Address 12h - 0000 Address 13h - 0000 (Input group 0) Address 0Eh - 1011 (Input 11) Address 0Fh - 1001 (Input 9) Address 10h - 0011 (Input 3) Address 11h - 0001 (Input 1) Address 12h - 0111 (Input 7) Address 13h - 0101 (Input 5) R/W 3:0 Address 0Eh - Selects the input for output 10 (lane switch mode) Address 0Fh - Selects the input for output 8 (lane switch mode) Address 10h - Selects the input for output 6 (lane switch mode) Address 11h - Selects the input for output 4 (lane switch mode) Address 12h - Selects the input for output 2 (lane switch mode) or group 2 (group switch mode) Address 13h - Selects the input for output 0 (lane switch mode) or group 0 (group switch mode) Address 0Eh - 0000 Address 0Fh - 0000 Address 10h - 0000 Address 11h - 0000 Address 12h - 0010 (Input group 2) Address 13h - 0001 (Input group 1) Address 0Eh - 1010 (Input 10) Address 0Fh - 1000 (Input 8) Address 10h - 0010 (Input 2) Address 11h - 0000 (Input 0) Address 12h - 0110 (Input 6) Address 13h - 0100 (Input 4) R/W Register Address: 14h, 15h, 16h, 17h, 18h, 19h Register Name: Intermediate Switch Configuration #2 (ISC #2) Description: Contains ISC #2 for output channels. In group switch mode, only addresses 18h and 19h are used. Bit Bit Description Default (Group Switch Mode) Default (Lane Switch Mode) R/W 7:4 Address 14h - Selects the input for output 11 (lane switch mode) Address 15h - Selects the input for output 9 (lane switch mode) Address 16h - Selects the input for output 7 (lane switch mode) Address 17h - Selects the input for output 5 (lane switch mode) Address 18h - Selects the input for output 3 (lane switch mode) Address 19h - Selects the input for output 1 (lane switch mode) or group 1 (group switch mode) Address 14h - 0000 Address 15h - 0000 Address 16h - 0000 Address 17h - 0000 Address 18h - 0000 Address 19h - 0000 (Input group 0) Address 14h - 0011 (Input 3) Address 15h - 0001 (Input 1) Address 16h - 0111 (Input 7) Address 17h - 0101 (Input 5) Address 18h - 1011 (Input 11) Address 19h - 1001 (Input 9) R/W 3:0 Address 14h - Selects the input for output 10 (lane switch mode) Address 15h - Selects the input for output 8 (lane switch mode) Address 16h - Selects the input for output 6 (lane switch mode) Address 17h - Selects the input for output 4 (lane switch mode) Address 18h - Selects the input for output 2 (lane switch mode) or group 2 (group switch mode) Address 19h - Selects the input for output 0 (lane switch mode) or group 0 (group switch mode) Address 14h - 0000 Address 15h - 0000 Address 16h - 0000 Address 17h - 0000 Address 18h - 0010 (Input group 2) Address 19h - 0001 (Input group 1) Address 14h - 0010 (Input 2) Address 15h - 0000 (Input 0) Address 16h - 0110 (Input 6) Address 17h - 0100 (Input 4) Address 18h - 1010 (Input 10) Address 19h - 1000 (Input 8) R/W 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 39 Control Registers Map and Descriptions Register Address: 1Ah, 1Bh, 1Ch Register Name: Input configuration A Description: Configures buffers for high-speed inputs. In group switch mode, only address 1Ch is used. Bit Bit Description Default R/W 7:6 00: Input 11 (address 1Ah), input 7 (address 1Bh), input 3 (address 1Ch) powered down with high impedance (>100 k single ended, 100 differential) termination 01: Input 11 (address 1Ah), input 7 (address 1Bh), input 3 (address 1Ch) powered down with source 50 single-ended (100 differential) termination 10: Input 11 (address 1Ah), input 7 (address 1Bh), input 3 (address 1Ch) powered on with high impedance (>100 k single ended, 100 differential) termination 11: Input 11 (address 1Ah), input 7 (address 1Bh), input 3 (address 1Ch) powered on with source 50 single-ended (100 differential) termination 11 R/W 5:4 00: Input 10 (address 1Ah), input 6 (address 1Bh), input 2 (address 1Ch) powered down with high impedance (>100 k single ended, 100 differential) termination 01: Input 10 (address 1Ah), input 6 (address 1Bh), input 2 (address 1Ch) powered down with source 50 single-ended (100 differential) termination 10: Input 10 (address 1Ah), input 6 (address 1Bh), input 2 (address 1Ch) powered on with high impedance (>100 k single ended, 100 differential) termination 11: Input 10 (address 1Ah), input 6 (address 1Bh), input 2 (address 1Ch) powered on with source 50 single-ended (100 differential) termination 11 R/W 3:2 00: Input 9 (address 1Ah), input 5 (address 1Bh), input 1 (address 1Ch) powered down with high impedance (>100 k single ended, 100 differential) termination 01: Input 9 (address 1Ah), input 5 (address 1Bh), input 1 (address 1Ch) powered down with source 50 single-ended (100 differential) termination 10: Input 9 (address 1Ah), input 5 (address 1Bh), input 1 (address 1Ch) powered on with high impedance (>100 k single ended, 100 differential) termination 11: Input 9 (address 1Ah), input 5 (address 1Bh), input 1 (address 1Ch) powered on with source 50 single-ended (100 differential) termination 11 R/W 1:0 00: Input 8 (address 1Ah), input 4 (address 1Bh), input 0 (address 1Ch) powered down with high impedance (>100 k single ended, 100 differential) termination 01: Input 8 (address 1Ah), input 4 (address 1Bh), input 0 (address 1Ch) powered down with source 50 single-ended (100 differential) termination 10: Input 8 (address 1Ah), input 4 (address 1Bh), input 0 (address 1Ch) powered on with high impedance (>100 k single ended, 100 differential) termination 11: Input 8 (address 1Ah), input 4 (address 1Bh), input 0 (address 1Ch) powered on with source 50 single-ended (100 differential) termination 11 R/W 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 40 Control Registers Map and Descriptions Register Address: 1Dh, 1Eh, 1Fh, 20h, 21h, 22h, 23h, 24h, 25h, 26h, 27h, 28h Register Name: Input Equalization Description: Sets the equalization for input 11 (address 1Dh), input 10 (address 1Eh), input 9 (address 1Fh), input 8 (address 20h), input 7 (address 21h), input 6 (address 22h), input 5 (address 23h), input 4(address 24h), input 3 (address 25h), input 2/Group 2 (address 26h), input 1/Group 1 (address 27h), input 0/Group 0 (address 28h). In group mode, only addresses 26h, 27h, and 28h are used. Bit 7:0 Bit Description 00h: Equalization level 1--Minimum Equalization 20h: Equalization level 2 11h: Equalization level 3 21h: Equalization level 4 31h: Equalization level 5 A1h: Equalization level 6 29h: Equalization level 7 33h: Equalization level 8 37h: Equalization level 9 45h: Equalization level 10 59h: Equalization level 11 5Eh: Equalization level 12 6Eh: Equalization level 13 7Fh: Equalization level 14 FAh: Equalization level 15 FFh: Equalization level 16--Maximum Equalization Default R/W 37h R/W Register Address: 35h, 36h, 37h, 38h, 39h, 3Ah, 3Bh, 3Ch, 3Dh, 3Eh, 3Fh, 40h Register Name: Input configuration B Description: Configures the LOS, squelch, and electrical idle functionality for input 11 (address 35h), input 10 (address 36h), input 9 (address 37h), input 8 (address 38h), input 7 (address 39h), input 6 (address 3Ah), input 5 (address 3Bh), input 4 (address 3Ch), input 3 (address 3Dh), input 2/group 2 (address 3Eh), input 1/group 1 (address 3Fh), input 0/group 0 (address 40h). In group switch mode, only addresses 3Eh, 3Fh, and 40h are used. Bit Default R/W Reserved, set to 11b 11b R/W 0: LOS Enabled 1: LOS Disabled 0b R/W Reserved, set to 00b 00b R/W 2 0: Normal operation 1: Force squelch on input channel 0b R/W 1 Reserved, set to 0b 0b R/W 0 0: Disable EI pass through mode 1: Enable EI pass through mode 0b R/W 7:6 5 4:3 Bit Description 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 41 Control Registers Map and Descriptions Register Address: 41h, 42h, 43h, 44h, 45h, 46h, 47h, 48h, 49h, 4Ah, 4Bh, 4Ch Register Name: Output configuration Description: Configures the output swing and de-emphasis for output 11 (address 41h), output 10 (address 42h), output 9 (address 43h), output 8 (address 44h), output 7 (address 45h), output 6 (output 46h), output 5 (address 47h), output 4 (address 48h), output 3 (address 49h), output 2/Group 2 (address 4Ah), output 1/Group 1 (address 4Bh), output 0/Group 0 (address 4Ch). In group switch mode, only addresses 4Ah, 4Bh, and 4Ch are used. Bit Default R/W 000b R/W Reserved, set to 0b 0b R/W 00: Output de-emphasis disabled 01: Approximately 2 dB output de-emphasis 10: Approximately 4 dB output de-emphasis 11: Approximately 6 dB output de-emphasis 00b R/W 1 0: Nominal de-emphasis time constant 1: Higher de-emphasis time constant 0b R/W 0 Reserved, set to 0b 0b R/W 7:5 4 3:2 Bit Description 00X: Power down 010: Minimum output swing 011: Nominal output swing : * 111: Maximum output swing 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 42 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 4Dh, 6Ch, 8Bh 00h PLL General Configuration Identifies the reference frequency and data type for the CDR to lock to for CDR Bank A, inputs 0-3 (address 4Dh), CDR Bank B, inputs 4-7 (address 6Ch), CDR Bank C, inputs 8-11 (address 8Bh) Bit Bit Description 7:6 Reserved 5:0 00h: SATA/SAS, 150 MHz Refclk 01h: Reserved 02h: SATA/SAS, 125 MHz Refclk 03h: Reserved 04h: SATA/SAS, 100 MHz Refclk 05h: Reserved 06h: Reserved 07h: Reserved 08h: FibreChannel, 212.5 MHz Refclk 09h: FibreChannel, 125 MHz Refclk 0Ah: FibreChannel, 106.25 MHz Refclk 0Bh: Reserved 0Ch: SONET (OC-96, OC-48, OC-24), 311.04 MHz Refclk 0Dh: SONET (OC-96, OC-48, OC-24), 155.52 MHz Refclk 0Eh: Reserved 0Fh: PCI-Express, 156.25 MHz Refclk 10h: Reserved 11h: PCI-Express, 125 MHz Refclk 12h: Reserved 13h: PCI-Express, 100 MHz Refclk 14h: Reserved 15h: Reserved 16h: Reserved 17h: XAUI, 250 MHz Refclk 18h: XAUI, 156.25 MHz Refclk 19h: XAUI, 125 MHz Refclk 1Ah: Reserved 1Bh: Gigabit Ethernet, 156.25 MHz Refclk 1Ch: Gigabit Ethernet, 125 MHz Refclk 1Dh: Gigabit Ethernet, 100 MHz Refclk 1Eh: Reserved 1Fh: Reserved 20h: SATA/SAS, 150 MHz Refclk 3Ch: SONET (OC-48, OC-12, OC-3), 311.04 MHz Refclk 3D'h: SONET (OC-48, OC-12, OC-3), 155.52 MHz Refclk 3E'h: Reserved Default R/W 00b R/W 00000b R/W Others: Complete manual configuration (see Chapter 5) 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 43 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 4Eh, 6Dh, 8Ch 00h PLL REFCLK Multiplier Identifies the reference clock multiplier to the PLL for CDR Bank A, inputs 0-3 (address 4Eh), CDR Bank B, inputs 4-7 (address 6Dh), CDR Bank C, inputs 8-11 (address 8Ch). See chapter 5 for a description of how to use this register. Bit 7 Bit Description Bank Power Down (ORed with bit 5 of register FAh) Default R/W 0b R/W 0000000b R/W 0: PLL and all 4 CDRs in bank powered on 1: PLL and all 4 CDRs in bank powered off 6:0 00h: Use automatic configuration selected via register 4Dh, 6Ch, or 8Bh 01h: Reference multiplier = 16 (The reference multiplier for data values of 01 through 10h is 16) : * 10h: Reference multiplier = 16 (The reference multiplier for data values of 01 through 10h is 16) 11h: Reference multiplier = 17 : * 7Fh: Reference Multiplier = 127 Register Address: Default: Register Name: Description: 4Fh, 6Eh, 8Dh 00h PLL Range Select Identifies the PLL frequency range for CDR Bank A, inputs 0-3 (address 4Fh), CDR Bank B, inputs 4-7 (address 6Eh), CDR Bank C, inputs 8-11 (address 8Dh). See chapter 5 for a description of how to use this register. Bit 7:2 Bit Description Reserved Default R/W 000000b R/W 1 0: Automatically select PLL tuning range based on settings in register 4Dh, 6Ch, or 8Bh 1: Use bit 1 to manually select PLL tuning range 0b R/W 0 0: PLL configured for 3.2-4.7 GHz operation when bit 1 is set to '1' 1: PLL configured for 4.7-6.25 GHz operation when bit 1 is set to '1' 0b R/W Register Address: Default: Register Name: Description: 50h, 6Fh, 8Eh 00h PLL Loop Bandwidth Sets the PLL Loop Bandwidth for CDR Bank A, inputs 0-3 (address 50h), CDR Bank B, inputs 4-7 (address 6Fh), CDR Bank C, inputs 8-11 (address 8Eh). See chapter 5 for a description of how to use this register. Bit 7:5 4 3:0 Bit Description Reserved 0: Automatically select PLL Loop Bandwidth based on settings in register 4Dh, 6Ch, or 8Bh 1: Use bits 3:0 to select PLL Loop Bandwidth 0h: Minimum PLL Loop Bandwidth : * Fh: Maximum PLL Loop Bandwidth 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential Default R/W 000b R/W 0b R/W 0000b R/W 44 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 52h, 55h, 58h, 5Bh, 71h, 74h, 77h, 7Ah, 90h, 93h, 96h, 99h 00h CDR General Configuration Power up/down for CDR for channel 0 (address 52h), channel 1 (address 55h), channel 2 (address 58h), channel 3(address 5Bh), channel 4 (address 71h), channel 5 (address 74h), channel 6 (address 77h), channel 7 (address 7Ah), channel 8 (address 90h), channel 9 (address 93h), channel 10 (address 96h), and channel 11 (address 99h) Bit Bit Description Default R/W 7:5 Reserved 000b R/W 4:3 00: CDR powered up and enabled 01: CDR fully powered down (no data passes through) 10: Unsupported mode 11: CDR bypassed 00b R/W 000b R/W NOTE: Bits [4:3] are ORed with bits [5:4] of register FAh. 2:0 Reserved Register Address: Default: Register Name: Description: 53h, 56h, 59h, 5Ch, 72h, 75h, 78h, 7Bh, 91h, 94h, 97h, 9Ah 00h Data Rate Select Configures prescale values for CDR for channel 0 (address 53h), channel 1 (address 56h), channel 2 (address 59h), channel 3(address 5Ch), channel 4 (address 72h), channel 5 (address 75h), channel 6 (address 78h), channel 7 (address 7Bh), channel 8 (address 91h), channel 9 (address 94h), channel 10 (address 97h), and channel 11 (address 9Ah). See chapter 5 for a description of how to use this register Bit 7:4 3 Bit Description Reserved 0: Enable Automatic Rate Detection (ARD): Prescale value automatically selected among available values, based on protocol register (4Dh, 6Ch, or 8Bh) Default R/W 0000b R/W 0b R/W 000b R/W 1: Disable Automatic Rate Detection (ARD): Prescale value manually selected using bits 2:0. 2:0 After a write operation, the value written to these bits will become the CDR prescale value. When read, these bits will identify the current prescale value selected by the ARD with the following decoding: 000: Prescale 1 (3.3 Gbps - 6.25 Gbps operation) 001: Prescale 2 (1.65 Gbps - 3.25 Gbps operation) 010: Prescale 4 (825 Mbps - 1.625 Gbps Operation) 011: Prescale 8 (412.5 Mbps - 812.5 Mbps Operation) 100: Prescale 16 (206.25 Mbps - 406.25 Mbps Operation) 101: Prescale 32 (103.125 Mbps - 203.125 Mbps Operation) 110, 111: Not Valid, do not use 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 45 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 54h, 57h, 5Ah, 5Dh, 73h, 76h, 79h, 7Ch, 92h, 95h, 98h, 9Bh 00h Loop Bandwidth/Peaking Sets CDR bandwidth/peaking for CDR for channel 0 (address 54h), channel 1 (address 57h), channel 2 (address 5Ah), channel 3(address 5Dh), channel 4 (address 73h), channel 5 (address 76h), channel 6 (address 79h), channel 7 (address 7Ch), channel 8 (address 92h), channel 9 (address 95h), channel 10 (address 98h), and channel 11 (address 9Bh). See Chapter 5 for a discussion of how to set this register Bit 7:4 Bit Description These bits are used to set the amount of peaking for the CDR Default R/W 0000b R/W 0000b R/W 0h: Use the default peaking selected with settings in register 6Ch or 8Dh 1h: Minimum peaking (SONET) : * 5h: Nominal data peaking : * Bh: Maximum peaking Ch: Disable second order loop : * Fh: Disable second order loop 3:0 These bits are used to control the CDR Loop Bandwidth 0h: Use the default Loop Bandwidth selected with settings in register 6Ch or 8Dh 1h: Nominal Loop Bandwidth 2h: 2X nominal LBW 3h: 8X nominal LBW 4h: 4X nominal LBW 5h: 6X nominal LBW 6h: 3X nominal LBW 7h: 1.75X nominal LBW 8h: 1.5X nominal LBW 9h: 1.25X nominal LBW Ah: 0.75X nominal LBW Bh: 0.5X nominal LBW Ch: 0.375X nominal LBW Dh: 0.25X nominal LBW Eh: 0.125X nominal LBW Fh: CDR Disabled 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 46 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 5Eh, 7Dh, 9Ch 00h PLL/CDR Status Current status of various Flags from the PLL and CDR for CDR Bank A, inputs 0-3 (address 5Eh), CDR Bank B, inputs 4-7 (address 7Dh), or CDR Bank C, inputs 8-11 (address 9Ch). Note: LOL alarm registers should not be used for data rates above 5.5 Gbps. Bit Default R/W Unused N/A R 5 1: PLL is not receiving a reference clock 0: PLL is receiving a reference clock N/A R 4 1: PLL is out of lock 0: PLL is in lock N/A R 3 1: CDR 3/7/11 is out of lock 0: CDR 3/7/11 is in lock N/A R 2 1: CDR 2/6/10 is out of lock 0: CDR 2/6/10 is in lock N/A R 1 1: CDR 1/5/9 is out of lock 0: CDR 1/5/9 is in lock N/A R 0 1: CDR 0/4/8 is out of lock 0: CDR 0/4/8 is in lock N/A R 7:6 Bit Description Register Address: Default: Register Name: Description: 5Fh, 7Eh, 9Dh 00h PLL/CDR Status Latch Latches the status of various Flags from the PLL and CDR for CDR Bank A, inputs 0-3 (address 9Dh), CDR Bank B, inputs 4-7 (address 7Eh), or CDR Bank C, inputs 8-11 (address 9Dh). When written, all latches are cleared. This latch responds to any assertion of the accompanying status flags (registers 7Dh and 9Ch). See Chapter 5 for a complete description. Note: LOL alarm registers should not be used for data rates above 5.5 Gbps. Bit Default R/W Unused N/A R 5 1: PLL reference clock has been lost since last write 0: PLL is receiving a reference clock N/A R 4 1: PLL has lost lock since last write 0: PLL is in lock N/A R 3 1: CDR 3/7/11 has lost lock since last write 0: CDR 3/7/11 is in lock N/A R 2 1: CDR 2/6/10 has lost lock since last write 0: CDR 2/6/10 is in lock N/A R 1 1: CDR 1/5/9 has lost lock since last write 0: CDR 1/5/9 is in lock N/A R 0 1: CDR 0/4/8 has lost lock since last write 0: CDR 0/4/8 is in lock N/A R 7:6 Bit Description 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 47 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 61h, 63h, 65h, 67h, 80h, 82h, 84h, 86h, 9Fh, A1h, A3h, A5h 00h PRBS Generator Controls PRBS Generation for input channel 0 (address 61h), channel 1 (address 63h), channel 2 (address 65h), channel 3 (address 67h), channel 4 (address 80h), channel 5 (address 82h), channel 6 (address 84h), channel 7 (address 86h), channel 8 (address 9Fh), channel 9 (address A1h), channel 10 (address A3h), and channel 11 (address A5h). Note that PRBS generation is done on the INPUT side of the cross-point switch Bit Default R/W Unused 00b R 5 Reserved 0b R/W 4 1: Enable PRBS Generation 0: Disable PRBS Generation 0b R/W 3 1: Invert the pattern in bits 2:0 0: Do not invert the pattern in bits 2:0 0b R/W 000b R/W 7:6 2:0 Bit Description Pattern Selection 000: 1010 clock pattern 001: 1100 clock pattern 010: 1111_0000 clock pattern 011: 1111_1111_0000_0000 clock pattern 100: PRBS7 pattern (X7 + X6 + 1) 101: PRBS15 pattern (X15 + X14 + 1) 110: PRBS23 pattern (X23 + X18 + 1) 111: PRBS31 pattern (X31 + X28 + 1) 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 48 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 62h, 64h, 66h, 68h, 81h, 83h, 85h, 87h, A0h, A2h, A4h, A6h 00h PRBS Detector Controls PRBS Detection and indicates current/latched error status for input channel 0 (address 62h), channel 1 (address 64h), channel 2 (address 66h), channel 3 (address 68h), channel 4 (address 81h), channel 5 (address 83h), channel 6 (address 85h), channel 7 (address 87h), channel 8 (address A0h), channel 9 (address A2h), channel 10 (address A4h), and channel 11 (address A6h) Bit Bit Description Default R/W 7 Unused 0b R/W 6 PRBS Error Latch 0b R 0b R When 1, a PRBS error has been observed since the last time this register was written. When 0, no PRBS error has been observed since the last time this register was written. This bit is cleared whenever this register is written to. 5 PRBS Error When 1, a PRBS error is currently being observed. When 0, no PRBS error is currently being observed. 4 1: Enable PRBS Detection 0: Disable PRBS Detection 0b R/W 3 1: Invert the pattern in bits 2:0 0: Do not invert the pattern in bits 2:0 0b R/W 000b R/W Note that inversion makes no difference on the clock patterns 2:0 Pattern Selection 000: 1010 clock pattern 001: 1100 clock pattern 010: 1111_0000 clock pattern 011: 1111_1111_0000_0000 clock pattern 100: PRBS7 pattern (X7 + X6 + 1) 101: PRBS15 pattern (X15 + X14 + 1) 110: PRBS23 pattern (X23 + X18 + 1) 111: PRBS31 pattern (X31 + X28 + 1) 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 49 Control Registers Map and Descriptions Register Address: C3h, C4h Register Name: LOS Alarm Status Description: Monitors the LOS alarm status for input channels. LOS alarms are latched into this register once asserted. This register is cleared by setting bit 4 of address 03h to "1" and then back to "0" Bit Bit Description Default R/W 7 0: Reserved (address C3h), No LOS on input 7 (address C4h) 1: Reserved (address C3h), LOS on input 7 (address C4h) N/A R 6 0: Reserved (address C3h), No LOS on input 6 (address C4h) 1: Reserved (address C3h), LOS on input 6 (address C4h) N/A R 5 0: Reserved (address C3h), No LOS on input 5 (address C4h) 1: Reserved (address C3h), LOS on input 5 (address C4h) N/A R 4 0: Reserved (address C3h), No LOS on input 4 (address C4h) 1: Reserved (address C3h), LOS on input 4 (address C4h) N/A R 3 0: No LOS on input 11 (address C3h), input 3 (address C4h) 1: LOS on input 11 (address C3h), input 3 (address C4h) N/A R 2 0: No LOS on input 10 (address C3h), input 2 (address C4h) 1: LOS on input 10 (address C3h), input 2 (address C4h) N/A R 1 0: No LOS on input 9 (address C3h), input 1 (address C4h) 1: LOS on input 9 (address C3h), input 1 (address C4h) N/A R 0 0: No LOS on input 8 (address C3h), input 0 (address C4h) 1: LOS on input 8 (address C3h), input 0 (address C4h) N/A R Default R/W Register Address: Default: Register Name: Description: FAh 04h Global CDR Control Controls status of all 3 banks of CDRs Bit Bit Description 7:6 Reserved 00b R/W 5:4 CDR Operational Mode 00b R/W 0100b R/W 00: CDRs Enabled 01: Unsupported mode 10: CDRs powered down (no output available) 11: CDRs bypassed 3:0 Reserved Register Address: FCh Register Name: MIC Checksum Description: After an EEPROM download, this register contains the checksum calculated value for registers 00h-4Ch. If this value is not equal to 2Eh after an MIC download, there was either an issue with the download or the checksum seed value in register 01h is not correct. Bit 7:0 Bit Description MIC Checksum Calculated Value Default R/W 00h R Default R/W 60h R Register Address: FDh Register Name: Chip Code Description: Contains the Chip ID code. Bit 7:0 Bit Description Device Identification Register 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential 50 Control Registers Map and Descriptions Register Address: FEh Register Name: Chip Revision Description: Contains the Chip revision number. Bit 7:0 Bit Description Device Revision Register M21463G-15 = 07h Default R/W --- R Register Address: FFh Register Name: Master Reset Description: Used to perform master reset of device. Write "AAh" to this register, followed by a second write of "00h" to perform a master reset. Bit 7:0 Bit Description 00h: Normal Operation AAh: Reset 21463-DSH-001-E Mindspeed Technologies(R) Mindspeed Proprietary and Confidential Default R/W 00h R/W 51 www.mindspeed.com General Information: Telephone: (949) 579-3000 Headquarters - Newport Beach 4000 MacArthur Blvd., East Tower Newport Beach, CA 92660 (c) 2011- 2012 Mindspeed Technologies(R), Inc. All rights reserved. Information in this document is provided in connection with Mindspeed Technologies(R) ("Mindspeed(R)") products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Except as provided in Mindspeed's Terms and Conditions of Sale for such products or in any separate agreement related to this document, Mindspeed assumes no liability whatsoever. Mindspeed assumes no responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. 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