NOTES:
tn = bit time before enable
negative-going transition
tn+1 = bit time after enable
negative-going transition
5-1
FAST AND LS TTL DATA
4-BIT D LATCH
The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem-
porary storage for binary information between processing units and input/out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW , the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH.
The SN54/74LS75 features complementary Q and Q output from a 4-bit
latch and is available in the 16-pin packages. For higher component density
applications the SN54/74LS77 4-bit latch is available in the 14-pin package
with Q outputs omitted.
14 13 12 11 10 9
1234567
16 15
8
CONNECTION DIAGRAMS DIP (TOP VIEW)
SN54/74LS75
14 13 12 11 10 9
123456
8
7
SN54/74LS77
Q0
Q0
Q1Q1E0–1 GND Q2
Q2Q3
D0D1E2–3 VCC D2D3Q3
Q0Q1E0–1 GND NC Q2Q3
D0D1E2–3 VCC D2D3NC
PIN NAMES LOADING (Note a)
HIGH LOW
D1–D4
E0–1
E2–3
Q1–Q4
Q1–Q4
Data Inputs
Enable Input Latches 0, 1
Enable Input Latches 2, 3
Latch Outputs (Note b)
Complimentary Latch Outputs (Note b)
0.5 U.L.
2.0 U.L.
2.0 U.L.
10 U.L.
10 U.L.
0.25 U.L.
1.0 U.L.
1.0 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 Unit Load (U.L.) = 40 µA HIGH.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
TRUTH TABLE
(Each latch)
tntn+1
D
H
L
Q
H
L
SN54/74LS75
SN54/74LS77
4-BIT D LATCH
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16 1
16
1
ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
16 1
D SUFFIX
SOIC
CASE 751B-03
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14 1
14
1
14 1
D SUFFIX
SOIC
CASE 751A-02
5-2
FAST AND LS TTL DATA
SN54/74LS75
LOGIC SYMBOLS
VCC = PIN 5
GND = PIN 12
2367
16 1 15 14 10 11 9 8
D0D1D2D3
13
4E0–1
E2–3Q0Q1Q2Q3
Q0Q1Q2Q3
SN54/74LS75
VCC = PIN 4
GND = PIN 11
NC = PIN 7, 10
1256
14 13 9 8
D0D1D2D3
12
3E0–1
E2–3
Q0Q3
Q1Q2
SN54/74LS77
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
V
IL
I
npu
t
LOW
V
o
lt
age 74 0.8
V
pg
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
V
OH
O
u
t
pu
t
HIGH
V
o
lt
age 74 2.7 3.5 V
CC ,OH ,IN IH
or VIL per T ruth Table
VOL
Output LOW Voltage
54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
O
u
t
pu
t
LOW
V
o
lt
age 74 0.35 0.5 V IOL = 8.0 mA
V
IN =
V
IL or
V
IH
per T ruth Table
IIH
Input HIGH Current
D Input
E Input 20
80 µA VCC = MAX, VIN = 2.7 V
I
IH
I
npu
t
HIGH
C
urren
t
D Input
E Input 0.1
0.4 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current D Input
E Input –0.4
–1.6 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 12 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
tPLH
tPHL Propagation Delay, Data to Q 15
9.0 27
17 ns
V50V
tPLH
tPHL Propagation Delay, Data to Q 12
7.0 20
15 ns VCC = 5.0 V
tPLH
tPHL Propagation Delay, Enable to Q 15
14 27
25 ns
CC
CL = 15 pF
tPLH
tPHL Propagation Delay, Enable to Q 16
7.0 30
15 ns
5-3
FAST AND LS TTL DATA
SN54/74LS77
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
V
IL
I
npu
t
LOW
V
o
lt
age 74 0.8
V
pg
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
V
OH
O
u
t
pu
t
HIGH
V
o
lt
age 74 2.7 3.5 V
CC ,OH ,IN IH
or VIL per T ruth Table
VOL
Output LOW Voltage
54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
O
u
t
pu
t
LOW
V
o
lt
age 74 0.35 0.5 V IOL = 8.0 mA
V
IN =
V
IL or
V
IH
per T ruth Table
IIH
Input HIGH Current
D Input
E Input 20
80 µA VCC = MAX, VIN = 2.7 V
I
IH
I
npu
t
HIGH
C
urren
t
D Input
E Input 0.1
0.4 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current D Input
E Input –0.4
–1.6 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 13 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
tPLH
tPHL Propagation Delay, Data to Q 11
9.0 19
17 ns VCC = 5.0 V
tPLH
tPHL Propagation Delay, Enable to Q 10
10 18
18 ns
CC
CL = 15 pF
5-4
FAST AND LS TTL DATA
SN54/74LS75
D
SN54/74LS77
LOGIC DIAGRAM
DATA
ENABLE
TO OTHER LATCH
Q (SN54/74LS75 ONLY)
Q
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V
TAOperating Ambient Temperature Range 54
74 –55
025
25 125
70 °C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 54
74 4.0
8.0 mA
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
tWEnable Pulse Width High 20 ns
V50V
tsSetup T ime 20 ns VCC = 5.0 V
thHold T ime 0 ns
AC WAVEFORMS
D
E
Q
Q
1.3 V 1.3 V
1.3 V 1.3 V 1.3 V
1.3 V 1.3 V
1.3 V1.3 V
th
ts
tPLH
tPLH tPHL tPHL
tPLH
tPHL
tPHL tPLH
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the
clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be
maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may
be released prior to the clock transition from HIGH-to-LOW and still be recognized.
