AT25SF321 32-Mbit, 2.5V Minimum SPI Serial Flash Memory with Dual-I/O and Quad-IO Support Features Single 2.5V - 3.6V Supply Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 and 3 Supports Dual and Quad Output Read 104MHz Maximum Operating Frequency Clock-to-Output (tV) of 6 ns Flexible, Optimized Erase Architecture for Code + Data Storage Applications Uniform 4-Kbyte Block Erase Uniform 32-Kbyte Block Erase Uniform 64-Kbyte Block Erase Full Chip Erase Hardware Controlled Locking of Protected Blocks via WP Pin 3 Protected Programmable Security Register Pages Flexible Programming Byte/Page Program (1 to 256 Bytes) Fast Program and Erase Times 0.7ms Typical Page Program (256 Bytes) Time 70ms Typical 4-Kbyte Block Erase Time 300ms Typical 32-Kbyte Block Erase Time 600ms Typical 64-Kbyte Block Erase Time JEDEC Standard Manufacturer and Device ID Read Methodology Low Power Dissipation 2A Deep Power-Down Current (Typical) 10A Standby current (Typical) 4mA Active Read Current (Typical) Endurance: 100,000 Program/Erase Cycles Data Retention: 20 Years Complies with Full Industrial Temperature Range Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options 8-lead SOIC (150-mil and 208-mil) 8-pad Ultra Thin DFN (5 x 6 x 0.6 mm) Die in Wafer Form DS-25SF321-047F-8/2017 Description The Adesto(R) AT25SF321 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25SF321 is ideal for data storage as well, eliminating the need for additional data storage devices. The erase block sizes of the AT25SF321 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. The device also contains three pages of Security Register that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. These Security Register pages can be individually locked. 1. Pin Descriptions and Pinouts Table 1-1. Symbol CS SCK Pin Descriptions Name and Function CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode (not Deep Power-Down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. Asserted State Type Low Input - Input - Input/Output SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched in on the rising edge of SCK. SI (I/O0) With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output pin (I/O0) in conjunction with other pins to allow two or four bits of data on (I/O3-0) to be clocked in on every falling edge of SCK To maintain consistency with the SPI nomenclature, the SI (I/O0) pin will be referenced as the SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it will be referenced as I/O0 Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted). AT25SF321 DS-25SF321-047F-8/2017 2 Table 1-1. Symbol Pin Descriptions (Continued) Name and Function Asserted State Type - Input/Output - Input/Output - Input/Output - Power - Power SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. SO (I/O1) With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked in on every falling edge of SCK To maintain consistency with the SPI nomenclature, the SO (I/O1) pin will be referenced as the SO pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O1 The SO pin will be in a high-impedance state whenever the device is deselected (CS is deasserted). WRITE PROTECT: The WP pin controls the hardware locking feature of the device. WP (I/O2) With the Quad-Input Byte/Page Program command, the WP pin becomes an input pin (I/O2) and, along with other pins, allows four bits (on I/O3-0) of data to be clocked in on every rising edge of SCK. With the Quad-Output Read commands, the WP Pin becomes an output pin (I/O2) in conjunction with other pins to allow four bits of data on (I/O33-0) to be clocked in on every falling edge of SCK. To maintain consistency with the SPI nomenclature, the WP (I/O2) pin will be referenced as the WP pin unless specifically addressing the Quad-I/O modes in which case it will be referenced as I/O2 The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to "Hold Function" on page 34 for additional details on the Hold operation. HOLD (I/O3) With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input pin (I/O3) and, along with other pins, allows four bits (on I/O3-0) of data to be clocked in on every rising edge of SCK. With the Quad-Output Read commands, the HOLD Pin becomes an output pin (I/O3) in conjunction with other pins to allow four bits of data on (I/O33-0) to be clocked in on every falling edge of SCK. To maintain consistency with the SPI nomenclature, the HOLD (I/O3) pin will be referenced as the HOLD pin unless specifically addressing the Quad-I/O modes in which case it will be referenced as I/O3 The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible. DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device. VCC GND Operations at invalid VCC voltages may produce spurious results and should not be attempted. GROUND: The ground reference for the power supply. GND should be connected to the system ground. AT25SF321 DS-25SF321-047F-8/2017 3 Figure 1-1. 8-SOIC (Top View) CS SO WP GND 2. 1 2 3 4 Figure 1-2. 8-UDFN (Top View) 8 7 6 5 CS SO WP GND VCC HOLD SCK SI 1 8 2 7 3 6 4 5 VCC HOLD SCK SI Block Diagram Figure 2-1. Block Diagram Control and Protection Logic CS I/O Buffers and Latches SRAM Data Buffer SI (I/O0) SO (I/O1) Interface Control And Logic WP (I/O2) Address Latch SCK Y-Decoder Y-Gating X-Decoder Flash Memory Array HOLD (I/O3) Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands. 3. Memory Array To provide the greatest flexibility, the memory array of the AT25SF321 can be erased in four levels of granularity including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the breakdown of each erase level. AT25SF321 DS-25SF321-047F-8/2017 4 Figure 3-1. Memory Architecture Diagram Block Erase Detail 64KB 32KB Page Program Detail 4KB 1-256 Byte Block Address Range 32KB 64KB Sector 62 *** *** 32KB 32KB 64KB Sector 0 32KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 00FFFFh-00F000h 00EFFFh-00E000h 00DFFFh-00D000h 00CFFFh-00C000h 00BFFFh-00B000h 00AFFFh-00A000h 009FFFh-009000h 008FFFh-008000h 007FFFh-007000h 006FFFh-006000h 005FFFh-005000h 004FFFh-004000h 003FFFh-003000h 002FFFh-002000h 001FFFh-001000h 000FFFh-000000h 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 3FFFFFh - 3FFF00h 3FFEFFh - 3FFE00h 3FFDFFh - 3FFD00h 3FFCFFh - 3FFC00h 3FFBFFh - 3FFB00h 3FFAFFh - 3FFA00h 3FF9FFh - 3FF900h 3FF8FFh - 3FF800h 3FF7FFh - 3FF700h 3FF6FFh - 3FF600h 3FF5FFh - 3FF500h 3FF4FFh - 3FF400h 3FF3FFh - 3FF300h 3FF2FFh - 3FF200h 3FF1FFh - 3FF100h 3FF0FFh - 3FF000h 3FEFFFh - 3FEF00h 3FEEFFh - 3FEE00h 3FEDFFh - 3FED00h 3FECFFh - 3FEC00h 3FEBFFh - 3FEB00h 3FEAFFh - 3FEA00h 3FE9FFh - 3FE900h 3FE8FFh - 3FE800h *** 32KB - 3FF000h - 3FE000h - 3FD000h - 3FC000h - 3FB000h - 3FA000h - 3F9000h - 3F8000h - 3F7000h - 3F6000h - 3F5000h - 3F4000h - 3F3000h - 3F2000h - 3F1000h - 3F0000h - 3EF000h - 3EE000h - 3ED000h - 3EC000h - 3EB000h - 3EA000h - 3E9000h - 3E8000h - 3E7000h - 3E6000h - 3E5000h - 3E4000h - 3E3000h - 3E2000h - 3E1000h - 3E0000h *** 64KB Sector 63 3FFFFFh 3FEFFFh 3FDFFFh 3FCFFFh 3FBFFFh 3FAFFFh 3F9FFFh 3F8FFFh 3F7FFFh 3F6FFFh 3F5FFFh 3F4FFFh 3F3FFFh 3F2FFFh 3F1FFFh 3F0FFFh 3EFFFFh 3EEFFFh 3EDFFFh 3ECFFFh 3EBFFFh 3EAFFFh 3E9FFFh 3E8FFFh 3E7FFFh 3E6FFFh 3E5FFFh 3E4FFFh 3E3FFFh 3E2FFFh 3E1FFFh 3E0FFFh *** 32KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB Page Address Range 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 0017FFh - 001700h 0016FFh - 001600h 0015FFh - 001500h 0014FFh - 001400h 0013FFh - 001300h 0013FFh - 001300h 0013FFh - 001300h 0012FFh - 001200h 0011FFh - 001100h 0010FFh - 001000h 000FFFh - 000F00h 000CFFh - 000C00h 000BFFh - 000B00h 000AFFh - 000A00h 0009FFh - 000900h 0008FFh - 000800h 0007FFh - 000700h 0006FFh - 000600h 0005FFh - 000500h 0004FFh - 000400h 0003FFh - 000300h 0002FFh - 000200h 0001FFh - 000100h 0000FFh - 000000h AT25SF321 DS-25SF321-047F-8/2017 5 4. Device Operation The AT25SF321 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25SF321 via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25SF321 supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. Figure 4-1. SPI Mode 0 and 3 CS SCK SI MSB SO 4.1 LSB MSB LSB Dual Output Read The AT25SF321 features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every clock cycle to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of data bytes. With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin. 4.2 Quad Output Read The AT25SF321 features a Quad-Output Read mode that allow four bits of data to be clocked out of the device every clock cycle to improve throughput. To accomplish this, the SI, SO, WP, HOLD pins are utilized as outputs for the transfer of data bytes. With the Quad-Output Read Array command, the SI, WP, HOLD pins become outputs along with the SO pin. 5. Commands and Addressing A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT25SF321 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation. Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0. Since the upper address limit of the AT25SF321 memory array is 3FFFFFh, address bits A23-A22 are always ignored by the device. AT25SF321 DS-25SF321-047F-8/2017 6 Table 5-1. Command Listing Command Opcode Clock Frequency Address Bytes Dummy Bytes Data Bytes Section Link Read Commands 0Bh 0000 1011 Up to 85 MHz 3 1 1+ 03h 0000 0011 Up to 50 MHz 3 0 1+ Dual Output Read 3Bh 0011 1011 Up to 85 MHz 3 1 1+ 6.2 Dual I/O Read BBh 1011 1011 Up to 85 MHz 3 0 1+ 6.3 Quad Output Read 6Bh 0110 1011 Up to 85 MHz 3 1 1+ 6.4 Quad I/O Read EBh 1110 1011 Up to 85 MHz 3 1 1+ 6.5 Continuous Read Mode Reset - Dual FFFFh 1111 1111 1111 1111 Up to 104 MHz 0 0 0 6.6 Continuous Read Mode Reset - Quad FFh 1111 1111 Up to 104 MHz 0 0 0 6.6 Block Erase (4 Kbytes) 20h 0010 0000 Up to 104 MHz 3 0 0 Block Erase (32 Kbytes) 52h 0101 0010 Up to 104 MHz 3 0 0 Block Erase (64 Kbytes) D8h 1101 1000 Up to 104MHz 3 0 0 60h 0110 0000 Up to 104 MHz 0 0 0 C7h 1100 0111 Up to 104 MHz 0 0 0 Byte/Page Program (1 to 256 Bytes) 02h 0000 0010 Up to 104 MHz 3 0 1+ 7.1 Program/Erase Suspend 75h 0111 0101 Up to 104 MHz 0 0 0 7.4 Program/Erase Resume 7Ah 0111 1010 Up to 104 MHz 0 0 0 7.5 Write Enable 06h 0000 0110 Up to 104 MHz 0 0 0 8.1 Write Disable 04h 0000 0100 Up to 104 MHz 0 0 0 8.2 Erase Security Register Page 44h 0100 0100 Up to 104 MHz 3 0 0 9.1 Program Security Register Page 42h 0100 0010 Up to 104 MHz 3 0 1+ 9.2 Read Security Register Page 48h 0100 1000 Up to 85MHz 3 1 1+ 9.3 Read Status Register Byte 1 05h 0000 0101 Up to 104 MHz 0 0 1 Read Status Register Byte 2 35h 0011 0101 Up to 104 MHz 0 0 1 Write Status Register 01h 0000 0001 Up to 104 MHz 0 0 1 or 2 10.2 Write Enable for Volatile Status Register 50h 0101 0000 Up to 104MHz 0 0 0 10.3 Read Array 6.1 Program and Erase Commands Chip Erase 7.2 7.3 Protection Commands Security Commands Status Register Commands AT25SF321 DS-25SF321-047F-8/2017 10.1 7 Table 5-1. Command Listing Command Opcode Clock Frequency Address Bytes Dummy Bytes Data Bytes Section Link Miscellaneous Commands Read Manufacturer and Device ID 9Fh 1001 1111 Up to 104MHz 0 0 3 11.1 Read ID 90h 1001 0000 Up to 104 MHz 0 3 2 11.2 Deep Power-Down B9h 1011 1001 Up to 104 MHz 0 0 0 11.3 Resume from Deep Power-Down ABh 1010 1011 Up to 104 MHz 0 0 0 11.4 Resume from Deep Power-Down and Read ID ABh 1010 1011 Up to 104 MHz 0 3 1 11.4 6. Read Commands 6.1 Read Array (0Bh and 03h) The Read Array command can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address is specified. The device incorporates an internal address counter that automatically increments every clock cycle. Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each opcode depends on the maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock frequency up to the maximum specified by fCLK, and the 03h opcode can be used for lower frequency read operations up to the maximum specified by fRDLF. To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. Following the three address bytes, an additional dummy byte needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation. After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in, additional clock cycles will result in data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array. Deasserting the CS pin will terminate the read operation and put the SO pin into high-impedance state. The CS pin can be deasserted at any time and does not require a full byte of data be read. Figure 6-1. Read Array - 03h Opcode &6 6&. 23&2'( 6, $''5(66%,76$$ 06% $ $ $ $ $ $ $ $ $ 06% '$7$%<7( 62 +,*+,03('$1&( ' 06% ' ' ' ' ' ' ' ' ' 06% AT25SF321 DS-25SF321-047F-8/2017 8 Figure 6-2. Read Array - 0Bh Opcode &6 6&. 23&2'( 6, $''5(66%,76$$ $ 06% $ $ $ $ $ $ 06% '21 7&$5( $ $ ; ; ; ; ; ; ; ; 06% '$7$%<7( +,*+,03('$1&( 62 ' ' ' ' ' ' ' 06% 6.2 ' ' ' 06% Dual-Output Read Array (3Bh) The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two bits of data to be clocked out of the device on every clock cycle, rather than just one. The Dual-Output Read Array command can be used at any clock frequency, up to the maximum specified by fRDDO. To perform the Dual-Output Read Array operation, the CS pin must first be asserted and then the opcode 3Bh must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must also be clocked into the device. After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being output on both the SO and SI pins. The data is always output with the MSB of a byte first and the MSB is always output on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same data byte is output on the SI pin. During the next clock cycle, bits five and four of the first data byte are output on the SO and SI pins, respectively. The sequence continues with each byte of data being output after every four clock cycles. When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading from the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.Deasserting the CS pin will terminate the read operation and put the SO and SI pins into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 6-3. Dual-Output Read Array CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SCK 23&2'( 6, 6,2 0 0 1 1 1 0 1 1 A A A A A A MSB SO $''5(66%,76$$ HI GHI MPEDANCE MSB DON' T &$5( OUTPUT DAT $%<7( OUTPUT DAT $%<7( A A A X X X X X X X X D6 D4 D2 D0 D6 D4 D2 D0 D6 D4 MSB D7 D5 D3 D1 D7 D5 D3 D1 D7 D5 MSB MSB MSB AT25SF321 DS-25SF321-047F-8/2017 9 6.3 Dual-I/O Read Array (BBh) The Dual-I/O Read Array command is similar to the Dual-Output Read Array command and can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address with two bits of address on each clock and two bits of data on every clock cycle. The Dual-I/O Read Array command can be used at any clock frequency, up to the maximum specified by fRDDO. To perform the Dual-I/O Read Array operation, the CS pin must first be asserted and then the opcode BBh must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte to read within the memory array. Following the three address bytes, a single mode byte must also be clocked into the device. After the three address bytes and the mode byte have been clocked in, additional clock cycles will result in data being output on both the SO and SI pins. The data is always output with the MSB of a byte first and the MSB is always output on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same data byte is output on the SI pin. During the next clock cycle, bits five and four of the first data byte are output on the SO and SI pins, respectively. The sequence continues with each byte of data being output after every four clock cycles. When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading from the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.Deasserting the CS pin will terminate the read operation and put the SO and SI pins into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 6-4. Dual I/O Read Array (Initial command or previous M5, M41,0) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 19 20 21 22 23 24 25 26 27 SCK Address Bits A23-A16 Opcode I/O0 (SI) 6.3.1 1 0 MSB 1 1 1 0 1 Address Bits A15-A8 A7-A0 1 A22 A20 A18 A16 A14 A M7-M0 Byte 1 Byte 2 A0 M6 M4 M2 M0 D6 D4 D2 D0 D6 MSB I/O1 A23 A21 A19 A17 A15 A (SO) MSB A 1 M 7 M 5 M 3 M1 D 7 D 5 D 3 D 1 D 7 Dual-I/O Read Array (BBh) with Continuous Read Mode The Fast Read Dual I/O command can further reduce instruction overhead through setting the Continuous Read Mode bits (M7-0) after the input Address bits (A23-0), as shown in Figure 6-5. The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O command through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don't care ("x"). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the "Continuous Read Mode" bits M5-4 = (1,0), then the next Fast Read Dual I/O command (after CS is raised and then lowered) does not require the BBH instruction code, as shown in Figure 15. This reduces the command sequence by eight clocks and allows the Read address to be immediately entered after CS is asserted low. If the "Continuous Read Mode" bits M5-4 do not equal to (1,0), the next command (after CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A Continuous Read Mode Reset command can also be used to reset (M7-0) before issuing normal commands. AT25SF321 DS-25SF321-047F-8/2017 10 Figure 6-5. Dual-I/O Read Array (Previous command set M5, M4 = 1,0) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SCK Address Bits A23-A16 I/O0 (SI) 6.4 A15-A8 A22 A20 A18 A16 A14 A Address Bits A7-A0 M7-M0 Byte 1 Byte 2 A 0 M 6 M4 M 2 M0 D 6 D 4 D 2 D 0 D 6 MSB I/O1 A23 A21 A19 A17 A15 A (SO) MSB A 1 M 7 M5 M3 M1 D 7 D 5 D 3 D 1 D 7 Quad-Output Read Array (6Bh) The Quad-Output Read Array command is similar to the Dual-Output Read Array command. The Quad-Output Read Array command allows four bits of data to be clocked out of the device on every clock cycle, rather than just one or two. The Quad Enable bit (QE) of the Status Register must be set to enable for the Quad-Output Read Array instruction. The Quad-Output Read Array command can be used at any clock frequency, up to the maximum specified by fRDQO. To perform the Quad-Output Read Array operation, the CS pin must first be asserted and then the opcode 6Bh must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must also be clocked into the device. After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being output on the I/O3-0 pins. The data is always output with the MSB of a byte first and the MSB is always output on the I/O3 pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O3 pin while bits 6, 5, and 4 of the same data byte will be output on the I/O2, I/O1, and I/O0 pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the first data byte will be output on the I/O3, I/O2, I/O1 and I/O0 pins, respectively. The sequence continues with each byte of data being output after every two clock cycles. When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading from the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.Deasserting the CS pin will terminate the read operation and put the WP, HOLD, SO, SI pins into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. AT25SF321 DS-25SF321-047F-8/2017 11 Figure 6-6. Quad-Output Read Array CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SCK Opcode I/O0 (SI) I/O1 0 1 1 0 1 Address Bits A23-A0 0 1 06% High-impedance 1 A 06% A A A A A A Byte 1 OUT Don't Care A A X X X X X X X X Byte 2 OUT Byte 3 OUT Byte 4 OUT Byte 5 OUT D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 06% D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 (SO) I/O2 High-impedance D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 (WP) I/O3 High-impedance (HOLD) 6.5 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 MSB MSB MSB MSB MSB Quad-I/O Read Array(EBh) The Quad-I/O Read Array command is similar to the Quad-Output Read Array command. The Quad-I/O Read Array command allows four bits of address to be clocked into the device on every clock cycle, rather than just one. The Quad-I/O Read Array command can be used at any clock frequency, up to the maximum specified by fRDQO. To perform the Quad-I/O Read Array operation, the CS pin must first be asserted and then the opcode EBh must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte to read within the memory array. Following the three address bytes, a single mode byte must also be clocked into the device. After the three address bytes, the mode byte and two dummy bytes have been clocked in, additional clock cycles will result in data being output on the I/O3-0 pins. The data is always output with the MSB of a byte first and the MSB is always output on the I/O3 pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O3 pin while bits 6, 5, and 4 of the same data byte will be output on the I/O2, I/O1 and I/O0 pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the first data byte will be output on the I/O3, I/O2, I/O1 and I/O0 pins, respectively. The sequence continues with each byte of data being output after every two clock cycles. When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading from the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.Deasserting the CS pin will terminate the read operation and put the I/O3, I/O2, I/O1 and I/O0 pins into a highimpedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.The Quad Enable bit (QE) of the Status Register must be set to enable for the Quad-I/O Read Array instruction. AT25SF321 DS-25SF321-047F-8/2017 12 Figure 6-7. Quad-I/O Read Array (Initial command or previous M5, M4 1,0) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Opcode I/O0 A23-A16 A15-A8 A7-A0 M7-M0 Dummy Byte 1 Byte 2 1 A20 A16 A12 A8 A4 A0 M4 M0 D4 D0 D4 D0 I/O1 A21 A17 A13 A9 A5 A1 M5 M1 D5 D1 D5 D1 I/O2 A22 A18 A14 A10 A6 A2 M6 M2 D6 D2 D6 D2 A23 A19 A15 A11 A7 A3 M7 M3 D7 D3 D7 D3 1 (SI) 1 1 0 1 0 1 MSB (SO) (WP) I/O3 (HOLD) 6.5.1 Quad-I/O Read Array (EBh) with Continuous Read Mode The Fast Read Quad I/O command can further reduce instruction overhead through setting the Continuous Read Mode bits (M7-0) after the input Address bits (A23-0), as shown in Figure 6-6. The upper nibble (M7-4) of the Continuous Read Mode bits controls the length of the next Fast Read Quad I/O command through the inclusion or exclusion of the first byte instruction code. The lower nibble bits (M3-0) of the Continuous Read Mode bits are don't care. However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the Continuous Read Mode bits M5-4 = (1,0), then the next Quad-I/O Read Array command (after CS is raised and then lowered) does not require the EBh instruction code, as shown in Fig 6-8. This reduces the command sequence by eight clocks and allows the Read address to be immediately entered after CS is asserted low. If the "Continuous Read Mode" bits M5-4 do not equal to (1,0), the next command (after CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A Continuous Read Mode Reset command can also be used to reset (M7-0) before issuing normal commands. Figure 6-8. Quad I/O Read Array with Continuous Read Mode (Previous Command Set M5-4 =1,0) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK A23-A16 A15-A8 I/O0 A7-A0 M7-M0 Dummy Byte 1 Byte 2 A20 A16 A12 A8 A4 A0 M4 M0 D4 D0 D4 D0 I/O1 A21 A17 A13 A9 A5 A1 M5 M1 D5 D1 D5 D1 I/O2 A22 A18 A14 A10 A6 A2 M6 M2 D6 D2 D6 D2 A23 A19 A15 A11 A7 A3 M7 M3 D7 D3 D7 D3 (SI) (SO) (WP) I/O3 (HOLD) 6.6 Continuous Read Mode Reset (FFh or FFFFh) The Continuous Read Mode bits are used in conjunction with the Dual I/O Read Array and the Quad I/O Read Array commands to provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus allowing more efficient XIP (execute in place) with this device family. AT25SF321 DS-25SF321-047F-8/2017 13 The "Continuous Read Mode" bits M7-0 are set by the Dual/Quad I/O Read Array commands. M5-4 are used to control whether the 8-bit SPI instruction code (BBh or EBh) is needed or not for the next instruction. When M5-4 = (1,0), the next instruction will be treated the same as the current Dual/Quad I/O Read Array command without needing the 8-bit instruction code. When M5-4 do not equal (1,0), the device returns to normal SPI instruction mode, in which all instructions can be accepted. M7-6 and M3-0 are reserved bits for future use; either 0 or 1 values can be used. See Figure 6-9, the Continuous Read Mode Reset instruction (FFh or FFFFh) can be used to set M4 = 1, thus the device will release the Continuous Read Mode and return to normal SPI operation. To reset Continuous Read Mode during Quad I/O operation, only eight clocks are needed to shift in instruction FFh. To reset Continuous Read Mode during Dual I/O operation, sixteen clocks are needed to shift in instruction FFFFh. Figure 6-9. Continuous Read Mode Reset (Quad) jz W X Y Z [ \ ] ^ zjr vwjvkl zp 1 1 1 1 1 1 1 1 9 10 11 12 13 14 15 tzi DON'T CARE zv Figure 6-10. Continuous Read Mode Reset (Dual) jz W X Y Z [ \ ] ^ 8 zjr vwjvkl zp 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MSB zv 7. Program and Erase Commands 7.1 Byte/Page Program (02h) DON'T CARE The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into previously erased memory locations. An erased memory location is one that has all eight bits set to the logical "1" state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write Enable command must have been previously issued to the device (see "Write Enable (06h)" on page 20) to set the Write Enable Latch (WEL) bit of the Status Register to a logical "1" state. To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer. If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this situation, any data AT25SF321 DS-25SF321-047F-8/2017 14 that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer. When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate memory array locations based on the starting address specified by A23-A0 and the number of data bytes sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and should take place in a time of tPP or tBP if only programming a single byte. The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. In addition, if the memory is in the protected state (see "Non-Volatile Protection" on page 21), then the Byte/Page Program command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical "0" state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or because the memory location to be programmed is protected. While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to determine if the data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status Register will be reset back to the logical "0" state. Figure 7-1. Byte Program &6 6&. 23&2'( 6, $''5(66%,76$$ 06% $ $ $ $ $ $ $ '$7$,1 $ $ 06% ' ' ' ' ' ' ' ' 06% +,*+,03('$1&( 62 Figure 7-2. Page Program &6 6&. 23&2'( 6, $''5(66%,76$$ 06% 62 $ 06% $ $ $ $ $ '$7$,1%<7( ' 06% ' ' ' ' ' ' '$7$,1%<7(Q ' ' ' ' ' ' ' ' ' 06% +,*+,03('$1&( AT25SF321 DS-25SF321-047F-8/2017 15 7.2 Block Erase (20h, 52h, or D8h) A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical "1" state) in a single operation by using one of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, or D8h is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical "1" state. To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the 4- or 32- or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally selftimed and should take place in a time of tBLKE. Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values can be either a logical "1" or "0". For a 32-Kbyte erase, address bits A14-A0 will be ignored by the device. For a 64-Kbyte erase, address bits A15-A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. If the memory is in the protected state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical "0" state if the erase cycle aborts due to an incomplete address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the region to be erased is protected. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBLKE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical "0" state. Figure 7-3. Block Erase &6 6&. 23&2'( 6, & & & & & & 06% 62 7.3 $''5(66%,76$$ & & $ $ $ $ $ $ $ $ $ $ $ $ 06% +,*+,03('$1&( Chip Erase (60h or C7h) The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical "1" state. Two opcodes (60h and C7h) can be used for the Chip Erase command. There is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two opcodes must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into AT25SF321 DS-25SF321-047F-8/2017 16 the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the device will erase the entire memory array. The erasing of the device is internally self-timed and should take place in a time of tCHPE. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if the memory array is in the protected state, then the Chip Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical "0" state if the CS pin is deasserted on uneven byte boundaries or if the memory is in the protected state. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tCHPE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical "0" state. Figure 7-4. Chip Erase &6 6&. 23&2'( 6, & & & & & & & & 06% 62 7.4 +,*+,03('$1&( Program/Erase Suspend (75h) In some code plus data storage applications, it is often necessary to process certain high-level system interrupts that require relatively immediate reading of code or data from the Flash memory. In such an instance, it may not be possible for the system to wait the microseconds or milliseconds required for the Flash memory to complete a program or erase cycle. The Program/Erase Suspend command allows a program or erase operation in progress to be suspended so that other device operations can be performed. For example, by suspending an erase operation to a particular block, the system can perform functions such as a program or read to a different block. Chip Erase cannot be suspended. The Program/Erase Suspend command will be ignored if it is issued during a Chip Erase.A program operation can be performed while an erase operation is suspended, but the program operation cannot be suspended while an erase operation is currently suspended. Other device operations, such as a Read Status Register, can also be performed while a program or erase operation is suspended. Table 7-4 outlines the operations that are allowed and not allowed during a program or erase suspend. Since the need to suspend a program or erase operation is immediate, the Write Enable command does not need to be issued prior to the Program/Erase Suspend command being issued. Therefore, the Program/Erase Suspend command operates independently of the state of the WEL bit in the Status Register. To perform a Program/Erase Suspend, the CS pin must first be asserted and the opcode of 75h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the program or erase operation currently in progress will be suspended within a time of tSUSE. The Suspend (SUS) bit in the Write Status Register will be set to the logical "1" state to indicate that the program or erase operation has been suspended. In addition, the RDY/BSY bit in the Status Register will indicate that the device is ready for another operation. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on a byte boundary (multiples of eight bits). Otherwise, no suspend operation will be performed. If a read operation is attempted to a suspended area (page for programming or block for erasing), then the device will output undefined data. Therefore, when performing a Read Array operation to an unsuspended area and the device's AT25SF321 DS-25SF321-047F-8/2017 17 internal address counter increments and crosses into the suspended area, the device will then start outputting undefined data until the internal address counter crosses to an unsuspended area. A program operation is not allowed to a block that has been erase suspended. If a program operation is attempted to an erase suspended block, then the program operation will abort and the WEL bit in the Status Register will be reset back to a logical "0" state. Likewise, an erase operation is not allowed to a block that included the page that has been program suspended. If attempted, the erase operation will abort and the WEL bit in the Status Register will be reset to a logical "0" state. If an attempt is made to perform an operation that is not allowed during a program or erase suspend, such as a Write Status Register operation, then the device will simply ignore the opcode and no operation will be performed. The state of the WEL bit in the Status Register will not be affected. Table 7-1. Operations Allowed and Not Allowed During a Program/Erase Suspend Command Command Read Commands Read Array (03h, 0Bh, 3Bh, BBh, 6Bh, EBh) Continuous Read Reset (FFh) Program and Erase Commands Block Erase (20h, 52h, D8h) Chip Erase (C7h, 60h) Byte/Page Program (02h) Program/Erase Suspend (75h) Program/Erase Resume (7Ah) Protection Commands Write Enable (06h) Write Disable (04h) Security Commands Erase Security Register Page (44h) Program Security Register Page (42h) Read Security Register Page (48h) Status Register Commands Read Status Register (05h, 35h) Write Status Register (01h) Volatile Write Enable Status Register (50h) Miscellaneous Commands Read Manufacturer and Device ID (9Fh) Read ID (90h) Deep Power-Down (B9h) Resume from Deep Power-Down (ABh) During Program Suspend During Erase Suspend Allowed (1) Allowed(1) Allowed(1) Allowed(1) Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed Allowed(1) Not Allowed Not Allowed Allowed Allowed Allowed Allowed Allowed Allowed Not Allowed Not Allowed Not Allowed Not Allowed Allowed Allowed Allowed Allowed Not Allowed Not Allowed Not Allowed Not Allowed Allowed Allowed Allowed Allowed Not Allowed Allowed 1. Allowed for all 64K-byte blocks other than the one currently suspended. 2. Allowed for reading Device ID. (2) Not Allowed Allowed(2) AT25SF321 DS-25SF321-047F-8/2017 18 Figure 7-5. Program/Erase Suspend CS 0 1 2 3 4 5 6 7 SCK OPCODE SI 0 1 1 1 0 1 0 1 MSB SO 7.5 HI GHI MPEDANCE Program/Erase Resume (7Ah) The Program/Erase Resume command allows a suspended program or erase operation to be resumed and continue programming a Flash page or erasing a Flash memory block where it left off. The Program/Erase Resume instruction will be accepted by the device only if the SUS bit in the Write Status Register equals 1 and the RDY/BSY bit equals 0. If the SUS bit equals 0 or the RDY/BSY bit equals to 1, the Program/Erase Resume command will be ignored by the device. As with the Program/Erase Suspend command, the Write Enable command does not need to be issued prior to the Program/Erase Resume command being issued. Therefore, the Program/Erase Resume command operates independently of the state of the WEL bit in the Status Register. To perform Program/Erase Resume, the CS pin must first be asserted and opcode 7Ah must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the program or erase operation currently suspended will resume within a time of tRES. The SUS bit in the Status Register will then be reset back to the logical "0" state to indicate the program or erase operation is no longer suspended. In addition, the RDY/BSY bit in the Status Register will indicate that the device is busy performing a program or erase operation. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on a byte boundary (multiples of eight bits). Otherwise, no resume operation will perform. During a simultaneous Erase Suspend/Program Suspend condition, issuing the Program/Erase Resume command will result in the program operation resuming first. After the program operation has been completed, the Program/Erase Resume command must be issued again in order for the erase operation to be resumed. While the device is busy resuming a program or erase operation, any attempts at issuing the Program/Erase Suspend command will be ignored. Therefore, if a resumed program or erase operation needs to be subsequently suspended again, the system must either wait the entire tRES time before issuing the Program/Erase Suspend command, or it must check the status of the RDY/BSY bit or the SUS bit in the Status Register to determine if the previously suspended program or erase operation has resumed. Figure 7-6. Program/Erase Resume. 0 1 2 3 4 5 6 7 SCK OPCODE SI 0 1 1 1 1 0 1 0 MSB SO HI GHI MPEDANCE AT25SF321 DS-25SF321-047F-8/2017 19 8. Protection Commands and Features 8.1 Write Enable (06h) The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical "1" state. The WEL bit must be set before a Byte/Page Program, Erase, Program Security Register Pages, Erase Security Register Pages or Write Status Register command can be executed. This makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to the issuance of one of these commands, then the command will not be executed. To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical "1". The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the WEL bit state will not change. Figure 8-1. Write Enable &6 6&. 23&2'( 6, 06% 62 8.2 +,*+,03('$1&( Write Disable (04h) The Write Disable command is us0d to reset the Write Enable Latch (WEL) bit in the Status Register to the logical "0" state. With the WEL bit reset, all Byte/Page Program, Erase, Program Security Register Page, and Write Status Register commands will not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to the WEL bit section of the Status Register description. To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical "0". The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the WEL bit state will not change. Figure 8-2. Write Disable &6 6&. 23&2'( 6, 06% 62 +,*+,03('$1&( AT25SF321 DS-25SF321-047F-8/2017 20 8.3 Non-Volatile Protection The device can be software protected against erroneous or malicious program or erase operations by utilizing the NonVolatile Protection feature of the device. Non-Volatile Protection can be enabled or disabled by using the Write Status Register command to change the value of the Protection (CMP, SEC, TB, BP2, BP1, BP0) bits in the Status Register. The following table outlines the states of the Protection bits and the associated protection area . Table 8-1. Memory Array with CMP=0 Protection Bits Memory Content SEC TB BP2 BP1 BP0 Address Range Portion X X 0 0 0 None None 0 0 0 0 1 3F0000h-3FFFFFh Upper 1/64 0 0 0 1 0 3E0000h-3FFFFFh Upper 1/32 0 0 0 1 1 3C0000h-3FFFFFh Upper 1/16 0 0 1 0 0 380000h-3FFFFFh Upper 1/8 0 0 1 0 1 300000h-3FFFFFh Upper 1/4 0 0 1 1 0 200000h-3FFFFFh Upper 1/2 0 1 0 0 1 000000h-00FFFFh Lower 1/64 0 1 0 1 0 000000h-01FFFFh Lower 1/32 0 1 0 1 1 000000h-03FFFFh Lower 1/16 0 1 1 0 0 000000h-07FFFFh Lower 1/8 0 1 1 0 1 000000h-0FFFFFh Lower 1/4 0 1 1 1 0 000000h-1FFFFFh Lower 1/2 X X 1 1 1 000000h-3FFFFFh ALL 1 0 0 0 1 3FF000h-3FFFFFh Upper 1/512 1 0 0 1 0 3FE000h-3FFFFFh Upper 1/256 1 0 0 1 1 3FC000h-3FFFFFh Upper 1/128 1 0 1 0 X 3F8000h-3FFFFFh Upper 1/64 1 0 1 1 0 3F8000h-3FFFFFh Upper 1/64 1 1 0 0 1 000000h-000FFFh Lower 1/512 1 1 0 1 0 000000h-001FFFh Lower 1/256 1 1 0 1 1 000000h-003FFFh Lower 1/128 1 1 1 0 X 000000h-007FFFh Lower 1/64 1 1 1 1 0 000000h-007FFFh Lower 1/64 AT25SF321 DS-25SF321-047F-8/2017 21 Table 8-2. Memory Array Protection with CMP=1 Protection Bits Memory Content SEC TB BP2 BP1 BP0 Address Range Portion X X 0 0 0 000000h-3FFFFFh All 0 0 0 0 1 000000h-3EFFFFh Lower 63/64 0 0 0 1 0 000000h-3DFFFFh Lower 31/32 0 0 0 1 1 000000h-3BFFFFh Lower 15/16 0 0 1 0 0 000000h-37FFFFh Lower 7/8 0 0 1 0 1 000000h-2FFFFFh Lower 3/4 0 0 1 1 0 000000h-1FFFFFh Lower 1/2 0 1 0 0 1 010000h-3FFFFFh Upper 63/64 0 1 0 1 0 020000h-3FFFFFh Upper 31/32 0 1 0 1 1 040000h-3FFFFFh Upper 15/16 0 1 1 0 0 080000h-3FFFFFh Upper 7/8 0 1 1 0 1 100000h-3FFFFFh Upper 3/4 0 1 1 1 0 200000h-3FFFFFh Upper 1/2 X X 1 1 1 NONE NONE 1 0 0 0 1 000000h-3FEFFFh Lower 1023/1024 1 0 0 1 0 000000h-3FDFFFh Lower 511/512 1 0 0 1 1 000000h-3FBFFFh Lower 255/256 1 0 1 0 X 000000h-3F7FFFh Lower 127/128 1 0 1 1 0 000000h-3F7FFFh Lower 127/128 1 1 0 0 1 001000h-3FFFFFh Upper 1023/1024 1 1 0 1 0 002000h-3FFFFFh Upper 511/512 1 1 0 1 1 004000h-3FFFFFh Upper 255/256 1 1 1 0 X 008000h-3FFFFFh Upper 127/128 1 1 1 1 0 008000h-3FFFFFh Upper 127/128 As a safeguard against accidental or erroneous protecting or unprotecting of the memory array, the Protection can be locked from updates by using the WP pin (see "Protected States and the Write Protect Pin" on page 22 for more details). 8.4 Protected States and the Write Protect Pin The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array. Instead, the WP pin, is used to control the hardware locking mechanism of the device. If the WP pin is permanently connected to GND, then the protection bits cannot be changed. AT25SF321 DS-25SF321-047F-8/2017 22 9. Security Register Commands The device contains three extra pages called Security Registers that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. The Security Registers are independent of the main Flash memory. Each page of the Security Register can be erased and programmed independently. Each page can also be independently locked to prevent further changes. 9.1 Erase Security Registers (44h) Before an erase Security Register Page command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical "1" state. To perform an Erase Security Register Page command, the CS pin must first be asserted and the opcode 44h must be clocked into the device. After the opcode has been clocked in, the three address bytes specifying the Security Register Page to be erased must be clocked in. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally self-timed and should take place in a time of tBE. Since the Erase Security Register Page command erases a region of bytes, the lower order address bits do not need to be decoded by the device. Therefore address bits A7-A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted right after the last address bit (A0); otherwise, the device will abort the operation and no erase operation will be performed. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBE time to determine if the device has finished erasing. At some point before the erase cycle completes, the RDY/BSY bit in the Status Register will be reset back to the logical "0" state. The WEL bit in the Status Register will be reset back to the logical "0" state if the erase cycle aborts due to an incomplete address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the region to be erased is protected. The Security Registers Lock Bits (LB3-LB1) in the Status Register can be used to OTP protect the security registers. Once a Lock Bit is set to 1, the corresponding Security Register will be permanently locked. The Erase Security Register Page instruction will be ignored for Security Registers which have their Lock Bit set. Table 9-1. Security Register Addresses for Erase Security Register Page Command Address A23-A16 A15-A8 A7-A0 Security Register 1 00H 01H Don't Care Security Register 2 00H 02H Don't Care Security Register 3 00H 03H Don't Care Figure 9-1. Erase Security Register Page &6 0 1 2 3 4 5 6 7 6&. OPCODE 6, %,7$''5(66 $ $ $ $ $ MSB AT25SF321 DS-25SF321-047F-8/2017 23 9.2 Program Security Registers (42h) The Program Security Registers command utilizes the internal 256-byte buffer for processing. Therefore, the contents of the buffer will be altered from its previous state when this command is issued. The Security Registers can be programmed in a similar fashion to the Program Array operation up to the maximum clock frequency specified by fCLK. Before a Program Security Registers command can be started, the Write Enable command must have been previously issued to the device (see "Write Enable (06h)" on page 20) to set the Write Enable Latch (WEL) bit of the Status Register to a logical "1" state. To program the Security Registers, the CS pin must first be asserted and the opcode of 42h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to program within the Security Register. Table 9-2. Security Register Addresses for Program Security Registers Command Address A23-A16 A15-A8 A7-A0 Security Register 1 00H 01H Byte Address Security Register 2 00H 02H Byte Address Security Register 3 00H 03H Byte Address Figure 9-2. Program Security Registers &6 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39 6&. OPCODE 6, 0 0 1 MSB 62 9.3 ADDRESS BI TS A23A0 A A A MSB DATAI NBYTE1 A A A D D D D D D D D MSB DATAI NBYTEn D D D D D D D D MSB HI GHI MPEDANCE Read Security Registers (48h) The Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum clock frequency specified by fCLK. To read the Security Register, the CS pin must first be asserted and the opcode of 48h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the Security Register. Following the three address bytes, one dummy byte must be clocked into the device before data can be output. After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in Security Register data being output on the SO pin. When the last byte (0003FFh) of the Security Register has been read, the device will continue reading back at the beginning of the register (000000h). No delays will be incurred when wrapping around from the end of the register to the beginning of the register. AT25SF321 DS-25SF321-047F-8/2017 24 Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 9-3. Security Register Addresses for Read Security Registers Command Address A23-A16 A15-A8 A7-A0 Security Register 1 00H 01H Byte Address Security Register 2 00H 02H Byte Address Security Register 3 00H 03H Byte Address Figure 9-3. Read Security Registers &6 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 6&. OPCODE 6, 0 1 MSB ADDRESS BI TS A23A0 A A A A A A MSB DON' TCARE A A A X X X X X X X X X MSB DATABYTE1 62 HI GHI MPEDANCE D D D D D D D D D D MSB 10. Status Register Commands 10.1 Read Status Register (05h and 35h) MSB The Status Register can be read to determine the device's ready/busy status, as well as the status of many other functions such as Block Protection. The Status Register can be read at any time, including during an internally self-timed program or erase operation. To read Status Register Byte 1, the CS pin must first be asserted and the opcode of 05h must be clocked into the device. After the opcode has been clocked in, the device will begin outputting Status Register Byte 1 data on the SO pin during every subsequent clock cycle. After the last bit (bit 0) of Status Register Byte 1 has been clocked out, the sequence will repeat itself starting again with bit 7 as long as the CS pin remains asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated, so each repeating sequence will output new data. Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. To read Status Register Byte 2, the CS pin must first be asserted and the opcode of 35h must be clocked into the device. After the opcode has been clocked in, the device will begin outputting Status Register Byte 2 data on the SO pin during every subsequent clock cycle. After the last bit (bit 0) of Status Register Byte 2 has been clocked out, the sequence will repeat itself starting again with bit 7 as long as the CS pin remains asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated, so each repeating sequence will output new data. Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. AT25SF321 DS-25SF321-047F-8/2017 25 Table 10-1. Status Register Format - Byte 1 Bit(1) Name Type(2) Description 7 SRP0 Status Register Protection bit-0 R/W See Table 10-3 on Status Register Protection 6 SEC Block Protection R/W See Table 8-1 and 8-2 on Non-Volatile Protection 5 TB Top or Bottom Protection R/W See Table 8-1 and 8-2 on Non-Volatile Protection 4 BP2 Block Protection bit-2 R/W See Table 8-1 and 8-2 on Non-Volatile Protection 3 BP1 Block Protection bit-1 R/W See Table 8-1 and 8-2 on Non-Volatile Protection 2 BP0 Block Protection bit-0 R/W See Table 8-1 and 8-2 on Non-Volatile Protection 1 WEL Write Enable Latch Status R 0 RDY/BSY Ready/Busy Status R Notes: 0 Device is not Write Enabled (default) 1 Device is Write Enabled 0 Device is ready 1 Device is busy with an internal operation 1. Only bits 7 through 2 of the Status Register can be modified when using the Write Status Register command. 2. R/W = Readable and writable R = Readable only Figure 10-1. Read Status Register Byte 1 CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SCK 23&2'( SI 0 0 0 0 0 1 0 1 MSB 67$7865(*,67(5 67$7865(*,67(5 BYTE 1 SO HI GHI MPEDANCE 67$7865(*,67(5 BYTE 1 BYTE 1 D D D D D D D D D D D D D D D D D D D D D D D D MSB MSB MSB Table 10-2. Status Register Format - Byte 2 Bit(1) Name Type(2) 7 SUS Suspend Status R 6 CMP Complement Block Protection R/W 5 LB3 Lock Security Register 3 R/W 4 LB2 Lock Security Register 2 R/W 3 LB1 Lock Security Register 1 R/W 2 RES Reserved for future use R Description 0 Device is not suspended (default) 1 Device is suspended from erase 0 See table on Block Protection 0 Security Register page-3 is not locked (default) 1 Security Register page-3 cannot be erased/programmed 0 Security Register page-2 is not locked (default) 1 Security Register page-2 cannot be erased/programmed 0 Security Register page-1 is not locked (default) 1 Security Register page-1 cannot be erased/programmed 0 Reserved for future use AT25SF321 DS-25SF321-047F-8/2017 26 Table 10-2. Status Register Format - Byte 2 Bit(1) 1 QE 0 SRP1 Notes: Type(2) Name Quad Enable R/W Status Register Protect bit-1 R/W Description 0 HOLD and WP function normally (default) 1 HOLD and WP are I/O pins See table on Status Register Protection 1. Only bits 6 through 3, 1, and 0 of the Status Register can be modified when using the Write Status Register command 2. R/W = Readable and writable R = Readable only. Figure 10-2. Read Status Register Byte 2 CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SCK 23&2'( SI 0 0 0 1 0 1 MSB 67$7865(*,67(5 67$7865(*,67(5 BYTE 2 SO HI GHI MPEDANCE 67$7865(*,67(5 BYTE 2 BYTE 2 D D D D D D D D D D D D D D D D D D D D D D D D MSB MSB MSB 10.1.1 SRP1, SRP0 Bits The SRP1 and SRP0 bits control whether the Status Register can be modified. The state of the WP pin along with the values of the SRP1 and SRP0 determine if the device is software protected, hardware protected, or permanently protected (see Table 10-3). Table 10-3. Status Register Protection Table 1. SRP1 SRP0 WP Status Register Description 0 0 X Software Protected The Status Register can be written to after a Write Enable instruction, WEL=1.(Factory Default) 0 1 0 Hardware Protected WP=0, the Status Register is locked and cannot be written. 0 1 1 Hardware Unprotected WP =1, the Status Register is unlocked and can be written to 1 0 X Power Supply LockDown (1) Status Register is protected and cannot be written to again until the next Power-Down, Power-Up cycle. 1 1 X One Time Program Status Register is permanently protected and cannot be written to. after a Write Enable instruction, WEL=1. When SRP1, SRP0 = (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to the (0, 0) state. 10.1.2 CMP, SEC, TB, BP2, BP1, BP0 Bits The CMP, SEC, TB, BP2, BP1, and BP0 bits control which portions of the array are protected from erase and program operations (see Tables 8-1 and 8-2). AT25SF321 DS-25SF321-047F-8/2017 27 The CMP bit complements the effect of the other bits. The SEC bit selects between large and small block size protection. The TB bit selects between top of the array or bottom of the array protection. The BP2, BP1, and BP0 bits determine how much of the array is protected. 10.1.3 WEL Bit The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical "0" state, the device will not accept any Byte/Page Program, erase, Program Security Register, Erase Security Register, or Write Status Register commands. The WEL bit defaults to the logical "0" state after a device power-up or reset operation. In addition, the WEL bit will be reset to the logical "0" state automatically under the following conditions: Write Disable operation completes successfully Write Status Register operation completes successfully or aborts Program Security Register operation completes successfully or aborts Erase Security Register operation completes successfully or aborts Byte/Page Program operation completes successfully or aborts Block Erase operation completes successfully or aborts Chip Erase operation completes successfully or aborts If the WEL bit is in the logical "1" state, it will not be reset to a logical "0" if an operation aborts due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Program Security Register, Erase Security Register, or Write Status Register command must have been clocked into the device. 10.1.4 RDY/BSY Bit The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical "1" to a logical "0". 10.1.5 LB3, LB2, LB1 Bits The LB3, LB2, and LB1 bits are used to determine if any of the three Security Register pages are locked. The LB3 bit is in the logical "1" state if Security Register page-2 is locked and cannot be erased or programmed. The LB2 bit is in the logical "1" state if Security Register page-1 is locked and cannot be erased or programmed. The LB1 bit is in the logical "1" state if Security Register page-0 is locked and cannot be erased or programmed. 10.1.6 QE Bit The QE bit is used to determine if the device is in the Quad Enabled mode. If the QE bit is in the logical "1" state, then the HOLD and WP pins functions as input/output pins similar to the SI and SO. If the QE bit is in the logical "0" state, then the HOLD pin functions as an input only and the WP pin functions as an input only. 10.2 Write Status Register (01h) The Write Status Register command is used to modify the Block Protection, Security Register Lock-down, Quad Enable, and Status Register Protection. Before the Write Status Register command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical "1". To issue the Write Status Register command, the CS pin must first be asserted and the opcode of 01h must be clocked into the device followed by one or two bytes of data. The first byte of data consists of the SRP0, SEC, TB, BP2, BP1, BP0 bit values and 2 dummy bits. The second byte is optional and consists of 1 dummy bit, the CMP, LB3, LB2, LB1, 1 dummy bit, the QE, and 1 dummy bit. When the CS pin is deasserted, the bit values in the Status Register will be modified, and the WEL bit in the Status Register will be reset back to a logical "0". AT25SF321 DS-25SF321-047F-8/2017 28 The complete one byte or two bytes of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of the Status Register bits will not change, memory protection status will not change, and the WEL bit in the Status Register will be reset back to the logical "0" state Table 10-4. Write Status Register Format. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRPO SEC TB BP2 BP1 BP0 WEL RDY/BSY Figure 10-3. Write Status Register CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Status Register In - Byte 1 Opcode SI 0 0 0 0 0 0 0 1 D D D D D MSB D D Status Register In - Byte 2 D D D D D D D D D MSB High-Impedance SO Table 10-5. Write Status Register Byte 2 10.3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SUS CMP LB3 LB2 LB1 reserved QE SRP1 Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits described in Table 10-1 and Table 10-2 can also be written to as volatile bits. During power up reset, the non-volatile Status Register bits are copied to a volatile version of the Status Register that is used during device operation. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register nonvolatile bits. To write the volatile version of the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to each Write Status Registers (01h) instruction. Write Enable for Volatile Status Register instruction will not set the Write Enable Latch bit. It is only valid for the next following Write Status Registers instruction, to change the volatile Status Register bit values. AT25SF321 DS-25SF321-047F-8/2017 29 Figure 10-4. Write Enable for Volatile Status Register &6 0 1 2 3 4 5 6 7 6&. OPCODE 6, MSB HI GHI MPEDANCE 62 11. Other Commands and Functions The AT25SF321 supports three different commands to access device identification that indicates the manufacturer, device type, and memory density. The returned data bytes provide information as shown in Table 11-1. Table 11-1. Manufacturer and Device ID Information Instruction Opcode Dummy Bytes Manufacturer ID (Byte #1) Device ID (Byte #2) Device ID (Byte #3) Read Manufacturer and Device ID 9Fh 0 1Fh 87h 01h Read ID (Legacy Command) 90h 3 1Fh Resume from Deep Power-Down and Read Device ID ABh 3 11.1 15h 15h Read Manufacturer and Device ID (9Fh) Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. Since not all Flash devices are capable of operating at very high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably low clock frequency to ensure all devices used in the application can be identified properly. Once the identification process is complete, the application can increase the clock frequency to accommodate specific Flash devices that are capable of operating at the higher clock frequencies. To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two bytes of Device ID information. Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 11-2. Manufacturer and Device ID Information Byte No. Data Type Value 1 Manufacturer ID 1Fh 2 Device ID (Part 1) 87h 3 Device ID (Part 2) 01h AT25SF321 DS-25SF321-047F-8/2017 30 Table 11-3. Manufacturer and Device ID Details Data Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 Hex Value Details JEDEC Assigned Code Manufacturer ID 0 0 0 1 1 Family Code 1 0 0 0 0 Sub Code 1 0 87h Family Code:100 (AT25SFxxx series) Density Code: 00111 (32-Mbit) 01h Sub Code: 000 (Standard series) Product Version: 00001 Product Version Code Device ID (Part 2) 0 JEDEC Code: 0001 1111 (1Fh for Adesto) Density Code Device ID (Part 1) 1 1Fh 0 0 0 0 0 1 Figure 11-1. Read Manufacturer and Device ID CS 0 6 7 8 14 15 16 22 23 24 30 31 32 SCK OPCODE SI SO 9Fh HIGH-IMPEDANCE Note: Each transition 11.2 1Fh 87h 01h MANUFACTURER ID DEVICE ID BYTE1 DEVICE ID BYTE2 shown for SI and SO represents one byte (8 bits) Read ID (Legacy Command) (90h) Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The preferred method for doing so is the JEDEC standard "Read Manufacturer and Device ID (9Fh)" method described in Section 11.1 on page 30; however, the legacy Read ID command is supported on the AT25SF321 to enable backwards compatibility to previous generation devices. To read the identification information, the CS pin must first be asserted and the opcode of 90h must be clocked into the device, followed by three dummy bytes. After the opcode has been clocked in followed by three dummy bytes, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID of 1Fh followed by a single byte of data representing a device code of 15h. After the device code is output, the sequence of bytes will repeat. Deasserting the CS pin will terminate the Read ID operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data read. AT25SF321 DS-25SF321-047F-8/2017 31 Figure 11-2. Read ID (Legacy Command) &6 0 1 2 3 4 5 6 7 29 30 31 32 33 34 35 36 37 38 39 6&. OPCODE 6, 1 0 '800<%<7(6 0 X X X X X MSB '(9,&(,' 62 HI GHI MPEDANCE D D D D D D D D MSB 11.3 Deep Power-Down (B9h) During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to place the device into an even lower power consumption state called the Deep Power-Down mode. When the device is in the Deep Power-Down mode, all commands including the Read Status Register command will be ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode of B9h, and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the Deep Power-Down mode within the maximum time of tEDPD. The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode after a power-cycle. The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-Down mode. Figure 11-3. Deep Power-Down &6 W('3' 6&. 23&2'( 6, 06% 62 +,*+,03('$1&( $FWLYH&XUUHQW ,&& 6WDQGE\0RGH&XUUHQW 'HHS3RZHU'RZQ0RGH&XUUHQW AT25SF321 DS-25SF321-047F-8/2017 32 11.4 Resume from Deep Power-Down (ABh) In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down command must be issued. The Resume from Deep Power-Down command is the only command that the device will recognize while in the Deep Power-Down mode. To resume from the Deep Power-Down mode, the CS pin must first be asserted and the opcode of ABh must be clocked into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will exit the Deep Power-Down mode within the maximum time of tRDPD and return to the standby mode. After the device has returned to the standby mode, normal command operations such as Read Array can be resumed. If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down mode. Figure 11-4. Resume from Deep Power-Down &6 t RDPD 0 1 2 3 4 5 6 7 6&. OPCODE 6, 1 0 1 0 1 0 1 1 MSB 62 HI GHI MPEDANCE Act i veCur r ent ,&& DeepPower DownModeCur r ent St andbyModeCur r ent 11.4.1 Resume from Deep Power-Down and Read Device ID (ABh) The Resume from Deep Power-Down command can also be used to read the Device ID. When used to release the device from the Power-Down state and obtain the Device ID, the CS pin must first be asserted and opcode of ABh must be clocked into the device, followed by 3 dummy bytes. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 11-4. This command only outputs a single byte Device ID. The Device ID value for the AT25SF321 is listed in Table 11-1. After the last bit (bit 0) of the Device ID has been clocked out, the sequence will repeat itself starting again with bit 7 as long as the CS pin remains asserted and the SCK pin is being pulsed. After CS is deasserted it must remain high for a time duration of tRDPO before new commands can be received. The same instruction may be used to read device ID when not in power down. In that case, /CS does not have to remain high remain after it is deasserted. AT25SF321 DS-25SF321-047F-8/2017 33 Figure 11-5. Resume from Deep Power-Down and Read Device ID &6 0 1 2 3 4 5 6 7 29 30 31 32 33 34 35 36 37 38 39 6&. OPCODE 6, 1 0 1 0 1 0 1 1 X '800<%<7(6 X X W5'32 X X MSB '(9,&(,' HI GHI MPEDANCE 62 D D D D D D D D MSB Act i v eCur r ent ,&& 'HHS3RZHU'RZQ0RGH&XUUHQW 11.5 6WDQGE\0RGH&XUUHQW Hold Function The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue until it is finished. If the QE bit value in the Status Register has been set to logical "1", then the HOLD pin does not function as a control pin. The HOLD pin will function as an output for Quad-Output Read and input/output for Quad-I/O Read. The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode won't be started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin are asserted. While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode. To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won't end until the beginning of the next SCK low pulse. If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical "0" state. AT25SF321 DS-25SF321-047F-8/2017 34 Figure 11-6. Hold Mode CS SCK HOLD Hold Hold Hold AT25SF321 DS-25SF321-047F-8/2017 35 12. Electrical Specifications 12.1 Absolute Maximum Ratings* Temperature under Bias. . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground . . . . . . . . . . . . . . -0.6V to +4.1V All Output Voltages with Respect to Ground . . . . . . . . . . -0.6V to VCC + 0.5V 12.2 *Notice: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC and AC Operating Range AT25SF321 Operating Temperature (Case) Industrial -40C to 85C VCC Power Supply 12.3 2.5V to 3.6V DC Characteristics 2.5V to 3.6V Symbol Parameter Condition IDPD Deep Power-Down Current ISB Standby Current ICC1 (1)(3) ICC2(1) ICC3(1) Active Current, Read (03h, 0Bh) Operation Active Current,(3Bh, BBh Read Operation (Dual) Active Current,(6Bh, EBh Read Operation (Quad) Min Typ Max Units CS, HOLD, WP = VIH All inputs at CMOS levels 2 5 A CS, HOLD, WP = VIH All inputs at CMOS levels 13 25 A f = 20MHz; IOUT = 0mA 3 6 mA f = 50MHz; IOUT = 0mA 4 7 mA f = 85MHz; IOUT = 0mA 5 8 mA f = 50MHz; IOUT = 0mA 5 8 mA f = 85MHz; IOUT = 0mA 6 10 mA f = 50MHz; IOUT = 0mA 6 10 mA f = 85MHz; IOUT = 0mA 8 14 mA ICC4(1) Active Current, Program Operation CS = VCC 10 16 mA ICC5(1) Active Current, Erase Operation CS = VCC 10 16 mA AT25SF321 DS-25SF321-047F-8/2017 36 2.5V to 3.6V 1. Symbol Parameter Condition ILI Input Load Current ILO Output Leakage Current VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage IOL = 1.6mA; VCC = 2.5V VOH Output High Voltage IOH = -100A Min Typ Max Units All inputs at CMOS levels 1 1 A All inputs at CMOS levels 1 1 A VCC x 0.3 V VCC x 0.7 V 0.4 VCC - 0.2V V V Typical values measured at 3.0V @ 25C for the 2.5V to 3.6V range 12.4 AC Characteristics - Maximum Clock Frequencies 2.5V to 3.6V Symbol Parameter fCLK Maximum Clock Frequency for All Operations (excluding opcodes below) fRDLF Max Units 104 104 MHz Maximum Clock Frequency for 03h Opcode 50 50 MHz fRDHF Maximum Clock Frequency for 0Bh Opcode 70 85 MHz fRDDO Maximum Clock Frequency for 3B, BBh Opcode 70 85 MHz fRDQO Maximum Clock Frequency for 6B, EBh Opcode 70 85 MHz Max Units 12.5 Min Typ 2.7V to 3.6V Max Min Typ AC Characteristics - All Other Parameters 2.5V to 3.6V 2.7V to 3.6V Symbol Parameter tCLKH Clock High Time 5 5 ns tCLKL Clock Low Time 5 5 ns tCLKR(1) Clock Rise Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns tCLKF(1) Clock Fall Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns tCSH Chip Select High Time 10 10 ns tCSLS Chip Select Low Setup Time (relative to Clock) 5 5 ns tCSLH Chip Select Low Hold Time (relative to Clock) 5 5 ns tCSHS Chip Select High Setup Time (relative to Clock) 5 5 ns Min Typ Max Min Typ AT25SF321 DS-25SF321-047F-8/2017 37 12.5 AC Characteristics - All Other Parameters 2.5V to 3.6V 2.7V to 3.6V Symbol Parameter tCSHH Chip Select High Hold Time (relative to Clock) 5 5 ns tDS Data In Setup Time 2 2 ns tDH Data In Hold Time 2 2 ns tDIS(1) Output Disable Time 7 6 ns Output Valid Time (03h, 0Bh) 7 6 ns Output Valid Time (3Bh, BBh - Dual) 7 7 Output Valid Time (6Bh, EBh - Quad) 8 8 tV Min Typ Max Min Typ Max Units tOH Output Hold Time 0 0 ns tHLS HOLD Low Setup Time (relative to Clock) 5 5 ns tHLH HOLD Low Hold Time (relative to Clock) 5 5 ns tHHS HOLD High Setup Time (relative to Clock) 5 5 ns tHHH HOLD High Hold Time (relative to Clock) 5 5 ns tHLQZ (1) HOLD Low to Output High-Z 6 6 ns tHHQZ(1) HOLD High to Output High-Z 6 6 ns tWPS(1) (2) Write Protect Setup Time 20 20 ns Write Protect Hold Time 100 100 ns tWPH (1)(2) tEDPD(1) Chip Select High to Deep Power-Down 1 1 s tRDPD(1) Chip Select High to Standby Mode 5 5 s tRDPO(1) Resume Deep Power-Down, CS High to ID 5 5 s 1. Not 100% tested (value guaranteed by design and characterization). 2. Only applicable as a constraint for the Write Status Register command when BPL = 1. 12.6 Program and Erase Characteristics 2.5 to 3.6V Symbol Parameter tPP (1) Page Program Time (256 Bytes) tBP Byte Program Time tBLKE(1) tCHPE(1) (2) Block Erase Time Chip Erase Time Min 2.7V to 3.6V Typ Max 0.7 5 5 Min Typ Max Units 0.7 3.0 ms 5 s 4 Kbytes 60 300 60 300 32 Kbytes 300 1300 300 1300 64 K bytes 500 3000 500 3000 25 60 25 60 AT25SF321 DS-25SF321-047F-8/2017 ms sec 38 12.6 Program and Erase Characteristics 2.5 to 3.6V Symbol Parameter tSRP(1) Security Register Program Time tSRP(1) tWRSR(2) Min Typ 2.7V to 3.6V Max Min Typ Max Units 2.5 2.5 ms Security Register Erase Time 15 15 ms Write Status Register Time 15 15 ms Max Units 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles. 2. Not 100% tested (value guaranteed by design and characterization). 12.7 Power-Up Conditions Symbol Parameter Min tVCSL Minimum VCC to Chip Select Low Time tPUW Power-up Device Delay Before Program or Erase Allowed 10 ms VPOR Power-on Reset Voltage 2.3 V 20 s AT25SF321 DS-25SF321-047F-8/2017 39 12.8 Input Test Waveforms and Measurement Levels 0.9VCC AC DRIVING LEVELS VCC/2 0.1VCC AC MEASUREMENT LEVEL tR, tF < 2 ns (10% to 90%) 12.9 Output Test Load Device Under Test 30pF 13. AC Waveforms Figure 13-1. Serial Input Timing W&6+ &6 W&6/+ W&/./ W&6/6 W&/.+ W&6++ W&6+6 6&. W'6 6, 62 W'+ 06% /6% 06% +,*+,03('$1&( Figure 13-2. Serial Output Timing &6 W&/.+ W&/./ W',6 6&. 6, W9 W2+ W9 62 AT25SF321 DS-25SF321-047F-8/2017 40 Figure 13-3. WP Timing for Write Status Register Command When BPL = 1 CS t WPH t WPS WP SCK SI 0 0 0 MSB OF WRITE STATUS REGISTER OPCODE SO X MSB LSB OF WRITE STATUS REGISTER DATA BYTE MSB OF NEXT OPCODE HIGH-IMPEDANCE Figure 13-4. HOLD Timing - Serial Input CS SCK tHHH tHLS tHLH tHHS tHLH tHHS HOLD SI SO HIGH-IMPEDANCE Figure 13-5. HOLD Timing - Serial Output CS SCK tHHH tHLS HOLD SI tHLQZ tHHQX SO AT25SF321 DS-25SF321-047F-8/2017 41 14. Ordering Information 14.1 Ordering Code Detail AT 2 5 S F 3 2 1 - SSHD - B Designator Shipping Carrier Option B = Bulk (tubes) T = Tape and reel Y = Tray Product Family Operating Voltage D = 2.5V to 3.6V Device Grade H = Green, NiPdAu lead finish, Industrial temperature range (-40C to +85C) Device Density 32 = 32-megabit Package Option Interface M = 8-pad, 5 x 6 x 0.6 mm UDFN SS = 8-lead, 0.150" wide SOIC S = 8-lead, 0.208" wide SOIC DWF = Die in Wafer Form 1 = Serial Ordering Code (1) AT25SF321-SSHD-B AT25SF321-SSHD-T AT25SF321-SHD-B AT25SF321-SHD-T Operating Voltage Max. Freq. (MHz) 2.5V to 3.6V 85MHz Operation Range 8S1 8S2 AT25SF321-MHD-T 8MA1 (2) DWF AT25SF321-DWF 1. Package Industrial (-40C to +85C) The shipping carrier option code is not marked on the devices. 2. Contact Adesto for mechanical drawing or Die Sales information. Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.208" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8MA1 8-pad (5 x 6 x 0.6mm body), Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead (UDFN) DWF Die in Wafer Form AT25SF321 DS-25SF321-047F-8/2017 42 15. Packaging Information 15.1 8S1 - 8-lead, .150" JEDEC SOIC C 1 E E1 L N O TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW SYMBOL MIN NOM MAX A 1.35 - 1.75 A1 0.10 - 0.25 b 0.31 - 0.51 C 0.17 - 0.25 D 4.80 - 5.05 E1 3.81 - 3.99 E 5.79 - 6.20 e Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. NOTE 1.27 BSC L 0.40 - 1.27 O 0 - 8 5/19/10 (R) Package Drawing Contact: contact@adestotech.com TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) GPC SWB DRAWING NO. 8S1 REV. F AT25SF321 DS-25SF321-047F-8/2017 43 15.2 8S2 - 8-lead, .208" EIAJ SOIC C 1 E E1 L N TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW SYMBOL MIN A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 0 e Notes: 1. 2. 3. 4. MAX NOM NOTE 2 8 1.27 BSC 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. (R) Package Drawing Contact: contact@adestotech.com TITLE 8S2, 8-lead, 0.208" Body, Plastic Small Outline Package (EIAJ) GPC STN DRAWING NO. 8S2 4/15/08 REV. F AT25SF321 DS-25SF321-047F-8/2017 44 15.3 8MA1 - UDFN E C Pin 1 ID SIDE VIEW D y TOP VIEW A1 A K E2 0.45 8 Option A Pin #1 Chamfer (C 0.35) 1 Pin #1 Notch (0.20 R) (Option B) 7 e 6 3 5 4 MIN NOM MAX A 0.45 0.55 0.60 A1 0.00 0.02 0.05 b 0.35 0.40 0.48 SYMBOL 2 D2 COMMON DIMENSIONS (Unit of Measure = mm) C b L BOTTOM VIEW 0.152 REF D 4.90 5.00 5.10 D2 3.80 4.00 4.20 E 5.90 6.00 6.10 E2 3.20 3.40 3.60 e L NOT E 1.27 0.50 0.60 0.75 y 0.00 - 0.08 K 0.20 - - 4/15/08 TITLE (R) Package Drawing Contact: contact@adestotech.com 8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) GPC YFG DRAWING NO. 8MA1 REV. D AT25SF321 DS-25SF321-047F-8/2017 45 16. Revision History Revision Level - Release Date History A - June 2015 Initial release B - July 2015 Updated operation description in Section 7.4 (Program/Erase Suspend) and references in Table 7-1. Updated Table 8-2. Updated specifications for Icc3 at 85 MHz and Chip Erase Time (max). C - August 2015 Added Die in Wafer Form ordering option. D - January 2016 Updated specification for TPP. Changed document status from Preliminary to Complete. E - April 2016 Updated 90h opcode description (added 3 dummy bytes). Added Suspend bit description. F - August 2017 Updated corporate address. AT25SF321 DS-25SF321-047F-8/2017 46 Corporate Office California | USA Adesto Headquarters 3600 Peterson Way Santa Clara, CA 95054 Phone: (+1) 408.400.0578 Email: contact@adestotech.com (c) 2017 Adesto Technologies. All rights reserved. / Rev.: DS-25SF321-047F-8/2017 Adesto(R), the Adesto logo, CBRAM(R), and DataFlash(R) are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective owners. Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.