30-276-WE99SN REV N - AMPHENOL - Datasheet.Directory

1. General description

The TJA1028 is a LIN 2.0/2.1/SAE J2602 transceiver with an integrated low-drop voltage

regulator. The voltage regulator can deliver up to 70 mA and is available in 3.3 V and

5.0 V variants. TJA1028 facilitates the development of compact nodes in Local

Interconnect Network (LIN) bus systems. To support robust designs, the TJA1028 offers

strong ElectroS tatic Discharg e (ESD) performance and can withstand high voltages on the

LIN bus. In order to minimize current consumption, the TJA1028 supports a Sleep mode

in which the LIN transceiver and the voltage regulator are powered down while still having

wake-up capability via the LIN bus.

The TJA1028 comes in an SO8 package, and also in a 3 mm 3 mm HVSON8 package

that reduces the required board space by over 70 %. This feature can prove extremely

valuable when board space is limited.

2. Features and benefits

LIN 2.0/2.1/2.2 compliant

SAE J2602 compliant

Downward compatible with LIN 1.3

Internal LIN slave termination resistor

Voltage regulator offering 5 V or 3.3 V, 70 mA capability

2 % voltage regulator accuracy over specified temperature and supply ranges

Voltage regulator output undervoltage detection with reset output

Voltage regulator is short-circuit proof to ground

Voltage regulator stable with ceramic, tantalum and aluminum electrolyte capacitors

Robust ESD performance; 8 kV according to IEC61000-4-2 for pins LIN and VBAT

Pins LIN and VBAT protected against transients in the automotive environment

(ISO 7637)

Very lo w LI N bus leak ag e cu rr en t of < 2 A when battery not connected

LIN pin short-circuit proof to battery and ground

Transmit data (TXD) dominant time-out function

Thermally protected

Very low ElectroMagnetic Emission (EME)

High ElectroMagnetic Immunity (EMI)

Typical Standby mode current of 45 A

Typical Sleep mode current of 12 A

LIN bus wake-up function

K-line compatible

Available in SO8 and HVSON8 packages

TJA1028

LIN transceiver with integrated voltage regulator

Rev. 4 — 25 July 2012 Product data sheet

Product data sheet Rev. 4 — 25 July 2012 2 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

Leadless HVSON8 package (3.0 mm 3.0 mm) with improved Automated Optical

Inspection (AOI) capability

Dark green product (halogen free and Restriction of Hazardous Subst ances (RoHS)

compliant)

3. Ordering information

[1] TJA1028T/5V0/xx and TJA1028TK/5V0/xx for the versions with the 5 V regulator; TJA1028T/3V3/xx and TJA1028TK/3V3/xx for the

versions with the 3.3 V regulator.

[2] TJA1028T/xxx/20 and TJA1028TK/xxx/20 for the normal slope versions that support baud rates up to 20 kBd; TJA1028T/xxx/10 and

TJA1028TK/xxx/10 for the low slope versions that support baud rates up to 10.4 kBd (SAE J2602).

4. Marking

Table 1. Ordering information

Type number Package

Name Description Version

TJA1028T/xxx/xx[1][2] SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

TJA1028TK/xxx/xx[1][2] HVSON8 plastic thermal enhanced very thin small outline package; no leads;

8 terminals; body 3  3  0.85 mm SOT782-1

Table 2. Marking codes

Type number Marking

TJA1028T/5V0/10 1028/51

TJA1028T/5V0/20 1028/52

TJA1028T/3V3/10 1028/31

TJA1028T/3V3/20 1028/32

TJA1028TK/5V0/10 28/51

TJA1028TK/5V0/20 28/52

TJA1028TK/3V3/10 28/31

TJA1028TK/3V3/20 28/32

Product data sheet Rev. 4 — 25 July 2012 3 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

5. Block diagram

Fig 1. Block diagram

CONTROL

VREG

OVERTEMP

DETECTION

VBAT

VOLTAGE

REFERENCE

VBAT

DET

VCC

DET

VCC

TJA1028

015aaa085

LIN

GND

TXD

TIMEOUT

TIMER

VBAT

RXD

TXD

VCC

RSTN

VCC

Product data sheet Rev. 4 — 25 July 2012 4 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

6. Pinning information

6.1 Pinning

6.2 Pin description

[1] For enhanced thermal and electrical performance, the exposed center pad of the HVSON8 package should

be soldered to board ground (and not to any other voltage level).

7. Functional description

The TJA1028 combines the functionality of a LIN transceiver and a voltage regulator in a

single chip and of fers wake-up by bus activity. The voltage regulator is designed to power

the Electronic Control Unit’s (ECU) microcontroller and its periphera ls.

The LIN transceiver is the interface between a LIN master/slave protocol controller and

the physical bus in a LIN netw or k. Acco r ding to the Op e n Syst em Inte r con n ec t (OSI )

model, these modules make up the LIN physical layer.

a. TJA1028T/xxx/xx: SO8 b. TJA1028TK/xxx/xx: HVSON8

Fig 2. Pin configuration di ag ra ms

TJA1028T

BAT

GND TXD

LIN RXD

015aaa082

7RSTN

015aaa244

TJA1028TK

RXD

GND

LIN

TXD

EN RSTN

VBAT VCC

Transparent top view

3 6

2 7

1 8

terminal 1

index area

Table 3. Pin description

Symbol Pin Description

VBAT 1 battery supply for the TJA1028

EN 2 enable input

GND 3[1] ground

LIN 4 LIN bus line

RXD 5 LIN receive data output

TXD 6 LIN transmit data input

RSTN 7 r eset output (active LOW)

VCC 8 voltage regulator output

Product data sheet Rev. 4 — 25 July 2012 5 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

The TJA1028T/xxx/20 and TJA1028TK/xxx/20 versions are optimized for a transmission

speed of 20 kBd, the maximum specified in the LIN standard. The TJA102 8 T/ xxx /1 0 an d

TJA1028TK/xxx/10 versions are optimized for a transmission speed of 10.4 kBd, as

specified in SAE J2602. All versions achieve optimum ElectroMagnetic Compatibility

(EMC) performance by wave shaping the LIN output.

7.1 LIN 2.x/SAE J2602 compliant

The TJA1028 is fully LIN 2.0, LIN 2.1, LIN 2.2 and SAE J2602 compliant. Since the LIN

physical layer is independent of higher OSI model layers (e.g. the LIN pr otocol), nodes

containing a LIN 2.2-compliant physical layer can be combined, without restriction, with

LIN physical layer nodes that comply with earlier revisions (i.e. LIN 1.0, LIN 1.1, LIN 1.2,

LIN 1.3, LIN 2.0 and LIN 2.1).

7.2 Operati ng modes

The TJA1028 supports four operating modes: Normal, Standby, Sleep and Off. The

operating modes, and the transitions between modes, are illustrated in Figure 3.

(1) In Normal mode, the LIN transmitter is enabled - but if EN and/or RSTN go LOW, the LIN

transmitter will be disabled. Remote wake-up signalling will be activated.

(2) Until VCC drops below 2 V.

(3) If a wake-up event and a go-to-sleep event occur simultaneously, the device will switch directly to

Standby mode without initiating a reset.

Fig 3. State diagram

NORMAL(1)

LIN = on

STANDBY

LIN = off

(RXD signals

wake source)

AII states

OFF

LIN = off

RXD = floating

RSTN = LOW

VBAT > Vth(det)pon AND

Tvj < Tth(rel)otp

Voltage regulator - on

Voltage regulator - off

wake-up(3)

event

015aaa086

EN = 1 AND

RSTN = 1

EN = 1 0 AND(3)

TXD = 0 AND

RSTN = 1

EN = 1

EN = 1 0 AND

TXD = 1 AND

RSTN = 1

VBAT < Vth(det)poff OR

Tvj > Tth(act)otp

SLEEP

LIN = off

RXD = VCC(2)

RSTN = LOW

remote

wake-up

Product data sheet Rev. 4 — 25 July 2012 6 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

7.2.1 Off mode

The TJA1028 switches to Off mode from all other modes if the battery supply voltage

drops below the power-off detection threshold (V th(det)poff) or the junction temperature

exceeds the overtemperature protection activation threshold (Tth(act)otp).

The voltage regulator and the LIN physical layer are disabled in Off mode, and pin RSTN

is forced LOW.

7.2.2 Standby mode

Standby mode is a low-power mode that guarantees very low current consumption.

The TJA1028 switches from Off mode to Standby mode as soon as the battery supply

voltage rises above the power-on detection threshold (VBAT > Vth(det)pon), provided the

junction temp er at ur e is belo w the ove rtem p er at ur e pr ot ection release thre sh o ld

(Tvj <T

th(rel)otp).

The TJA1028 switches to Standby mode from Normal mode during the mode select

window if TXD is HIGH and EN is LOW (see Section 7.2.5), provided RSTN = 1.

A remote wake-up event will trigger a transition to Standby mode from Sleep mode. The

remote wake-up event will be signalled by a continuous LOW level on pin RXD.

In Standby mode, the voltage regulator is on, the LIN physical layer is disabled and

remote wake-up detection is active. The wake-u p source is indicated by the level on RXD

(LOW indicates a remote wake-up).

7.2.3 Normal mode

If the EN pin is pulled HIGH while the TJA1028 is in Standby mode (with RSTN = 1) or

Sleep mode, the device will enter Normal mode. The LIN physical layer and the voltage

regulator are enabled in Normal mode.

7.2.3.1 The LIN transceiver in Normal mode

The LIN transceiver is activated when the TJA1028 enters Normal mode.

In Normal mode, the transceiver can transmit and receive data via the LIN bus. The

receiver detects data streams on th e LIN pin and transfers them to th e microcon trolle r via

pin RXD. LIN recessive is represented by a HIGH level on RXD, LIN dominant by a LOW

level.

The transmit data streams of the protocol controller at the TXD input are converted by the

transmitter into bus signals with optimized slew rate and wave shaping to minimize EME.

A LOW level at the TXD input is converted to a LIN dominant level while a HIGH level is

converted to a LIN recessive level.

7.2.4 Sleep mode

Sleep mode features extremely low power consumption.

The TJA1028 switches to Sleep mode from Normal mode during the mode select window

if TXD and EN are both LOW (see Section 7.2.5), provided RSTN = 1.

The volt age reg ulator and the LIN physical layer are disab led in Sleep mode. Pin RSTN is

forced LOW. Remote wake-up detection is active.

Product data sheet Rev. 4 — 25 July 2012 7 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

7.2.5 Transition from Normal to Sleep or Standby mode

When EN is driven LOW in Normal mode, the TJA1028 disables the transmit path. The

mode select window opens t msel(min) after EN goes LOW, and remains op en until tmsel(max)

after EN goes LOW (see Figure 4).

The TXD pin is sampled in the mode select window. A transition to Standby mode is

triggered if TXD is HIGH, or to Sleep mode if TXD is LOW.

To avoid complicated timing in the application, EN and TXD can be pulled LOW at the

same time without having any effect on the LIN bus. In order to ensure that the remote

wake-up time (twake(dom)LIN) is not reset on a transition to Sleep mode, TXD should be

pulled LOW at least td(EN-TXD) after EN goes LOW. This is guaranteed by design.

The user must ensure the appropriate level is present on pin TXD while the mode select

window is open.

7.3 Power supplies

7.3.1 Battery (pin VBAT)

The TJA1028 contains a single supply pin, VBAT. An external diode is needed in series to

protect the device against negative voltages. The operating range is from 4.5 V to 28 V.

The TJA1028 can hand le voltages up to 40 V ( max). If the voltage on p in V BAT falls below

Vth(det)poff, the TJA1028 switches to Off mode, shutting down the internal logic and the

voltage regulator and disabling the LIN transmitter. The TJA1028 exits Off mode as soon

as the voltage rises above Vth(det)pon, provided the junction temperature is below Tth(rel)otp.

7.3.2 Voltage regulator (pin VCC)

The TJA1028 contains a voltage regulator supplied via pin VBAT, which delivers up to

70 mA. It is designed to supply the microcontroller and its periphery via pin VCC.

TXD is sampled during the mode select window . The TJA1028 switches to St andby (TXD HIGH) or

Sleep (TXD LOW) mode after sampling.

Fig 4. Transiti on from Normal to Sleep/ Standby mode

TXD

operating

mode

mode select window

Normal with TXD

path blocked

Normal Sleep or Standby depending on

TXD level in mode select window

tmsel(max)

tmsel(min)

015aaa087

Product data sheet Rev. 4 — 25 July 2012 8 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

7.3.3 Reset (pin RSTN)

The output voltage on pin VCC is monitored continuously and a system reset signal is

generated (pin RSTN goes LOW) if an undervoltage event is detected (VCC < Vuvd for

tdet(uv)(VCC)). Pin RSTN will go HIGH again once the voltage on VCC exceeds the

undervoltage recovery threshold (Vuvr) for trst.

7.4 LIN transceiver

The transceiv er is the in te r fac e be twe e n a LI N mas te r/s lav e pr ot ocol controller and the

physical bus in a LIN network. It is primarily intended for in-vehicle sub-networks using

baud rates from 2.4 kBd up to 20 kBd and is LIN 2.0/LIN 2.1/SAE J2602 compliant.

7.5 Remote wake-up

A remote wake-up is triggered by a falling edge on pin LIN, followed by LIN remaining

LOW for at least twake(dom)LIN, followed by a ri sing edge on pin LIN (see Figure 5).

The remote wake-up request is communicated to the microcontroller in Standby mode by

a continuous LOW level on pin RXD.

Note that twake(dom)LIN is measured in Sleep and Standby modes, and in Normal mode if

TXD is HIGH.

7.6 Fail-safe features

7.6.1 General fail-safe features

The following general fail-safe features have been implemented:

•An internal pull-up towards VCC on pin TXD guarantees a recessive bus le vel if the pin

is left floating by a bad solder joint or floating microcontroller port pin.

•The current in the transmitter output stage is limited in order to p rote ct the transmitter

against short circuits to pin VBAT.

•A loss of power (pins VBAT and GND) has no impact on the bus line or on the

microcontroller. There will be no reverse currents from the bus.

•The LIN transmitter is automatically disabled when either EN or RSTN is LOW.

Fig 5. Remote wake-up behavior

015aaa088

LIN recessive

LIN dominant

Standby/Sleep mode Standby mode

VBUSdom

VBUSrec

ground

VBAT

VLIN

LOW

Sleep: floating/Standby: HIGH

RXD

twake(dom)LIN

Product data sheet Rev. 4 — 25 July 2012 9 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

•After a transition to Normal mode, the LIN transmitter is only enabled if a recessive

level is present on pin TXD.

7.6.2 TXD dominant time-out function

A TXD dominant time-out timer circuit prevents the bus line being driven to a perma n ent

dominant state (blocking all network communications) if TXD is forced permanently LOW

by a hardware or sof tware applicat ion failure. The timer is triggere d by a negative edge on

the TXD pin. If the pin remains LOW for longer than the TXD dominant time-out time

(tto(dom)TXD), the transmitter is disabled, driving th e bus line to a recessive state. Th e timer

is reset by a positive edge on TXD.

7.6.3 Temperature protection

The temperat ur e of th e IC is moni to re d in Normal, Standby and Off modes. If the

temperature is too high (Tvj >T

th(act)otp), the TJA1028 will switch to Off mode (if in S t andby

or Normal modes). The voltage regulator and the LIN transmitter will be switched off and

the RSTN pin driven LOW.

When the temperature falls below the overtemperature protection release threshold

(Tvj <T

th(rel)otp), the TJA1028 switches to Standby mode.

8. Limiting values

[1] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k).

[2] VCC and VBAT connected to GND, emulating application circuit.

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VBAT b attery supply voltage DC; continuous 0.3 +40 V

Vxvoltage on pin x DC value

pin VCC 0.3 +7 V

pins TXD, RXD, RSTN and EN 0.3 VCC +0.3 V

pin LIN with respect to GND 40 +40 V

VESD electrostatic discharge

voltage HBM [1]

at pins LIN and VBAT [2] 8+8 kV

at any other pin 2+2 kV

IEC 61000-4-2 [3]

at pins LIN and VBAT 8+8 kV

MM [4]

at any pin 250 +250 V

CDM [5]

at corner pins 750 +750 V

at any other pin 500 +500 V

Vtrt transient voltage on pin VBAT via revers e po l a rit y diod e/capac it or ;

on pin LIN via 1 nF coupling capacitor

[6] 150 +100 V

Tvj virtual junction temperature [7] 40 +150 C

Tstg storage temperature 55 +150 C

Product data sheet Rev. 4 — 25 July 2012 10 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

[3] ESD performance of pins LIN and VBAT according to IEC 61000-4-2 (150 pF, 330 ) has been verified by an external test house.

[4] Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ).

[5] Charged Device Model (CDM): according to AEC-Q100-011 (field induced charge; 4 pF).

[6] Verified by an external test house to ensure pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b.

[7] Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tj=T

amb +PRth(j-a), where Rth(j-a) is a fixed value.

The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).

9. Thermal characteristics

[1] According to JEDEC JESD51-2 and JESD51-3 at natural convection on 1s board.

[2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers

(thickness: 35 m) and thermal via array under the package connected to the first inner copper layer.

[3] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers

(thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer.

10. Static characteristics

Table 5. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to ambient SO8; single-layer board [1] 132 K/W

SO8; four-layer board [2] 93 K/W

HVSON8; single-layer board [1] 129 K/W

HVSON8; four-layer board [3] 67 K/W

Table 6. Static characteristics

VBAT = 5.5 V to 28 V; Tvj =





C to +150



C; RL(LIN-VBAT) = 500



; all voltages are defined with respect to ground; positive

currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supply; pin VBAT

IBAT b attery supply current Standby mode; VLIN =V

BAT -4559A

Sleep mode; VLIN =V

BAT -1218A

Normal mode; bus recessive;

VLIN =V

BAT; VRXD =V

CC; VRSTN =HIGH - 850 1800 A

Normal mode; bus dominant;

VBAT =12V; V

TXD =0V; V

RSTN =HIGH -2.04.5mA

Vth(det)pon power-on de tection threshol d

voltage - - 5.25 V

Vth(det)poff power-off detection threshold

voltage 3-4.2V

Vhys(det)pon power-on detection hysteresis

voltage VBAT = 2 V to 28 V 50 - - mV

Supply; pin VCC

VCC supply voltage VCC(nom) = 5 V; IVCC = 70 mA to 0 mA 4.9 5 5.1 V

VCC(nom) = 3.3 V; VBAT = 4.5 V to 28 V;

IVCC = 70 mA to 0 mA 3.234 3.3 3.366 V

IOlim output current limit VCC = 0 V to 5.5 V 250 - 70 mA

Product data sheet Rev. 4 — 25 July 2012 11 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

Vuvd undervoltage detection

voltage VCC(nom) = 5 V 4.5 - 4.75 V

VCC(nom) = 3.3 V 2.97 - 3.135 V

Vuvr undervoltage recovery

voltage VCC(nom) = 5 V 4.6 - 4.9 V

VCC(nom) = 3.3 V 3.036 - 3.234 V

R(VBAT-VCC) resistance between pin VBAT

and pin VCC

VCC(nom) = 5 V; VBAT = 4.5 V to 5.5 V;

IVCC =70 mA to 5 mA;

regulator in saturation

[1]

[2]

Tvj =85C--7

Tvj =150C--9

Cooutput capacit ance equivalent series resistance < 5 [2] 1.8 10 - F

LIN transmit data input; pin TXD

Vth(sw) switching threshold voltage VCC = 2.97 V to 5.5 V 0.3 

VCC

-0.7 

VCC

Vhys(i) input hysteresis voltage VCC = 2.97 V to 5.5 V 200 - - mV

Rpu pull-up resistance 5 12 25 k

LIN receive data output; pi n RXD

IOH HIGH-level output current Normal mode;

VLIN =V

BAT; V RXD = VCC  0.4 V --0.4 mA

IOL LOW-level output current Normal mode;

VLIN = GND; VRXD = 0.4 V 0.4 - - mA

Enable input; pin EN

Vth(sw) switching threshold voltage 0.8 - 2 V

Rpd pull-down resistance 50 130 400 k

Reset output; pin RSTN

Rpu pull-up resistance VRSTN = VCC  0.4 V;

VCC = 2.97 V to 5.5 V 3-12k

IOL LOW-level output current VRSTN = 0.4 V; VCC = 2.97 V to 5.5 V;

40 C< T

vj < 195 C3.2 - 40 mA

VOL LOW-level output voltage VCC = 2.5 V to 5.5 V;

40 C< T

vj < 195 C0-0.5V

VOH HIGH-level output voltage 40 C< T

vj < 195 C0.8

VCC

-V

CC +

0.3 V

LIN bus line; pin LIN

IBUS_LIM current limitation for driver

dominant state VBAT = VLIN =18V; V

TXD = 0 V 40 - 100 mA

IBUS_PAS_rec receiver recessive input

leakage current VLIN = 18 V; VBAT = 5.5 V; VTXD = VCC --2A

IBUS_PAS_dom receiver dominant inpu t

leakage current including

pull-up resistor

Normal mode;

VTXD = VCC; VLIN = 0 V; VBAT = 12 V 600 - - A

IBUS_NO_GND loss-of-ground bus current VBAT = 18 V; VLIN = 0 V 750 - +10 A

IBUS_NO_BAT loss-of-battery bus current VBAT = 0 V; VLIN = 18 V - - 2 A

Table 6. Static characteristics …continued

VBAT = 5.5 V to 28 V; Tvj =





C to +150



C; RL(LIN-VBAT) = 500



; all voltages are defined with respect to ground; positive

currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 4 — 25 July 2012 12 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

[1] See Figure 1 and Figure 6.

[2] Not tested in production; guaranteed by design.

[3] See Figure 8.

VBUSrec receiver recessive state VBAT = 5.5 V to 18 V 0.6 

VBAT

--V

VBUSdom receiver dominant state VBAT = 5.5 V to 18 V - - 0.4 

VBAT

VBUS_CNT receiver center voltage VBAT = 5.5 V to 18 V;

VBUS_CNT = (VBUSdom + VBUSrec)/2 [3] 0.475 

VBAT

0.5 

VBAT

0.525

 VBAT

VHYS receiver hysteresis voltage VBAT = 5.5 V to 18 V;

VHYS = VBUSrec  VBUSdom

[3] 0.05 

VBAT

0.15 

VBAT

0.175

 VBAT

VSerDiode voltage drop at the serial

diode in pull-up path with Rslave;

ISerDiode =0.9mA [2] 0.4 - 1.0 V

CLIN capacitance on pin LIN with respect to GND [2] - - 30 pF

VO(dom) domin an t ou t pu t vol tage Normal mode;

VTXD = 0 V; VBAT = 7 V --1.4V

Normal mode;

VTXD = 0 V; VBAT = 18 V --2.0V

Rslave slave resistance between pin LIN and VBAT;

VLIN =0 V; V

BAT =12V 20 30 60 k

Temperature protection

Tth(act)otp overte mperature protection

activation threshold

temperature

165 180 195 C

Tth(rel)otp overte mperature protection

release threshold

temperature

126 138 150 C

Table 6. Static characteristics …continued

VBAT = 5.5 V to 28 V; Tvj =





C to +150



C; RL(LIN-VBAT) = 500



; all voltages are defined with respect to ground; positive

currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 4 — 25 July 2012 13 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

11. Dynamic characteristics

Fig 6. Graph of R(VBAT-VCC)(typ) as a function of junction temperature (Tvj)

Tvj (°C)

-50 0 50 100 150

001aan953

R(VBAT-VCC)(typ)

(Ω)

Table 7. Dynamic characteristics

VBAT = 5.5 V to 18 V; Tvj =





C to +150



C; RL(LIN-VBAT) = 500



; all voltages are defined with respect to ground; positive

currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified. [1]

Symbol Parameter Conditions Min Typ Max Unit

Duty cycles

1 duty cycle 1 Vth(rec)(max) = 0.744VBAT;

Vth(dom)(max) = 0.581VBAT;

tbit =50s;

VBAT = 7 V to 18 V

[2][3]

[4][5] 0.396 - -

Vth(rec)(max) = 0.76VBAT;

Vth(dom)(max) = 0.593VBAT;

tbit =50s;

VBAT = 5.5 V to 7.0 V

[2][3]

[4][5] 0.396 - -

2 duty cycle 2 Vth(rec)(min) = 0.422VBAT;

Vth(dom)(min) = 0.284VBAT:

tbit =50s;

VBAT = 7.6 V to 18 V

[2][4]

[5][6] - - 0.581

Vth(rec)(min) = 0.41VBAT;

Vth(dom)(min) = 0.275VBAT;

tbit =50s;

VBAT = 6.1 V to 7.6 V

[2][4]

[5][6] - - 0.581

3 duty cycle 3 Vth(rec)(max) = 0.778VBAT;

Vth(dom)(max) = 0.616VBAT;

tbit =96s;

VBAT = 7 V to 18 V

[3][4]

[5] 0.417 - -

Vth(rec)(max) = 0.797VBAT;

Vth(dom)(max) = 0.630VBAT;

tbit =96s;

VBAT = 5.5 V to 7 V

[3][4]

[5] 0.417 - -

Product data sheet Rev. 4 — 25 July 2012 14 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to

cover the specified temperature and power supply voltage ranges.

[2] Not applicable to the low slope versions (TJA1028T/xxx/10 and TJA1028TK/xxx/10) of the TJA1028.

[3] . Variable tbus(rec)(min) is illustrated in the LIN timing diagram in Figure 8.

[4] Bus load conditions are: CBUS = 1 nF and RBUS =1k; CBUS = 6.8 nF and RBUS =660; CBUS = 10 nF and RBUS = 500 .

[5] For VBAT > 18 V, the LIN transmitter might be suppressed. If TXD is HIGH then the LIN transmitter output is recessive.

[6] . Variable tbus(rec)(max) is illustrated in the LIN timing diagram in Figure 8.

[7] Not tested in production; guaranteed by design.

4 duty cycle 4 Vth(rec)(min) = 0.389VBAT

Vth(dom)(min) = 0.251VBAT

tbit =96s

VBAT = 7.6 V to 18 V

[4][5]

[6] - - 0.590

Vth(rec)(min) = 0.378VBAT;

Vth(dom)(min) = 0.242VBAT;

tbit =96s;

VBAT = 6.1 V to 7.6 V

[4][5]

[6] - - 0.590

Tim in g ch ar acteristi cs

trx_pd receiver propagation delay rising and fallin g;

CRXD = 20 pF -- 6s

trx_sym receiver propagation delay symmetry CRXD =20pF 2- +2s

twake(dom)LIN LIN dominant wake-up time Sleep mode 30 80 150 s

tto(dom)TXD TXD dominant time-out time VTXD =0V 6 - 20 ms

tmsel mode select time 3 - 20 s

td(EN-TXD) delay time from EN to TXD [7] 0- 1s

tdet(uv)(VCC) undervoltage detection time on pin VCC CRSTN = 20 pF 1 - 15 s

Reset output; pin RSTN

trst reset time 2 - 8 ms

Table 7. Dynamic characteristics …continued

VBAT = 5.5 V to 18 V; Tvj =





C to +150



C; RL(LIN-VBAT) = 500



; all voltages are defined with respect to ground; positive

currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified. [1]

Symbol Parameter Conditions Min Typ Max Unit

13tbus recmin

bit



-------------------------------

24tbus recmax

bit



--------------------------------

Fig 7. Timing test circuit for LIN transceiver

TJA1028

VBAT

TXD

RLIN

CLIN

RXD

CRXD LIN

GND

015aaa198

Product data sheet Rev. 4 — 25 July 2012 15 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

12. Test information

12.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated

circuits, and is suitable for use in automotive applications.

Fig 8. LIN transceiver timing diagram

015aaa199

VTXD

VBAT

tbit

tbus(rec)(min)

Vth(rec)(max) thresholds of

receiving node A

Vth(dom)(max)

Vth(rec)(min)

Vth(dom)(min)

trx_pdr

trx_pdf

trx_pdr trx_pdf

tbus(rec)(max)

tbit tbit

thresholds of

receiving node B

output of receiving

node A VRXD

output of receiving

node B VRXD

tbus(dom)(max)

tbus(dom)(min)

LIN bus

signal

Product data sheet Rev. 4 — 25 July 2012 16 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

13. Package outline

Fig 9. Package outline SOT96-1 (SO8)

UNIT A

max. A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 5.0

4.8 4.0

3.8 1.27 6.2

5.8 1.05 0.7

0.6 0.7

0.3 8

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

detail X

vMA

(A )

pin 1 index

076E03 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.20

0.19 0.16

0.15 0.05 0.244

0.228 0.028

0.024 0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

99-12-27

03-02-18

Product data sheet Rev. 4 — 25 July 2012 17 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

Fig 10. Package outline SOT782-1 (HVSON8)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT782-1 - - -- - -

sot782-1_po

09-08-25

09-08-28

Unit(1)

mm max

nom

min

1.00

0.85

0.80

0.05

0.03

0.00 0.2 3.10

3.00

2.90

2.45

2.40

2.35

3.10

3.00

2.90 0.65 1.95 0.45

0.40

0.35 0.1

Dimensions

Note

1. Plastic or metal protrusions of 0.075 maximum per side are not included.

HVSON8: plastic thermal enhanced very thin small outline package; no leads;

8 terminals; body 3 x 3 x 0.85 mm SOT782-1

A1b

0.35

0.30

0.25

cDD

hEE

1.65

1.60

1.55

0.35

0.30

0.25

0.1

0.05

0 1 2 mm

scale

MO-229

detail X

B A

terminal 1

index area

eAC B

vCw

1 4

8 5

terminal 1

index area

Product data sheet Rev. 4 — 25 July 2012 18 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

14. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) un der

normal handling. When handling ensure that the appropriate pre ca u tio ns ar e taken as

described in JESD625-A or equivalent standards.

15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

15.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 4 — 25 July 2012 19 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

15.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 11) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low en ough that the

packages and/or boards are not damaged. Th e peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 8 and 9

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 11.

Table 8. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 9. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 4 — 25 July 2012 20 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

16. Soldering of HVSON packages

Section 15 contains a brief intr oduction to the techniques most commonly used to solder

Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON

leadless package ICs can found in the following application notes:

•AN10365 ‘Surface mount reflow soldering description”

•AN10366 “HVQFN application information”

MSL: Moisture Sensitivity Level

Fig 11. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 4 — 25 July 2012 21 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

17. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TJA1028 v.4 20120725 Product data sheet - TJA1028 v.3

Modifications: •Table 5: text of table note section amended

•Table 3: text of table note amended

•Section 2, Section 7, Section 7.3.2: text revised

•Section 7.1, Section 7.3.3: ad ded

•Figure 1, Figure 5: amended

•Table 6: parameters values/conditio ns chang ed: Vth(det)pon, Vth(det)poff

TJA1028 v.3 20110519 Product data sheet - TJA1028 v.2

TJA1028 v.2 20100225 Product data sheet - TJA1028 v.1

TJA1028 v.1 20100921 Product data sheet - -

Product data sheet Rev. 4 — 25 July 2012 22 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

18. Legal information

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond tho se described in the

Product data sheet.

18.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregat e and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless ot herwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, lif e-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applicati ons or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by cust omer.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 4 — 25 July 2012 23 of 24

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

No offer to sell or license — Nothing in this document may be interpret ed or

construed as an of fer to sell product s that is op en for accept ance or the grant ,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated) version of a docume nt is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

18.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors TJA1028

LIN transceiver with integrated voltage regulator

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 July 2012

Document identifier: TJA1028

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

20. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 4

7.1 LIN 2.x/SAE J2602 compliant. . . . . . . . . . . . . . 5

7.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5

7.2.1 Off mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.2.2 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.2.3 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.2.3.1 The LIN transceiver in Normal mode . . . . . . . . 6

7.2.4 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.2.5 Transition from Normal to Sleep or

Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.3 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.3.1 Battery (pin VBAT) . . . . . . . . . . . . . . . . . . . . . . . 7

7.3.2 Voltage regulator (pin VCC). . . . . . . . . . . . . . . . 7

7.3.3 Reset (pin RSTN). . . . . . . . . . . . . . . . . . . . . . . 8

7.4 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 8

7.5 Remote wake-up . . . . . . . . . . . . . . . . . . . . . . . 8

7.6 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 8

7.6.1 General fail-safe features . . . . . . . . . . . . . . . . . 8

7.6.2 TXD dominant time-out function. . . . . . . . . . . . 9

7.6.3 Temperature protection. . . . . . . . . . . . . . . . . . . 9

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9

9 Thermal characteristics . . . . . . . . . . . . . . . . . 10

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 10

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13

12 Test information. . . . . . . . . . . . . . . . . . . . . . . . 15

12.1 Quality information . . . . . . . . . . . . . . . . . . . . . 15

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

14 Handling information. . . . . . . . . . . . . . . . . . . . 18

15 Soldering of SMD packages . . . . . . . . . . . . . . 18

15.1 Introduction to soldering . . . . . . . . . . . . . . . . . 18

15.2 Wave and reflow soldering . . . . . . . . . . . . . . . 18

15.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 18

15.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 19

16 Soldering of HVSON packages. . . . . . . . . . . . 20

17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21

18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22

18.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 22

18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 22

18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 23

19 Contact information . . . . . . . . . . . . . . . . . . . . 23

20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24