1. General description
The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with
separate D-type inputs with bus hold (74LVCH162373A only) for each latch and 3-state
outputs for bus-oriented applications. One latch enable (pin nLE) input and one output
enable (pin nOE) are provided for each octal. Input s can be driven from either 3.3 V or 5 V
devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow
the use of these de vice s in mixed 3.3 V and 5 V applications. The device consists of two
sections of eight D-type transparent latches with 3-state true outputs. When pi n nLE is
HIGH, data at the corr esponding data input s (pins nDn) enter the latches. In this condition,
the latches are transparent, that is, the latch output changes each time its corresponding
data inputs changes. When pin nLE is LOW, the latches store the information that was
present at the data inputs a set-up time preceding the HIGH to LOW transition of pin
nLE.When pin nOE is LOW, the contents of the eight latches are available at the outputs.
When pin nOE is HIGH, the outputs go to the high-impedance OFF-st ate. Operation of the
nOE input does not affect the state of the latches.
The device is designed with 30 series termination resistors in both HIGH and LOW
output stages to reduce line noise. Bus hold on data inputs eliminates the need for
external pull-up resistors to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH162373A only)
High-impedance when VCC =0V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 series termination
resistors; 5 V tolerant inputs/outputs; 3-state
Rev. 4 — 14 May 2013 Product data sheet
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 2 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C t o +85 C and 40 C to +125 C
3. Ordering information
4. Functional diagram
Tabl e 1. Ordering information
Type number Package
Temperature
range Name Description Version
74LVC162373ADGG 40 C to +125 C TSSOP48 plastic thin shrink small outline package;
48 leads; body width 6.1 mm SOT362-1
74LVCH162373ADGG
74LVC162373ADL 40 C to +125 C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm SOT370-1
74LVCH162373ADL
Fig 1. Logic symbol Fig 2. IEC logic symbol
mgu768
1Q0
1Q1
1LE 2LE
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1OE
47
46
48 25
44
43
41
40
38
37
2
3
1
5
6
8
9
11
12
24
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
36
35
33
32
30
29
27
26
13
14
16
17
19
20
22
23
2OE
23
mgu770
37 12
11
9
8
6
5
47
46
44
43
41
40
38
1D7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
2
3
1Q7
1Q6
1Q5
1Q4
1Q3
1Q2
1Q0
1Q1
26
22
20
19
17
16
36
35
33
32
30
29
27
2D5
2D0
2D1
2D2
2D3
2D4
13
14
2Q5
2Q4
2Q3
2Q2
2Q1
2Q0
24
25 2EN
1OE 11EN
1LE
2OE
2LE
48 C3
C4
3D 1
4D 2
2D7
2D6
2Q7
2Q6
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 3 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
Fig 3. Logic diagram
mgu769
2LE
D
LATCH
9
Q
2OE
to 7 other channels
LE LE
2Q02D0
1LE
D
LATCH
1
Q
1OE
to 7 other channels
LE LE
1Q01D0
Fig 4. Bus hold circuit
to internal circuit
mna428
VCC
input
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 4 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration (T)SSOP48
162373A
001aaa336
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1Q0
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
VCC
2Q4
2Q5
GND
2Q6
2Q7
2OE
1OE
1D0
1D1
GND
1D2
1D3
VCC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
VCC
2D4
2D5
GND
2D6
2D7
2LE
1LE
Table 2. Pin description
Symbol Pin Description
1OE 1 output enable inpu t (active LOW)
2OE 24 output enable inpu t (active LOW)
GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V)
VCC 7, 18, 31, 42 supply voltage
1LE 48 latch enable input (active HIGH)
2LE 25 latch enable input (active HIGH)
1D[0:7] 47, 46, 44, 43, 41, 40, 38, 37 data in put
2D[0:7] 36, 35, 33, 32, 30, 29, 27, 26 data in put
1Q[0:7] 2, 3, 5, 6, 8, 9, 11, 12 data output
2Q[0:7] 13, 14, 16, 17, 19, 20, 22, 23 data ou tput
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 5 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
6. Functional description
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = high-impedance OFF-state
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] Above 60 C, the value of Ptot derates linearly with 5.5 mW/K.
Table 3. Functional tab le (per sec tion of 8 bits)[1]
Operating modes Input Internal Latch Output nQn
nOE nLE nDn
Enable and read register
(transparent mode) LHLLL
LHHHH
Latch and read register L L l L L
LLhHH
Latch register and disable outputs H L l L Z
HLhHZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA
VOoutput voltage output HIGH or LOW state [2] 0.5 VCC + 0.5 V
output 3-state [2] 0.5 +6.5 V
IOoutput current VO = 0 V to VCC -50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C[3] -500mW
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 6 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V
VIinput voltage 0 - 5.5 V
VOoutput voltage output HIGH or LOW state 0 - VCC V
output 3-state 0 - 5.5 V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level input
voltage VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level input
voltage VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC -0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=100 A;
VCC =1.65Vto3.6V VCC 0.2 VCC -V
CC 0.3 - V
IO=2mA; V
CC = 1.65 V 1.2 - - 1.05 - V
IO=4mA; V
CC = 2.3 V 1.7 - - 1.55 - V
IO=6mA; V
CC = 2.7 V 2.2 - - 2.05 - V
IO=12 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO= 100 A;
VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V
IO=2mA; V
CC = 1.65 V - - 0.45 - 0.65 V
IO=4mA; V
CC = 2.3 V - - 0.6 - 0.8 V
IO=6mA; V
CC = 2.7 V - - 0.4 - 0.6 V
IO=12mA; V
CC = 3.0 V - - 0.55 - 0.8 V
IIinput leakage
current VCC = 3.6 V;
VI=5.5VorGND
[2] -0.1 5- 20 A
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 7 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25C.
[2] The bus hold circuit is switched off when VI>V
CC allowing 5.5 V on the input pin.
[3] Valid for data inputs (74LVCH162373A) on ly; control inputs do not have a bus hold circuit.
[4] The specified sustaining current at the data inputs holds the input below the specified VI level.
[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.
IOZ OFF-state output
current VI=V
IH or VIL; VCC = 3.6 V;
VO=5.5VorGND
[2] -0.15- 20 A
IOFF power-off
leakage current VCC = 0 V; VIor VO= 5.5 V - 0.1 10 - 20 A
ICC supply current VCC = 3.6 V;
VI=V
CC or GND; IO=0A -0.120-80A
ICC additional supply
current per input pin;
VCC = 2.7 V t o 3.6 V;
VI=V
CC 0.6 V; IO=0A
- 5 500 - 5000 A
CIinput
capacitance VCC = 0 V to 3.6 V;
VI=GNDtoV
CC
-5.0---pF
IBHL bus hold LOW
current VCC = 1.65; VI = 0.58 V [3][4] 10 - - 10 - A
VCC = 2.3; VI = 0.7 V 30 - - 25 - A
VCC = 3.0; VI = 0.8 V 75 - - 60 - A
IBHH bus hold HIGH
current VCC = 1.65; VI = 1.07 V [3][4] 10 - - 10 - A
VCC = 2.3; VI = 1.7 V 30 - - 25 - A
VCC = 3.0; VI = 2.0 V 75 - - 60 - A
IBHLO bus hold LOW
overdrive current VCC = 1.95 V [3][5] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
IBHHO bus hold HIGH
overdrive current VCC = 1.95 V [3][5] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
Table 6. Static characteristics …continued
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 8 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions Tamb =40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay nDn to nQn; see Figure 6 [2]
VCC = 1.2 V - 12 - - - ns
VCC = 1.65 V to 1.95 V 1.5 6.6 15.0 1.5 17.2 ns
VCC = 2.3 V to 2.7 V 1.0 3.5 7.4 1.0 8.5 ns
VCC = 2.7 V 1.5 3.5 6.7 1.5 8.5 ns
VCC = 3.0 V to 3.6 V 1.0 3.0 5.9 1.0 7.5 ns
nLE to nQn; see Figure 7
VCC = 1.2 V - 14 - - - ns
VCC = 1.65 V to 1.95 V 2.4 7.6 16.0 2.4 18.5 ns
VCC = 2.3 V to 2.7 V 1.7 4.0 7.9 1.7 9.1 ns
VCC = 2.7 V 1.5 3.7 7.0 1.5 9.0 ns
VCC = 3.0 V to 3.6 V 1.5 3.4 6.1 1.5 8.0 ns
ten enable time nOE to nQn; see Figure 8 [2]
VCC = 1.2 V - 18 - - - ns
VCC = 1.65 V to 1.95 V 1.7 7.1 15.6 1.7 17.9 ns
VCC = 2.3 V to 2.7 V 1.5 4.0 8.2 1.5 9.4 ns
VCC = 2.7 V 1.5 4.2 7.5 1.5 9.5 ns
VCC = 3.0 V to 3.6 V 1.0 3.2 6.1 1.0 8.0 ns
tdis disable time nOE to nQn; see Figure 8 [2]
VCC = 1.2 V - 11 - - - ns
VCC = 1.65 V 2.5 4.2 8.5 2.5 9.8 ns
VCC = 2.3 V to 2.7 V 1.0 2.3 4.6 1.0 5.3 ns
VCC = 2.7 V 1.5 3.2 4.8 1.5 6.0 ns
VCC = 3.0 V to 3.6 V 1.5 2.9 4.6 1.5 6.0 ns
tWpulse width nLE HIGH; see Figure 7
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns
VCC = 2.7 V 3.0 - - 3.0 - ns
VCC = 3.0 V to 3.6 V 3.0 2.0 - 3.0 - ns
tsu set-up time nDn to nLE; see Figure 9
VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns
VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns
VCC = 2.7 V 2.0 - - 2.0 - ns
VCC = 3.0 V to 3.6 V 2.0 1.0 - 2.0 - ns
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 9 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
[1] Typical values are measured at Tamb =25C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CLVCC2fo) = sum of the outputs
thhold time nDn to nLE; see Figure 9
VCC = 1.65 V to 1.95 V 2.5 - - 2.5 - ns
VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns
VCC = 2.7 V 0.9 - - 0.9 - ns
VCC = 3.0 V to 3.6 V +0.9 1.0 - +0.9 - ns
tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns
CPD power dissipation
capacitance per input; VI=GNDtoV
CC [4]
VCC = 1.65 V to 1.95 V - 10.8 - - - pF
VCC = 2.3 V to 2.7 V - 13.0 - - - pF
VCC = 3.0 V to 3.6 V - 15.0 - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions Tamb =40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 10 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
11. AC waveforms
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Input (nDn) to output (nQn) propagation delays
mna429
nDn input
nQn output
t
PLH
t
PHL
GND
V
I
V
M
V
M
V
OH
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Latch enable (nLE) pulse width, and the latch enable input to output (nQn) propagation delays
mna430
nLE input
nQn output
tPHL
tW
GND
VI
VM
VM
VOH
VOL
tPLH
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 11 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. 3-st ate enable and disable times
mna432
t
PZL
t
PZH
t
PHZ
t
PLZ
GND
GND
V
I
V
CC
V
OL
V
OH
V
M
V
M
V
M
V
X
V
Y
outputs
disabled outputs
enabled
outputs
enabled
nQn output
LOW-to-OFF
OFF-to-LOW
nQn output
HIGH-to-OFF
OFF-to-HIGH
nOE input
Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable
output performance.
Fig 9. Data set-up an d ho ld times for the nDn input to the nLE input
mna431
t
h
t
su
nDn input
GND
V
I
V
M
t
h
t
su
nLE input
GND
V
I
V
M
Table 8. Measurement points
Supply voltage Input Output
VCC VIVMVMVXVY
1.2 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
1.65 V to 1.95 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.3 V to 2.7 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 12 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
CL
RT
RL
RL
G
Table 9. Test data
Supply voltage Input Load VEXT
VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
1.2 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
1.65 V to 1.95 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND
2.7V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
3.0Vto3.6V 2.7V 2.5 ns 5 0 pF 500 open 2 VCC GND
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 13 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
12. Package outline
Fig 11. Package outline SOT370-1 (SSOP48)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.4
0.2 2.35
2.20 0.25 0.3
0.2 0.22
0.13 16.00
15.75 7.6
7.4 0.635 1.4 0.25
10.4
10.1 1.0
0.6 1.2
1.0 0.85
0.40 8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
48 25
MO-118
24
1
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
A
max.
2.8
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 14 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
Fig 12. Package outline SOT362-1 (TSSOP48)
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 99-12-27
03-02-19
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 15 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charged Device Model
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transisto r Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC_ LVCH162373A v.4 20130514 Product data sheet - 74LVC_LVCH162373A v.3
Modifications: •Typenumbers: 74LVC162373ADGG and 74LVC162373ADL added.
74LVC_ LVCH162373A v.3 20130118 Product data sheet - 74LVC_LVCH16 2373A v.2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges.
74LVC_LVCH162373A v.2 20040205 Product specification - 74LVC_LVCH162373A v.1
74LVC_LVCH162373A v.1 19980805 Product specification - -
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 16 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an inf ormation
source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — Nexperia products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specificati on for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 14 May 2013 17 of 18
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lified nor tested
in accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies Nexperia for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond Nexperia’s
standard warranty and Nexperia’s product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Nexperia 74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional de scription . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16 Contact information. . . . . . . . . . . . . . . . . . . . . 17
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
14 May 2013
