9 Ty, Ground 30A067-00 REV. 8DPZ1MW16A3 Dense-Pac Microsystems, Inc. PRELIMINARY DEVICE OPERATION: The FLASH devices are electrically erasable and program- mable memories that function similarly to an EPROM device, but can be erased without being removed from the system and exposed to ultraviolet light. Each 128K x 16 device can be erased individually eliminating the need to re-program the entire module when partial code changes are required. READ: With Vpp = OV to Vop (Vppio), the devices are read-only memories and can be read like a standard EPROM. By selecting the device to be read (see Truth Table and Functional Block Diagram), the data programmed into the device will appear on the appropriate 1/O pins. When Vpp = +12.5V + 0.5 (Vppii), reads can be accomplished in the same manner as described above but must be preceded by writing 0000H to the command register prior to reading the device. When Vpp is raised to Vpptu the contents of the command register default to OOOOH and remain that way until the command register is allered. STANDBY: When the appropriate CEs are raised to a logic-high level, the standby operation disables the FLASH devices reducing the power consumption substantially. The outputs are placed in a high impedance state, independent of the OF input if the module is deselected during programming, erasure, or autoerase, the device upon which the operation was being performed will continue to draw active current until the operation is completed. PROGRAM: The programming and erasing functions are accessed via the command register when high voltage is applied to Vpp. The contents of the command register control the functions of the memory device (see Command Definition Table). The command registeris not an addressable memory location. The register stores the address, data, and command informa- tion required to execute the command. When Vpp = Vepio the command register is reset to OOOOH returning the device to the read-only mode. The command register is written by enabling the device upon which that the operation is to be performed (see Functional Block Diagram). While the device is enabled bring WE to a logictow (Vi). The address is latched on the falling edge of WE and datais latched on the rising edge of WE. Programming is initiated by writing 4040H (program setup command) to the command register. On the next falling edge of WE the address to be programmed will be latched, followed by the data being latched on the rising edge of WE (see AC Operating and Characteristics Table). PROGRAM VERIFY: The FLASH devices are programmed one location at a time. Each location may be programmed sequentially or at random. Following each programming operation, the data written must be verified. To initiate the program-verify mode, COCOH must be written to the command register of the device just programmed. The programming operation is terminated on the rising edge of The programverify command is then written to the command register. Alter the program~verify command is written to the command register, the memory device applies an intemally generated margin voltage to the location just written. After waiting 6s the data written can be verified by doing a read. If true data is read from the device, the location write was successful and the next location may be programmed. if the device fails to verify, the program/verify operation is repeated up to 20 times. ERASE: The erase function is a command-only operation and can only be executed while Vpp = Vppti. To setup the chip-erase, 2020H must be written to the com- mand register. The chip-erase is then executed by once again writing 2020H to the command register (see AC Operating and Characterstics Table). To ensure a reliable erasure, all bits in the device to be erased should be programmed to their charged state (data = 0000H) Prior to starting the erase operation. With the algorithm provided, this operation should take approximately 2 seconds (typ.). ERASE VERIFY: The erase operation erases all locations in the device selected in parallel. Upon completion of the erase operation, each location must be verified. This operation is initiated by writing AOAOH to the command register. The address to be verified i be supplied in order to be latched on the falling edge of The memory device internally generates a margin vollage and applies it to the addressed location. If FFFFH is read from the device, it indicates the location is erased. The erase/verify command is issued prior to each location verification to latch the address of the location to be verified. This continues until FFFFH is not read from the device or the last address for the device being erased is read. If FFFFH is not read from the location being verified, an additional erase operation is performed. Verification then resumes from the last location verified. Once all locations in the device being erased are verified, the erase operation is complete. The verify opertation should now be terminated by writing a valid command such as program set-up to the command register.Dense-Pac Microsystems, Inc. DPZ1MW16A3 PRELIMINARY AUTOMATIC ERASE: An automatic erase function is also available eliminating the need lo program all locations to OOOOH or do an erase verify. The automatic erase will program all locations to OOOOH and do a continuous erase/verify until all locations in the device are erased. To setup the chip-erase, 3030H must be written to the com mand register. The chip-erase is then executed by once again writing 3030H to the command register (see AC Operating Characteristics Table). To determine if the automatic erase cycle is complete, the mostsignificant (MSB) pin for the device being erased (1/O7, 1/015) is read. If the data = 0 on each of these bits, the cycle is not complete. The erase cycle is complete when the data = 1 on the MSB for the device being erased. DESIGN CONSIDERATIONS: Ver traces should use trace widths and layout considerations comparable to that of the Voo power bus. The Vee supply traces should also be decoupled to help decrease voltage spikes. Power-up sequencing should be such that Vpp doesnt go above Vpp + 2.0V before Vpoo reaches a steady state voltage, while on power-down Vpp should be below Vpp + 2.0V before Voo is lowered, It is recommended that a 4.7pF to 10yF electrolytic capacitor be placed near the memory module connected across Voo and Vss for bulk storage. Decoupling capacitors should also be placed near the module, connected across Vpp and Vss. COMMAND DEFINITION TABLE Bus First Bus Cycle Second Bus Cycle COMMAND Rowd Operation Address Data Operation Address Data Read Memory 1 Write x 0000H . - . Setup Erase / Erase 2 Write x 202010 Write x 2020H Erase Verify 2 Write EA AOAGH Read x EVD Setup Autoerase / Autoerase 2 Write x 3030H Write x 303011 Setup Program / Program 2 Write x 4040H Write PA PD Program Verify 2 Write X COCOH Read x PvD Reset 2 Write x FFFFHA Write x FFFFH EA = Address to Verify EVD = Data Read from Location EA PA = Address to Program PD = Data to be Programmed at Location PA PVA = Data to be Read from Location PA at Program Verify TRUTH TABLE WE DESCRIPTION Not Selected Disable Read Not Selected Disable Read Write e{efe[zfeje |r Current Active Active Active Active Active xje[xixfejz}<19 30A067.00 REV. BDPZ1MW16A3 Dense-Pac Microsystems, Inc. PRELIMINARY ABSOLUTE MAXIMUM RATINGS Parameter RECOMMENDED OPERATING RANGE! Symbol Characteristic Min, |Typ.| Max. | Unit Vop_ | Supply Voltage 4.5 | 5.0 5.5 Vv Capr Vpp | Programming Voltage 2| 12.0}12.5] 13.0 | V Vi | Input LOW Voltage 0.33 0.8 Vv Cwe | Write Vin input HIGH Voltage 2.2 Voot1.0} V Ta Operating Temp. -55 |+25| +125 | C Data CAPACITANCE *: Ta = F = 1.0MHz Max. 100 30 100 pF 100 80 Vin? = OV to +] to +1 3370 DC OUTPUT CHARACTERISTICS Symbol] Parameter Conditions | Min. | Max. Unit -0.6 to +14.0 Vv Von | HIGH Voltage |lou=-400pA] 2.4 : Vv 0.6 to +7.0 Vv Vor | LOW Voltage lov=2.1mA : 0.45]; V DC OPERATING CHARACTERISTICS: Over operating ranges TvP. Limils . Symbol Characteristics Test Conditions (*) Min. Max. Unit fin Input Leakage Current Vin = OV to Voo . 30 +30 pA four Output Vyo OV to Voo, . . Leakage Current or OE = Vin, or WE = Vie 15 +15 pA Iecr Active CE = Vi, Vin Vian or View Supply Current lout = OmA, f = OMHz 35 45 mA tco2 Operating CE = Vu, Vin @ Vu or Vig Supply Current lour = OmA, f = BMHz - 65 Ws mA Icc3 Vop Programming Current Programming in Progress 25 55 mA loca Vop Erase Current Erasure in Progress 35 95 mA Isev Standby Current (TTL) CE = Vin 16 mA $sp2 Full Standby Supply Current (CMOS) | CE Vpp 0.2V 3.2 mA lpps Vee Leakage Current Vep = Verto 320 pA ippy Vep Read Current Vep = Vera 20 mA lep2 Ver Programming Current Vee = Vepra, Programming in Progress 10 80 mA lees Ver Erase Current Vep Vppra, Erasure in Progress 70 180 mA * Typical measurements made at 125C, Cycle min, Voo = 5.0V. 4 30A067-00Dense-Pac Microsystems, Inc. PRELIMINARY AC TEST CONDITIONS Input Pulse Levels OV to 3.0V Input Pulse Rise and Fall Times 5ns Input and Output 1.5V Timing Reference Levels . o . Cmte | eavand av OUTPUT LOAD Load CL Parameters Measured 1 100 pF j except tor 2 30 pF} tor DPZ1IMW16A3 Figure 1. Output Load * Including Probe and jig Capacitance. +5V AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operatin ranges No.| Symbol Parameter 2 20 1 50 1 70 - -200 250 Unit Min. | Max.| Min.| Max.| Min.| Max.| Min.| Max.| Min.| Max, 1 tce Chip Enable Access Time 120 150 170 200 250| ns 2 tacc Address Access Time 420 150 170 200 250} ns 3 tor Output Enabe Access Time 60 70 75 80 90 | ns 4 tor Output Disable to Output in HIGH-Z 5 & Oo | 40} 0 | 50/ O | 55 60 70 | ns 5 tou Ouiput Hold from Address Change 5 5 5 5 5 ns AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE: Over operating ranges No.| Symbol Parameter 2120 | 150} 170_ 200 | 250 nit Min.| Max.| Min.] Max.| Min.| Max.| Min.| Max.| Min.| Max, 6 tcwc_| Write Cycle Time 120 150 170 200 250 ns 7 tas Address Setup Time 0 0 0 0 0 ns 8 taH Address Hold Time 60 60 60 60 60 ns 9 tps Data Setup Time 50 50 50 50 50 ns 10 tou Data Hold Time 10 10 10 10 10 ns 11 tces Chip Enable Setup Time 0 0 O 0 0 ns 12 tceH Chip Enable Hold Time 18 15 15 15 15 ns 13 tves Vee Setup Time 7. 8 100 100 100 100 100 ns 14] ven Vee Hold Time 7. 8 100 100 100 100 100 ns 15 twep Write Enable Pulse Width 70 70 80 80 90 ns 16 twit Write Enable Pulse Width HIGH Time 20 20 20 20 20 ns 17 | toxws_| Seal onble Selp Tine belo 0 : 18 | tors Output Enable Setup Time before Verify 6 6 ps 19 WA Verify Access Time 120 150 170 200 250] ns 20 | tops Output Enable Setup Time before Status Polling | 20 20 20 20 20 ns 21 tspa Status Polling Access Time 120 150 170 200 250} ns 22 tepw Standby Time before Programming 25 25 25 25 25 ps 23 ter Standby Time in Erase 11 11 1 11 4 ms 24 tart Total Erase Time in Autoerase 0.5 | 30 | 0.5| 30 | 0.5} 30 | 0.5 | 30 | 0.5 | 30 S 30A067-00 REV. 8DPZ1MW16A3 Dense-Pac Microsystems, Inc, PRELIMINARY READ CYCLE TRC ADDRESS ADORESS VALID TCE CEO - CET OE TOE WE HIGH-Z DATA OUT ouTPUT VALID PROGRAMMING CYCLE jmet- SETUP PROGRAM ~am| pem- PROGRAM VERIFY ne| Voo (5.0V) TVPH Wes 12.5V Vep 5.0V TERRE RRRRRNY somes ADDRESS QR KR KOA_MAUD TCEH -w TCEH ~~" / CEO - CET N k j . TceH TCES -==| je ICES ne oe Of \ x TCWCtn TPPW TOEWS TWEH p=t-TOERS 4 TWEP TWEP WE N y \ y y yo K_S/ LS LSA TOS | TOH TDs | ToH 1s | 7H TVA OF DATA/O rc {mane = coma Ein ar 6 30A067-00 REV. 8Dense-Pac Microsystems, Inc. DP L1 MW1 6A3 PRELIMINARY ERASE CYCLE ERASE VERIFY Vop (5.0V) 12.5V 5.0V ADDRESS WE Tos | TOH TOF DATA W/O HiGH-z f S*NANO VALID DAtA OUT WAVEFORM KEY SOKOO XOX) WW. _W77 BET Data Valid Transition from Transition from Data Undefined HIGH to LOW LOW to HIGH or Dont Care 30A067-00 7 REV. BDPZ1 MW1 6A3 Dense-Pac Microsystems, Inc. PRELIMINARY AUTOMATIC ERASE CYCLE [nt SETUP AUTO ERASE jue AUTO ERASE & STATUS POLLING am Von (5.0V) TVPH TVPS 12.5V Ver 5.0V ADDRESS _ TCEH ~~ TCEH CEO - CE7 I TCES =] ICES ~- =F ICES OE f \ j _ Tewc bane-TOEP Some} TOEWS, 7 TWEH oe TAET \ fo \ y WE a, NS , Tos | TH 1s | 10H TSPA oe Pai 1/07, 1/015 HWGH-z Command coun f -_ pa) STATUS POLLING ~~ 1/00 -1/O6, __ _ COMMAND COMMAND Vos- i/o 2 " m NOTES: 1. All voltages are with respect to Vss. 2. When operating device at temperatures less than OC (-55C to OC), Vep must be 7.4 Vdc above during Program/Erase functions. 3. -2,0V min. for pulse width less than 20ns (Vi. min. = -0.6V at DC level). 4. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 5. This parameter is guaranteed and not 100% tested. 6. Transition is measured at the point of +500mV from steady state voltage. 7. Vcc must be applied before Vpp and removed after Vpp. 8. Vpp must not exceed 14V, including overshoot 9. The lotal erase times shown are for one (1) 128Kx16 device, to erase the entire module would be 8x the times shown. 8 30A067-00 REV. BDense-Pac Microsystems, Inc. DP Z1 MW1 6A3 PRELIMINARY WRITE ALGORITHM START PROGRAMMING VPP x 12.5 COUNT = @ i WRITE SETUP PROGRAM COMMAND { WRITE VALID DATA TIME OUT 25 ys WRITE PROGRAM VERIFY COMMAND READ DATA FROM DEVICE SET VPP = @V TO VDD +2.0V PROGRAM ERROR NEXT ADORESS WRITE READ COMMAND ! SET VPP = BV TO VOD +2.aVv PROGRAMMING COMPLETED 30A067-00 9 REV. BDP LI MW1 6A3 Dense-Pac Microsystems, Inc. PRELIMINARY ERASE ALGORITHM NO PROGRAM ALL LOCATIONS TO 2280+ ADDRESS = ADDRESS MIN. COUNT = @ WRITE ERASE SETUP COMMAND WRITE ERASE COMMAND WRITE ERASE VERFY COMMAND TIME OUT 6 us READ DATA FROM DEWCE YES SET VPP = Vv TO VDD +2.8v INCREMENT ADDRESS ves WRITE READ COMMAND SET VPP = OV TO VOD +2.0V ERASURE COMPLE TED 10 30A067-00 REV. BDense-Pac Microsystems, Inc. DPZ1MW16A3 PRELIMINARY AUTOMATIC ERASE START AUTOMATIC ERASURE VPP = 12.5V WRITE AUTOERASE SETUP COMMAND WRITE AUTOERASE COMMAND STATUS POLLING ON 1/07, 1/015 3 Vor. 1/or 5 SECONDS LATER ? WRITE READ COMMAND SET vPP = @V TO VDD +2.8V ERASURE COMPLETED 30A067-00 1 REV. B 1DP Z1 MW1 6A3 Dense-Pac Microsystems, Inc. PRELIMINARY ORDERING INFORMATION DP Z iM W 16 A3 XX xX PREFIX DEPTH DESIG. WITH FACRACE SPFED T C COMMERCIAL BC to +7BC 1 INDUSTRIAL -48C to +85'C M_ MILITARY -55C to +125C B MIL-PROCESSED -55C to +125C 12. 12@ns (COMMERCIAL ONLY) 1 158ns 17 178ns 28 228ns 25 258ns _________} 5a PiN PGA/3D DENSE-STACK WORD CONTROLLED WITHOUT LOGIC FLASH EEPROM MECHANICAL DRAWING ft -999+.018 ~I Fae EEE BS Er =e SARS oY Top Oo , mg 8 ee 540.006 PIN Al WNDEX . .828 MAX 258 TYP. SIDE 4 view T .18@ REF. 858 DIA. +.005 t- 045 REF. -188 TYP. 018 DIA. +.082 188 TYP. -408+.005 -9086+.885 Dense-Pac Microsystems, Inc. 7321 Lincoln Way @ Garden Grove, California 92641-1428 (714) 898-0007 @ (800) 642-4477 (Outside CA) @ FAX: (714) 897-1772 12 30A067-00