BU2090FS-TL - ROHM Co., Ltd. - Datasheet.Directory

TECHNICAL NOTE

Serial-in / Parallel-out Driver Series

Serial / Parallel

2-input Driver

BU2098F, BU2090F/FS

●Description

Serial-in-parallel-out driver is a open dr ain o utput driver. It incorporates a built-in shift register and a latch circuit to turn on a

maximum of 12 LED by a 2-line interface, linked to a microcontroller.

A open drain output provides maximum of 25mA current.

●Features

1) LED can be driven directly. (Output current 25mA)

2) 8/12 Bit parallel output

3) This product can be operated on low voltage.

4) Compatible with I2C BUS. (BU2098)

* I2C BUS is a registered trademark of Phillips.

●Use

For AV equipment such as, audio stereo sets, videos and TV sets, PCs, control microcontroller mounted equipment.

ver.C Oct.2007

2/15

●Line up

Parameter BU2098F BU2090F BU2090FS Unit

Output current 25 25 mA

Output line 8 12 lines

Package SOP16 SOP16 SSOP-A16 －

●Thermal derating curv e

●Electrical characteristics

BU2098F (unless otherwise noted, VDD=5V, Vss=0V, Ta=25℃)

Parameter Symbol Min. Typ. Max. Unit Condition

Input High-level voltage VIH 0.7ＸVDD - - V

Input Low-level voltage VIL - - 0.3ＸVDD V

Output Low-level voltage VOL - - 0.4 V IOUT=10mA

Input Low-level current IIL - 2.0 μA VIN=0

Input High-level current IIH - - -2.0 μA VIN=VDD

Output leakage current IOZ - - ±5.0 μA Output=High impedance

VOUT=VDD

Static dissipation current IDD - - 2.0 μA

BU2090F/FS (unless otherwise noted, VDD=5V/3V, VSS=0V, Ta=25℃)

Parameter Symbol Min. Typ. Max. Unit Condition

Input High-level voltage VIH 3.5/2.5* - - V

Input Low-level voltage VIL - - 1.5/0.4* V

Output Low-level voltage VOL - - 2.0/1.0* V IOL=20mA

“H” output disable current IOZH - - 10 μA VO=25V

“L” output disable current IOZL - -5.0 μA VO=0V

Static dissipation current IDD - - 5.0/3.0* μA

(*the value at 5V /3V)

700

600

500

400

300

200

100

025 50 75 100 125 150 175

BU2090F

090

700

600

500

400

300

200

100

025 50 75 100 125 150 175

Ambient temper atur e Ta [℃]

Power dissipation Pd [mW]

BU2098F

85℃

Ambient temper atur e Ta [℃]

Power dissipation Pd [mW]

3/15

●Operating conditions (Ta=25℃, VSS=0V)

Parameter Symbol Limits Unit

BU2098F BU2090F/FS

Power Supply Voltage VDD +2.7～5.5 V

Output Voltage Vo 0～+15 0～+25 V

●Absolute maximum ratings

BU2098F

Parameter Symbol

Limits Unit

BU2098F

Power supply voltage VDD -0.5～+7.0 V

Power dissipation Pd 300 * mW

Operating temperature range Topr -40～+85 ℃

Storage temperature range Tstg -55～+125 ℃

Output voltage Vo VSS～+18.0 V

Input voltage VIN -0.5～VDD+0.5 V

Allowable loss of single unit

* Reduced by 3mW/℃ over 25℃. (BU2098F)

BU2090F/FS

Parameter Symbol Limits Unit

BU2090F BU2090FS

Power supply voltage VDD -0.3～+7.0 V

Power dissipation 1 Pd1 300 *1 500 *2 mW

Power dissipation 2 Pd2 500 *3 650 *4 mW

Operating temperature range Topr -40～+85 ℃

Storage temperature range Tstg -55～+125 ℃

Output voltage Vo VSS-0.3～+25 V

Input voltage VIN V

SS-0.3～VDD+0.3 V

Allowable loss of single unit

*1 Reduced b y 3 m W/℃ over 25℃.

*2 Reduced b y 5 m W/℃ over 25℃.

*3 Reduced by 5.0mW for each increase in Ta of 1℃ over 25℃.(When mounted on a board 70mm×70mm×1.6mm Glass-epoxy PCB)

*4 Reduced by 6.5mW for each increase in Ta of 1℃ over 25℃.(When mounted on a board 70mm×70mm×1.6mm Glass-epoxy PCB)

4/15

●Pin descriptions

BU2098F

PIN No. Pin Name I/O Function

1 A0 I

Address input, internally pull-up

2 A1 I

3 A2 I

4 Q0

O Open drain output

5 Q1

6 Q2

7 Q3

8 VSS - GND

9 Q4

O Open drain output

10 Q5

11 Q6

12 Q7

13 N.C. - Non connected

14 SCL I Serial clock input

15 SDA I/O Serial data input/output

16 VDD - Power supply

BU2090F/FS

PIN No. Pin Name I/O Function

1 VSS - GND

2 DATA I Serial data input

3 CLOCK I

Data shift clock input

(rising edge trigger)

The shift data is transferred to the output when the input data logic

level is high during the falling transition of the clock pulse.

4 Q0

Parallel data output (Nch Open Drain FET)

Latch data L H

Output FET ON OFF

5 Q1

6 Q2

7 Q3

8 Q4

9 Q5

10 Q6

11 Q7

12 Q8

13 Q9

14 Q10

15 Q11

16 VDD - Power supply

5/15

●Block diagram

BU2098F

BU2090F/FS

Power-On Reset

I2C Bus

Controller

Shift

SCL

8bit

Write

Buffer

Q0～Q7

Controller

Shift

12bit

Write

Buffer

Q0～Q11

CLOCK

DAT

6/15

●Interfaces

BU2090F/FS BU2090F/FS

DATA, CLOCK Q0～Q11

BU2098F BU2098F

Q0～Q7 A0～A2

BU2098F BU2098F

SDA SCL

GND (VSS) GND (VSS)

VDD V

GND (VSS)

OUT

GND (VSS)

OUT

GND (VSS)GND (VSS)

VDD VDD

VDD

GND (VSS)

GND (VSS)GND (VSS)

VDD

GND (VSS) GND (VSS)

VDD

GND (VSS)

7/15

【BU2098F】

●AC characteristics (Unless otherwise note d, VDD=5V, VSS=0 V, Ta=25℃)

Parameter Symbol

Fast mode I2Cbus Standard mode I 2Cbus Unit

Min. Max. Min. Max.

SCL clock frequency fSCL 0 400 0 100 kHz

Bus free time between start-stop condition tBUS 1.3 - 4.7 - μs

Hold time start condition tHD:STA 0.6 - 4.0 - μs

Low period of the SCL clock tLOW 1.3 - 4.7 - μs

High period of the SCL clock tHIGH 0.6 - 4.0 - μs

Set up time Re-start condition tSU:STA 0.6 - 4.7 - μs

Data hold time tHD:DAT 0 0.9 0 - μs

Data set up time tSU:DAT 100 - 250 - ns

Rise time of SDA and SCL tR 20+0.1Cb 300 - 1000 ns

Fall time of SDA and SCL tF 20+0.1Cb 300 - 300 ns

Set up time stop condition tSU:STO 0.6 - 4.0 - μs

Capacitive load for SDA line and SC L line Cb - 400 - 400 pF

●Timing chart

Fig.1 SDA, SCL timing chart

tBUS

SDA

tSU:STO

tHD:STA

tSU:STA

tSU:DAT

tLOW

tHD:DAT

P tHD:STA

SCL

8/15

●Function

○Start condition

The start condition is a “HIGH” to “LOW” transition of the SDA line while SCL is “HIGH”.

○Stop condition

The stop condition is a “LOW” to “HIGH” transition of the SDA line while SCL is “HIGH”.

Fig.2 Start / Stop conditi on

○Acknowledge

The master (μp) puts a resistive “HIGH” level on the SDA line during the acknowledge clock pulse. The peripheral

(audio processor) that acknowledge has to pull-down (“LOW”) the SDA line during the acknowledge clock pulse, so

that the SDA line is stable “LOW” during this clock pulse.

The slave which has been addressed has to generate an acknowledgement after the reception of each byte, otherwise

the SDA line remains at the “HIGH” level during the ninth clock pulse time. In this case the master transmitter can

generate the STOP information in order to abort the transfer.

Fig.3 Acknowledge

SCL

Start

condition

Stop

condition

9 8

SCL

(from master)

SDA

(from master)

SDA

(from slave) S

not confirm

ACK signal

confirm

clock for acknowledge

9/15

○Write DATA

Send the stave address from master following the start condition (S). This address consists of 7 bits. The left 1 bit (the

foot bit) is fixed “0”. The stop condition (P) is needed to fin ish the data transferred. But the re-send starting condition

(Sr) enables to transfer the data without STOP (P).

Fig.4 DATA transmit

○Data format

The format is following.

Table 1 for WRIT E format

Slave address A0～A2 Each bit can be defined by the input levels o f pins A0～A3.

A3～A6 These 4 bits are fixed.

R/W “0”

Write Data D0～D7 Write “1” to D0 makes Q0 pin High-impedance. And write “0” makes Q0

pin LOW. D[1:7] and Q[1:7] are same as D0 and Q0.

Table 2 for (A2, A1, A0) to SLAVE ADDRESS

A6 A5 A4 A3 A2 A1 A0 Slave address

0 1 1 1 0 0 0 38H

0 1 1 1 0 0 1 39H

0 1 1 1 0 1 0 3AH

0 1 1 1 0 1 1 3BH

0 1 1 1 1 0 0 3CH

0 1 1 1 1 0 1 3DH

0 1 1 1 1 1 0 3EH

0 1 1 1 1 1 1 3FH

S slave address R/W ACK DATA ACK P

S slave address R/W ACK DATA ACK Sr slave address R/W ACK DATA ACK P

S A6 A5 A4 A3 A2 A1 A0 R/W ACK D6 D5 D4 D3 D2 D1 D0 D7 ACK P

SLA VE ADDRESS WRITE DATA

Fixed for BU2098F Defined by external pin A0～A2

“0” (Write) “0” (Write)

“0” (Write)

10/15

○Data transmission timing

Fig.5 Timing chart for WRITE

Command sample for driving LEDs. These are all off. (terminal A0～A2 is open)

・RESET CONDITION

After reset, Q0～Q7 pins are ON. (LEDs are all ON.)

・RISING TIME OF POWER SUPPLY

DD must rise within 10ms. If the rise time would exceed 10ms, it is afraid not to reset the BU2098F.

Fig.6 Rising time of power supply

VDD

GND

t≦10ms

S A6 A5 A4 A3 A2 A1 A0 R/W ACK D6 D5 D4 D3 D2 D1 D0 D7 ACK P

Slave address Write data

Output the write data to Q7～Q0 at the same time.

SDA

Latch pulse

Output (Q7～Q0)

S 0 1 1 1 1 1 1 0 ACK 1 1 1 1 1 1 1 1ACK P

Slave address Write data

SDA

LEDs all-ON with power supply ON

LEDs are all-off by this command.

Power Supply ON

11/15

【BU2090F/FS】

●AC characteristics (unless otherwise note d, VDD=5V, VSS=0 V, Ta=25℃)

Parameter Symbol Limit Unit Condition

Min. Typ. Max.

Minimum clock frequency tw 500 - - ns VDD=5V

1000 - - ns VDD=3V

Data shift set up time tSU 200 - - ns VDD=5V

300 - - ns VDD=3V

Data shift hold time tH 200 - - ns VDD=5V

400 - - ns VDD=3V

Data latch set up time tLSUH 50 - - ns VDD=5V

100 - - ns VDD=3V

Data latch hold time tLHH 250 - - ns VDD=5V

500 - - ns VDD=3V

Data latch ”L”

set up time tLSUL 200 - - ns VDD=5V

400 - - ns VDD=3V

Data latch ”L”

hold time tLHL 250 - - ns VDD=5V

500 - - ns VDD=3V

●Switching time test circuit

Fig.7

●Switching time test waveforms

Fig.8

CLOCK

Pulse

Gen.

DATA

Pulse

Gen. Q11

RL 10kΩ

±25V

RL 10kΩ

±25V

VDD

GND (Vss)

10% 10% 10% 10%

90%

tW tW

90%

10% 10%

90% 90%

tLSUH tLHHtLSUL tLHL

tHtSU

CLOCK

DATA

VDD

GND (Vss)

VDD

GND (Vss)

12/15

●Timing chart

【BU2098F】

SCL

SDA

VCC

1 2 3 4 5 6 7 89 12345678 9

Start condition Sto

condition

A6 A5 A4 A3 A2 A1 A0 RW ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Device code

Slave address

External terminal

Note) Diagram shows a status where a pull-up resistor is connected to output.

13/15

●Timing chart

【BU2090F/FS】

Note1) Indicates undefined output.

Note2) Output terminal is provided with a pull-up resistor.

CLOCK

DATA

Q11

Q10

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

14/15

●Operation Notes

1. Absolute maximum ratings

An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can

break down the devices, thus making impossible to identif y breaking mode, such as a short circuit or an open circuit. If an y

over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as

fuses.

2. Connecting the power supply co nnector backward

Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply

lines. An external d irection diode can be added.

3. Power supply lines

Design PCB layout pattern to provi de low impedance GND and suppl y lines. To obtain a low noise gro und and supply line,

separate the ground section and supply lines of the digital and analog bloc ks. Furthermore, for all power supply terminals to

ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit,

not that capacitance characteristic values are reduced at low temperatures.

4. GND voltage

The potential of GND pin mus t be minimum potential in all operating conditions.

5. Thermal design

Use a thermal design that allows for a sufficient margin in light of the po wer dissipation (Pd) in actual operating conditions.

6. Inter-pin shorts and mounting errors

Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any

connection error or if pins are shorted together.

7. Actions in strong electromagnetic field

Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.

8. Testing on application boards

When testing the IC on an application board, conn ecting a capacitor to a pin with lo w impedance su bjects the IC to stress.

Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or

removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure.

Use similar precaution when transporting or storing the IC.

9. Ground Wiring Pattern

When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing

a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused

by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern

of any external components, either.

10. Unused input terminals

Connect all unused input terminals to VDD or VSS in order to prevent excessive current or oscillation.

Insertion of a resistor (100kΩ approx.) is also recommended.

15/15

●Type Designations (Selecti ons) for Ordering

B U 20 9 F ―E 2

Product name

・BU2098

・BU2090

Packa

e t

F : SOP16

FS : SSOP-A16

E1 Emboss tape reel Pin 1 on dra

-out side

E2 Emboss tape reel Pin 1 opposite draw-out side

TL Emboss tape reel Pin 1 on dra w-out side

TR Emboss tape reel Pin 1 opposite draw-out side

Tape

Quantity

Direction

of feed

Embossed carrier tape

2500pcs

(The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand)

Reel

1Pin

1234

SOP16

(Unit:mm)

0.15±0.1

0.3Min.

4.4±0.2

6.2±0.3

0.11

1.5±0.1

0.4±0.1

16 10.0±0.2

1.27 0.1

Direction of feed

※When you order , please order in times the amount of package quantity.

(Unit:mm)

SSOP-A16

6.6±0.2

4.4±0.2

6.2±0.3

0.11

1.5±0.1

0.36±0.1

0.3Min.

0.8

0.15±0.1

0.1

Tape

Quantity

Direction

of feed

Embossed carrier tape

2500pcs

(The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand)

Reel

1Pin

1234

Direction of feed

※When you order , please order in times the amount of package quantity.

Notes

No technical content pages of this document may be reproduced in any form or transmitted by any

means without prior permission of ROHM CO.,LTD.

The contents described herein are subject to change without notice. The specifications for the

product described in this document are for reference only. Upon actual use, therefore, please request

that specifications to be separately delivered.

Application circuit diagrams and circuit constants contained herein are shown as examples of standard

use and operation. Please pay careful attention to the peripheral conditions when designing circuits

and deciding upon circuit constants in the set.

Any data, including, but not limited to application circuit diagrams information, described herein

are intended only as illustrations of such devices and not as the specifications for such devices. ROHM

CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any

third party's intellectual property rights or other proprietary rights, and further, assumes no liability of

whatsoever nature in the event of any such infringement, or arising from or connected with or related

to the use of such devices.

Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or

otherwise dispose of the same, no express or implied right or license to practice or commercially

exploit any intellectual property rights or other proprietary rights owned or controlled by

ROHM CO., LTD. is granted to any such buyer.

Products listed in this document are no antiradiation design.

Appendix1-Rev2.0

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More detail product informations and catalogs are available, please contact your nearest sales office.

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www.rohm.com

The products listed in this document are designed to be used with ordinary electronic equipment or devices

(such as audio visual equipment, office-automation equipment, communications devices, electrical

appliances and electronic toys).

Should you intend to use these products with equipment or devices which require an extremely high level

of reliability and the malfunction of which would directly endanger human life (such as medical

instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers

and other safety devices), please be sure to consult with our sales representative in advance.

It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance

of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow

for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in

order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM

cannot be held responsible for any damages arising from the use of the products under conditions out of the

range of the specifications or due to non-compliance with the NOTES specified in this catalog.

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FAX : +81-75-315-0172

Appendix