DS04-27203-8Ea
FUJITSU MICROELECTRONICS
DATA SHEET
Copyright©1994-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2006.5
ASSP
BIPOLAR
Switching Regulator Controller
MB3778
■DESCRIPTION
The MB3778 is a dual switching regulator control IC. It has a two-channel basic circuit that controls PWM system
switching regulator power. Complete synchronization is achieved by using the same oscillator output wave.
This IC can accept any two of the following types of output voltage: step-down, step-up, or voltage inversion
(inverting voltage can be output to only one circuit). The MB3778’s low pow er consumption makes it ideal for use
in portable equipment.
■FEATURES
• Wide input voltage range : 3.6 V to 18 V
• Low current consumption : 1.7 mA Typ operation, 10 µA Max stand-by
• Wide oscillation frequency range:1 kHz to 500 kHz
• Built-in timer latch short-circuit protection circuit
• Built-in under-voltage lockout circuit
• Built-in 2.46 V reference voltage circuit : 1.23 V output can be obtained from RT terminal
• Vari able dead-t im e provides co ntr ol over total range
• Built-in stand-by function: power on/off function
• Two types of packages (SOP-16pin :1 type, SSOP-16pin :1 type)
■APPLICATIONS
• LCD monitor/panel
• Surveillance camera etc.
MB3778
2
■PIN ASSIGNMENT
(TOP VIE W)
1
2
3
4
5
6
7
8
CT
RT
+IN1
−IN1
FB1
DTC1
OUT1
E/GND
VREF
SCP
CTL
−IN2
FB2
DTC2
OUT2
VCC
16
15
14
13
12
11
10
9
(FPT-16P- M 05)
(FPT-16P- M 06)
MB3778
3
■PIN DESCRIPTION
No. Pin Function
1C
TOscillator timing capacitor terminal (150 pF to 15,000 pF) .
2R
TOscillator timing resistor terminal (5.1 kΩ to 100 kΩ) .
VREF × 1/2 voltage is also available at this pin for error amplifier reference input.
3+IN1 Error amplifier 1 non-inverted input terminal.
4−IN1 Error amplifier 1 inverted input terminal.
5FB1
Error amplifier 1 output terminal.
A resistor and a capacitor are connected between this terminal and the −IN1 terminal to adjust
gain and frequency.
6DTC1
OUT1 dead-time control terminal.
Dead-time control is adjusted by an external resistive divider connected to the VREF pin.
A capacitor connected between this terminal and GND enables soft-start operation.
7OUT1
Open collector output terminal.
Output transistor has common ground independent of signal ground.
This output can source or sink up to 50 mA.
8 E/GND Ground terminal.
9V
CC Power supply terminal (3.6 V to 18 V)
10 OUT2 Open collector output terminal.
Output transistor has common ground independent of signal ground.
This output can source or sink up to 50 mA.
11 DTC2 Sets the dead-time of OUT2.
The use of this terminal is the same as that of DTC1.
12 FB2
Error amplifier 2 output terminal.
Sets the gain and adjusts the frequency when a resistor and a capacitor are connected
between this terminal and the −IN2 terminal.
Voltage of VREF × 1/2 voltage is internally connected to the non-inverted input of error amplifier
2. Uses error amplifier 2 for positive vol tage output.
13 −IN2 Error amplifier 2 inverted input terminal.
14 CTL
Power control terminal.
The IC is set in the stand-by state when this terminal is set “Low.”
Current consumption is 10 µA or lower in the stand-by state.
The input can be driven by TTL or CMOS.
15 SCP
The time constant setting capacitor connection terminal of the timer latch short-circuit
protection circuit.
Connects a capacitor between this pin and GND.
For de tai ls, see “ ■ HOW TO SET TIME CONSTANT FOR TIMER LATCH SHORT-CIRCUIT
PROTECTION CIRCUIT”.
16 VREF 2.46 V reference voltage output terminal which can be obtained up to 1 mA.
This pin is used to set the reference input and idle period of the error amplifiers.
MB3778
4
■BLO C K DIAGRAM
−
+
−
+
−
+
+
−
+
+
−
+
−
−
+
−
1.1 V
1.23 V
2.1 V
2.46 V
1.9 V
1.3 V
1.23 V
2.46 V
1 µA
2.46 V
9
16
3
4
5
12
13
15
611
10
7
2
1
8
OUT1
OUT2
PWM Comp.1
PWM Comp.2
R
U. V. L. O.
R S
Latch
D.T.C. Comp.
Error Amp 2
Error Amp 1 S.C.P. Comp.
14
Reference
Voltage Triangular
Oscillator
Power
Supply
Control
MB3778
5
■OPERATION DESCRIPTION
1. Reference voltage circuit
The reference voltage circuit generates a temperature-compensated reference voltage ( := 2.46 V) from VCC
terminal (pin 9) . The reference voltage is used as an operation power supply for internal circuit.
The reference is obtained from the VREF terminal (pin 16).
2. Triangular wave oscillator
Tri angular wave for ms can be generated at any freque ncy by connect ing a timing capacitor an d resistor to the
CT terminal (pin 1) and to the RT terminal (pin 2) .
The amplitude of this waveform is from 1.3 V to 1.9 V. These waveforms are connected to the non-inverting
inputs of the PWM comparator and can be output through the CT terminal (pin 1) .
3. Error amplifiers (Error Amp)
The er ror am plifi er detect s the o utput voltage o f the switchin g regu lator and out puts P WM co ntrol s ignals.The
in-phase input voltage range is from 1.05 V to 1.45 V.The reference voltage obtained by dividing the reference
voltage output (r ec omm end ed value : VREF/2) or the RT terminal (p in 2 ) voltage (1 .23 V) is su ppl ie d to th e non-
inverting input. The VREF/2 voltage is internally connected to non-inverting input of the other error amplifier.
Any loop ga in c an be c hosen by c onn ec tin g t he feedback resisto r and c ap ac itor to the i nverti ng i npu t te rmin al
from the output terminal of the error amplifier.Stable phase compensation is possible.
4. Timer latch short circuit protection circuit
This circuit detects the output levels of each error amplifier. If the output level of one or both of the error amplifiers
is 2.1 V or higher, the timer circuit begins charging the externally connected protection enable-capacitor.
If the output level of the error amplifier does not drop below the normal voltage range before the capacitor voltage
reaches the transistor base-emitter vo ltage, VBE( := 0.65 V), the latc h circuit tur ns the output dr i ve transis tor off
and sets the idle period to 100%.
5. Under voltage lock-out circuit
The transition state at power-on or a momentary drops in supply voltage may cause the control IC to malfunction,
which may adversely affect or even destroy the system. The under voltage lockout circuit monitors VCC with
reference to the internal reference voltage and resets the latch circuit to turn the output drive transistor off. The
idle period is set to 100%. It also pulls the SCP terminal (pin 15) “Low”.
6. PWM comparator unit
Each PWM compa rator has one i nver t ing i nput an d two non-invert ing i nputs. This voltage-to- pulse- width c on-
verter controls the turning on time of the output pulse according to the input voltage.
The PWM comparator turns the output drive transistor on while triangular waveforms from the oscillator are
lower than the error amplifier output and the DTC terminal voltage.
7. Output drive transistor
The output drive transistors have open collector outputs with common source supply and common grounds
independent of VCC and signal ground. The output drive transistors for switching can sink or source up to 50 mA.
8. Power control unit
The CTL terminal (pin 14) controls power on/off modes(the power supply current in stand-by mode is 10 µA or
lower).
MB3778
6
■ABSOLUTE MAXIMUM RATINGS
*1:The packages are mounted on the epoxy board (4 cm × 4 cm)
*2:The packages are mounted on the epoxy board (10 cm × 10 cm)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
Parameter Symbol Condition Rating Unit
Min Max
Power Supply Voltage VCC 20 V
Error Amp Input Voltage VIN −0.3 +10 V
Control Input Voltage VCTL −0.3 +20 V
Collector Output Voltage VOUT 20 V
Collector Output Current IOUT 75 mA
Power Dissipation PDTa ≤ +25 °C (SOP) 620*1mW
Ta ≤ +25 °C (SSOP) 444*2mW
Operating Ambient Temperature Ta −30 +85 °C
Storage Temperature Tstg −55 +125 °C
Parameter Symbol Value Unit
Min Typ Max
Power Supply Voltage VCC 3.6 6.0 18 V
Error Amp Input Voltage VIN 1.05 1.45 V
Control Input Voltage VCTL 018 V
Collector Output Voltage VOUT 18 V
Collector Output Current IOUT 0.3 50 mA
Timing Capacitor CT150 15000 pF
Timing Resistor RT5.1 100 kΩ
Oscillator Frequency fOSC 1500 kHz
Operating Ambient Temperature Ta −30 +25 +85 °C
MB3778
7
■ELECTRICAL CHARACTERISTICS (Ta = +25 °C, VCC = 6 V)
(Continued)
Parameter Symbol Condition Value Unit
Min Typ Max
Reference Block
Output Voltage VREF IOR = −1 mA 2.41 2.46 2.51 V
Output Temp. Stability VRTC Ta = −30 °C to +85 °C−2±0.2 +2%
Input Sta bil it y Line VCC = 3.6 V to 18 V 210mV
Load Sta bil it y Load IOR = −0.1 mA to −1 mA 17.5mV
Short Circuit Output Current IOS VREF = 2 V −30 −10 −3mA
Under Voltage Lockout Protection Block
Threshold Voltage VtH IOR = −0.1 mA 2.72 V
VtL IOR = −0.1 mA 2.60 V
Hysteresis Width VHYS IOR = −0.1 mA 80 120 mV
Res et Voltage (VCC) VR1.5 1.9 V
Protection Circuit Block (S.C.P.)
Input Thr esh ol d Volt age VtPC 0.60 0.65 0.70 V
Input Stand by Vol tag e VSTB No pull up 50 100 mV
Input Latch Voltag e VIN No pull up 50 100 mV
Input Sour ce Cur rent Ibpc −1.4 −1.0 −0.6 µA
Comparator Threshold Voltage VtC Pin 5, Pin 12 2.1 V
Triangular Waveform Oscillator Block
Oscillator Frequency fOSC CT = 330 pF, RT = 15 kΩ160 200 240 kHz
Frequency Deviation fdev CT = 330 pF, RT = 15 kΩ ±5%
Frequency Stability (VCC) fdV VCC = 3.6 V to 18 V ±1%
Frequency Stability (Ta) fdT Ta = −30 °C to +85 °C−4+4%
Dead-Time Control Block (D.T.C.)
Input Bias Current Ibdt 0.2 1 µA
Latch Mode Sink Current Idt Vdt = 2.5 V 150 500 µA
Latch Input Voltage Vdt Idt = 100 µA0.3 V
MB3778
8
(Continued) (Ta = +25 °C, VCC = 6 V)
Parameter Symbol Condition Value Unit
Min Typ Max
Error Amp Block
Input Offse t Voltage VIO VO = 1.6 V −6+6mV
Input Offset Curren t IIO VO = 1.6 V −100 +100 nA
Input Bias Current IBVO = 1.6 V −500 −100 nA
Common Mode Input Voltage
Range VICR VCC = 3.6 V to 18 V 1.05 1.45 V
Voltage Gain AVRNF = 200 kΩ70 80 dB
Frequency Band Width BW AV = 0 dB 1.0 MHz
Common Mode Rejection Ratio CMRR 60 80 dB
Max Output Voltage Width VOM+VREF
− 0.3 V
VOM−0.7 0.9 V
Output Sink Current IOM+VO = 1.6 1.0 mA
Output Source Current IOM−VO = 1.6 −60 µA
PWM Comparator Block
Input Thr esh ol d Volt age
(fOSC = 10 kHz) Vt100 Duty Cycle = 100%1.9 2.25 V
Vt0 Duty Cycle = 0%1.05 1.3 V
On duty Cycle Dtr Vdt = VREF/1.45 55 65 75 %
Input Sink Current IIN+Pin 5, Pin 12 = 1.6 V 1.0 mA
Input Sour ce Cur rent IIN−Pin 5, Pin 12 = 1.6 V −60 µA
Control Block
Input Off Condit ion VOFF 0.7 V
Input On Condition VON 2.1 V
Control Terminal Current ICTL VCTL = 10 V 200 400 µA
Output Block
Output Leak Current Leak VO = 18 V 10 µA
Output Saturation Voltage VSAT IO = 50 mA 1.1 1.4 V
All Device Block
Stand-by Current ICCS VCTL = 0 V 10 µA
Average Supply Current ICCa VCTL = VCC, No Output
Load 1.7 2.4 mA
MB3778
9
■TEST CIRCUIT
■TIMING CHART (Internal Waveform)
4.7 kΩ
330 pF
16 15 14 13 12 11 10 9
12345678
MB3778
4.7 kΩ
15 kΩ
TEST INPUT
OUTPUT 1
OUTPUT 2
TEST INPUT
SW
CTL
CPE
VCC = 6 V
Power “OFF”
Short circuit protection
comparator Reference
input
Dead Time, PWM input
voltage
Triangular waveform oscillator output
Error Amp output
PWM comparator
output
Output Transistor
collector waveform
S.C.P. Terminal
waveform
Short circuit protection
comparator output
Control Input
voltage (VCTL : Min Value)
(VCC : Min Value)
Power supply voltage
Power “ON”
Protection Enable Time tPE 0.6 × 106 × CPE (µs)
0 V
3.6 V
0 V
2.1 V
"Low"
"High"
0.05 V
0.65 V
"Low"
"High"
"Low"
"High"
2.1 V
1.9 V
1.6 V
1.3 V
tPE
DEAD TIME 100%
MB3778
10
■APPLICATION CIRCUIT
• Chopper Type Step Down/inverting
220 µF
330 Ω
CTL
220 µF
1 µF
220 µF
1 µF
0.033
µF
0.1 µF
0.033
µF
330 Ω
5.6 kΩ
2.4 kΩ
9.1 kΩ
330 Ω
330 Ω
10 kΩ
1.8 kΩ
8.2 kΩ
4.7 kΩ
1.8 kΩ
4.7 kΩ
4.7 kΩ10 kΩ
150
kΩ
820 pF
120 µH
120 µH
56 µH
VIN (10 V)
MB3778
− + − +
− +
+ −
− +
150
kΩ
116
2
3
4
5
6
7
8
15
14
13
12
11
10
9
GND
VO−
( −5 V) VO+
( 5 V)
MB3778
11
• Chopper Type Step Up/Inverting
220 µF
CTL
220 µF
1 µF
220 µF
1 µF
0.033
µF
0.1 µF
0.033
µF
3.9 kΩ
16 kΩ
4.7 kΩ
9.1 kΩ
330 Ω
330 Ω
10 kΩ
1.8 kΩ
8.2 kΩ
4.7 kΩ
1.8 kΩ
4.7 kΩ
4.7 kΩ10 kΩ
150
kΩ
820 pF
120 µH
120 µH
56 µH
VIN (5 V)
MB3778
− ++ −
− +
+ −
− +
150
kΩ
116
2
3
4
5
6
7
8
15
14
13
12
11
10
9
GND
100 Ω
VO+
( 5 V)
VO−
( −5 V)
MB3778
12
• Multi Output Type (Apply Transformer)
220 µF
0.1 µF
0.033
µF
10 kΩ
1.8 kΩ
MB3778 150
kΩ
116
2
3
4
5
6
7
8
15
14
13
12
11
10
9
220 µF 220 µF 220 µF
220 Ω
5.6 kΩ
1.8 kΩ
220 µF
820 pF
1000 pF
4.7 kΩ
8.2 kΩ
56 µH
GND
CTL VIN (10 V)
− +
− +
− +
VO1+
( 12 V)
VO2+
( 5 V)
VO1−
( −5 V)
VO2−
( −12 V)
− +− +
MB3778
13
■HOW TO SET THE OUTPUT VOLTAGE
The output voltage is set using the connections shown in “Connection of error Amp Output Voltage V0 ≥ 0” and
“Connection of Error Amp Output Voltage V0 < 0”.
The error amplifier power is supplied by the reference voltage circuit as is that of the other internal circuits. The
common mode input voltage range is from 1.05 V to 1.45 V.
Set 1.23 V (VREF/2) as the reference input voltage that is connected to either inver ting or non-inverting input
terminals.
• Connection of Error Amp Output Voltage V0 ≥ 0
• Connection of Error Amp Output Voltage V0 < 0
RR2
RR1
RNF
VREF VO
VOVREF
2 × R2(R1 + R2)
+
=
−
+
+
PIN 5 or PIN 12
RR
2
RR
1
R
NF
V
REF
V
O
V
REF
2 × R
1
(R
1
+ R
2
) + V
REF
+
= −
V
O
−
−
−
PIN 5
MB3778
14
■HOW TO SET TIME CONSTANT FOR TIMER LATCH SHORT-CIRCUIT
PR OTECTION CIRCUIT
Below Figure shows the configuration of the protection latch circuit.
Each error amplifier output is connected to the inverting inputs of the short-circuit protection comparator and is
always compared with the reference voltage (2.1 V) connected to the non-inverting input.
When the load condition of the switching regulator is stable, the error amplifier has no output fluctuation. Thus,
short-circuit protection control is also kept in balance, and the SCP terminal (pin 15) voltage is held at about 50 mV .
If the load changes drastically due to a load short-circuit and if the inverting inputs of the short-circuit protection
comparat or go above 2.1 V, th e s hort-circui t pr ote ction co mpa rator o utpu t go es “L ow” to t urn off transistor Q1.
The SCP terminal voltage is discharged, and then the short-circuit protection comparator charges the protection
enable capacitor CPE according to the following formula :
VPE = 50 mV + tPE × 10 − 6 / CPE
0.65 = 50 mV + tPE × 10 − 6 / CPE
CPE = tPE / 0.6 (µF)
When the protection enable capacitor is charged to about 0.65 V, the protection latch is set to enable the under
voltage lockout circ uit and th e output dr ive trans istor is t urned off. T he idle p eriod is also se t to 100 % at the
same time.
Once the under voltage lockout circuit is enabled, the protection enable is released; however, the protection
latch is not reset if the power is not turned off.
The in v erting inputs (pin 6 or 11) of the D.T.C. comparator are compared to the reference voltage (about 1.1 V)
connected to the non-inverting input.
To prevent m alfunctio n of the short-circu it protection -circuit when the soft-star t op eration is done by using the
DTC ter min al (pin 6 or 11) , the D.T.C. comparator outp uts a “High” level while the DT C term inal (pin 6 or 11)
goes up to about 1.1 V, and then closes the SCP terminal (pin 15) by turning transistor Q2 on.
• Protection Latch Circuit
2.46 V
1 µA
Q
1
C
PE
2.1 V
1.1 V
−
+
−
−
+
6
11
D.T.C. Comp.
S.C.P. Comp.
Q
2
Q
3
DTC1
DTC2
U.V.L.O.
S R
Latch
SCP
R
1
Error Amp1
Error Amp2
15
−
MB3778
15
■SETTING THE IDLE PERIOD
When voltage step-up, fly-back step-up or inv erted output are set, the voltage at the FB terminal may go higher
than the tr iangul ar wave vo ltage due to lo ad fluctuati on, etc. In this case the ou tput transistor will be in full-on
state(ON duty 100%). This can be prev ented by setting the maximum duty for the output transistor . This is done
by setting the DTC1 terminal (pin 6) voltage using resistance division of the VREF voltage as illustrated below.
When the DTC1 terminal voltage is higher than the triangular waveform voltage, the output transistor is turned
on. If th e tria ngular wavefor m amplit ude specified by the maximum duty calculatio n for mula is 0.6 V , and the
lower voltage limit of the triangular waveform is 1.3 V, the formula would be as follows (other channels are similar) :
Duty (ON) max (%) := (Vdt − 1.3 V) / 0.6 V × 100, Vdt (V) = Rb / (Ra + Rb) × VREF
Also, if no output duty setting is required, the voltage shou ld be set greater than the upp er limit volta ge of the
triangular wav eform, which is 1.9 V.
• Setting the idle time at DTC1 (DTC2 is similar)
VREF
Ra
Rb Vdt
DTC1
16
6
MB3778
16
■SETTING THE SOFT START TIME
When power is s witched on, the current begins charging the capacitor (CDTC1) connected the DTC1 terminal (pin
6). The soft start process operates by comparing the soft start setting voltage, which is proportional to the DTC1
terminal voltage, with the triangular waveform, and varying the ON-duty of the OUT terminal (pin 7).
The soft start time until the ON duty reaches 50% is determined by the following equation:
Soft start time (time until output ON duty = 50%) .
ts (s) := − CDTC1 × Ra × Rb / (Ra + Rb) × ln (1 − 1.6 (Ra + Rb) / (2.46 Rb) )
For example, if Ra = 4.7 kΩ and Rb = 10 kΩ, the result is:
ts (s) := 0.01 × CDTC1 (µF)
• Soft Start on DCT1 terminal (DTC2 is similar)
VREF
Ra
Rb CDTC1
DTC1
16
6
MB3778
17
■USING THE RT TERMINAL
The triangular wav es, as shown in Figure “No VREF/2 connection to external circuits from RT terminal”, act to set
the oscillator frequency by charging and discharging the capacitor connected to the CT terminal using the current
value of the resistor connected to the RT termi nal .
In additi on, when voltage level VREF/2 is output to exte rnal ci rcuits from the RT terminal (pin 2) , care must be
taken in making the external circuit connections to adjust for the fact that I1 is increased by the value of the
current I2 to the external circuits in determining the oscillator frequency (see Figure “VREF/2 connection to external
circuits from RT terminal”).
• No VREF/2 connection to external circuits from RT terminal
• VREF/2 connection to external circuits from RT term in al
2 1
ICT
CT
RT
IRT
ICT = IRT
VREF
2RT
=
VREF
2
( )
Triangular wave
oscillator
Triangular wave
oscillator
2 1
ICT
CT
RT
IRT
ICT = IRT
VREF
2RT
= + I2
VREF
2
( )
I1
I2
= I1 + I2
To external circuits
MB3778
18
■SYNCHRONIZATION OF ICs
A fixed condenser and resistor are inser ted in the CT and RT terminals of IC which becomes a master when
sync hroni zi ng by usin g plu rality of M B3 778 . As a res ul t, the s lave ICs os ci ll ate autom ati ca ll y. The RT terminals
(pin 2) of the slave ICs are connected to the VREF ter minal (pin 16) to disable the charge/discharge circuit for
triangular wave oscillation. The CT terminals of the master and slave ICs are connected together.
• Connection of Master, Slave
CTRT
VCC
MB3778
(MASTER)
MB3778
(SLAVE)
MB3778
(SLAVE)
MB3778
19
■TYPICAL CHARACTERISTICS
(Continued)
Power supply voltage VCC (V)
Reference voltage VREF (V)
0 4 8 12 16 20
0
2.5
5.0 Ta = +25 °C
Power supply voltage V
CC
(V)
Average supply current I
CCa
(mA)
0 4 8 12 16 20
0
1.0
2.0 Ta = +25 °C
Operating ambient temperature Ta (°C)
Reference voltage VREF (V)
0
2.40
2.41
2.42
2.47
2.46
2.44
2.45
2.43
−40 +20 +40 +60 +80 +100−20
VCC = VCTL = 6 V
IOR = −1 mA
Timing capacitor CT (pF)
Triangular waveform Upper / Lower Limit voltage (V)
102
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
103104
VCC = 6 V
RT = 15 kΩ
Ta = +25 °C
Upper limit
Lower limit
Sink current (mA)
Collector saturation voltage (V)
0
0
1.0
2.0
3.0
4.0
5.0
100 200 300 400 500
VCC = 6 V
Ta = +25 °C
Frequency (Hz)
Error Amp Max output voltage (V)
0
100 500 1 k 5 k 10 k 50 k 100 k 500 k
1.0
2.0
3.0 VCC = 6 V
Ta = +25 °C
Reference voltage vs. Power supply voltage Average supply current vs. Power supply voltage
Reference voltage vs.
Operating ambient temperature Triangular waveform Upper/Lower Limit voltage vs.
Timing capacitor
Collector saturation voltage vs.
Sink Current Error Amp Max output voltage vs.
Frequency
MB3778
20
(Continued)
Timing resistor RT (Ω)
Oscillation frequency fOSC (Hz)
1 M
100 k
10 k
1 k
1 k 5 k 10 k 50 k100 k 500 k
CT = 15000 pF
CT = 1500 pF
CT = 150 pF
VCC = 6 V
Ta = +25 °C
Triangular waveform cycle (µs)
Timing capacitor CT (pF)
100
10
1102103104105
VCC = 6 V
RT = 15 kΩ
Ta = +25 °C
Operating ambient temperature Ta (°C)
Frequency stability f
dT
(%)
10
0
−10 −40 −20 0 +20 +40 +60 +80 +100 +120
V
CC
= 6 V
C
T
= 330 pF
R
T
= 15 kΩ
Oscillation frequency fOSC (Hz)
ON duty cycle Dtr (%)
100
80
60
40
20
05 k 10 k 50 k 100 k 500 k 1 M
VCC = 6 V
CT = 330 pF
RT = 15 kΩ
Ta = +25 °C
Control voltage VCTL (V)
Reference voltage VREF (V)
5.0
2.5
0012345
VCC = 6 V
Ta = +25 °C
Control input voltage VCTL (V)
Control terminal current ICTL (µA)
500
250
0048121620
VCC = 6 V
Ta = +25 °C
Oscillation frequency vs.Timing resistor Triangular waveform cycle vs.
Timing capacitor
Frequency stability vs.
Operati ng ambient temperatu re ON duty cycle vs. Oscillation frequency
Reference voltage vs. Control voltage Control terminal current vs. Control input voltage
MB3778
21
(Continued)
40
20
0
−20
−40
10 100 1 k 10 k 100 k 1 M
−180
−90
0
90
180
AV
φ
Frequency f (Hz)
Voltage gain AV (dB)
Phase φ (deg)
CNF = OPEN
Frequency f (Hz)
Voltage gain A
V
(dB)
Phase φ (deg)
40
20
0
−20
−40
10 100 1 k 10 k 100 k 1 M
−180
−90
0
90
180
C
NF
= 0.047 µF
A
V
φ
Frequency f (Hz)
Voltage gain AV (dB)
Phase φ (deg)
40
20
0
−20
−40
10 100 1 k 10 k 100 k 1 M
−180
−90
0
90
180
CNF = 470 pF
AV
φ
Frequency f (Hz)
Voltage gain AV (dB)
Phase φ (deg)
40
20
0
−20
−40
10 100 1 k 10 k 100 k 1 M
−180
−90
0
90
180
CNF = 4700 pF
AV
φ
Error Amp
−
+
+
−
10 µF
C
NF
240 kΩ
V
REF
V
REF
IN
4.7 kΩ4.7 kΩ
4.7 kΩ
4.7 kΩ
OUT
Voltage gain/Ph ase vs. Freq uency Voltage gain/P hase vs. Fr equ ency
(Actual Data)
Voltage gain/Phase vs. Freque ncy
(Actual Data) Voltage gain/Phase vs. Frequency
(Actual Data)
Actual Circuit
MB3778
22
(Continued)
Power dissipation
PD (mW)
Operating ambient temperature Ta (°C)
700
600
500
400
300
200
100
0
620
−40 −20 0 +20 +40 +60 +80 +100
Power dissipation
P
D
(mW)
Operating ambient temperature Ta (°C)
−40 −20 0 +20 +40 +60 +80 +100
500
400
300
200
100
0
444
Power Dissi p atio n vs.
Operating ambient temperature (SOP) Power Dissipation vs.
Operating ambient temperature (SSOP)
MB3778
23
■EQUIVALENT SERIES RESISTOR AND STABILITY OF SMOOTHING CAPACITOR
The equiv alent series resistor (ESR) of the smoothing capacitor in the DC/DC conv erter greatly aff ects the loop
phase characteristic.
The stability of the system is improved so that the phase characteristic may advance the phase to the ideal
capacitor by ESR in the high frequency region (see “Voltage gain vs. Frequency” and “Phase vs. Frequency”).
A smoothing capacitor with a low ESR reduces system stability. Use care when using low ESR electrolytic
capacitors (OS-CONTM) and tantalum capacitors.
Note: OS-CON is a trademark of Sanyo Electric Co., Ltd.
VIN D
L
RC
RL
C
Tr
DC/DC Converter Basic Circuit
10 100 1 k 10 k 100 k
−60
−40
−20
0
20
(1) : RC = 0 Ω
(2) : RC = 31 mΩ(1)
(2)
Frequency f (Hz)
Voltage gain AV (dB)
10 100 1 k 10 k 100 k
−180
−90
0
(1) : RC = 0 Ω
(2) : RC = 31 mΩ
(2)
(1)
Frequency f (Hz)
Phase φ (deg)
Voltage gain vs. Frequency Phase vs. Frequency
MB3778
24
• Reference data
If an alumi num elect rolyt ic smoo thing c apaci tor (RC ≅ 1.0 Ω) is repl aced wi th a low ESR ele ctroly tic ca pacito r
(OS-CONTM : RC ≅ 0.2 Ω), the phase margin is reduced by half(see Fig.1 and Fig.2).
AV vs. φ characteristic
Between these points
Error Amp
−
+
CNF
VOUT
FB
VREF/2
R1
R2VIN
−IN
+IN
VO+
DC/DC Converter AV vs. φ characteristic Test Circuit
Figure 2 DC/DC Converter +5 V output Voltage gain/Phase vs. Frequency
Phase φ (deg)
Voltage gain AV (dB)
AI Capacitor
220 µF (16 V)
RC ≅ 1.0 Ω : fOSC = 1 kHz
VO+
GND
+
−
60
40
20
0
−20
−4010 100 1 k 10 k 100 k
62 °
AVφ
−180
−90
0
90
180
VCC = 10 V
RL = 25 Ω
CP = 0.1 µF
Frequency f (Hz)
Phase φ (deg)
Frequency f (Hz)
Voltage gain A
V
(dB)
OS-CON
TM
22 µF (16 V)
R
C
≅ 0.2 Ω : f
OSC
= 1 kHz
V
O
+
GND
+
−
60
40
20
0
−20
−4010 100 1 k 10 k 100 k
27 °
A
V
φ
−180
−90
0
90
180
V
CC
= 10 V
R
L
= 25 Ω
C
P
= 0.1 µF
Figure 1 DC/DC Converter +5 V output Voltage gain/Phase vs. Frequency
MB3778
25
■NOTES ON USE
• Take account of common impedance when designing the earth line on a printed wiring board.
• Take measures against static electricity.
- For semiconductors, use antistatic or conductive containers.
- When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container.
- The work table, tools and measuring instruments must be grounded.
- The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series.
• Do not apply a negative voltage
- Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in
malfunction.
■ORDERING INFORMATION
■RoHS Compliance Information of Lead (Pb) Free version
The LS I products of Fujits u Microele ctronic s with “E1 ” are com pliant wit h RoHS Dir ective , and has o bser ved
the standard of lead, cadmium, mercury, Hexa valent chromium, polybrominated biphenyls (PBB) , and polybro-
minated diphenyl ethers (PBDE) .
The product that conforms to this standard is added “E1” at the end of the part number.
Part number Package Remarks
MB3778PFV-❏❏❏ 16-pin plastic SSOP
(FPT-16P-M05) Conventional version
MB3778PF-❏❏❏ 16-pin plastic SOP
(FPT-16P-M06) Conventional version
MB3778PFV-❏❏❏E1 16-pin plastic SSOP
(FPT-16P-M05) Lead Free version
MB3778PF-❏❏❏E1 16-pin plastic SOP
(FPT-16P-M06) Lead Free version
MB3778
26
■MARKING FORMAT (Lead Free version)
INDEX
MB3778
XXXX XXX
E1
INDEX
3778
E1XXXX
XXX
Lead Free version
Lead Free version
SSOP-16
(FPT-16P-M05)
SOP-16
(FPT-16P-M06)
MB3778
27
■LABELING SAMPLE (Lead free version)
2006/03/01
ASSEMBLED IN JAPAN
G
QC PASS
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
1,000
PCS
0605 - Z01A
1000
1/1
1561190005
MB123456P - 789 - GE1
MB123456P - 789 - GE1
MB123456P - 789 - GE1
Pb
Lead Free version
lead-free mark
JEITA logo JEDEC logo
MB3778
28
■MB3778PF-❏❏❏E1, MB3778PFV-❏❏❏E1
RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL
[Temperature Profile for FJ Standard IR Reflow]
(1) IR (infrared reflow)
(2) Manual soldering (partial heating method )
Conditi ons : Temperature 400 °C Max
Times : 5 s max/pin
Item Condition
Mounting Method IR (infrared reflow) , Manual soldering (partial heating method)
Mounting tim es 2 times
Storage period
Before opening Please use it within two years after
Manufacture.
From opening to the 2nd
reflow Less than 8 days
When the storage period after
opening was exceeded Please processes within 8 days
after baking (125 °C, 24H)
Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
260 °C
(e)
(d')
(d)
255 °C
170 °C
190 °C
RT (b)
(a)
(c)
to
Note : Temperature : the top of the package body
(a) Te mperat ure Incr ease grad ient : Average 1 °C/s to 4 °C/s
(b) Preliminary heating : Temperature 170 °C to 190 °C, 60s to 180s
(c) Tem perat ure Increas e grad ient : Aver age 1 °C/s to 4 °C/s
(d) Actual heating : Temperature 260 °C Max; 255 °C or more, 10s or less
(d’) : Temperature 230 °C or more, 40s or less
or
Temperature 225 °C or more, 60s or less
or
Temperature 220 °C or more, 80s or less
(e) Cooling : Natural cooling or forced cooling
H rank : 260 °C Max
MB3778
29
■PACKAGE DIMENSIONS
(Continued)
16-pin plastic SOP Lead pitch 1.27 mm
Package width
×
package length
5.3 × 10.15 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 2.25 mm MAX
Weight 0.20 g
Code
(Reference) P-SOP16-5.3×10.15-1.27
16-pin plastic SOP
(FPT-16P-M06)
(FPT-16P-M06)
C
2002 FUJITSU LIMITED F16015S-c-4-7
0.13(.005) M
Details of "A" part
7.80±0.405.30±0.30
(.209±.012) (.307±.016)
–.008
+.010
–0.20
+0.25
10.15
INDEX
1.27(.050)
0.10(.004)
18
916
0.47±0.08
(.019±.003)
–0.04
+0.03
0.17
.007 +.001
–.002
"A" 0.25(.010)
(Stand off)
0~8˚
(Mounting height)
2.00 +0.25
–0.15
.079 +.010
–.006
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10 +0.10
–0.05
–.002
+.004
.004
.400
*1
*2
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
MB3778
30
(Continued)
16-pin plastic SSOP Lead pitch 0.65 mm
Package width
×
package length
4.40 × 5.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.45mm MAX
Weight 0.07g
Code
(Reference) P-SSOP16-4.4×5.0-0.65
16-pin plastic SSOP
(FPT-16P-M05)
(FPT-16P-M05)
C
2003 FUJITSU LIMITED F16013S-c-4-6
5.00±0.10(.197±.004)
4.40±0.10 6.40±0.20
(.252±.008)(.173±.004)
.049 –.004
+.008
–0.10
+0.20
1.25 (Mounting height)
0.10(.004)
0.65(.026) 0.24±0.08
(.009±.003)
18
16 9
"A"
0.10±0.10 (Stand off)
0.17±0.03
(.007±.001)
M
0.13(.005)
(.004±.004)
Details of "A" part
0~8˚
(.024±.006)
0.60±0.15
(.020±.008)
0.50±0.20
0.25(.010)
LEAD No.
INDEX
*1
*2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
MB3778
31
MEMO
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited Strategic Business Development Dept.
