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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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June 2015
FDBL0150N60 N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation
FDBL0150N60 Rev. 1.0
www.fairchildsemi.com1
FDBL0150N60
N-Channel PowerTrench® MOSFET
60 V, 240 A, 1.5 mΩ
Features
Typical RDS(on) = 1.1 mΩ at VGS = 10V, ID = 80 A
Typical Qg(tot) = 130 nC at VGS = 10V, ID = 80 A
UIS Capability
RoHS Compliant
Applications
Industrial Motor Drive
Industrial Power Supply
Industrial Automation
Battery Operated tools
Battery Protection
Solar Inverters
UPS and Energy Inverters
Energy Storage
Load Switch
MOSFET Maximum Ratings TJ = 25°C unless otherwise noted.
Symbol Parameter Ratings Units
VDSS Drain-to-Source Voltage 60 V
VGS Gate-to-Source Voltage ±20 V
ID
Drain Current - Continuous (VGS=10) (Note 1) TC = 25°C 240 A
Pulsed Drain Current TC = 25°C See Figure 4
EAS Single Pulse Avalanche Energy (Note 2) 614 mJ
PD
Power Dissipation 357 W
Derate Above 25oC2.38W/
oC
TJ, TSTG Operating and Storage Temperature -55 to + 175 oC
RθJC Thermal Resistance, Junction to Case 0.42 oC/W
RθJA Maximum Thermal Resistance, Junction to Ambient (Note 3) 43 oC/W
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FDBL0150N60 FDBL0150N60 MO-299A 13" 24mm 2000 units
Notes:
1: Current is limited by silicon.
2: Starting TJ = 25°C, L = 0.3mH, IAS = 64A, VDD = 60V during inductor charging and VDD = 0V during time in avalanche.
3: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder
mounting surface of the drain pins. RθJC is guaranteed by design, while RθJAis determined by the board design. The maximum rating
presented here is based on mounting on a 1 in2 pad of 2oz copper.
Forcurrentpackagedrawing,pleaserefertotheFairchildweb‐
siteathttp://www.fairchildsemi.com/dwg/PS/PSOF08A.pdf.
S
D
G
FDBL0150N60 N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation
FDBL0150N60 Rev. 1.0
www.fairchildsemi.com2
Electrical Characteristics TJ = 25°C unless otherwise noted.
Off Characteristics
On Characteristics
Dynamic Characteristics
Symbol Parameter Test Conditions Min. Typ. Max. Units
BVDSS Drain-to-Source Breakdown Voltage ID = 250μA, VGS = 0V 60 - - V
IDSS Drain-to-Source Leakage Current VDS = 6 0 V , T J = 25oC --1μA
VGS = 0V TJ = 175oC (Note 4) - - 1 mA
IGSS Gate-to-Source Leakage Current VGS = ±20V - - ±100 nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250μA 2.0 2.9 4.0 V
RDS(on) Drain to Source On Resistance ID = 80A,
VGS= 10V
TJ = 25oC -1.11.5mΩ
TJ = 175oC (Note 4) - 2.1 2.9 mΩ
Ciss Input Capacitance VDS = 30V, VGS = 0V,
f = 1MHz
- 10300 - pF
Coss Output Capacitance - 2590 - pF
Crss Reverse Transfer Capacitance - 270 - pF
RgGate Resistance f = 1MHz - 4.3 - Ω
Qg(ToT) Total Gate Charge at 10V VGS = 0 to 10V VDD = 48V
ID = 80A
- 130 169 nC
Qg(th) Threshold Gate Charge VGS = 0 to 2V - 19 - nC
Qgs Gate-to-Source Gate Charge -48-nC
Qgd Gate-to-Drain “Miller“ Charge - 20 - nC
Switching Characteristics
Drain-Source Diode Characteristics
Note:
4: The maximum value is specified by design at TJ = 175°C. Product is not tested to this condition in production.
ton Turn-On Time
VDD = 30V, ID = 80A,
VGS = 10V, RGEN = 6Ω
- - 160 ns
td(on) Turn-On Delay - 30 - ns
trRise Time - 77 - ns
td(off) Turn-Off Delay - 78 - ns
tfFall Time - 57 - ns
toff Turn-Off Time - - 200 ns
VSD Source-to-Drain Diode Voltage ISD =80A, VGS = 0V - - 1.25 V
ISD = 40A, VGS = 0V - - 1.2 V
trr Reverse-Recovery Time IF = 80A, dISD/dt = 100A/μs,
VDD=48V
- 94 140 ns
Qrr Reverse-Recovery Charge - 131 200 nC
FDBL0150N60 N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation
FDBL0150N60 Rev. 1.0
www.fairchildsemi.com3
Typical Characteristics
Figure 1. Normalized Power Dissipation vs. Case
Temperature
0 25 50 75 100 125 150 175
0.0
0.2
0.4
0.6
0.8
1.0
1.2
POWER DISSIPATION MULTIPLIER
TC, CASE TEMPERATURE(oC)
Figure 2. Maximum Continuous Drain Current vs.
Case Temperature
25 50 75 100 125 150 175 200
0
50
100
150
200
250
300
350
400
CURRENT LIMITED
BY SILICON
VGS = 10V
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE(oC)
Figure 3.
10-5 10-4 10-3 10-2 10-1 100101
0.01
0.1
1
SINGLE PULSE
D = 0.50
0.20
0.10
0.05
0.02
0.01
NORMALIZED THERMAL
IMPEDANCE, ZθJC
t, RECTANGULAR PULSE DURATION(s)
DUTY CYCLE - DESCENDING ORDER
2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TC
PDM
t1
t2
Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
10-5 10-4 10-3 10-2 10-1 100101
10
100
1000
10000
VGS = 10V
SINGLE PULSE
IDM, PEAK CURRENT (A)
t, RECTANGULAR PULSE DURATION(s)
T
C
= 25
o
C
I = I
2
175 - T
C
150
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
FDBL0150N60 N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation
FDBL0150N60 Rev. 1.0
www.fairchildsemi.com4
Figure 5.
0.1 1 10 100
0.1
1
10
100
1000
100us
1ms
10ms
-ID, DRAIN CURRENT (A)
-VDS, DRAIN TO SOURCE VOLTAGE (V)
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
TC = 25oC100ms
200
Forward Bias Safe Operating Area
0.001 0.01 0.1 1 10 100 1000 10000
1
10
100
1000
2000
STARTING TJ = 150oC
STARTING TJ = 25oC
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 7.
2345678
0
50
100
150
200
250
300
350
TJ = -55oC
TJ = 25oC
TJ = 175oC
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
VDD = 5V
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Transfer Characteristics Figure 8.
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.1
1
10
100
350
TJ = 25 oC
TJ = 175 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Forward Diode Characteristics
Figure 9.
012345
0
50
100
150
200
250
300
350 VGS
15V Top
10V
8V
7V
6V
5.5V
5V Bottom
80μs PULSE WIDTH
Tj=25oC
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Saturation Characteristics Figure 10.
012345
0
50
100
150
200
250
300
350
VGS
15V Top
10V
8V
7V
6V
5.5V
5V Bottom
80μs PULSE WIDTH
Tj=175oC
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Saturation Characteristics
Typical Characteristics
FDBL0150N60 N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation
FDBL0150N60 Rev. 1.0
www.fairchildsemi.com5
Figure 11.
246810
0
10
20
30
40
50
ID = 80A PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
rDS(on), DRAIN TO SOURCE
ON-RESISTANCE (mΩ)
VGS, GATE TO SOURCE VOLTAGE (V)
TJ = 25oC
TJ = 175oC
RDSON vs. Gate Voltage Figure 12. Normalized RDSON vs. Junction
Temperature
-80 -40 0 40 80 120 160 200
0.4
0.8
1.2
1.6
2.0
2.4
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
ID = 80A
VGS = 10V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNCTION TEMPERATURE(oC)
Figure 13.
-80 -40 0 40 80 120 160 200
0.0
0.3
0.6
0.9
1.2
1.5 VGS = VDS
ID = 250μA
NORMALIZED GATE
THRESHOLD VOLTAGE
TJ, JUNCTION TEMPERATURE(oC)
Normalized Gate Threshold Voltage vs.
Temperature
Figure 14.
-80 -40 0 40 80 120 160 200
0.90
0.95
1.00
1.05
1.10
ID = 5mA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
TJ, JUNCTION TEMPERATURE (oC)
Normalized Drain to Source
Breakdown Voltage vs. Junction Temperature
Figure 15.
0.1 1 10 100
10
100
1000
10000
100000
f = 1MHz
VGS = 0V
Crss
Coss
Ciss
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Capacitance vs. Drain to Source
Voltage
Figure 16.
0 306090120150
0
2
4
6
8
10
VDD = 30V
VDD =24V
ID = 80A
VDD = 36V
Qg, GATE CHARGE(nC)
VGS, GATE TO SOURCE VOLTAGE(V)
Gate Charge vs. Gate to Source
Voltage
Typical Characteristics
FDBL0150N60 N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation
FDBL0150N60 Rev. 1.0
www.fairchildsemi.com6
Dimensional Outline and Pad Layout
10°
7.40
7.60
3.75
1.90
2.10
6.55
6.75
BOTTOM VIEW
6.64
13.28
8.10
0.60
2.90
2.95
10.20
4.45
0.80 1.20
6.64
LAND PATTERN
RECOMMENDATION
9.70
9.90
0.50
0.70
0.60
0.80
(3.30)
A
B
1.20
0.60 0.70
0.90
0.20 C A B
(0.40)
2.20
2.40
0.40
0.60
TOP VIEW
SIDE VIEW
C
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-299, ISSUE A, DATED NOVEMBER
2009.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) DRAWING FILE NAME: MKT-PSOF08AREV3
DETAIL "B"
9.80
10.00
(0.35)
10.28
10.48
8.40
1 8
18
(8.00)
DETAIL "B"
(0.35)
DETAIL "A"
DETAIL "A"
10°
0.60
0.80
0.40
0.60
2.80
0.25 C A B
0.20 C
0.20 C
11.58
11.78
7X
0.65
3.30
2.60
0.10
2X
4.73
(2X)
5.19
5.89
1.20
3X
4.99
1.46
0.86
2.04
5.10
(2X)
(2X)
(8X)
(2X)
0.10 C
0.20 C A B
(7.15)
(8.30)
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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