© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 11 1Publication Order Number:
MC14007UB/D
MC14007UB
Dual Complementary Pair
Plus Inverter
The MC14007UB multipurpose device consists of three N−Channel
and three P−Channel enhancement mode devices packaged to provide
access to each device. These versatile parts are useful in inverter
circuits, pulse−shapers, linear amplifiers, high input impedance
amplifiers, threshold detectors, transmission gating, and functional
gating.
Features
•Diode Protection on All Inputs
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
•Pin−for−Pin Replacement for CD4007A or CD4007UB
•This device has 2 outputs without ESD Protection. Antistatic
precautions must be taken.
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range −0.5 to +18.0 V
Vin, Vout Input or Output Voltage Range
(DC or Transient) −0.5 to VDD +0.5 V
Iin, Iout Input or Output Current
(DC or Transient) per Pin ±10 mA
PDPower Dissipation, per Package
(Note 1) 500 mW
TAAmbient Temperature Range −55 to +125 °C
Tstg Storage Temperature Range −65 to +150 °C
TLLead Temperature
(8 second Soldering) 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be af fected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/°C from 65°C 5o 125°C. See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
11
12
13
14
8
9
105
4
3
2
1
7
6
GATEC
S−PC
OUTC
D−PA
VDD
D−NA
S−NC
S−NB
GATEB
S−PB
D−PB
VSS
GATEA
D−NB
PIN ASSIGNMENT
D = DRAIN
S = SOURCE
MARKING DIAGRAM
SOIC−14
D SUFFIX
CASE 751A
1
14
14007UG
AWLYWW
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Indicator
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MC14007UB
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2
Figure 1. Typical Application: 2−Input Analog Multiplexer
A
B
C
INPUT
INPUT
A
B
C
12
1
3
5
9
2
4
11
10
14
VDD
6
7V
SS
8
13
INPUT
1
0
OUTPUT CONDITION
A = C, B = OPEN
A = B, C = OPEN
Substrates of P−Channel devices internally
connected to VDD; substrates of N−Channel
devices internally connected to VSS.
Figure 2. Schematic
14 13 2 1 11
126
78 3 4 510 9
VDD = PIN 14
VSS = PIN 7
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Symbo
l
Characteristic VDD
Vdc
−55°C 25°C 125°C
Unit
Min Max Min Typ
(Note 2) Max Min Max
VOL Output Voltage “0” Leve
l
Vin = VDD or 0
Vin = 0 or VDD “1” Leve
l
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH 5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
VIL Input Voltage “0” Leve
l
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
(VO = 0.5 Vdc) “1” Leve
l
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
5.0
10
15
−
−
−
1.0
2.0
2.5
−
−
−
2.25
4.50
6.75
1.0
2.0
2.5
−
−
−
1.0
2.0
2.5
Vdc
VIH 5.0
10
15
4.0
8.0
12.5
−
−
−
4.0
8.0
12.5
2.75
5.50
8.25
−
−
−
4.0
8.0
12.5
−
−
−
Vdc
IOH Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc) Sin
k
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
−
−
−
−
–2.4
–0.51
−1.3
−3.4
–5.0
–1.0
–2.5
–10
−
−
−
−
–1.7
−0.36
–0.9
−2.4
−
−
−
−
mAdc
IOL 5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
1.0
2.5
10
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Iin Input Current 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc
Cin Input Capacitance
(Vin = 0) − − − − 5.0 7.5 − − pF
IDD Quiescent Current
(Per Package) 5.0
10
15
−
−
−
0.25
0.5
1.0
−
−
−
0.0005
0.0010
0.0015
0.25
0.5
1.0
−
−
−
7.5
15
30
mAdc
ITTotal Supply Current (Notes 3 and 4)
(Dynamic plus Quiescent,
Per Gate) (CL = 50 pF)
5.0
10
15
IT = (0.7 mA/kHz) f + IDD/6
IT = (1.4 mA/kHz) f + IDD/6
IT = (2.2 mA/kHz) f + IDD/6
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25°C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.003.
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SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25°C)
Symbol Characteristic VDD
Vdc Min Typ
(Note 6) Max Unit
tTLH Output Rise Time
tTLH = (1.2 ns/pF) CL + 30 ns
tTLH = (0.5 ns/pF) CL + 20 ns
tTLH = (0.4 ns/pF) CL + 15 ns
5.0
10
15
−
−
−
90
45
35
180
90
70
ns
tTHL Output Fall Time
tTHL = (1.2 ns/pF) CL + 15 ns
tTHL = (0.5 ns/pF) CL + 15 ns
tTHL = (0.4 ns/pF) CL + 10 ns
5.0
10
15
−
−
−
75
40
30
150
80
60
ns
tPLH Turn−Off Delay Time
tPLH = (1.5 ns/pF) CL + 35 ns
tPLH = (0.2 ns/pF) CL + 20 ns
tPLH = (0.15 ns/pF) CL + 17.5 ns
5.0
10
15
−
−
−
60
30
25
125
75
55
ns
tPHL Turn−On Delay T ime
tPHL = (1.0 ns/pF) CL + 10 ns
tPHL = (0.3 ns/pF) CL + 15 ns
tPHL = (0.2 ns/pF) CL + 15 ns
5.0
10
15
−
−
−
60
30
25
125
75
55
ns
5. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 3. Typical Output Source Characteristics Figure 4. Typical Output Sink Characteristics
VDD = -VGS VDD = VGS
14
14
VDS = VOH - VDD VDS = VOL
VSS VSS
7
7
IOH IOL
IOH, DRAIN CURRENT (mAdc)
IOL , DRAIN CURRENT (mAdc)
0
-4.0
-8.0
-12
-16
-20
-8.0-10 -6.0 -4.0 -2.0 -0
VDS, DRAIN VOLTAGE (Vdc)
20
16
12
8.0
4.0
0
0 2.0 4.0 6.0 8.0 10
VDS, DRAIN VOLTAGE (Vdc)
TA = -55°C
TA = +25°C
TA = +125°C
a
b
c
VGS = -5.0 Vdc b
c
a
-10 Vdc -15 Vdc
c
bc
b
a
a
a
b
c
a
bc
a
b
c
5.0 Vdc
TA = -55°C
TA = +25°C
TA = +125°C
a
b
c
VGS = 15 Vdc
10 Vdc
All unused inputs connected to ground. All unused inputs connected to ground.
These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.
MC14007UB
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5
Figure 5. Switching Time and Power Dissipation Test Circuit and Waveforms
PULSE
GENERATOR
VDD
500mF0.01 mF
CERAMIC
14
CL
Vout
VSS
7
Vin
IDVin
Vout
90%
50%
10%
90%
50%
10%
20 ns 20 ns
VDD
VSS
VOH
VOL
tTHL tTLH
tPHL tPLH
APPLICATIONS
The MC14007UB dual pair plus inverter, which has access to all its elements offers a number of unique circuit applications.
Figures 1, 6, and 7 are a few examples of the device flexibility.
Figure 6. 3−State Buffer
+VDD
DISABLE3
INPUT10
DISABLE6
12OUTPUT
11
1
2
9
8
7
INPUT DISABLE OUTPUT
1
0
X
0
0
1
0
1
OPEN
X = Don’t Care
Figure 7. AOI Functions Using Tree Logic
VDD
14
13
11
10
3
6
B
C
A
9
5
4
8
7
1
2
OUTPUT
OUT = A+B•C
Substrates of P−Channel devices internally connected to VDD;
Substrates of N−Channel devices internally connected to VSS.
12
MC14007UB
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6
ORDERING INFORMATION
Device Package Shipping†
MC14007UBDG SOIC−14
(Pb−Free) 55 Units / Rail
MC14007UBDR2G SOIC−14
(Pb−Free) 2500 / Tape & Reel
NLV14007UBDR2G* SOIC−14
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
MC14007UB
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7
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
H
14 8
71
M
0.25 B M
C
h
X 45
SEATING
PLANE
A1
A
M
_
S
A
M
0.25 B S
C
b
13X
B
A
E
D
e
DET AIL A
L
A3
DET AIL A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
D8.55 8.75 0.337 0.344
E3.80 4.00 0.150 0.157
A1.35 1.75 0.054 0.068
b0.35 0.49 0.014 0.019
L0.40 1.25 0.016 0.049
e1.27 BSC 0.050 BSC
A3 0.19 0.25 0.008 0.010
A1 0.10 0.25 0.004 0.010
M0 7 0 7
H5.80 6.20 0.228 0.244
h0.25 0.50 0.010 0.019
__ __
6.50
14X
0.58
14X
1.18
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent− Marking.pdf. S CILLC r eserves t he r ight t o make changes without further n ot ice to a ny p roducts h erein. S CILLC m akes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all l iabilit y, including without limitation special, consequential or i ncident al d amages. “Typical” parameters which may be p r ovided in SCILLC data s heet s
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application b y cust omer’s technical expert s. S CILLC does n ot convey any l icense u nder i ts p atent r ights n or the rights of o thers. SCILLC products are n ot d esigned, intended,
or authorized for use as c omponent s i n s yst ems i nt ended f or s urgic al i m plant i nt o the body, or other applications intended t o support or sustain life, o r for any other application i n w hich
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
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alleges t hat S CILLC w as n egligent r egarding t he d esign o r m anufact ure of the part. S CILLC is an E qual O pportunity/Affirmat ive Action Employer . T his literature is s ubject t o all applicable
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P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
MC14007UB/D
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