LTC3407EMSE-4#PBF - ANALOG DEVICES

LTC3407-4

34074fa

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Dual Synchronous, 800mA,

2.25MHz Step-Down

DC/DC Regulator

The LTC

3407-4 is a dual, constant frequency, synchro-

nous step down DC/DC converter. Intended for low power

applications, it operates from 2.5V to 5.5V input voltage

range and has a constant 2.25MHz switching frequency,

allowing the use of tiny, low cost capacitors and induc-

tors with a proﬁ le ≤1mm. Each output voltage is adjust-

able from 0.6V to 5V. Internal synchronous 0.35Ω, 1.2A

power switches provide high efﬁ ciency without the need

for external Schottky diodes.

A user selectable mode input is provided to allow the user

to trade-off noise ripple for low power efﬁ ciency. Burst

Mode

operation provides high efﬁ ciency at light loads,

while pulse-skipping mode provides low noise ripple at

light loads.

To further maximize battery life, the P-channel MOSFETs

are turned on continuously in dropout (100% duty cycle),

and both channels draw a total quiescent current of only

40μA. In shutdown, the device draws <1μA.

The LTC3407-4 is identical to the LTC3407-2 except for

the reduced power-on reset delay time.

Figure 1. 2.5V/1.8V at 800mA Step-Down Regulators

n High Efﬁ ciency: Up to 95%

n Very Low Quiescent Current: Only 40μA

n 2.25MHz Constant Frequency Operation

n High Switch Current: 1.2A on Each Channel

n No Schottky Diodes Required

n Low RDS(ON) Internal Switches: 0.35Ω

n Current Mode Operation for Excellent Line

and Load Transient Response

n Short-Circuit Protected

n Low Dropout Operation: 100% Duty Cycle

n Ultralow Shutdown Current: IQ < 1μA

n Output Voltages from 5V down to 0.6V

n Power-On Reset Output

n Externally Synchronizable Oscillator

n Small Thermally Enhanced MSOP and 3mm × 3mm

DFN Packages

n PDAs/Palmtop PCs

n Digital Cameras

n Cellular Phones

n Portable Media Players

n PC Cards

n Wireless and DSL Modems

LTC3407-4 Efﬁ ciency/Power Loss Curve

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (W)

100

0.1 10 100 1000

34074 TA02

0.001

0.1

0.01

0.0001

RUN2 VIN

VIN*

2.5V TO 5.5V

VOUT2

2.5V

800mA

VOUT1

1.8V

800mA

RUN1

POR

SW1

VFB1

GND

VFB2

SW2

MODE/SYNC

LTC3407-4

10μF

100k

RESET

C4, 22pFC5, 22pF

2.2μH

887k

604k

301k

280k

10μF

3407 TA01

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML L1, L2: MURATA LQH32CN2R2M33

*VOUT CONNECTED TO VIN FOR VIN ≤ 2.8V

L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks

of Linear Technology Corporation. All other trademarks are the property of their respective

owners. Protected by U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466,

6611131.

LTC3407-4

34074fa

ABSOLUTE MAXIMUM RATINGS

VIN Voltages .................................................–0.3V to 6V

VFB1, VFB2 Voltages .......................... –0.3V to VIN + 0.3V

RUN1, RUN2 Voltages .................................–0.3V to VIN

MODE/SYNC Voltage ....................................–0.3V to VIN

SW1, SW2 Voltage ........................... –0.3V to VIN + 0.3V

POR Voltage ................................................. –0.3V to 6V

(Note 1)

TOP VIEW

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

1VFB2

RUN2

POR

SW2

MODE/

SYNC

VFB1

RUN1

VIN

SW1

GND

TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W

EXPOSED PAD (PIN 11) IS PGND, MUST BE SOLDERED TO GND

TOP VIEW

VFB1

RUN1

VIN

SW1

GND

VFB2

RUN2

POR

SW2

MODE/

SYNC

MSE PACKAGE

10-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W

EXPOSED PAD (PIN 11) IS PGND, MUST BE SOLDERED TO GND

PIN CONFIGURATION

ELECTRICAL CHARACTERISTICS

Ambient Operating Temperature

Range (Note 2) ......................................... –40°C to 85°C

Junction Temperature (Note 5) ............................. 125°C

Storage Temperature Range ...................– 65°C to 125°C

Lead Temperature (Soldering, 10 sec)

LTC3407EMSE-4 only ....................................... 300°C

Reﬂ ow Peak Body Temperature ............................ 260°C

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 3.6V, unless otherwise speciﬁ ed. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Operating Voltage Range ●2.5 5.5 V

IFB Feedback Pin Input Current ●30 nA

VFB Feedback Voltage (Note 3) 0°C ≤ TA ≤ 85°C

–40°C ≤ TA ≤ 85°C ●

0.588

0.585

0.6

0.612

ΔVLINE REG Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 3) 0.3 0.5 %/V

ΔVLOAD REG Output Voltage Load Regulation (Note 3) 0.5 %

ISInput DC Supply Current (Note 4)

Active Mode

Sleep Mode

Shutdown

VFB1 = VFB2 = 0.5V

VFB1 = VFB2 = 0.63V, MODE/SYNC = 3.6V

RUN = 0V, VIN = 5.5V, MODE/SYNC = 0V

700

0.1

950

μA

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3407EDD-4#PBF LTC3407EDD-4#TRPBF LCJD 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C

LTC3407EMSE-4#PBF LTC3407EMSE-4#TRPBF LTCJC 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

LTC3407-4

34074fa

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime. Pins of regulators should not exceed 6V

Note 2: The LTC3407E-4 is guaranteed to meet speciﬁ ed performance

from 0°C to 85°C. Speciﬁ cations over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 3.6V, unless otherwise speciﬁ ed. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fOSC Oscillator Frequency VFBX = 0.6V ●1.8 2.25 2.7 MHz

fSYNC Synchronization Frequency 2.25 MHz

ILIM Peak Switch Current Limit VIN = 3V, VFBX = 0.5V, Duty Cycle <35% 0.95 1.2 1.6 A

RDS(ON) Top Switch On-Resistance

Bottom Switch On-Resistance

(Note 6)

0.35

0.30

0.45

ISW(LKG) Switch Leakage Current VIN = 5V, VRUN = 0V, VFBX = 0V 0.01 1 μA

POR Power-On Reset Threshold VFBX Ramping Up, MODE/SYNC = 0V

VFBX Ramping Down, MODE/SYNC = 0V

8.5

–8.5

Power-On Reset On-Resistance 100 200 Ω

Power-On Reset Delay 65536 Cycles

VRUN RUN Threshold ●0.3 1 1.5 V

IRUN RUN Leakage Current ●0.01 1 μA

VMODE MODE Threshold Low 0 0.5 V

MODE Threshold High VIN – 0.5 VIN V

Note 3: The LTC3407-4 is tested in a proprietary test mode that connects

VFB to the output of the error ampliﬁ er.

Note 4: Dynamic supply current is higher due to the internal gate charge

being delivered at the switching frequency.

Note 5: TJ is calculated from the ambient TA and power dissipation PD

according to the following formula: TJ = TA + (PD • θJA).

Note 6: The DFN switch on-resistance is guaranteed by correlation to

wafer level measurements.

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C unless otherwise speciﬁ ed.

Burst Mode Operation Pulse-Skipping Mode Load Step

5V/DIV

VOUT

20mV/DIV

200mA/DIV

VIN = 3.6V

VOUT = 1.8V

ILOAD = 100mA

2μs/DIV 34073 G01

5V/DIV

VOUT

20mV/DIV

200mA/DIV

VIN = 3.6V

VOUT = 1.8V

ILOAD = 20mA

1μs/DIV 34073 G02

500mA/DIV

VOUT

200mV/DIV

ILOAD

500mA/DIV

VIN = 3.6V

VOUT = 1.8V

ILOAD = 80mA ~ 800mA

10μs/DIV 34074 G03

LTC3407-4

34074fa

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁ ciency vs Input Voltage

Oscillator Frequency vs

Temperature

Oscillator Frequency Deviation

vs Supply Voltage

Reference Voltage vs

Temperature RDS(ON) vs Input Voltage RDS(ON) vs Temperature

Efﬁ ciency vs Load Current Efﬁ ciency vs Load Current Load Regulation

INPUT VOLTAGE (V)

EFFICIENCY (%)

100

34074 G04

LOAD = 100mA

LOAD = 800mA

LOAD = 1mA

LOAD = 10mA

VOUT = 1.8V

Burst Mode OPERATION

2.5

2.4

2.3

2.2

2.1

2.0

FREQUENCY (MHz)

TEMPERATURE (°C)

–50 25 75

34074 G05

–25 0 50 100 125

VIN = 3.6V 10

–2

–4

–6

–8

–10

FREQUENCY DEVIATION (%)

SUPPLY VOLTAGE (V)

34074 G06

3456

0.615

0.610

0.605

0.600

0.595

0.590

0.585

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

–50 25 75

34074 G07

–25 0 50 100 125

VIN = 3.6V

VIN (V)

500

450

400

350

300

250

200

34074 G08

2357

RDS(ON) (mΩ)

MAIN

SWITCH

SYNCHRONOUS

SWITCH

TEMPERATURE (°C)

–50

550

500

450

400

350

300

250

200

150

100

25 75

34074 G09

–25 0 50 100 150125

RDS(ON) (mΩ)

MAIN SWITCH

SYNCHRONOUS SWITCH

VIN = 3.6V

VIN = 4.2V

VIN = 2.7V

LOAD CURRENT (mA)

EFFICIENCY (%)

100

10 100 1000

LTC1273/75/76 • F25

VIN = 2.7V

VIN = 3.6V

VIN = 4.2V

VOUT = 2.5V

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

LOAD CURRENT (mA)

EFFICIENCY (%)

100

10 100 1000

34074 G11

Burst Mode

OPERATION

PULSE-SKIPPING

MODE

VIN = 3.6V, VOUT = 1.8V

NO LOAD ON OTHER CHANNEL

LOAD CURRENT (mA)

VOUT ERROR (%)

10 100 1000

34074 G12

–2

–1

–3

–4

Burst Mode

OPERATION

PULSE-SKIPPING

MODE

VIN = 3.6V, VOUT = 1.8V

NO LOAD ON OTHER CHANNEL

LTC3407-4

34074fa

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁ ciency vs Load Current Efﬁ ciency vs Load Current Line Regulation

LOAD CURRENT (mA)

EFFICIENCY (%)

10 100 1000

34074 G13

100

VIN = 2.7V

VIN = 4.2V

VIN = 3.6V

VOUT = 1.2V

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

LOAD CURRENT (mA)

EFFICIENCY (%)

100

10 100 1000

34074 G14

VIN = 2.7V

VIN = 4.2V

VIN = 3.6V

VOUT = 1.5V

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

VIN (V)

VOUT ERROR (%)

0.2

0.4

34074 G15

–0.4

–0.2

–1.0

345

–0.6

–0.8

0.8

0.6

VOUT = 1.8V

IOUT = 200mA

TA = 25°C

PIN FUNCTIONS

VFB1 (Pin 1): Output Feedback. Receives the feedback volt-

age from the external resistive divider across the output.

Nominal voltage for this pin is 0.6V.

RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to VIN

enables regulator 1, while forcing it to GND causes regulator

1 to shut down. This pin must be driven; do not ﬂ oat.

VIN (Pin 3): Main Power Supply. Must be closely decoupled

to GND.

SW1 (Pin 4): Regulator 1 Switch Node Connection to the

Inductor. This pin swings from VIN to GND.

GND (Pin 5): Ground. This pin is not connected internally.

Connect to PCB ground for shielding.

MODE/SYNC (Pin 6): Combination Mode Selection and

Oscillator Synchronization. This pin controls the opera-

tion of the device. When tied to VIN or GND, Burst Mode

operation or pulse-skipping mode is selected, respectively.

Do not ﬂ oat this pin. The oscillation frequency can be

synchronized to an external oscillator applied to this pin

and pulse-skipping mode is automatically selected.

SW2 (Pin 7): Regulator 2 Switch Node Connection to the

Inductor. This pin swings from VIN to GND.

POR (Pin 8): Power-On Reset . This common-drain logic

output is pulled to GND when the output voltage is not

within ±8.5% of regulation and goes high after 29ms when

both channels are within regulation.

RUN2 (Pin 9): Regulator 2 Enable. Forcing this pin to VIN

enables regulator 2, while forcing it to GND causes regulator

2 to shut down. This pin must be driven; do not ﬂ oat.

VFB2 (Pin 10): Output Feedback. Receives the feedback

voltage from the external resistive divider across the output.

Nominal voltage for this pin is 0.6V.

Exposed Pad (GND) (Pin 11): Power Ground. Connect to

the (–) terminal of COUT

, and (–) terminal of CIN. Must be

connected to electrical ground on PCB.

LTC3407-4

34074fa

BLOCK DIAGRAM

OPERATION

The LTC3407-4 uses a constant frequency, current mode

architecture. The operating frequency is set at 2.25MHz

and can be synchronized to an external oscillator. Both

channels share the same clock and run in-phase. To suit a

variety of applications, the selectable Mode pin allows the

user to choose between low noise and high efﬁ ciency.

The output voltage is set by an external divider returned

to the VFB pins. An error ampliﬁ er compares the divided

output voltage with a reference voltage of 0.6V and adjusts

the peak inductor current accordingly. Overvoltage and

undervoltage comparators will pull the POR output low if

the output voltage is not within ±8.5%. The POR output

will go high after 216 clock cycles (about 29ms in pulse-

skipping mode) of achieving regulation.

Main Control Loop

During normal operation, the top power switch (P-channel

MOSFET) is turned on at the beginning of a clock cycle

when the VFB voltage is below the the reference voltage.

The current into the inductor and the load increases until

the current limit is reached. The switch turns off and

energy stored in the inductor ﬂ ows through the bottom

switch (N-channel MOSFET) into the load until the next

clock cycle.

The peak inductor current is controlled by the internally

compensated ITH voltage, which is the output of the er-

ror ampliﬁ er. This ampliﬁ er compares the VFB pin to the

0.6V reference. When the load current increases, the

VFB voltage decreases slightly below the reference. This

–

+–+

–

UVDET

OVDET

0.6V

0.65V

0.55V

–

0.35V

ITH

SWITCHING

LOGIC

AND

BLANKING

CIRCUIT

LATCH

BURST

–

ICOMP

IRCMP

ANTI

SHOOT-

THRU

BURST

CLAMP

SLOPE

COMP

SLEEP

POR

COUNTER

0.6V REF OSC

OSC

REGULATOR 2 (IDENTICAL TO REGULATOR 1)

PGOOD1

PGOOD2

34074 BD

SHUTDOWN

VIN

REGULATOR 1

SW1

GND

POR

GND

SW2

5Ω

MODE/SYNC

VFB1

RUN1

RUN2

VFB2

LTC3407-4

34074fa

OPERATION

APPLICATIONS INFORMATION

A general LTC3407-4 application circuit is shown in

Figure 2. External component selection is driven by the

load requirement, and begins with the selection of the

inductor L. Once the inductor is chosen, CIN and COUT

can be selected.

Inductor Selection

Although the inductor does not inﬂ uence the operat-

ing frequency, the inductor value has a direct effect on

ripple current. The inductor ripple current ΔIL decreases

with higher inductance and increases with higher VIN or

VOUT

IL=VOUT

fO•L •1–

VOUT

VIN











Accepting larger values of ΔIL allows the use of low

inductances, but results in higher output voltage ripple,

greater core losses, and lower output current capability.

A reasonable starting point for setting ripple current is

ΔIL = 0.3 • ILIM, where ILIM is the peak switch current limit.

The largest ripple current ΔIL occurs at the maximum input

voltage. To guarantee that the ripple current stays below a

speciﬁ ed maximum, the inductor value should be chosen

according to the following equation:

LVOUT

fO•IL

•1– VOUT

VIN(MAX)













The inductor value will also have an effect on Burst Mode

operation. The transition from low current operation

decrease causes the error ampliﬁ er to increase the ITH

voltage until the average inductor current matches the

new load current.

The main control loop is shut down by pulling the RUN

pin to ground.

Low Current Operation

Two modes are available to control the operation of the

LTC3407-4 at low currents. Both modes automatically

switch from continuous operation to the selected mode

when the load current is low.

To optimize efﬁ ciency, the Burst Mode operation can be

selected. When the load is relatively light, the LTC3407-4

automatically switches into Burst Mode operation, in which

the PMOS switch operates intermittently based on load

demand with a ﬁ xed peak inductor current. By running

cycles periodically, the switching losses which are domi-

nated by the gate charge losses of the power MOSFETs

are minimized. The main control loop is interrupted when

the output voltage reaches the desired regulated value.

A hysteretic voltage comparator trips when ITH is below

0.35V, shutting off the switch and reducing the power. The

output capacitor and the inductor supply the power to the

load until ITH exceeds 0.65V, turning on the switch and the

main control loop which starts another cycle.

For lower ripple noise at low currents, the pulse-skipping

mode can be used. In this mode, the LTC3407-4 continues

to switch at a constant frequency down to very low cur-

rents, where it will begin skipping pulses. The efﬁ ciency in

pulse-skipping mode can be improved slightly by connect-

ing the SW node to the MODE/SYNC input which reduces

the clock frequency by approximately 30%.

Dropout Operation

When the input supply voltage decreases toward the

output voltage, the duty cycle increases to 100% which

is the dropout condition. In dropout, the PMOS switch is

turned on continuously with the output voltage being equal

to the input voltage minus the voltage drops across the

internal P-channel MOSFET and the inductor.

An important design consideration is that the RDS(ON)

of the P-channel switch increases with decreasing input

supply voltage (See Typical Performance Characteristics).

Therefore, the user should calculate the power dissipation

when the LTC3407-4 is used at 100% duty cycle with low

input voltage (See Thermal Considerations in the Applica-

tions Information Section).

Low Supply Operation

To prevent unstable operation, the LTC3407-4 incorporates

an Under-Voltage Lockout circuit which shuts down the

part when the input voltage drops below about 1.65V.

LTC3407-4

34074fa

APPLICATIONS INFORMATION

begins when the peak inductor current falls below a level

set by the burst clamp. Lower inductor values result in

higher ripple current which causes this to occur at lower

load currents. This causes a dip in efﬁ ciency in the upper

range of low current operation. In Burst Mode operation,

lower inductance values will cause the burst frequency

to increase.

Inductor Core Selection

Different core materials and shapes will change the size/

current and price/current relationship of an inductor. Toroid

or shielded pot cores in ferrite or permalloy materials are

small and don’t radiate much energy, but generally cost

more than powdered iron core inductors with similar elec-

trical characteristics. The choice of which style inductor

to use often depends more on the price vs size require-

ments and any radiated ﬁ eld/EMI requirements than on

what the LTC3407-4 requires to operate. Table 1 shows

some typical surface mount inductors that work well in

LTC3407-4 applications.

Input Capacitor (CIN) Selection

In continuous mode, the input current of the converter is a

square wave with a duty cycle of approximately VOUT/VIN.

To prevent large voltage transients, a low equivalent series

resistance (ESR) input capacitor sized for the maximum

RMS current must be used. The maximum RMS capacitor

current is given by:

IRMS ≈IMAX

VOUT VIN –V

OUT

()

VIN

where the maximum average output current IMAX equals

the peak current minus half the peak-to-peak ripple cur-

rent, IMAX = ILIM – ΔIL/2.

This formula has a maximum at VIN = 2VOUT

, where IRMS

= IOUT/2. This simple worst-case is commonly used to

design because even signiﬁ cant deviations do not offer

much relief. Note that capacitor manufacturer’s ripple cur-

rent ratings are often based on only 2000 hours lifetime.

This makes it advisable to further derate the capacitor,

or choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to meet

the size or height requirements of the design. An additional

0.1μF to 1μF ceramic capacitor is also recommended on

VIN for high frequency decoupling, when not using an all

ceramic capacitor solution.

Table 1. Representative Surface Mount Inductors

PART

NUMBER

VALUE

(μH)

DCR

(Ω MAX)

MAX DC

CURRENT (A)

SIZE

W × L × H (mm3)

Sumida

CDRH3D16

2.2

3.3

4.7

0.075

0.110

0.162

1.20

1.10

0.90

3.8 × 3.8 × 1.8

Sumida

CDRH2D11

1.5

2.2

0.068

0.170

0.900

0.780

3.2 × 3.2 × 1.2

Sumida

CMD4D11

2.2

3.3

0.116

0.174

0.950

0.770

4.4 × 5.8 × 1.2

Murata

LQH32CN

1.0

2.2

0.060

0.097

1.00

0.79

2.5 × 3.2 × 2.0

Toko

D312F

2.2

3.3

0.060

0.260

1.08

0.92

2.5 × 3.2 × 2.0

Panasonic

ELT5KT

3.3

4.7

0.17

0.20

1.00

0.95

4.5 × 5.4 × 1.2

Output Capacitor (COUT) Selection

The selection of COUT is driven by the required ESR to

minimize voltage ripple and load step transients. Typically,

once the ESR requirement is satisﬁ ed, the capacitance

is adequate for ﬁ ltering. The output ripple (ΔVOUT) is

determined by:

VOUT ILESR+1

8fOCOUT











where f = operating frequency, COUT = output capacitance

and ΔIL = ripple current in the inductor. The output ripple

is highest at maximum input voltage since ΔIL increases

with input voltage. With ΔIL = 0.3 • ILIM the output ripple

will be less than 100mV at maximum VIN and fO = 2.25MHz

with:

ESRCOUT < 150mΩ

Once the ESR requirements for COUT have been met, the

RMS current rating generally far exceeds the IRIPPLE(P-P)

requirement, except for an all ceramic solution.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the capacitance, ESR or

RMS current handling requirement of the application.

Aluminum electrolytic, special polymer, ceramic and dry

tantulum capacitors are all available in surface mount

packages. The OS-CON semiconductor dielectric capacitor

available from Sanyo has the lowest ESR(size) product

of any aluminum electrolytic at a somewhat higher price.

Special polymer capacitors, such as Sanyo POSCAP,

LTC3407-4

34074fa

APPLICATIONS INFORMATION

Figure 2. LTC3407-4 General Schematic

Panasonic Special Polymer (SP), and Kemet A700, of-

fer very low ESR, but have a lower capacitance density

than other types. Tantalum capacitors have the highest

capacitance density, but they have a larger ESR and it

is critical that the capacitors are surge tested for use in

switching power supplies. An excellent choice is the AVX

TPS series of surface mount tantalums, available in case

heights ranging from 2mm to 4mm. Aluminum electrolytic

capacitors have a signiﬁ cantly larger ESR, and are often

used in extremely cost-sensitive applications provided that

consideration is given to ripple current ratings and long

term reliability. Ceramic capacitors have the lowest ESR

and cost, but also have the lowest capacitance density,

a high voltage and temperature coefﬁ cient, and exhibit

audible piezoelectric effects. In addition, the high Q of

ceramic capacitors along with trace inductance can lead

to signiﬁ cant ringing.

In most cases, 0.1μF to 1μF of ceramic capacitors should

also be placed close to the LTC3407-4 in parallel with the

main capacitors for high frequency decoupling.

RUN2 VIN

VIN

2.5V TO 5.5V

VOUT2 VOUT1

RUN1

POR

SW1

VFB1

GND

VFB2

SW2

MODE/SYNC

LTC3407-4

CIN R5

POWER-ON

RESET

C4C5

R4 R2

COUT2 COUT1

34074 F02

PS*

BM*

*MODE/SYNC = 0V: PULSE-SKIPPING

MODE/SYNC = VIN: Burst Mode OPERATION

Ceramic Input and Output Capacitors

Higher value, lower cost ceramic capacitors are now be-

coming available in smaller case sizes. These are tempting

for switching regulator use because of their very low ESR.

Unfortunately, the ESR is so low that it can cause loop

stability problems. Solid tantalum capacitor ESR generates

a loop “zero” at 5kHz to 50kHz that is instrumental in giving

acceptable loop phase margin. Ceramic capacitors remain

capacitive to beyond 300kHz and usually resonate with their

ESL before ESR becomes effective. Also, ceramic caps are

prone to temperature effects which requires the designer

to check loop stability over the operating temperature

range. To minimize their large temperature and voltage

coefﬁ cients, only X5R or X7R ceramic capacitors should

be used. A good selection of ceramic capacitors is available

from Taiyo Yuden, AVX, Kemet, TDK, and Murata.

Great care must be taken when using only ceramic input

and output capacitors. When a ceramic capacitor is used

at the input and the power is being supplied through long

wires, such as from a wall adapter, a load step at the output

can induce ringing at the VIN pin. At best, this ringing can

couple to the output and be mistaken as loop instability.

At worst, the ringing at the input can be large enough to

damage the part.

Since the ESR of a ceramic capacitor is so low, the input

and output capacitor must instead fulﬁ ll a charge storage

requirement. During a load step, the output capacitor must

instantaneously supply the current to support the load

until the feedback loop raises the switch current enough

to support the load. The time required for the feedback

loop to respond is dependent on the compensation and

the output capacitor size. Typically, 3-4 cycles are required

to respond to a load step, but only in the ﬁ rst cycle does

the output drop linearly. The output droop, VDROOP, is

usually about 2-3 times the linear drop of the ﬁ rst cycle.

Thus, a good place to start is with the output capacitor

size of approximately:

COUT ≈2.5 ΔIOUT

fO•V

DROOP

More capacitance may be required depending on the duty

cycle and load step requirements.

In most applications, the input capacitor is merely required

to supply high frequency bypassing, since the impedance

to the supply is very low. A 10μF ceramic capacitor is

usually enough for these conditions.

Setting the Output Voltage

The LTC3407-4 develops a 0.6V reference voltage be-

tween the feedback pin, VFB, and the ground as shown in

Figure 2. The output voltage is set by a resistive divider

according to the following formula:

LTC3407-4

34074fa

APPLICATIONS INFORMATION

VOUT =0.6V 1+R2











Keeping the current small (<5μA) in these resistors maxi-

mizes efﬁ ciency, but making them too small may allow

stray capacitance to cause noise problems and reduce the

phase margin of the error amp loop.

To improve the frequency response, a feed-forward capaci-

tor CF may also be used. Great care should be taken to

route the VFB line away from noise sources, such as the

inductor or the SW line.

Power-On Reset

The POR pin is an open-drain output which pulls low

when either regulator is out of regulation. When both

output voltages are within ±8.5% of regulation, a timer is

started which releases POR after 216 clock cycles (about

29ms). This delay can be signiﬁ cantly longer in Burst Mode

operation with low load currents, since the clock cycles

only occur during a burst and there could be milliseconds

of time between bursts. This can be bypassed by tying the

POR output to the MODE/SYNC input, to force pulse-skip-

ping mode during a reset. In addition, if the output voltage

faults during Burst Mode sleep, POR could have a slight

delay for an undervoltage output condition and may not

respond to an overvoltage output. This can be avoided by

using pulse-skipping mode instead. When either channel

is shut down, the POR output is pulled low, since one or

both of the channels are not in regulation.

Mode Selection & Frequency Synchronization

The MODE/SYNC pin is a multipurpose pin which provides

mode selection and frequency synchronization. Connect-

ing this pin to VIN enables Burst Mode operation, which

provides the best low current efﬁ ciency at the cost of a

higher output voltage ripple. Connecting this pin to ground

selects pulse-skipping mode, which provides the lowest

output ripple, at the cost of low current efﬁ ciency.

The LTC3407-4 can also be synchronized to an external

2.25MHz clock signal (such as the SW pin on another

LTC3407-4) by the MODE/SYNC pin. During synchro-

nization, the mode is set to pulse-skipping and the top

switch turn-on is synchronized to the rising edge of the

external clock.

Checking Transient Response

The regulator loop response can be checked by look-

ing at the load transient response. Switching regulators

take several cycles to respond to a step in load current.

When a load step occurs, VOUT immediately shifts by an

amount equal to ΔILOAD • ESR, where ESR is the effective

series resistance of COUT

. ΔILOAD also begins to charge

or discharge COUT

, generating a feedback error signal

used by the regulator to return VOUT to its steady-state

value. During this recovery time, VOUT can be monitored

for overshoot or ringing that would indicate a stability

problem.

The initial output voltage step may not be within the

bandwidth of the feedback loop, so the standard second-

order overshoot/DC ratio cannot be used to determine

phase margin. In addition, a feed-forward capacitor, CF,

can be added to improve the high frequency response, as

shown in Figure 2. Capacitor CF provides phase lead by

creating a high frequency zero with R2, which improves

the phase margin.

The output voltage settling behavior is related to the stability

of the closed-loop system and will demonstrate the actual

overall supply performance. For a detailed explanation of

optimizing the compensation components, including a re-

view of control loop theory, refer to Application Note 76.

In some applications, a more severe transient can be caused

by switching in loads with large (>1μF) input capacitors.

The discharged input capacitors are effectively put in paral-

lel with COUT

, causing a rapid drop in VOUT

. No regulator

can deliver enough current to prevent this problem, if the

switch connecting the load has low resistance and is driven

quickly. The solution is to limit the turn-on speed of the

load switch driver. A Hot Swap™ controller is designed

speciﬁ cally for this purpose and usually incorporates cur-

rent limiting, short-circuit protection, and soft-starting.

Efﬁ ciency Considerations

The percent efﬁ ciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁ ciency and which change would

Hot Swap is a trademark of Linear Technology Corporation.

LTC3407-4

34074fa

APPLICATIONS INFORMATION

produce the most improvement. Percent efﬁ ciency can

be expressed as:

%Efﬁ ciency = 100% - (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, 4 main sources usually account for most of the

losses in LTC3407-4 circuits: 1)VIN quiescent current, 2)

switching losses, 3) I2R losses, 4) other losses.

1) The VIN current is the DC supply current given in the

Electrical Characteristics which excludes MOSFET driver

and control currents. VIN current results in a small (<0.1%)

loss that increases with VIN, even at no load.

2) The switching current is the sum of the MOSFET driver

and control currents. The MOSFET driver current results

from switching the gate capacitance of the power MOSFETs.

Each time a MOSFET gate is switched from low to high

to low again, a packet of charge dQ moves from VIN to

ground. The resulting dQ/dt is a current out of VIN that is

typically much larger than the DC bias current. In continu-

ous mode, IGATECHG = fO(QT + QB), where QT and QB are

the gate charges of the internal top and bottom MOSFET

switches. The gate charge losses are proportional to VIN

and thus their effects will be more pronounced at higher

supply voltages.

3) I2R losses are calculated from the DC resistances of

the internal switches, RSW, and external inductor, RL. In

continuous mode, the average output current ﬂ ows through

inductor L, but is “chopped” between the internal top and

bottom switches. Thus, the series resistance looking into

the SW pin is a function of both top and bottom MOSFET

RDS(ON) and the duty cycle (DC) as follows:

SW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)

The RDS(ON) for both the top and bottom MOSFETs can

be obtained from the Typical Performance Characteristics

curves. Thus, to obtain I2R losses:

2R losses = IOUT2(RSW + RL)

4) Other ‘hidden’ losses such as copper trace and internal

battery resistances can account for additional efﬁ ciency

degradations in portable systems. It is very important

to include these “system” level losses in the design of a

system. The internal battery and fuse resistance losses

can be minimized by making sure that CIN has adequate

charge storage and very low ESR at the switching frequency.

Other losses including diode conduction losses during

dead-time and inductor core losses generally account for

less than 2% total additional loss.

Thermal Considerations

In a majority of applications, the LTC3407-4 does not

dissipate much heat due to its high efﬁ ciency. However,

in applications where the LTC3407-4 is running at high

ambient temperature with low supply voltage and high

duty cycles, such as in dropout, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 150°C,

both power switches will turn off and the SW node will

become high impedance.

To prevent the LTC3407-4 from exceeding the maximum

junction temperature, the user will need to do some thermal

analysis. The goal of the thermal analysis is to determine

whether the power dissipated exceeds the maximum

junction temperature of the part. The temperature rise is

given by:

RISE = PD • θJA

where PD is the power dissipated by the regulator and θJA

is the thermal resistance from the junction of the die to

the ambient temperature.

The junction temperature, TJ, is given by:

J = TRISE + TAMBIENT

As an example, consider the case when the LTC3407-4 is

in dropout on both channels at an input voltage of 2.7V

with a load current of 800mA and an ambient temperature

of 70°C. From the Typical Performance Characteristics

graph of Switch Resistance, the RDS(ON) resistance of

the main switch is 0.425Ω. Therefore, power dissipated

by each channel is:

D = IOUT2 • RDS(ON) = 272mW

The MS package junction-to-ambient thermal resistance,

θJA, is 45°C/W. Therefore, the junction temperature of

LTC3407-4

34074fa

APPLICATIONS INFORMATION

the regulator operating in a 70°C ambient temperature is

approximately:

J = 2 • 0.272 • 45 + 70 = 94.5°C

which is below the absolute maximum junction tempera-

ture of 125°C.

Design Example

As a design example, consider using the LTC3407-4 in

an portable application with a Li-Ion battery. The battery

provides a VIN = 2.8V to 4.2V. The load requires a maximum

of 800mA in active mode and 2mA in standby mode. The

output voltage is VOUT = 2.5V. Since the load still needs

power in standby, Burst Mode operation is selected for

good low load efﬁ ciency.

First, calculate the inductor value for about 30% ripple

current at maximum VIN:

L2.5V

2.25MHz • 300mA•1–

2.5V

4.2V









=1.5μH

Choosing a vendor’s closest inductor value of 2.2μH,

results in a maximum ripple current of:

IL=2.5V

2.25MHz • 2.2μH•12.5V

4.2V









=204mA

For cost reasons, a ceramic capacitor will be used. COUT

selection is then based on load step droop instead of ESR

requirements. For a 5% output droop:

COUT ≈2.5 800mA

2.25MHz •(5% • 2.5V) =7.1μF

A good standard value is 10μF. Since the output impedance

of a Li-Ion battery is very low, CIN is typically 10μF.

The output voltage can now be programmed by choosing

the values of R1 and R2. To maintain high efﬁ ciency, the

current in these resistors should be kept small. Choosing

2μA with the 0.6V feedback voltage makes R1~300k. A close

standard 1% resistor is 280k, and R2 is then 887k.

The POR pin is a common drain output and requires a pull-

up resistor. A 100k resistor is used for adequate speed.

Figure 1 shows the complete schematic for this design

example.

Board Layout Considerations

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3407-4. These items are also illustrated graphically

in the layout diagram of Figure 3. Check the following in

your layout:

1. Does the capacitor CIN connect to the power VIN (Pin

3) and GND (exposed pad) as close as possible? This

capacitor provides the AC current to the internal power

MOSFETs and their drivers.

2. Are the COUT and L1 closely connected? The (–) plate of

COUT returns current to GND and the (–) plate of CIN.

3. The resistor divider, R1 and R2, must be connected

between the (+) plate of COUT and a ground sense line

terminated near GND (Exposed Pad). The feedback signals

VFB should be routed away from noisy components and

traces, such as the SW line (Pins 4 and 7), and its trace

should be minimized.

4. Keep sensitive components away from the SW pins. The

input capacitor CIN and the resistors R1 to R4 should be

routed away from the SW traces and the inductors.

5. A ground plane is preferred, but if not available, keep

the signal and power grounds segregated with small signal

components returning to the GND pin at one point and

should not share the high current path of CIN or COUT

6. Flood all unused areas on all layers with copper. Flood-

ing with copper will reduce the temperature rise of power

components. These copper areas should be connected to

VIN or GND.

Figure 3. LTC3407-4 Layout Diagram (See Board Layout Checklist)

RUN2 VIN

VIN

VOUT2 VOUT1

RUN1

POR

SW1

VFB1

GND

VFB2

SW2

MODE/SYNC

LTC3407-4

CIN

C4C5

R4 R2

COUT2 COUT1

3407 F03

BOLD LINES INDICATE HIGH CURRENT PATHS

LTC3407-4

34074fa

TYPICAL APPLICATIONS

Low Ripple Buck Regulators Using Ceramic Capacitors

Efﬁ ciency vs Load Current

1mm Height Core Supply

Efﬁ ciency vs Load Current

RUN2 VIN

VIN

2.5V TO 5.5V

VOUT2

1.8V

800mA

VOUT1

1.2V

800mA

RUN1

POR

SW1

VFB1

GND

VFB2

SW2

MODE/SYNC

LTC3407-4

10μF

100k

POWER-ON

RESET

C4, 22pFC5, 22pF

4.7μH

887k

604k

442k

10μF

3407 TA03

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML L1, L2: SUMIDA CDRH2D18/HP-4R7NC LOAD CURRENT (mA)

EFFICIENCY (%)

100 1000

34074 TA03b

100

VIN = 3.6V

PULSE-SKIPPING MODE

NO LOAD ON OTHER CHANNEL

VOUT = 1.8V

VOUT = 1.2V

RUN2 VIN

VIN

3.6V TO 5.5V

VOUT2

3.3V

800mA

VOUT1

1.8V

800mA

RUN1

POR

SW1

VFB1

GND

VFB2

SW2

MODE/SYNC

LTC3407-4

C1*

10μF

100k

POWER-ON

RESET

C4, 22pFC5, 100pF

2.2μH

887k

604k

301k

196k

10μF

3407 TA07

C1, C2, C3: TAIYO YUDEN JMK212BJ106MD-B

L1, L2: COILTRONICS LPO3310-222MX

*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,

ADDITIONAL CAPACITANCE MAY BE REQUIRED.

LOAD CURRENT (mA)

EFFICIENCY (%)

10 100 1000

34074 TA08

100

VIN = 5V

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

VOUT = 3.3V

VOUT = 1.8V

LTC3407-4

34074fa

PACKAGE DESCRIPTION

3.00 p0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 p 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 p 0.10

(2 SIDES)

0.75 p0.05

R = 0.125

TYP

2.38 p0.10

(2 SIDES)

106

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD) DFN REV B 0309

0.25 p 0.05

2.38 p0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 p0.05

(2 SIDES)

2.15 p0.05

0.50

BSC

0.70 p0.05

3.55 p0.05

PACKAGE

OUTLINE

0.25 p 0.05

0.50 BSC

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev B)

LTC3407-4

34074fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

MSOP (MSE) 0908 REV C

0.53 p 0.152

(.021 p .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 – 0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

12345

4.90 p 0.152

(.193 p .006)

0.497 p 0.076

(.0196 p .003)

REF

8910

3.00 p 0.102

(.118 p .004)

(NOTE 3)

3.00 p 0.102

(.118 p .004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0o – 6o TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 p 0.127

(.035 p .005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 p 0.038

(.0120 p .0015)

TYP

2.083 p 0.102

(.082 p .004)

2.794 p 0.102

(.110 p .004)

0.50

(.0197)

BSC

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.83 p 0.102

(.072 p .004)

2.06 p 0.102

(.081 p .004)

0.1016 p 0.0508

(.004 p .002)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.05 REF

0.29

REF

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev C)

LTC3407-4

34074fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0809 REV A • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator

Efﬁ ciency vs Load Current Efﬁ ciency vs Load Current

RUN2 VIN

VIN

2.8V TO 4.2V

VOUT2

3.3V AT 100mA

VOUT1

1.8V AT 800mA

RUN1

POR

SW1

VFB1

GND

VFB2

SW2

MODE/SYNC

LTC3407-4

10μF

100k

POWER-ON

RESET

C4, 33pF

C5, 22pF

2.2μH

15μH

887k

604k

301k

196k

4.7μF

22μF

10μF

34074 TA04

C1, C2: TAIYO YUDEN JMK316BJ106ML

C3: MURATA GRM21BR60J475KA11B

C6: KEMET C1206C226K9PAC

D1: PHILIPS PMEG2010

L1: MURATA LQH32CN2R2M33

L2: TOKO A914BYW-150M (D52LC SERIES)

M1: SILICONIX Si2302DS

LOAD CURRENT (mA)

EFFICIENCY (%)

30 10 100 1000

34074 TA05

VOUT = 3.3V

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

4.2V

2.8V

3.6V

LOAD CURRENT (mA)

EFFICIENCY (%)

100

60 10 100 1000

34074 TA06

VOUT = 1.8V

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

4.2V

2.8V

3.6V

PART NUMBER DESCRIPTION COMMENTS

LTC1878 600mA (IOUT), 550kHz,

Synchronous Step-Down DC/DC Converter

95% Efﬁ ciency, VIN: 2.7V to 6V, VOUT(MIN) = 0.8V, IQ = 10μA,

ISD <1μA, MSOP-8, Package

LT1940 Dual Output 1.4A(IOUT), Constant 1.1MHz,

High Efﬁ ciency Step-Down DC/DC Converter

VIN: 3V to 25V, VOUT(MIN) = 1.2V, IQ = 2.5mA, ISD = <1μA,

TSSOP-16E Package

LTC3252 Dual 250mA (IOUT), 1MHz, Spread Spectrum

Inductorless Step-Down DC/DC Converter

88% Efﬁ ciency, VIN: 2.7V to 5.5V, VOUT(MIN) = 0.9V to 1.6V,

IQ = 60μA, ISD < 1μA, DFN-12 Package

LTC3405/LTC3405A 300mA (IOUT), 1.5MHz,

Synchronous Step-Down DC/DC Converters

96% Efﬁ ciency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20μA,

ISD <1μA, ThinSOT™ Package

LTC3406/LTC3406B 600mA (IOUT), 1.5MHz,

Synchronous Step-Down DC/DC Converters

96% Efﬁ ciency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA,

ISD <1μA, ThinSOT Package

LTC3407/LTC3407-2 600mA/800mA, 1.5MHz

Dual Synchronous Step-Down DC/DC Converter

96% Efﬁ ciency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA,

ISD <1μA, MSE, DFN Package

LTC3411 1.25A (IOUT), 4MHz,

Synchronous Step Down DC/DC Converter

95% Efﬁ ciency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA,

ISD <1μA, MSOP-10 Package

LTC3412 2.5A (IOUT), 4MHz,

Synchronous Step Down DC/DC Converter

95% Efﬁ ciency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA,

ISD <1μA, TSSOP-16E Package

LTC3414 4A (IOUT), 4MHz,

Synchronous Step Down DC/DC Converter

95% Efﬁ ciency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA,

ISD <1μA, TSSOP-28E Package

LTC3440 600mA (IOUT), 2MHz,

Synchronous Buck-Boost DC/DC Converter

95% Efﬁ ciency, VIN: 2.5V to 5.5V, VOUT(MIN) = 2.5V, IQ = 25μA,

ISD <1μA, MSOP-10 Package

ThinSOT is a trademark of Linear Technology Corporation.