ETM33E-03 Application Manual Real Time Clock Module RX-4803SA/LC Preliminary * * * * * * * NOTICE This material is subject to change without notice. Any part of this material may not be reproduced or duplicated in any form or any means without the written permission of Seiko Epson. The information about applied circuitry, software, usage, etc. written in this material is intended for reference only. Seiko Epson does not assume any liability for the occurrence of infringing on any patent or copyright of a third party. This material does not authorize the licensing for any patent or intellectual copyrights. When exporting the products or technology described in this material, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 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All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective. RX - 4803 SA / LC Contents 1. Overview........................................................................................................................ 1 2. Block Diagram ............................................................................................................... 1 3. Terminal description ...................................................................................................... 2 3.1. Terminal connections ....................................................................................................................... 2 3.2. Pin Functions .................................................................................................................................... 2 4. Absolute Maximum Ratings ........................................................................................... 3 5. Recommended Operating Conditions ............................................................................ 3 6. Frequency Characteristics ............................................................................................. 3 7. Electrical Characteristics................................................................................................ 4 7.1. DC characteristics ............................................................................................................................ 4 7.2. AC Characteristics ............................................................................................................................ 5 8. Use Methods.................................................................................................................. 6 8.1. Description of Registers ................................................................................................................... 6 8.1.1. Write / Read and Bank Select ............................................................................................ 6 8.1.2. Register table (Bank1) ....................................................................................................... 6 8.1.3. Register table (Bank2) ....................................................................................................... 7 8.1.4. Register table (Bank3) ....................................................................................................... 7 8.2. Details of Registers .......................................................................................................................... 8 8.2.1. Clock counter ( 1/100S, SEC - HOUR ) ............................................................................. 8 8.2.2. Calendar counter ( WEEK - YEAR ) ................................................................................... 9 8.2.3. Alarm registers ................................................................................................................. 10 8.2.4. Fixed-cycle timer control registers.................................................................................... 10 8.2.5. Extension register............................................................................................................. 10 8.2.6. Flag register ..................................................................................................................... 11 8.2.7. Control register ................................................................................................................. 12 8.2.8. OSC Offset Contorol ( Reg -C / Bank 3 ) ........................................................................ 14 8.2.9. Capture Buffer / Event control ( Bank 3 ) ......................................................................... 14 8.3. Fixed-cycle Timer Interrupt Function .............................................................................................. 16 8.3.1. Diagram of fixed-cycle timer interrupt function ................................................................. 16 8.3.2. Related registers for function of time update interrupts. .................................................. 16 8.3.3. Fixed-cycle timer interrupt interval (example) .................................................................. 18 8.3.4. Fixed-cycle timer start timing............................................................................................ 18 8.4. Time Update Interrupt Function ...................................................................................................... 19 8.4.1. Time update interrupt function diagram ........................................................................... 19 8.4.2. Related registers for time update interrupt functions. ...................................................... 20 8.5. Alarm Interrupt Function ................................................................................................................. 21 8.4.1. Diagram of alarm interrupt function .................................................................................. 21 8.5.2. Related registers .............................................................................................................. 22 8.5.2. Examples of alarm settings .............................................................................................. 23 8.6. Read/Write of data ......................................................................................................................... 24 8.6.1. Write of data ..................................................................................................................... 24 8.6.2. Read of data ..................................................................................................................... 24 8.7. VDD and CE timing ........................................................................................................................ 24 8.8. Backup and Recovery .................................................................................................................... 25 8.8. Connection with Typical Microcontroller ......................................................................................... 26 8.9. When used as a clock source (32 kHz-TCXO) ............................................................................... 26 9. External Dimensions / Marking Layout ......................................................................... 27 10. Application notes ....................................................................................................... 29 RX - 4803 SA / LC Serial Interface Real-time Clock Module RX - 4803 SA / LC * Features built-in 32.768 kHz DTCXO, High Stability. * Serial interface in 4 lines form * Alarm interrupt function for day, date, hour, and minute settings * Fixed-cycle timer interrupt function * Time update interrupt function (Seconds, minutes) * 32.768 kHz output with OE function (FOE and FOUT pins) * Auto correction of leap years (from 2000 to 2099) * Wide interface voltage range: 1.6 V to 5.5 V * Wide time-keeping voltage range: 1.6 V to 5.5 V * Low current consumption: 0.75A / 3 V (Typ.) . 1. Overview This module is an serial interface real-time clock which includes a 32.768 kHz DTCXO. In addition to providing a calendar (year, month, date, day, hour, minute, second) function and a clock counter function, this module provides an abundance of other functions including an alarm function, fixed-cycle timer function, time update interrupt function, and 32.768 kHz output function. The devices in this module are fabricated via a C-MOS process for low current consumption, which enables long-term battery back-up. All of these many functions are implemented in SOP-14 pin and VSOJ-12 pin package. 2. Block Diagram 32.768 kHz 32kHz DTCXO DIVIDER FOE FOUT EVIN / INT CLOCK and CALENDAR FOUT CONTROLLER TIMER REGISTER INTERRUPT CONTROLLER ALARM REGISTER DI DO INTERFACE CLK CIRCUIT SYSTEM CONTROLLER and CONTROL REGISTER CE Page - 1 ETM33E - 03 RX - 4803 SA / LC 3. Terminal description 3.1. Terminal connections RX - 4803 SA RX - 4803 LC 1. CE 14. D I 2. CLK 13. DO 3. FOUT 12. T2 (VPP) 4. N.C. 5. TEST 1. N.C. 12. EVIN 2. FOE 11. / INT 11. GND 3. VDD 10. GND 10. / INT 4. FOUT 9. T2 (VPP) 6. VDD 9. EVIN 5. CLK 8. D O 7. FOE 8. N.C. 6. C E 7. D I VSOJ - 12pin SOP - 14pin 3.2. Pin Functions Signal name I/O Function CE Input This is the chip enabled input pin. It has a built-in pull-down resistance. When the CE pin is at the "H" level, access to this RTC becomes possible. Also, when the chip is not selected, the DO pin is at the high impedance level, and the CLK and DI pins would not accept input. CLK Input This is the shift clock input pin for serial data transfer. In the write mode, it takes in data from the DI pin using the CLK signal rise edge. In the read mode, it outputs data from the DO pin using the fall edge. DI Input This is the data input pin for serial data transfer. DO Output This is the data output pin for serial data transfer. FOUT Output This is the C-MOS output pin with output control provided via the FOE pin. When FOE = "H" (high level), this pin outputs a 32.768 kHz signal. When output is stopped, the FOUT pin = "Hi-Z"( high impedance ). FOE Input This is an input pin used to control the output mode of the FOUT pin. When this pin's level is high, the FOUT pin is in output mode. When it is low, output via the FOUT pin is stopped. / INT Output This pins is used to output alarm signals, timer signals, time update signals, and other signals. This pin is an open drain pin. EVIN Input VDD - This pin is connected to a positive power supply. GND - This pin is connected to a ground. TEST Input Use by the manufacture for testing. ( Do not connect externally.) T2(VPP) - Use by the manufacture for testing. ( Do not connect externally.) N.C. - This pin is not connected to the internal IC. Leave N.C. pins open or connect them to GND or VDD. External event input pin. Note: Be sure to connect a bypass capacitor rated at least 0.1 F between VDD and GND. Page - 2 ETM33E - 03 RX - 4803 SA / LC 4. Absolute Maximum Ratings GND = 0 V Item Symbol Condition Rating Unit Supply voltage VDD Between VDD and GND -0.3 to +6.5 V Input voltage VIN1 CE, CLK, DI, FOE, EVIN pin -0.3 to +6.5 V Output voltage (1) VOUT1 DO, FOUT pin GND-0.3 to VDD+0.3 V Output voltage (2) VOUT2 /INT pins GND-0.3 to +6.5 V Storage temperature TSTG When stored separately, without packaging -55 to +125 C 5. Recommended Operating Conditions GND = 0 V Item Symbol Condition Min. Typ. Max. Unit Operating supply voltage VDD Interface voltage 1.6 3.0 5.5 V Temp. compensation voltage VTEM Temperature compensation voltage 2.2 3.0 5.5 V Clock supply voltage VCLK - 1.6 3.0 5.5 V Operating temperature TOPR No condensation -40 +25 +85 C 6. Frequency Characteristics Item Frequency stability GND = 0 V Symbol Condition Rating UA Ta= 0 to +50 C, VDD=3.0 V Ta=-40 to +85 C, VDD=3.0 V 1.9 (1) UB Ta= 0 to +50 C, VDD=3.0 V Ta=-40 to +85 C, VDD=3.0 V 3.8 (3) UC Ta= 0 to +50 C, VDD=3.0 V Ta=-30 to +70 C, VDD=3.0 V 3.8 AA Ta= f/f +25 C, VDD=3.0 V 3.4 (2) 5.0 (4) x 10- (3) 5.0 (4) +5 5.0 (5) Frequency/voltage characteristics f/V Ta= +25 C, VDD=2.2 V to 5.5 V Oscillation start time tSTA Ta= +25 C, VDD=1.6 V Ta=-40 to +85 C, VDD=1.6 V to 5.5 V 1.0 Max. Aging fa Ta= +25 C, VDD=3.0 V, first year 3 Max. *1 ) Equivalent to 5 seconds of month deviation. *3 ) Equivalent to 10 seconds of month deviation. Unit 1.0 Max. x 10- / V s 3.0 Max. x 10- / year *2 ) Equivalent to 9 seconds of month deviation. *4 ) *5 ) Equivalent to 13 seconds of month deviation. ( excluding offset ) Page - 3 ETM33E - 03 RX - 4803 SA / LC 7. Electrical Characteristics 7.1. DC characteristics Item Symbol Current consumption (1) IDD1 Current consumption (2) IDD2 Current consumption (3) IDD3 Current consumption (4) IDD4 Current consumption (5) IDD5 Current consumption (6) IDD6 Current consumption (7) IDD7 Current consumption (8) IDD8 Current consumption (9) IDD9 Current consumption (10) High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leakage current Output leakage current Input resistance *Unless otherwise specified, GND = 0 V , VDD = 1.6 V to 5.5 V , Ta = -40 C to +85 C Condition Min. Typ. Max. CE = GND, /INT = VDD FOE = GND FOUT : output OFF ( High Z ) Compensation interval 2.0 s VDD =5 V 0.75 3.4 VDD=3 V 0.75 2.1 CE = GND, /INT, FOE = VDD FOUT : 32 kHz, CL = 0 pF Compensation interval 2.0 s VDD=5 V 2.0 7.5 VDD=3 V 1.5 5.0 CE = GND, /INT, FOE = VDD FOUT: 32 kHz, CL = 30 pF Compensation interval 2.0 s VDD=5 V 7.0 20.0 VDD=3 V 4.5 12.0 CE = GND, /INT, FOE = GND FOUT : output OFF ( High Z ) Compensation OFF VDD=5 V 0.7 2.95 VDD=3 V 0.7 1.85 VDD=5 V 120 900 VDD=3 V 115 350 Unit A A A A IDD10 CE = GND, /INT, FOE = GND FOUT : output OFF ( High Z ) Compensation ON ( peak ) VIH CE, DI, CLK, FOE, EVIN pins 0.8 x VDD 5.5 V VIL CE, DI, CLK, FOE, EVIN pins GND - 0.3 0.2 x VDD V 4.5 2.2 2.9 GND GND GND GND GND 5.0 3.0 3.0 GND+0.5 GND+0.8 GND+0.1 GND+0.25 GND+0.4 VOH1 VOH2 VOH3 VOL1 VOL2 VOL3 VOL4 VOL5 FOUT, DO pins FOUT, DO pins /INT pin A VDD=5 V, IOH=-1 mA VDD=3 V, IOH=-1 mA VDD=3 V, IOH=-100 A VDD=5 V, IOL=1 mA VDD=3 V, IOL=1 mA VDD=3 V, IOL=100 A VDD=5 V, IOL=1 mA VDD=3 V, IOL=1 mA V V V ILK CE, DI, CLK, FOE pins, VIN = VDD or GND -0.5 0.5 A IOZ /INT, DO, FOUT pins, VOUT = VDD or GND -0.5 0.5 A RDWN CE pin VDD=5 V 75 150 300 VDD=3 V 150 300 600 k * Temperature compensation and consumption current Compensation ON 1 ms IDD9,10 Average IDD7,8 Compensation OFF IDD1,2 Compensation interval ( 2.0 s ) Page - 4 ETM33E - 03 RX - 4803 SA / LC 7.2. AC Characteristics * Unless otherwise specified, GND = 0 V , Ta = -40 C to +85 C Item Symbol 2.4V VDD < 4.5V Min. Max. Condition 4.5V VDD 5.5V Min. Max. Unit CLK clock cycle tCLK 500 350 ns CLK H pulse width tWH 220 155 ns CLK L pulse width tWL 220 155 ns tRF CLK rise and fall time 60 40 ns CLK setup time tCLKS 50 25 ns CE setup time tCS 200 150 ns CE hold time tCH 200 150 ns tCR 300 CE recovery time tWCE CE enable time 200 ns 0.95 0.95 s Write data setup time tDS 100 50 ns Write data hold time tDH 100 50 ns Read data delay time tRD DO output switching time tZR DO output disable time tRZ DI/DO conflict avoiding time tZZ FOUT duty CL=50 pF CL=50 pF RL=10 k 200 150 ns 50 20 ns 200 150 ns 0 tW / t 50% VDD level 40 0 60 ns 40 60 % Timing chart tWCE tCS CE tRF tCLKS tCLK tRF tWL tWH tCH tCR 80% CLK 20% * Read DI tDS tDH M3 M2 A0 tRD tRZ tZZ Hi-Z DO D7 D6 D7 D6 D0 tZR * Write DI M3 DO M2 A0 D0 Hi-Z If DI and DO pins are wired-OR connected to make it to 3 lines form, secure tzz to avoid bus conflict. Page - 5 ETM33E - 03 RX - 4803 SA / LC 8. Use Methods 8.1. Description of Registers 8.1.1. Write / Read and Bank Select R/W and Register bank are specified by the four bits mode setting code. Bank1: Basic time and calendar register ... Bank1 is compatible with RX-4801. Bank2: Extension register ... Adds 1/100s Counter. Bank3: Extension register ... Capture buffer and Event control registers. Mode Bank 1 Bank 2 Bank 3 Read Write 9h 1h Ah 2h Bh 3h The register of the same name of Bank1 and Bank2 is the same register. 8.1.2. Register table (Bank1) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read Write 0 SEC 40 20 10 8 4 2 1 P P 1 MIN 40 20 10 8 4 2 1 P P 2 HOUR 20 10 8 4 2 1 P P 3 WEEK 6 5 4 3 2 1 0 P P 4 DAY 20 10 8 4 2 1 P P 5 MONTH 10 8 4 2 1 P P 6 YEAR 80 40 20 10 8 4 2 1 P P 7 RAM * * * * * * * * P P 8 MIN Alarm AE 40 20 10 8 4 2 1 P P 9 HOUR Alarm AE * 20 10 8 4 2 1 P P 6 5 4 3 2 1 0 * P P 20 10 8 4 2 1 WEEK Alarm A AE DAY Alarm Note B Timer Counter 0 128 64 32 16 8 4 2 1 P P C Timer Counter 1 * * * * 2048 1024 512 256 P P D Extension Register P P E Flag Register F Control Register TEST WADA USEL CSEL1 CSEL0 TE FSEL1 FSEL0 TSEL1 TSEL0 UF TF AF EVF VLF VDET P P UIE TIE AIE EIE RESET P P P : Possible , I : Impossible When after the initial power-up or when the result of read out the VLF bit is "1" , initialize all registers, before using the module. Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data or time data is incorrect. 1) During the initial power-up, the TEST bit is reset to "0" and the VLF bit is set to "1". At this point, all other register values are undefined, so be sure to perform a reset before using the module. 2) Only a "0" can be written to the UF, TF, AF, VLF, or VDET bit. 3) Any bit marked with "" should be used with a value of "0" after initialization. 4) Any bit marked with "*" is a RAM bit that can be used to read or write any data. 5) The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit when writing. Page - 6 ETM33E - 03 RX - 4803 SA / LC 8.1.3. Register table (Bank2) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read Write 0 1/100 S 80 40 20 10 8 4 2 1 P I 1 SEC 40 20 10 8 4 2 1 P P 2 MIN 40 20 10 8 4 2 1 P P 3 HOUR 20 10 8 4 2 1 P P 4 WEEK 6 5 4 3 2 1 0 P P 5 DAY 20 10 8 4 2 1 P P 6 MONTH 10 8 4 2 1 P P 7 YEAR 80 40 20 10 8 4 2 1 P P 8 MIN Alarm AE 40 20 10 8 4 2 1 P P 9 HOUR Alarm AE * 20 10 8 4 2 1 P P 6 5 4 3 2 1 0 * P P 20 10 8 4 2 1 WEEK Alarm A AE DAY Alarm B Timer Counter 0 128 64 32 16 8 4 2 1 P P C Timer Counter 1 * * * * 2048 1024 512 256 P P D Extension Register P P E Flag Register F Control Register TEST WADA USEL CSEL1 CSEL0 TE FSEL1 FSEL0 TSEL1 TSEL0 UF TF AF EVF VLF VDET P P UIE TIE AIE EIE RESET P P 1/100S Reg. is cleared to "00" by writing in the SEC Reg. or RESET bit and the ERST bit operation. 8.1.4. Register table (Bank3) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read Write 0 1/100 S CP 80 40 20 10 8 4 2 1 P I 1 SEC CP 40 20 10 8 4 2 1 P I 2 - - - - - - - - - - - 3 - - - - - - - - - - - 4 - - - - - - - - - - - 5 - - - - - - - - - - - 6 - - - - - - - - - - - 7 - - - - - - - - - - - 8 - - - - - - - - - - - 9 - - - - - - - - - - - A - - - - - - - - - - - B - - - - - - - - - - - C OSC Offset P P D - - - - - E - - - - - - F Event Control ECP EHL ET1 ET0 OFS3 OFS2 OFS1 OFS0 - - - - - - - - - - - ERST P P When an initial power on, frequency offset is 0 selected by "0000". Page - 7 ETM33E - 03 RX - 4803 SA / LC 8.2. Details of Registers It explains each register based on Bank2. 8.2.1. Clock counter ( 1/100S, SEC - HOUR ) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 2 3 1/100 S SEC MIN HOUR 80 40 40 40 20 20 20 20 10 10 10 10 8 8 8 8 4 4 4 4 2 2 2 2 1 1 1 1 ) "o" indicates write-protected bits. A zero is always read from these bits. * The clock counter counts 1/100s, seconds, minutes, and hours. * The data format is BCD format. For example, when the "seconds" register value is "0101 1001" it indicates 59 seconds. Note with caution that writing non-existent time data may interfere with normal operation of the clock counter. 1) 1/100 Second counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1/100 S 80 40 20 10 8 4 2 1 * This second counter counts from "00" to "01," "02," and up to 99/100 seconds, after which it starts again from 00 seconds. 2) Second counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 SEC 40 20 10 8 4 2 1 * This second counter counts from "00" to "01," "02," and up to 59 seconds, after which it starts again from 00 seconds. 3) Minute counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 MIN 40 20 10 8 4 2 1 * This minute counter counts from "00" to "01," "02," and up to 59 minutes, after which it starts again from 00 minutes. 4) Hour counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3 HOUR 20 10 8 4 2 1 * This hour counter counts from "00" hours to "01," "02," and up to 23 hours, after which it starts again from 00 hours. Page - 8 ETM33E - 03 RX - 4803 SA / LC 8.2.2. Calendar counter ( WEEK - YEAR ) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 WEEK 6 5 4 3 2 1 0 ) "o" indicates write-protected bits. A zero is always read from these bits. 1) Day of the WEEK counter * The day (of the week) is indicated by 7 bits, bit 0 to bit 6. The day data values are counted as: Day 01h Day 02h Day 04h Day 08h Day 10h Day 20h Day 40h Day 01h Day 02h, etc. * The correspondence between days and count values is shown below. WEEK bit 7 Write/Read Write prohibit bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 Do not set "1" to more than one day at the same time. Also, note with caution that any setting other than the seven shown above should not be made as it may interfere with normal operation. 1 0 0 0 0 0 0 Day Data [h] Sunday Monday Tuesday Wednesday Thursday Friday Saturday 01 h 02 h 04 h 08 h 10 h 20 h 40 h - - Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 5 6 7 DAY MONTH YEAR 20 80 40 20 10 10 10 8 8 8 4 4 4 2 2 2 1 1 1 ) "o" indicates write-protected bits. A zero is always read from these bits. * The auto calendar function updates all dates, months, and years from January 1, 2001 to December 31, 2099. * The data format is BCD format. For example, a date register value of "0011 0001" indicates the 31st. Note with caution that writing non-existent date data may interfere with normal operation of the calendar counter. 2) Date counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 DAY 20 10 8 4 2 1 * The updating of dates by the date counter varies according to the month setting. A leap year is set whenever the year value is a multiple of four (such as 04, 08, 12, 88, 92, or 96). In February of a leap year, the counter counts dates from "01," "02," "03," to "28," "29," "01," etc. DAY Write/Read Month Date update pattern 01, 02, 03 30, 31, 01 01, 02, 03 30, 01, 02 01, 02, 03 28, 01, 02 01, 02, 03 28, 29, 01 1, 3, 5, 7, 8, 10, or 12 4, 6, 9, or 11 February in normal year February in leap year 3) Month counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 5 MONTH 10 8 4 2 1 * The month counter counts from 01 (January), 02 (February), and up to 12 (December), then starts again at 01 (January). 4) Year counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6 YEAR Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 * The year counter counts from 00, 01, 02 and up to 99, then starts again at 00. * Any year that is a multiple of four (04, 08, 12, 88, 92, 96, etc.) is handled as a leap year. Page - 9 ETM33E - 03 RX - 4803 SA / LC 8.2.3. Alarm registers Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8 9 MIN Alarm HOUR Alarm WEEK Alarm DAY Alarm AE AE 40 * 6 * 20 20 5 20 10 10 4 10 8 8 3 8 4 4 2 4 2 2 1 2 1 1 0 1 A AE * The alarm interrupt function is used, along with the AEI, AF, and WADA bits, to set alarms for specified date, day, hour, and minute values. * When the settings in the above alarm registers and the WADA bit match the current time, the /INT pin goes to low level and "1" is set to the AF bit to report that and alarm interrupt event has occurred. 8.2.4. Fixed-cycle timer control registers Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 B C Timer Counter 0 Timer Counter 1 128 * 64 * 32 * 16 * 8 2048 4 1024 2 512 1 256 * These registers are used to set the preset countdown value for the fixed-cycle timer interrupt function. The TE, TF, TIE, and TSEL0/1 bits are also used to set the fixed-cycle timer interrupt function. * When the value in the above fixed-cycle timer control register changes from 001h to 000h, the /INT pin goes to low level and "1" is set to the TF bit to report that a fixed-cycle timer interrupt event has occurred. 8.2.5. Extension register Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D Extension Register TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0 (Default) (0) (-) (-) (-) (0) (0) (-) (-) 1) 2) 3) The default value is the value that is read (or is set internally) after powering up from 0 V. "o" indicates write-protected bits. A zero is always read from these bits. "-" indicates a default value is undefined. * This register is used to specify the target for the alarm function or time update interrupt function and to select or set operations such as fixed-cycle timer operations. 1) TEST bit This is the manufacturer's test bit. Its value should always be "0". Be careful to avoid writing a "1" to this bit when writing to other bits. Data Description TEST Default 0 Normal operation mode 1 Setting prohibited (manufacturer's test bit) Write/Read 2) WADA ( Week Alarm/Day Alarm ) bit This bit is used to specify either WEEK or DAY as the target of the alarm interrupt function. Writing a "1" to this bit specifies DAY as the comparison obLCct for the alarm interrupt function. Writing a "0" to this bit specifies WEEK as the comparison obLCct for the alarm interrupt function. 3) USEL ( Update Interrupt Select ) bit This bit is used to specify either "second update" or "minute update" as the update generation timing of the time update interrupt function. Auto reset time Data update interrupts USEL tRTN Write/Read 0 second update 1 minute update Default 500 ms 7.813 ms 4) TE ( Timer Enable ) bit This bit controls the start/stop setting for the fixed-cycle timer interrupt function. Writing a "1" to this bit specifies starting of the fixed-cycle timer interrupt function (a countdown starts from a preset value). Writing a "0" to this bit specifies stopping of the fixed-cycle timer interrupt function. Page - 10 ETM33E - 03 RX - 4803 SA / LC 5) FSEL0,1 ( FOUT frequency Select 0, 1 ) bits The combination of these two bits is used to set the FOUT frequency. FSEL1 FSEL0 FOUT frequency FSEL0,1 (bit 3) (bit 2) Write/Read 0 0 32768 Hz Output 0 1 1024 Hz Output 1 0 1 Hz Output 1 1 32768 Hz Output Default 6) TSEL0,1 ( Timer Select 0, 1 ) bits The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer interrupt function (four settings can be made). TSEL1 TSEL0 Source clock TSEL0,1 (bit 1) (bit 0) Write/Read 0 0 4096 Hz / Once per 244.14 s 0 1 64 Hz / Once per 15.625 ms 1 0 "Second" update / Once per second 1 1 "Minute" update / Once per minute 8.2.6. Flag register Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 E Flag register UF TF AF EVF VLF VDET (Default) (0) (0) (-) (-) (-) (0) (1) (1) 1) The default value is the value that is read (or is set internally) after powering up from 0 V. 2) "o" indicates write-protected bits. A zero is always read from these bits. 3) "-" indicates a default value is undefined. * This register is used to detect the occurrence of various interrupt events and reliability problems in internal data. 1) UF ( Update Flag ) bit If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a time update interrupt event has occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it. For details, see "8.4. Time Update Interrupt Function". 2) TF ( Timer Flag ) bit If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a fixed-cycle timer interrupt event has occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it. For details, see "8.3. Fixed-cycle Timer Interrupt Function". 3) AF ( Alarm Flag ) bit If set to "0" beforehand, this flag bit's value changes from "0" to 1" when an alarm interrupt event has occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it. For details, see "8.5. Alarm Interrupt Function". 4) EVF ( Event Flag ) bit If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a event input interrupt has occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it. 5) VLF ( Voltage Low Flag ) bit This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1" when data loss occurs, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is retained until a "0" is written to it. When after powering up from 0 V this bit's value is "1" . Page - 11 ETM33E - 03 RX - 4803 SA / LC Data VLF Description 0 The VLF bit is cleared to zero to prepare for the next status detection. 1 This bit is invalid after a "1" has been written to it. 0 Data loss is not detected. 1 Data loss is detected. All registers must be initialized. ( This setting is retained until a "zero" is written to this bit. ) Write Read 5) VDET ( Voltage Detection Flag ) bit This flag bit indicates the status of temperature compensation. Its value changes from "0" to "1" when stop the temperature compensation, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is retained until a "0" is written to it. When after powering up from 0 V this bit's value is "1". VDET Data Description 0 The VDET bit is cleared to zero to prepare for the next low voltage detection. 1 The write access of "1" to this bit is invalid. 0 Temperature compensation is normal. 1 Temperature compensation is stop detected. Write Read 8.2.7. Control register Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 F Control Register CSEL1 CSEL0 UIE TIE AIE EIE RESET (Default) (0) (1) (-) (-) (-) (0) (0) (-) 1) The default value is the value that is read (or is set internally) after powering up from 0 V. 2) "o" indicates write-protected bits. A zero is always read from these bits. 3) "-" indicates no default value has been defined. * This register is used to control interrupt event output from the /INT pin and the stop/start status of clock and calendar operations. 1) CSEL0,1 ( Compensation interval Select 0, 1 ) bits The combination of these two bits is used to set the temperature compensation interval. CSEL1 CSEL0 Compensation interval CSEL0,1 (bit 7) (bit 6) Write/Read 0 0 0.5 s 0 1 2.0 s 1 0 10 s 1 1 30 s Default 2) UIE ( Update Interrupt Enable ) bit When a time update interrupt event is generated (when the UF bit value changes from "0" to "1"), this bit's value specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an interrupt event is generated. When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs. Page - 12 ETM33E - 03 RX - 4803 SA / LC UIE Data 0 Write/Read 1 Function When a time update interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z). When a time update interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Z to low). When a time update interrupt event occurs, low-level output from the /INT pin occurs only when the value of the control register's UIE bit is "1". This /INT status is automatically cleared (/INT status changes from low to Hi-Z) 7.8 ms after the interrupt occurs. 2) TIE ( Timer Interrupt Enable ) bit When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an interrupt event is generated. When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs. Data Function TIE 0 Write/Read 1 When a fixed-cycle timer interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z). When a fixed-cycle timer interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Z to low). * When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z). 3) AIE ( Alarm Interrupt Enable ) bit When an alarm timer interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an interrupt event is generated. When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs. Data Function AIE 0 Write/Read 1 When an alarm interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z). When an alarm interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Z to low). When an alarm interrupt event has been generated low-level output from the /INT pin occurs only when the value of the control register's AIE bit is "1". This setting is retained until the AF bit value is cleared to zero. (No automatic cancellation) For details, see "8.5. Alarm Interrupt Function". [Caution] (1) The /INT pin is a shared interrupt output pin for three types of interrupts. It outputs the OR'ed result of these interrupt outputs. When an interrupt has occurred (when the /INT pin is at low level), the UF, TF, read AF flags to determine which flag has a value of "1" (this indicates which type of interrupt event has occurred). (2) To keep the /INT pin from changing to low level, write "0" to the UIE, TIE, and AIE bits. To check whether an event has occurred without outputting any interrupts via the /INT pin, use software to monitor the value of the UF, TF, and AF interrupt flags. 4) EIE ( Event Interrupt Enable ) bit When a Event input is generated (when the EVF bit value changes from "0" to "1"), this bit's value specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an interrupt event is generated. When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs. 5) RESET bit When this bit is set to "1", values (less than seconds) of the counter in the Clock & Calendar circuitry is reset, and the clock also stops. After "1" is written to this bit, this can be released by setting CE to "L". Page - 13 ETM33E - 03 RX - 4803 SA / LC 8.2.8. OSC Offset Contorol ( Reg -C / Bank 3 ) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 C OSC Offset OFS3 OFS2 OFS1 OFS0 1) OFS bits (OFS3-OFS0) The offset adjustment is done to the oscillation frequency. -6 OFS3 OFS2 OFS1 OFS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Adjust value ( x 10 ) RX-4803SA RX-4803LC 0.0 0.0 -0.6 -0.7 -1.2 -1.4 -1.8 -2.1 -2.4 -2.8 -3.0 -3.5 -3.6 -4.2 -4.2 -4.9 +4.8 +5.6 +4.2 +4.9 +3.6 +4.2 +3.0 +3.5 +2.4 +2.8 +1.8 +2.1 +1.2 +1.4 +0.6 +0.7 *The OFS register affects the frequency stability. Please refer to a lower graph. Please be careful if you offset and adjust it. The offset function is effective for frequency adjustment at the normal temperature. Frequency Stability vs. Temperature vs. OSC Offset Value (Typ_data) 20 OSC_Offset:08h Frequency Stability [10-6] 15 10 5 OSC_Offset:00h 0 -5 -10 -15 OSC_Offset:07h -20 -40 -15 10 35 60 85 Temperature [] Page - 14 ETM33E - 03 RX - 4803 SA / LC 8.2.9. Capture Buffer / Event control ( Bank 3 ) Address Function bit 7 bit 6 bit 5 0 1/100 S CP 80 40 20 1 SEC CP 40 20 F Event Control ECP EHL ET1 It is a register that sets it concerning the event detection. bit 4 10 10 ET0 bit 3 8 8 bit 2 4 4 bit 1 2 2 bit 0 1 1 ERST 1) ECP bit ( Event Capture enable ) It is specified whether to do the second and 1/100S data to the capture buffer in capture when the event is detected. ECP 0 1 Operation Capture doesn't operate Capture operation 2) EHL bit ( High/Low detection select ) The disregard level of the event input is specified. The event is detected by maintaining the level specified by the EHL bit longer than the chattering removal cycle. EHL 0 1 Operation "L" level detect "H" level detect 3) ET1,ET0 bits ( Event chattering Time Set ) The removal cycle of the chattering removal function is set. Chattering removal cycle ET1 ET0 0 0 0 1 1 0 1 1 Cycle not provided 3.9 ms 15.6 ms 125 ms 4) ERST bit When this bit is made "1", the counter of the Clock&Calendar circuit (counter for 16KHz to 2Hz and 1/100 seconds) at less than second is reset synchronizing with the external event detection. ALL "0" is cleared to CP and the CP register of the second at the same time for 1/100 seconds. Timing continues until the event is generated after "1" is written in the ERST bit. The counter at less than second when an external event is detected is reset, and the ERST bit is cleared. Moreover, it is also possible to assume this reset action to be invalid by doing "0" writing directly to the ERST bit before the event is generated. When the highly accurate time suiting is done, this bit is used. The time for the counter at less than second to be reset influences the operation of the alarm, the fixed cycle timer, and the update interrupt of time, etc. Page - 15 ETM33E - 03 RX - 4803 SA / LC 8.3. Fixed-cycle Timer Interrupt Function The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set between 244.14 s and 4095 minutes. When an interrupt event is generated, the /INT pin goes to low level and "1" is set to the TF bit to report that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically cleared (/INT status changes from low-level to Hi-Z). Example of /INT operation 7.8ms (Max.) TIE = " 1 " " 0 " period TIE = " 1 " TE = " 0 " " 1 " 8.3.1. Diagram of fixed-cycle timer interrupt function Fixed-cycle timer starts Fixed-cycle timer stops "1" (1) TE bit (7) Operation of fixed-cycle timer "0" (9) "1" "1" (5) TIE bit "0" Hi - z /INT output (6) (7) tRTN tRTN tRTN tRTN (8) Even when the TF bit is (3) TF bit (1) * * * 001 period h 000 h "1" "0" period Event occurs cleared to zero, /INT remains low during the tRTN time. (4) Even when the TE bit is cleared to zero, /INT remains low during the tRTN time. "L" period period (2) (7) When the TE bit value change s from "0" to "1" the fixed-cycle timer function starts. The counter always starts counting down from the preset value when the TE value changes from "0" to "1". RTC internal operation Write operation (1) (2) (3) (4) (5) (6) (7) (8) (9) When a "1" is written to the TE bit, the fixed-cycle timer countdown starts from the preset value. A fixed-cycle timer interrupt event starts a countdown based on the countdown period (source clock). When the count value changes from 001h to 000h, an interrupt event occurs. After the interrupt event that occurs when the count value changes from 001h to 000h, the counter automatically reloads the preset value and again starts to count down. (Repeated operation) When a fixed-cycle timer interrupt event occurs, "1" is written to the TF bit. When the TF bit = "1" its value is retained until it is cleared to zero. If the TIE bit = "1" when a fixed-cycle timer interrupt occurs, /INT pin output goes low. If the TIE bit = "0" when a fixed-cycle timer interrupt occurs, /INT pin output remains Hi-Z. Output from the /INT pin remains low during the tRTN period following each event, after which it is automatically cleared to Hi-Z status. /INT is again set low when the next interrupt event occurs. When a "0" is written to the TE bit, the fixed-cycle timer function is stopped and the /INT pin is set to Hi-Z status. When /INT = low, the fixed-cycle timer function is stopped. The tRTN period is the maximum amount of time before the /INT pin status changes from low to Hi-Z. When /INT = low, the /INT pin status changes from low to Hi-Z as soon as the TF bit value changes from "1" to "0". When /INT = low, the /INT pin status changes from low to Hi-Z as soon as the TIE bit value changes from "1" to "0". 8.3.2. Related registers for function of time update interrupts. Page - 16 ETM33E - 03 RX - 4803 SA / LC Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 B C D E F Timer Counter 0 Timer Counter 1 Extension Register Flag Register Control Register 128 * 64 * 32 * 8 2048 4 1024 TEST WADA USEL FSEL1 FSEL0 2 512 TSEL1 1 256 TSEL0 UF AF EVF VLF VDET CSEL1 CSEL0 UIE 16 * TE TF TIE AIE EIE RESET 1) 2) "o" indicates write-protected bits. A zero is always read from these bits. Bits marked with "*" are RAM bits that can contain any value and are read/write-accessible. Before entering settings for operations, we recommend writing a "0" to the TE and TIE bits to prevent hardware interrupts from occurring inadvertently while entering settings. When the RESET bit value is "1" the time update interrupt function operates only partially. (Operation continues if the source clock setting is 4096 Hz. Otherwise, operation is stopped.) When the fixed-cycle timer interrupt function is not being used, the fixed-cycle timer control register (Reg - B to C) can be used as a RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the TE and TIE bits. 1) TSEL0,1 bits (Timer Select 0, 1) The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer interrupt function (four settings can be made). Effects of TSEL1 TSEL0 Auto reset time TSEL0,1 Source clock (bit 1) (bit 0) tRTN RESET bits 0 0 4096 Hz / Once per 244.14 s / Once per 15.625 ms 122 s - 0 1 64 Hz 7.8125 ms Does not operate Write/Read 1 0 "Second" update / Once per second 7.8125 ms when the RESET bit value is "1". 1 1 "Minute" update / Once per minute 7.8125 ms 1) The /INT pin's auto reset time (tRTN) varies as shown above according to the source clock setting. 2) When the source clock has been set to "second update" or "minute update", the timing of both countdown and interrupts is coordinated with the clock update timing. 2) Fixed-cycle Timer Control register (Reg - B to C) This register is used to set the default (preset) value for the counter. Any count value from 1 (001 h) to 4095 (FFFh) can be set. The counter counts down based on the source clock's period, and when the count value changes from 001h to 000h, the TF bit value becomes "1". The countdown that starts when the TE bit value changes from "0" to "1" always begins from the preset value. Be sure to write "0" to the TE bit before writing the preset value. If a value is written while TE = "1" the first subsequent event will not be generated correctly. Address C Address B Timer Counter 1 Timer Counter 0 bit 7 bit 6 bit 5 bit 4 * * * * bit 3 2048 bit 2 1024 bit 1 512 bit 0 256 bit 7 128 bit 6 64 bit 5 32 bit 4 16 bit 3 8 bit 2 4 bit 1 2 bit 0 1 3) TE (Timer Enable) bit This bit controls the start/stop setting for the fixed-cycle timer interrupt function. Data Description TE 0 Stops fixed-cycle timer interrupt function. 1 Starts fixed-cycle timer interrupt function. The countdown that starts when the TE bit value changes from "0" to "1" always begins from the Write/Read preset value. 4) TF (Timer Flag) bit If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a fixed-cycle timer interrupt event has occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it. Data Description TF The TF bit is cleared to zero to prepare for the next status detection 0 1 This bit is invalid after a "1" has been written to it. 0 Fixed-cycle timer interrupt events are not detected. 1 Fixed-cycle timer interrupt events are detected. (Result is retained until this bit is cleared to zero.) Write Read Clearing this bit to zero enables /INT low output to be canceled (/INT remains Hi-Z) when timer interrupt event has occurred. Page - 17 ETM33E - 03 RX - 4803 SA / LC 5) TIE (Timer Interrupt Enable) bit When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value specifies whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). Data Description TIE 1) When a fixed-cycle timer interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status remains Hi-Z). 2) When a fixed-cycle timer interrupt event occurs, the interrupt signal is canceled (/INT status changes from low to Hi-Z). Even when the TIE bit value is "0" another interrupt event may change the /INT status to low (or 0 may hold /INT = "L"). Write/Read When a fixed-cycle timer interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Z to low). When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin 1 occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z). 8.3.3. Fixed-cycle timer interrupt interval (example) Timer Counter setting Source clock 4096 Hz 64 Hz TSEL1,0 = 0,0 TSEL1,0 = 0,1 - 244.14 s 488.28 s 0 1 2 "Second" update "Minute" update TSEL1,0 = 1,0 TSEL1,0 = 1,1 - 15.625 ms 31.25 ms * * * * * * * * * 41 205 410 2048 10.010 ms 50.049 ms 100.10 ms 500.00 ms * * * * * * * * * 4095 0.9998 s 63.984 s 640.63 ms 3.203 s 6.406 s 32.000 s - 1s 2s - 1 min 2 min * * * * * * 41 s 205 s 410 s 2048 s 41 min 205 min 410 min 2048 min * * * * * * 4095 s 4095 min * Time error in fixed-cycle timer A time error in the fixed-cycle timer will produce a positive or negative time period error in the selected source clock. The fixed-cycle timer's time is within the following range relative to the time setting. (Fixed-cycle timer's time setting () - source clock period) to (timer's time setting) ) The timer's time setting = source clock period x timer counter's division value. The time actually set to the timer is adjusted by adding the time described above to the communication time for the serial data transfer clock used for the setting. 8.3.4. Fixed-cycle timer start timing Counting down of the fixed-cycle timer value starts at the rising edge of the CLK signal that occurs when the TE value is changed from "0" to "1" (after bit 0 is transferred). Address D CLK pin D O pin TE FSEL1 FSEL0 TSEL1 TSEL0 Internal timer /INT pin Operation of timer Page - 18 ETM33E - 03 RX - 4803 SA / LC 8.4. Time Update Interrupt Function The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the timing of the internal clock. When an interrupt event occurs, the UF bit value becomes "1" and the /INT pin goes to low level to indicate that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the /INT pin occurs only when the value of the control register's UIE bit is "1". This /INT status is automatically cleared (/INT status changes from low level to Hi-Z) 7.8 ms (fixed value) after the interrupt occurs. /INT operation example 7.8ms UIE = " 1 " " 0 " period UIE = " 1 " 8.4.1. Time update interrupt function diagram "1" (7) "1" (4) UIE bit "0" Hi - z /INT output (5) "L" tRTN tRTN tRTN tRTN (6) (3) (2) UF bit period period /INT status change when U F bit is cleared to zero. period "1" "0" period (1) Events Operation in RTC int' operation Write operation (1) A time update interrupt event occurs when the internal clock's value matches either the second update time or the minute update time. The USEL bit's specification determines whether it is the second update time or the minute update time that must be matched. (2) When a time update interrupt event occurs, the UF bit value becomes "1". (3) When the UF bit value is "1" its value is retained until it is cleared to zero. (4) When a time update interrupt occurs, /INT pin output is low if UIE = "1". If UIE = "0" when a timer update interrupt occurs, the /INT pin status remains Hi-Z. (5) Each time an event occurs, /INT pin output is low only up to the tRTN time (which is fixed as 7.1825 ms for time update interrupts) after which it is automatically cleared to Hi-Z. /INT pin output goes low again when the next interrupt event occurs. (6) When /INT = low, the /INT pin status changes from low to Hi-Z as soon as the UF bit value changes from "1" to "0". (7) When /INT = low, the /INT pin status changes from low to Hi-Z as soon as the UIE bit value changes from "1" to "0". Page - 19 ETM33E - 03 RX - 4803 SA / LC 8.4.2. Related registers for time update interrupt functions. Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D E F Extension Register Flag Register Control Register TEST WADA USEL UF UIE TE FSEL1 FSEL0 TSEL1 TSEL0 TF AF EVF VLF VDET TIE AIE EIE RESET ) CSEL1 CSEL0 "o" indicates write-protected bits. A zero is always read from these bits. Before entering settings for operations, we recommend writing a "0" to the UIE bit to prevent hardware interrupts from occurring inadvertently while entering settings. When the RESET bit value is "1" time update interrupt events do not occur. Although the time update interrupt function cannot be fully stopped, if "0" is written to the UIE bit, the time update interrupt function can be prevented from changing the /INT pin status to low. 1) USEL (Update Interrupt Select) bit This bit is used to select "second" update or "minute" update as the timing for generation of time update interrupt events. Data Description USEL 0 Selects "second update" (once per second) as the timing for generation of interrupt events 1 Selects "minute update" (once per minute) as the timing for generation of interrupt events Write/Read 2) UF (Update Flag) bit Once it has been set to "0", this flag bit value changes from "0" to "1" when a time update interrupt event occurs. When this flag bit = "1" its value is retained until a "0" is written to it. Data Description UF 0 The UF bit is cleared to zero to prepare for the next status detection Clearing this bit to zero does not enable the /INT low output status to be cleared (to Hi-Z). 1 This bit is invalid after a "1" has been written to it. 0 Time update interrupt events are not detected. 1 Time update interrupt events are detected. (The result is retained until this bit is cleared to zero.) Write Read 3) UIE (Update Interrupt Enable) bit When a time update interrupt event occurs (UF bit value changes from "0" to "1"), this bit selects whether to generate an interrupt signal (/INT status changes from Hi-Z to low) or to not generate it (/INT status remains Hi-Z). Data Description UIE 0 1) Does not generate an interrupt signal when a time update interrupt event occurs (/INT remains Hi-Z) 2) Cancels interrupt signal triggered by time update interrupt event (/INT changes from low to Hi-Z). Even when the UIE bit value is "0" another interrupt event may change the /INT status to low (or may hold /INT = "L"). Write/Read 1 When a time update interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Z to low). When a time update interrupt event occurs, low-level output from the /INT pin occurs only when the UIE bit value is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z). Page - 20 ETM33E - 03 RX - 4803 SA / LC 8.5. Alarm Interrupt Function The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an event has occurred. Example of /INT operation AIE = " 1 " ( AF = " 0 " " 1 " ) AF = " 1 " " 0 " or AIE = " 1 " " 0 " 8.4.1. Diagram of alarm interrupt function "1" "1" (4) AIE bit "0" (5) Hi - z (7) /INT output "L" (6) "1" (3) (2) AF bit "0" (1) Event occurs RTC internal operation Write operation (1) The hour, minute, date or day when an alarm interrupt event is to occur is set in advance along with the WADA bit, and when the setting matches the current time an interrupt event occurs. (Note) Even if the current date/time is used as the setting, the alarm will not occur until the counter counts up to the current date/time (i.e., an alarm will occur next time, not immediately). (2) When a time update interrupt event occurs, the AF bit values becomes "1". (3) When the AF bit = "1", its value is retained until it is cleared to zero. (4) If AIE = "1" when an alarm interrupt occurs, the /INT pin output goes low. When an alarm interrupt event occurs, /INT pin output goes low, and this status is then held until it is cleared via the AF bit or AIE bit. (5) If the AIE value is changed from "1" to "0" while /INT is low, the /INT status immediately changes from low to Hi-Z. After the alarm interrupt occurs and before the AF bit value is cleared to zero, the /INT status can be controlled via the AIE bit. (6) If the AF bit value is changed from "1" to "0" while /INT is low, the /INT status immediately changes from low to Hi-Z. (7) If the AIE bit value is "0" when an alarm interrupt occurs, the /INT pin status remains Hi-Z. Page - 21 ETM33E - 03 RX - 4803 SA / LC 8.5.2. Related registers Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 2 3 4 8 9 MIN HOUR WEEK DAY MIN Alarm HOUR Alarm WEEK Alarm DAY Alarm Extension Register Flag Register Control Register 40 6 10 10 4 10 10 10 4 10 8 8 3 8 8 8 3 8 4 4 2 4 4 4 2 4 2 2 1 2 2 2 1 2 1 1 0 1 1 1 0 1 TSEL0 A D E F 1) 2) AE AE 40 * 6 * 20 20 5 20 20 20 5 20 TEST WADA USEL TE FSEL1 FSEL0 TSEL1 UF TF EVF VLF VDET CSEL1 CSEL0 UIE TIE AF AIE EIE RESET AE "o" indicates write-protected bits. A zero is always read from these bits. Bits marked with "*" are RAM bits that can contain any value and are read/write-accessible. Before entering settings for operations, we recommend writing a "0" to the AIE bit to prevent hardware interrupts from occurring inadvertently while entering settings. When the RESET bit value is "1" alarm interrupt events do not occur. When the alarm interrupt function is not being used, the Alarm registers (Reg - 8 to A) can be used as a RAM register. In such cases, be sure to write "0" to the AIE bit. When the AIE bit value is "1" and the Alarm registers (Reg - 8 to A) is being used as a RAM register, /INT may be changed to low level unintentionally. 1) WADA (Week Alarm /Day Alarm) bit The alarm interrupt function uses either "Day" or "Week" as its target. The WADA bit is used to specify either WEEK or DAY as the target for alarm interrupt events. Data Description WADA 0 Sets WEEK as target of alarm function (DAY setting is ignored) 1 Sets DAY as target of alarm function (WEEK setting is ignored) Write/Read 2) Alarm registers (Reg - 8 to A) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8 9 MIN Alarm HOUR Alarm WEEK Alarm DAY Alarm AE AE 40 * 6 * 20 20 5 20 10 10 4 10 8 8 3 8 4 4 2 4 2 2 1 2 1 1 0 1 A AE The hour, minute, date or day when an alarm interrupt event will occur is set using this register and the WADA bit. In the WEEK alarm /Day alarm register (Reg - A), the setting selected via the WADA bit determines whether WEEK alarm data or DAY alarm data will be set. If WEEK has been selected via the WADA bit, multiple days can be set (such as Monday, Wednesday, Friday, Saturday). When the settings made in the alarm registers and the WADA bit match the current time, the AF bit value is changed to "1". At that time, if the AIE bit value has already been set to "1", the /INT pin goes low. 1) The register that "1" was set to "AE" bit, doesn't compare alarm. (Example) Write 80h (AE = "1") to the WEEK Alarm /DAY Alarm register (Reg - A): Only the hour and minute settings are used as alarm comparison targets. The week and date settings are not used as alarm comparison targets. As a result, alarm occurs if only an hour and minute accords with alarm data. 2) If all three AE bit values are "1" the week/date settings are ignored and an alarm interrupt event will occur once per minute. Page - 22 ETM33E - 03 RX - 4803 SA / LC 3) AF (Alarm Flag) bit When this flag bit value is already set to "0", occurrence of an alarm interrupt event changes it to "1". When this flag bit value is "1", its value is retained until a "0" is written to it. Data Description AF 0 Write The AF bit is cleared to zero to prepare for the next status detection Clearing this bit to zero enables /INT low output to be canceled (/INT remains Hi-Z) when an alarm interrupt event has occurred. 1 This bit is invalid after a "1" has been written to it. 0 Alarm interrupt events are not detected. 1 Alarm interrupt events are detected. (Result is retained until this bit is cleared to zero.) Read 4) AIE (Alarm Interrupt Enable) bit When an alarm interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value specifies whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). Data Description AIE 0 1) When an alarm interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status remains Hi-Z). 2) When an alarm interrupt event occurs, the interrupt signal is canceled (/INT status changes from low to Hi-Z). Even when the AIE bit value is "0" another interrupt event may change the /INT status to low (or may hold /INT = "L"). Write/Read 1 When an alarm interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Z to low). When an alarm interrupt event occurs, low-level output from the /INT pin occurs only when the AIE bit value is "1". This value is retained (not automatically cleared) until the AF bit is cleared to zero. 8.5.2. Examples of alarm settings 1) Example of alarm settings when "Day" has been specified (and WADA bit = "0") Reg - A Day is specified bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 WADA bit = "0" AE S F T W T M S Reg - 9 Reg - 8 HOUR Alarm MIN Alarm Monday through Friday, at 7:00 AM Minute value is ignored 0 0 1 1 1 1 1 0 07 h 80 h to FF h Every Saturday and Sunday, for 30 minutes each hour Hour value is ignored 0 1 0 0 0 0 0 1 80 h to FF h 30 h 18 h 59 h Reg - 9 Reg - 8 HOUR Alarm MIN Alarm Every day, at 6:59 AM 0 1 1 1 1 1 1 1 1 : Don't care 2) Example of alarm settings when "Day" has been specified (and WADA bit = "1") Reg - A Day is specified WADA bit = "1" First of each month, at 7:00 AM Minute value is ignored bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 AE * 20 10 08 04 02 01 0 0 0 0 0 0 0 1 07 h 80 h to FF h 15 of each month, for 30 minutes each hour Hour value is ignored 0 0 0 1 0 1 0 1 80 h to FF h 30 h Every day, at 6:59 PM 1 18 h 59 h th : Don't care Page - 23 ETM33E - 03 RX - 4803 SA / LC 8.6. Read/Write of data For both read and write, first set up chip condition (internally CE="H") to CE="H" , then specify the 4-bits address, and finally read or write in 8-bits units. Both read and write use MSB-first. In continuous operation, objected address is auto incremented. Auto incrementing of the address is cyclic, so address "F" is followed by address "0". 8.6.1. Write of data 1) One-shot writing CE CLK 1 DI 2 0 3 0 4 0 5 x 6 A3 Mode 7 A2 A1 8 9 10 11 A0 D7 D6 D5 Address N DO 12 13 D4 D3 14 15 16 D2 D1 D0 D0 D7 D6 Data N Hi-Z 2) Continuous writing CE CLK 1 DI 2 0 3 0 4 0 5 x 6 A3 Mode 7 A2 A1 8 9 10 A0 D7 11 D6 Address N DO D5 D1 Data N D1 D0 D7 D6 Data N+1 D1 D0 Data N+m Hi-Z *When writing data, the data needs to be entered in 8-bits units. If the input of data in 8-bits unit is not completed before CE input falls, the 8-bits data will not be written properly at the time CE input falls. 8.6.2. Read of data 1) One-shot reading CE CLK 1 DI 2 1 3 0 4 0 5 x 6 A3 Mode DO 7 A2 8 A1 9 10 11 D7 D6 12 13 14 15 16 D2 D1 A0 Address N Hi-Z D5 D4 D3 D0 Data N 2) Continuous reading CE CLK DI 1 1 2 0 3 4 0 Mode DO Hi-Z 5 x A3 6 A2 7 A1 8 9 10 11 A0 Address N D7 D6 D5 Data N D1 D0 D7 D6 D1 Data N+1 D0 D7 D6 D1 D0 Data N+m 8.7. VDD and CE timing * When the power is turned to ON, use with CE = " L " ( VCL[V] in the diagram ) as illustrated in the following timing chart. Page - 24 ETM33E - 03 RX - 4803 SA / LC 1.6 V VDD tCL VCL CE Item Symbol CE voltage when power is turned to ON VCL CE=VCL[V] time when power is turned to ON tCL Remark Specification Unit CE impressed voltage until VDD = 1.6 V 0.3 (Max.) V Time to maintain CE=VCL[V] until VDD = 1.6 V 30 ( Min. ) ms 8.8. Backup and Recovery VDD VDET VCLK 0V t R1 tF t R2 Back up Item Max. Unit. - 2.2 V VLOW - 1.6 V tF - Initial power-up time t R1 - Clock maintenance power-up time t R2 Power supply detection voltage ( 1 ) Power supply detection voltage ( 2 ) Power supply drop time Symbol Condition VDET Min. Typ. s /V 2 10 ms /V 1.6V VDD 3.6V 5 s /V 1.6V VDD > 3.6V 15 s /V Page - 25 ETM33E - 03 RX - 4803 SA / LC 8.8. Connection with Typical Microcontroller D1 4.7 F Note VDD Schottky Barrier Diode + RX-4803 VDD CE DI DO 0.1 F CLK / INT FOUT FOE GND Note : It uses the secondary battery or a lithium battery. When using the seconding battery, the diode is not required. When using the lithium battery, the diode is required. For detailed value on the resistance, please consult a battery maker. 8.9. When used as a clock source (32 kHz-TCXO) VDD RX-4803 VDD CE DI DO TEST T2 0.1 F CLK EVIN 32.768kHz OE FOUT / INT FOE GND Page - 26 ETM33E - 03 RX - 4803 SA / LC 9. External Dimensions / Marking Layout 9.1. RX - 4803 SA 9.1.1. External dimensions RX - 4803 SA ( SOP - 14pin ) * External dimensions * Recommended soldering pattern 10.1 0.2 #14 0 - 10 #8 1.4 5.0 7.4 0.2 5.4 0.6 #1 #7 0.05 Min. 0.35 1.27 1.4 0.15 1.27 0.7 1.27 x 6 = 7.62 3.2 0.1 1.2 Unit : mm The cylinder of the crystal oscillator can be seen in this area ( front ), but it has no affect on the performance of the device. 9.1.2. Marking layout RX - 4803 SA ( SOP - 14pin ) Frequency Stability Type R 4803 A UA : A UB : Blank UC : C AA : W E A123B Logo Production lot Contents displayed indicate the general markings and display, but are not the standards for the fonts, sizes and positioning. Page - 27 ETM33E - 03 RX - 4803 SA / LC 9.2. RX - 4803 LC 9.2.1. External dimensions RX - 4803 LC ( VSOJ - 20pin ) * External dimensions * Recommended soldering pattern 3.7 0.2 2.5 0.27 2.4 1.6 0.5 0.8 3.2 ( 0.4 ) 2.8 0.2 0.8 #7 2.4 # 12 0.1 #6 2.77 0.08 M 0.22 0 Min. 0.5 1.2 Max. #1 Unit : mm 0.08 The cylinder of the liquid crystal oscillator can be seen in this area ( back and front ), but it has no affect on the performance of the device. 9.2.2. Marking layout RX - 4803 LC ( VSOJ - 20pin ) Type Logo E 4803 A Frequency Stability UA : A UB : Blank UC : C AA : W A123B Production lot #1 Pin Mark Contents displayed indicate the general markings and display, but are not the standards for the fonts, sizes and positioning. Page - 28 ETM33E - 03 RX - 4803 SA / LC 10. Application notes 1) Notes on handling This module uses a C-MOS IC to realize low power consumption. Carefully note the following cautions when handling. (1) Static electricity While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by a large discharge of static electricity. Containers used for packing and transport should be constructed of conductive materials. In addition, only soldering irons, measurement circuits, and other such devices which do not leak high voltage should be used with this module, which should also be grounded when such devices are being used. (2) Noise If a signal with excessive external noise is applied to the power supply or input pins, the device may malfunction or "latch up." In order to ensure stable operation, connect a filter capacitor (preferably ceramic) of greater that 0.1 F as close as possible to the power supply pins (between VDD and GNDs). Also, avoid placing any device that generates high level of electronic noise near this module. * Do not connect signal lines to the shaded area in the figure shown in Fig. 1 and, if possible, embed this area in a GND land. (3) Voltage levels of input pins When the input pins are at the mid-level, this will cause increased current consumption and a reduced noise margin, and can impair the functioning of the device. Therefore, try as much as possible to apply the voltage level close to VDD or GND. (4) Handling of unused pins Since the input impedance of the input pins is extremely high, operating the device with these pins in the open circuit state can lead to unstable voltage level and malfunctions due to noise. Therefore, pull-up or pull-down resistors should be provided for all unused input pins. 2) Notes on packaging (1) Soldering heat resistance. If the temperature within the package exceeds +260 C, the characteristics of the crystal oscillator will be degraded and it may be damaged. The reflow conditions within our reflow profile is recommended. Therefore, always check the mounting temperature and time before mounting this device. Also, check again if the mounting conditions are later changed. * See Fig. 2 profile for our evaluation of Soldering heat resistance for reference. (2) Mounting equipment While this module can be used with general-purpose mounting equipment, the internal crystal oscillator may be damaged in some circumstances, depending on the equipment and conditions. Therefore, be sure to check this. In addition, if the mounting conditions are later changed, the same check should be performed again. (3) Ultrasonic cleaning Depending on the usage conditions, there is a possibility that the crystal oscillator will be damaged by resonance during ultrasonic cleaning. Since the conditions under which ultrasonic cleaning is carried out (the type of cleaner, power level, time, state of the inside of the cleaning vessel, etc.) vary widely, this device is not warranted against damage during ultrasonic cleaning. (4) Mounting orientation This device can be damaged if it is mounted in the wrong orientation. Always confirm the orientation of the device before mounting. (5) Leakage between pins Leakage between pins may occur if the power is turned on while the device has condensation or dirt on it. Make sure the device is dry and clean before supplying power to it. Fig. 1 : Example GND Pattern RX - 4803 SA Fig. 2 : Reference profile for our evaluation of Soldering heat resistance. Temperature [ C ] 300 ; +260 C OVER TP +255 C 250 200 TL ; +217 C Ts max ; +200 C tp ; at least 30 s Ramp-up rate +3 C/s Max. tL Ramp-down rate -6 C/s Max. 60 s to 150 s ( +217 C over ) RX - 4803 LC 150 Ts min ; +150 C ts 60 s to 120 s ( +150 C to +200 C) 100 The shaded part ( ) indicates where a GND pattern should be set without getting too close to a signal line 50 Time +25 C to Peak 0 60 120 180 240 300 360 420 480 540 600 660 720 780 Time [ s ] Page - 29 ETM33E - 03 Application Manual AMERICA EPSON ELECTRONICS AMERICA, INC. HEADQUARTER Chicago Office El Segundo Office 214 Devcon Drive, San Jose, CA 95112, U.S.A. Phone: (1)800-228-3964 FAX :(1)408-922-0238 http://www.eea.epson.com 1827 Walden Office Square. Suite 450 Schaumburg, IL 60173 Phone: (1)847-925-8350 Fax: (1)847 925-8965 1960 E. Grand Ave., 2nd Floor, El Segundo, CA 90245, U.S.A. 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