LGA-14L
(2.5 x 3.0 x 0.83 mm) typ.
Features
• Power consumption: 0.55 mA in combo high-performance mode
• “Always-on" experience with low power consumption for both accelerometer and
gyroscope
• Smart FIFO up to 9 kbyte
• Android compliant
• ±2/±4/±8/±16 g full scale
• ±125/±250/±500/±1000/±2000 dps full scale
• Analog supply voltage: 1.71 V to 3.6 V
• Independent IO supply (1.62 V)
• Compact footprint: 2.5 mm x 3 mm x 0.83 mm
• SPI / I²C & MIPI I3CSM serial interface with main processor data synchronization
• Auxiliary SPI for OIS data output for gyroscope and accelerometer
• OIS configurable from Aux SPI, primary interface (SPI / I²C & MIPI I3CSM)
• Advanced pedometer, step detector and step counter
• Significant Motion Detection, Tilt detection
• Standard interrupts: free-fall, wakeup, 6D/4D orientation, click and double-click
• Programmable finite state machine: accelerometer, gyroscope and external
sensors
• Machine Learning Core
• S4S data synchronization
• Embedded temperature sensor
•ECOPACK®, RoHS and “Green” compliant
Applications
• Motion tracking and gesture detection
• Sensor hub
• Indoor navigation
• IoT and connected devices
• Smart power saving for handheld devices
• EIS and OIS for camera applications
• Vibration monitoring and compensation
Description
The LSM6DSOX is a system-in-package featuring a 3D digital accelerometer and a
3D digital gyroscope boosting performance at 0.55 mA in high-performance mode
and enabling always-on low-power features for an optimal motion experience for the
consumer.
The LSM6DSOX supports main OS requirements, offering real, virtual and batch
sensors with 9 kbytes for dynamic data batching. ST’s family of MEMS sensor
modules leverages the robust and mature manufacturing processes already used for
the production of micromachined accelerometers and gyroscopes. The various
sensing elements are manufactured using specialized micromachining processes,
Product status link
LSM6DSOX
Product summary
Order code LSM6DSOX LSM6DSOXTR
Temperature
range [°C] -40 to +85
Package LGA-14L
(2.5 x 3.0 x 0.83 mm)
Packing Tray Tape & Reel
Product label
iNEMO inertial module: always-on 3D accelerometer and 3D gyroscope
LSM6DSOX
Datasheet
DS12814 - Rev 3 - January 2019
For further information contact your local STMicroelectronics sales office. www.st.com
while the IC interfaces are developed using CMOS technology that allows the design
of a dedicated circuit which is trimmed to better match the characteristics of the
sensing element.
The LSM6DSOX has a full-scale acceleration range of ±2/±4/±8/±16 g and an
angular rate range of ±125/±250/±500/±1000/±2000 dps.
The LSM6DSOX fully supports EIS and OIS applications as the module includes a
dedicated configurable signal processing path for OIS and auxiliary SPI, configurable
for both the gyroscope and accelerometer. The LSM6DSOX OIS can be configured
from the Auxiliary SPI and primary interface (SPI / I²C & MIPI I3CSM).
High robustness to mechanical shock makes the LSM6DSOX the preferred choice of
system designers for the creation and manufacturing of reliable products. The
LSM6DSOX is available in a plastic land grid array (LGA) package.
LSM6DSOX
DS12814 - Rev 3 page 2/199
1Overview
The LSM6DSOX is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis
digital gyroscope.
The LSM6DSOX delivers best-in-class motion sensing that can detect orientation and gestures in order to
empower application developers and consumers with features and capabilities that are more sophisticated than
simply orienting their devices to portrait and landscape mode.
The event-detection interrupts enable efficient and reliable motion tracking and contextual awareness,
implementing hardware recognition of free-fall events, 6D orientation, click and double-click sensing, activity or
inactivity, stationary/motion detection and wakeup events.
The LSM6DSOX supports main OS requirements, offering real, virtual and batch mode sensors. In addition, the
LSM6DSOX can efficiently run the sensor-related features specified in Android, saving power and enabling faster
reaction time. In particular, the LSM6DSOX has been designed to implement hardware features such as
significant motion detection, stationary/motion detection, tilt, pedometer functions, timestamping and to support
the data acquisition of an external magnetometer.
The LSM6DSOX offers hardware flexibility to connect the pins with different mode connections to external
sensors to expand functionalities such as adding a sensor hub, auxiliary SPI, etc.
Up to 9 kbytes of FIFO with compression and dynamic allocation of significant data (i.e. external sensors,
timestamp, etc.) allows overall power saving of the system.
Like the entire portfolio of MEMS sensor modules, the LSM6DSOX leverages the robust and mature in-house
manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The
various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces
are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better
match the characteristics of the sensing element.
The LSM6DSOX is available in a small plastic land grid array (LGA) package of 2.5 x 3.0 x 0.83 mm to address
ultra-compact solutions.
LSM6DSOX
Overview
DS12814 - Rev 3 page 3/199
2Embedded low-power features
The LSM6DSOX has been designed to be fully compliant with Android, featuring the following on-chip functions:
• 9 kbytes data buffering, data can be compressed two or three times
– 100% efficiency with flexible configurations and partitioning
– Possibility to store timestamp
• Event-detection interrupts (fully configurable)
– Free-fall
– Wakeup
– 6D orientation
– Click and double-click sensing
– Activity/Inactivity recognition
– Stationary/Motion detection
• Specific IP blocks with negligible power consumption and high-performance
– Pedometer functions: step detector and step counters
– Tilt
– Significant Motion Detection
– Finite State Machine (FSM) for accelerometer, gyroscope, and external sensors
– Machine Learning Core (MLC)
• Sensor hub
– Up to 6 total sensors: 2 internal (accelerometer and gyroscope) and 4 external sensors
• S4S data rate synchronization with external trigger for reduced sensor access and enhanced fusion
2.1 Tilt detection
The tilt function helps to detect activity change and has been implemented in hardware using only the
accelerometer to achieve targets of both ultra-low power consumption and robustness during the short duration of
dynamic accelerations.
The tilt function is based on a trigger of an event each time the device's tilt changes and can be used with
different scenarios, for example:
• Triggers when phone is in a front pants pocket and the user goes from sitting to standing or standing to
sitting;
• Doesn’t trigger when phone is in a front pants pocket and the user is walking, running or going upstairs.
2.2 Significant Motion Detection
The Significant Motion Detection (SMD) function generates an interrupt when a ‘significant motion’, that could be
due to a change in user location, is detected. In the LSM6DSOX device this function has been implemented in
hardware using only the accelerometer.
SMD functionality can be used in location-based applications in order to receive a notification indicating when the
user is changing location.
LSM6DSOX
Embedded low-power features
DS12814 - Rev 3 page 4/199
2.3 Finite State Machine
The LSM6DSOX can be configured to generate interrupt signals activated by user-defined motion patterns. To do
this, up to 16 embedded finite state machines can be programmed independently for motion detection such as
glance gestures, absolute wrist tilt, shake and double-shake detection.
Definition of Finite State Machine
A state machine is a mathematical abstraction used to design logic connections. It is a behavioral model
composed of a finite number of states and transitions between states, similar to a flow chart in which one can
inspect the way logic runs when certain conditions are met. The state machine begins with a start state, goes to
different states through transitions dependent on the inputs, and can finally end in a specific state (called stop
state). The current state is determined by the past states of the system. The following figure shows a generic
state machine.
Figure 1. Generic state machine
Finite State Machine in the LSM6DSOX
The LSM6DSOX works as a combo accelerometer-gyroscope sensor, generating acceleration and angular rate
output data. It is also possible to connect an external sensor (magnetometer) by using the Sensor Hub feature
(Mode 2). These data can be used as input of up to 16 programs in the embedded Finite State Machine
(Figure 2. State machine in the LSM6DSOX).
All 16 finite state machines are independent: each one has its dedicated memory area and it is independently
executed. An interrupt is generated when the end state is reached or when some specific command is performed.
Figure 2. State machine in the LSM6DSOX
LSM6DSOX
Finite State Machine
DS12814 - Rev 3 page 5/199
2.4 Machine Learning Core
The LSM6DSOX embeds a dedicated core for machine learning processing that provides system flexibility,
allowing some algorithms run in the application processor to be moved to the MEMS sensor with the advantage of
consistent reduction in power consumption.
Machine Learning Core logic allows identifying if a data pattern (for example motion, pressure, temperature,
magnetic data, etc.) matches a user-defined set of classes. Typical examples of applications could be activity
detection like running, walking, driving, etc.
The LSM6DSOX Machine Learning Core works on data patterns coming from the accelerometer and gyro
sensors, but it is also possible to connect and process external sensor data (like magnetometer) by using the
Sensor Hub feature (Mode 2).
The input data can be filtered using a dedicated configurable computation block containing filters and features
computed in a fixed time window defined by the user.
Machine learning processing is based on logical processing composed of a series of configurable nodes
characterized by "if-then-else" conditions where the "feature" values are evaluated against defined thresholds.
Figure 3. Machine Learning Core in the LSM6DSOX
INPUT
Sensor Data & Hub
Machine
Learning Core OUTPUT
Accelerometer Results
Gyroscope
External Sensor
Features
Filters
Interrupts
Machine
Learning Core
Logical processing
The LSM6DSOX can be configured to run up to 8 flows simultaneously and independently and every flow can
generate up to 16 results. The total number of nodes can be up to 256.
The results of the machine learning processing are available in dedicated output registers readable from the
application processor at any time.
The LSM6DSOX Machine Learning Core can be configured to generate an interrupt when a change in the result
occurs.
LSM6DSOX
Machine Learning Core
DS12814 - Rev 3 page 6/199
3Pin description
Figure 4. Pin connections
LSM6DSOX
Pin description
DS12814 - Rev 3 page 7/199
3.1 Pin connections
The LSM6DSOX offers flexibility to connect the pins in order to have four different mode connections and
functionalities. In detail:
•Mode 1: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is available;
•Mode 2: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface and I2C interface master for
external sensor connections are available;
•Mode 3: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is available for the application
processor interface while an auxiliary SPI (3- and 4-wire) serial interface for external sensor connections is
available for the gyroscope ONLY;
•Mode 4: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is available for the application
processor interface while an auxiliary SPI (3- and 4-wire) serial interface for external sensor connections is
available for the accelerometer and gyroscope.
Figure 5. LSM6DSOX connection modes
HOST
LSM6DSOX
HOST
LSM6DSOX
HOST
LSM6DSOX
LSM6DSM
LSM6DSM
External
sensors
I2C /
SPI (3/4-w)
I2C /
SPI (3/4-w)
I2C /
SPI (3/4-w)
Aux SPI (3/4-w)Master I2C
Mode 1 Mode 2 Mode 3
HOST
LSM6DSOX
I2C /
SPI (3/4-w)
Aux SPI (3/4-w)
Mode 4
For gyro
data only
For XL and
gyro data
Camera
module
Camera
module
MIPI I3CSM / MIPI I3CSM / MIPI I3CSM / MIPI I3CSM /
In the following table each mode is described for the pin connections and function.
Table 1. Pin description
Pin# Name Mode 1 function Mode 2 function Mode 3 / Mode 4 function
1 SDO/SA0
SPI 4-wire interface serial data
output (SDO)
I²C least significant bit of the device
address (SA0)
SPI 4-wire interface serial data output
(SDO)
I²C least significant bit of the device
address (SA0)
SPI 4-wire interface serial data output
(SDO)
I²C least significant bit of the device
address (SA0)
2 SDx Connect to VDDIO or GND I²C serial data master (MSDA)
Auxiliary SPI 3/4-wire interface serial data
input (SDI)
and SPI 3-wire serial data output (SDO)
3 SCx Connect to VDDIO or GND I²C serial clock master (MSCL) Auxiliary SPI 3/4-wire interface serial port
clock (SPC_Aux)
LSM6DSOX
Pin connections
DS12814 - Rev 3 page 8/199
Pin# Name Mode 1 function Mode 2 function Mode 3 / Mode 4 function
4 INT1 Programmable interrupt in I²C and SPI
5VDDIO(1) Power supply for I/O pins
6 GND 0 V supply
7 GND 0 V supply
8VDD(1) Power supply
9 INT2 Programmable interrupt 2
(INT2) / Data enable (DEN)
Programmable interrupt 2 (INT2) /
Data enable (DEN) /
I2C master external synchronization
signal (MDRDY)
Programmable interrupt 2 (INT2) / Data
enable (DEN)
10 OCS_Aux Leave unconnected(2) Leave unconnected(2) Auxiliary SPI 3/4-wire interface enable
11 SDO_Aux Connect to VDD_IO or leave
unconnected(2)
Connect to VDD_IO or leave
unconnected(2)
Auxiliary SPI 3-wire interface: leave
unconnected(2)
Auxiliary SPI 4-wire interface: serial data
output (SDO_Aux)
12 CS
I²C / MIPI I3CSM/ SPI mode selection
(1: SPI idle mode / I²C / MIPI I3CSM
communication enabled;
0: SPI communication mode / I²C /
MIPI I3CSM disabled)
I²C / MIPI I3CSM/ SPI mode selection
(1: SPI idle mode / I²C / MIPI I3CSM
communication enabled;
0: SPI communication mode / I²C /
MIPI I3CSM disabled)
I²C / MIPI I3CSM / SPI mode selection
(1: SPI idle mode / I²C / MIPI I3CSM
communication enabled;
0: SPI communication mode / I²C / MIPI
I3CSM disabled)
13 SCL I²C / MIPI I3CSM serial clock (SCL)
SPI serial port clock (SPC)
I²C / MIPI I3CSM serial clock (SCL)
SPI serial port clock (SPC)
I²C / MIPI I3CSM serial clock (SCL)
SPI serial port clock (SPC)
14 SDA
I²C / MIPI I3CSM serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output
(SDO)
I²C / MIPI I3CSM serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output
(SDO)
I²C / MIPI I3CSM serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data
output (SDO)
1. Recommended 100 nF filter capacitor.
2. Leave pin electrically unconnected and soldered to PCB.
LSM6DSOX
Pin connections
DS12814 - Rev 3 page 9/199
4Module specifications
4.1 Mechanical characteristics
@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted.
Table 2. Mechanical characteristics
Symbol Parameter Test conditions Min. Typ.(1) Max. Unit
LA_FS Linear acceleration measurement range
±2
g
±4
±8
±16
G_FS Angular rate measurement range
±125
dps
±250
±500
±1000
±2000
LA_So Linear acceleration sensitivity(2)
FS = ±2 g0.061
mg/LSB
FS = ±4 g0.122
FS = ±8 g0.244
FS = ±16 g0.488
G_So Angular rate sensitivity(2)
FS = ±125 dps 4.375
mdps/LSB
FS = ±250 dps 8.75
FS = ±500 dps 17.50
FS = ±1000 dps 35
FS = ±2000 dps 70
G_So% Sensitivity tolerance(3) at component level ±1 %
LA_SoDr Linear acceleration sensitivity change vs. temperature(4) from -40° to +85° ±0.01 %/°C
G_SoDr Angular rate sensitivity change vs. temperature(4) from -40° to +85° ±0.007 %/°C
LA_TyOff Linear acceleration zero-g level offset accuracy(5) ±20 mg
G_TyOff Angular rate zero-rate level(5) ±1 dps
LA_OffDr Linear acceleration zero-g level change vs. temperature(4) ±0.1 mg/°C
G_OffDr Angular rate typical zero-rate level change vs. temperature(4) ±0.010 dps/°C
Rn Rate noise density in high-performance mode(6) 3.8 mdps/√Hz
RnRMS Gyroscope RMS noise in normal/low-power mode(7) 75 mdps
An Acceleration noise density in high-performance mode(8)
FS = ±2 g70
µg/√Hz
FS = ±4 g75
FS = ±8 g80
FS = ±16 g110
LSM6DSOX
Module specifications
DS12814 - Rev 3 page 10/199
Symbol Parameter Test conditions Min. Typ.(1) Max. Unit
RMS Acceleration RMS noise in normal/low-power mode(9) (10)
FS = ±2 g1.8
mg(RMS)
FS = ±4 g2.0
FS = ±8 g2.4
FS = ±16 g3.0
Acceleration RMS noise in ultra-low-power mode(9)(10) FS = ±2 g5.5
LA_ODR Linear acceleration output data rate
1.6(11)
12.5
26
52
104
208
416
833
1666
3332
6664 Hz
G_ODR Angular rate output data rate
12.5
26
52
104
208
416
833
1666
3332
6664
Vst
Linear acceleration self-test output change(12)(13) (14) 50 1700 mg
Angular rate self-test output change(15)(16) FS = 250 dps 20 80 dps
FS = 2000 dps 150 700 dps
Top Operating temperature range -40 +85 °C
1. Typical specifications are not guaranteed.
2. Sensitivity values after factory calibration test and trimming.
3. Subject to change.
4. Measurements are performed in a uniform temperature setup and they are based on characterization data
in a limited number of samples. Not measured during final test for production.
5. Values after factory calibration test and trimming.
6. Gyroscope rate noise density in high-performance mode is independent of the ODR and FS setting.
7. Gyroscope RMS noise in normal/low-power mode is independent of the ODR and FS setting.
8. Accelerometer noise density in high-performance mode is independent of the ODR.
9. Accelerometer RMS noise in normal/low-power/ultra-low-power mode is independent of the ODR.
10. Noise RMS related to BW = ODR/2.
11. This ODR is available when the accelerometer is in low-power mode.
12. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated
register for all axes.
LSM6DSOX
Mechanical characteristics
DS12814 - Rev 3 page 11/199
13. The linear acceleration self-test output change is defined with the device in stationary condition as the
absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.061 mg
at ±2 g full scale.
14. Accelerometer self-test limits are full-scale independent.
15. The sign of the angular rate self-test output change is defined by the STx_G bits in a dedicated register for
all axes.
16. The angular rate self-test output change is defined with the device in stationary condition as the absolute
value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at ±2000
dps full scale.
LSM6DSOX
Mechanical characteristics
DS12814 - Rev 3 page 12/199
4.2 Electrical characteristics
@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted.
Table 3. Electrical characteristics
Symbol Parameter Test conditions Min. Typ.(1) Max. Unit
Vdd Supply voltage 1.71 1.8 3.6 V
Vdd_IO Power supply for I/O 1.62 3.6 V
IddHP Gyroscope and accelerometer current consumption in high-performance
mode 0.55 mA
LA_IddHP Accelerometer current consumption in high-performance mode 170 µA
LA_IddLP Accelerometer current consumption in low-power mode ODR = 50 Hz
ODR = 1.6 Hz
26
4.5 µA
LA_IddULP Accelerometer current consumption in ultra-low-power mode ODR = 50 Hz
ODR = 1.6 Hz
9.5
4.4 µA
IddPD Gyroscope and accelerometer current consumption during power-down 3 µA
Ton Turn-on time 35 ms
VIH Digital high-level input voltage 0.7 *
VDD_IO V
VIL Digital low-level input voltage 0.3 *
VDD_IO V
VOH High-level output voltage IOH = 4 mA(2) VDD_IO
- 0.2 V
VOL Low-level output voltage IOL = 4 mA(2) 0.2 V
Top Operating temperature range -40 +85 °C
1. Typical specifications are not guaranteed.
2. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital
pin in order to guarantee the correct digital output voltage levels VOH and VOL.
4.3 Temperature sensor characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
Table 4. Temperature sensor characteristics
Symbol Parameter Test condition Min. Typ. (1) Max. Unit
TODR(2) Temperature refresh rate 52 Hz
Toff Temperature offset(3) -15 +15 °C
TSen Temperature sensitivity 256 LSB/°C
TST Temperature stabilization time(4) 500 µs
T_ADC_res Temperature ADC resolution 16 bit
Top Operating temperature range -40 +85 °C
1. Typical specifications are not guaranteed
2. When the accelerometer is in low-power mode or ultra-low-power mode and the gyroscope part is turned off, the TODR
value is equal to the accelerometer ODR.
3. The output of the temperature sensor is 0 LSB (typ.) at 25 °C.
4. Time from power ON to valid data based on characterization data.
LSM6DSOX
Electrical characteristics
DS12814 - Rev 3 page 13/199
4.4 Communication interface characteristics
4.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 5. SPI slave timing values (in mode 3)
Symbol Parameter
Value(1)
Unit
Min Max
tc(SPC) SPI clock cycle 100 ns
fc(SPC) SPI clock frequency 10 MHz
tsu(CS) CS setup time 5
ns
th(CS) CS hold time 20
tsu(SI) SDI input setup time 5
th(SI) SDI input hold time 15
tv(SO) SDO valid output time 50
th(SO) SDO output hold time 5
tdis(SO) SDO output disable time 50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on
characterization results, not tested in production
Figure 6. SPI slave timing diagram (in mode 3)
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO for both input and output ports.
LSM6DSOX
Communication interface characteristics
DS12814 - Rev 3 page 14/199
4.4.2 I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Table 6. I²C slave timing values
Symbol Parameter
I²C standard mode(1) I²C fast mode (1)
Unit
Min Max Min Max
f(SCL) SCL clock frequency 0 100 0 400 kHz
tw(SCLL) SCL clock low time 4.7 1.3 µs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100 ns
th(SDA) SDA data hold time 0 3.45 0 0.9 µs
th(ST) START condition hold time 4 0.6
µs
tsu(SR) Repeated START condition setup time 4.7 0.6
tsu(SP) STOP condition setup time 4 0.6
tw(SP:SR) Bus free time between STOP and START condition 4.7 1.3
1. Data based on standard I²C protocol requirement, not tested in production.
Figure 7. I²C slave timing diagram
t
su(SP)
t
w(SCLL)
t
su(SDA)
t
su(SR)
t
h(ST)
t
w(SCLH)
t
h(SDA)
t
w(SP:SR)
START
REPEATED
START
START
STOP
SDA
SCL
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO for both ports.
LSM6DSOX
Communication interface characteristics
DS12814 - Rev 3 page 15/199
4.5 Absolute maximum ratings
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device under these conditions is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.
Table 7. Absolute maximum ratings
Symbol Ratings Maximum value Unit
Vdd Supply voltage -0.3 to 4.8 V
TSTG Storage temperature range -40 to +125 °C
Sg Acceleration g for 0.2 ms 20,000 g
ESD Electrostatic discharge protection (HBM) 2 kV
Vin Input voltage on any control pin
(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0) -0.3 to Vdd_IO +0.3 V
Note: Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
LSM6DSOX
Absolute maximum ratings
DS12814 - Rev 3 page 16/199
4.6 Terminology
4.6.1 Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device.
Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards
the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the
output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value
from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes
very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large
number of sensors (see Table 2).
An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation
around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a
defined angular velocity to it. This value changes very little over temperature and time (see Table 2).
4.6.2 Zero-g and zero-rate level
Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal
output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on
both the X-axis and Y-axis, whereas the Z-axis will measure 1 g. Ideally, the output is in the middle of the dynamic
range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from
the ideal value in this case is called zero-g offset.
Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after
mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes
little over temperature, see “Linear acceleration zero-g level change vs. temperature” in Table 2. The zero-g level
tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors.
Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise
MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly
change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress.
This value changes very little over temperature and time (see Table 2).
LSM6DSOX
Terminology
DS12814 - Rev 3 page 17/199
5Digital interfaces
5.1 I²C/SPI interface
The registers embedded inside the LSM6DSOX may be accessed through both the I²C and SPI serial interfaces.
The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The device is compatible
with SPI modes 0 and 3.
The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the CS line must be tied
high (i.e connected to Vdd_IO).
Table 8. Serial interface pin description
Pin name Pin description
CS
SPI enable
I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
SCL/SPC I²C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
SDA/SDI/SDO
I²C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SDO/SA0 SPI Serial Data Output (SDO)
I²C less significant bit of the device address
5.1.1 I²C serial interface
The LSM6DSOX I²C is a bus slave. The I²C is employed to write the data to the registers, whose content can also
be read back.
The relevant I²C terminology is provided in the table below.
Table 9. I²C terminology
Term Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master The device which initiates a transfer, generates clock signals and terminates a transfer
Slave The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial DAta line (SDA). The
latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be
connected to Vdd_IO through external pull-up resistors. When the bus is free, both the lines are high.
The I²C interface is implemented with fast mode (400 kHz) I²C standards as well as with the standard mode.
In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h).
LSM6DSOX
Digital interfaces
DS12814 - Rev 3 page 18/199
5.1.2 I²C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to
LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the
bus is considered busy. The next byte of data transmitted after the start condition contains the address of the
slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting
data to the slave. When an address is sent, each device in the system compares the first seven bits after a start
condition with its address. If they match, the device considers itself addressed by the master.
The Slave ADdress (SAD) associated to the LSM6DSOX is 110101xb. The SDO/SA0 pin can be used to modify
the less significant bit of the device address. If the SDO/SA0 pin is connected to the supply voltage, LSb is ‘1’
(address 1101011b); else if the SDO/SA0 pin is connected to ground, the LSb value is ‘0’ (address 1101010b).
This solution permits to connect and address two different inertial modules to the same I²C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge
pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the
acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each
byte of data received.
The I²C embedded inside the LSM6DSOX behaves like a slave device and the following protocol must be
adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been
returned, an 8-bit sub-address (SUB) is transmitted. The increment of the address is configured by the CTRL3_C
(12h) (IF_INC).
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition
must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with
direction unchanged. Table 10 explains how the SAD+Read/Write bit pattern is composed, listing all the possible
configurations.
Table 10. SAD+Read/Write patterns
Command SAD[6:1] SAD[0] = SA0 R/W SAD+R/W
Read 110101 0 1 11010101 (D5h)
Write 110101 0 0 11010100 (D4h)
Read 110101 1 1 11010111 (D7h)
Write 110101 1 0 11010110 (D6h)
Table 11. Transfer when master is writing one byte to slave
Master ST SAD + W SUB DATA SP
Slave SAK SAK SAK
Table 12. Transfer when master is writing multiple bytes to slave
Master ST SAD + W SUB DATA DATA SP
Slave SAK SAK SAK SAK
Table 13. Transfer when master is receiving (reading) one byte of data from slave
Master ST SAD + W SUB SR SAD + R NMAK SP
Slave SAK SAK SAK DATA
Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP
Slave SAK SAK SAK DATA DATA DATA
LSM6DSOX
I²C/SPI interface
DS12814 - Rev 3 page 19/199
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred
per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive
another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to
force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and
releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive
because it is performing some real-time function) the data line must be left HIGH by the slave. The master can
then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a
STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge.
5.1.3 SPI bus interface
The LSM6DSOX SPI is a bus slave. The SPI allows writing and reading the registers of the device.
The serial interface communicates to the application using 4 wires: CS, SPC, SDI and SDO.
Figure 8. Read and write protocol (in mode 3)
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and
goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high
when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. Those
lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case
of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at
the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling
edge of SPC just before the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is
read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When the CTRL3_C (12h)
(IF_INC) bit is ‘0’, the address used to read/write data remains the same for every block. When the CTRL3_C
(12h) (IF_INC) bit is ‘1’, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
LSM6DSOX
I²C/SPI interface
DS12814 - Rev 3 page 20/199
5.1.3.1 SPI read
Figure 9. SPI read protocol (in mode 3)
CS
SPC
SDI
SDO
RW
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
AD5 AD4 AD3 AD2 AD1 AD0
AD6
The SPI Read command is performed with 16 clock pulses. A multiple byte read command is performed by
adding blocks of 8 clock pulses to the previous one.
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
bit 16-...: data DO(...-8). Further data in multiple byte reads.
Figure 10. Multiple byte SPI read protocol (2-byte example) (in mode 3)
CS
SPC
SDI
SDO
RW
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
AD5 AD4 AD3 AD2 AD1 AD0
DO15 DO14 DO13 DO12 DO11DO10 DO9 DO8
AD6
LSM6DSOX
I²C/SPI interface
DS12814 - Rev 3 page 21/199
5.1.3.2 SPI write
Figure 11. SPI write protocol (in mode 3)
CS
SPC
SDI
RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
AD5 AD4 AD3 AD2 AD1 AD0AD6
The SPI Write command is performed with 16 clock pulses. A multiple byte write command is performed by
adding blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
bit 1 -7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 12. Multiple byte SPI write protocol (2-byte example) (in mode 3)
CS
SPC
SDI
RW
AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
AD6
5.1.3.3 SPI read in 3-wire mode
A 3-wire mode is entered by setting the CTRL3_C (12h) (SIM) bit equal to ‘1’ (SPI serial interface mode
selection).
Figure 13. SPI read protocol in 3-wire mode (in mode 3)
CS
SPC
SDI/O
RW DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
AD5 AD4 AD3 AD2 AD1 AD0
AD6
The SPI read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
LSM6DSOX
I²C/SPI interface
DS12814 - Rev 3 page 22/199
5.2 MIPI I3CSM interface
5.2.1 MIPI I3CSM slave interface
The LSM6DSOX interface includes an MIPI I3CSMSDR only slave interface (compliant with release 1.0 of the
specification) with MIPI I3CSM SDR embedded features:
• CCC command
• Direct CCC communication (SET and GET)
• Broadcast CCC communication
• Private communications
• Private read and write for single byte
• Multiple read and write
• In-Band Interrupt request
Error Detection and Recovery Methods (S0-S6)
Refer to Section 5.3 I²C/I3C coexistence in LSM6DSOX for details concerning the choice of the interface when
powering up the device.
5.2.2 MIPI I3CSM CCC supported commands
The list of MIPI I3CSM CCC commands supported by the device is detailed in the following table.
Table 15. MIPI I3CSM CCC commands
Command Command code Default Description
ENTDAA 0x07 DAA procedure
SETDASA 0x87 Assign Dynamic Address using Static Address 0x6B/0x6A depending on SDO pin
ENEC 0x80 / 0x00 Slave activity control (direct and broadcast)
DISEC 0x81/ 0x01 Slave activity control (direct and broadcast)
ENTAS0 0x82 / 0x02 Enter activity state (direct and broadcast)
ENTAS1 0x83 / 0x03 Enter activity state (direct and broadcast)
ENTAS2 0x84 / 0x04 Enter activity state (direct and broadcast)
ENTAS3 0x85 / 0x05 Enter activity state (direct and broadcast)
SETXTIME 0x98 / 0x28 Timing information exchange
GETXTIME 0x99
0x07
0x00
0x05
0x92
Timing information exchange
RSTDAA 0x86 / 0x06 Reset the assigned dynamic address (direct and broadcast)
SETMWL 0x89 / 0x08 Define maximum write length during private write (direct and broadcast)
SETMRL 0x8A / 0x09 Define maximum read length during private read (direct and broadcast)
SETNEWDA 0x88 Change dynamic address
GETMWL 0x8B
0x00
0x08
(2 byte)
Get maximum write length during private write
LSM6DSOX
MIPI I3CSM interface
DS12814 - Rev 3 page 23/199
Command Command code Default Description
GETMRL 0x8C
0x00
0x10
0x09
(3 byte)
Get maximum read length during private read
GETPID 0x8D
0x02
0x08
0x00
0x6C
0x10
0x0B
Device ID register
GETBCR 0x8E 0x07
(1 byte) Bus characteristics register
GETDCR 0x8F 0x44 default MIPI I3CSM Device Characteristic Register
GETSTATUS 0x90
0x00
0x00
(2 byte)
Status register
GETMXDS 0x94
0x00
0x20
(2 byte)
Return max data speed
LSM6DSOX
MIPI I3CSM interface
DS12814 - Rev 3 page 24/199
5.3 I²C/I3C coexistence in LSM6DSOX
In the LSM6DSOX, the SDA and SCL lines are common to both I²C and I3C. The I²C bus requires anti-spike
filters on the SDA and SCL pins that are not compatible with I3C timing.
The device can be connected to both I²C and I3C or only to the I3C bus depending on the connection of the INT1
pin when the device is powered up:
• INT1 pin floating (internal pull-down): I²C/I3C both active, see Figure 14
• INT1 pin connected to VDD_IO: only I3C active, see Figure 15
Figure 14. I²C and I3C both active (INT1 pin not connected)
1. Address assignment (DAA or ENTDA) must be performed with I²C Fast Mode Plus Timing. When the slave
is addressed, the I²C slave is disabled and the timing is compatible with I3C specifications.
Figure 15. Only I3C active (INT1 pin connected to VDD_IO)
1. When the slave is I3C only, the I²C slave is always disabled. The address can be assigned using I3C SDR
timing.
LSM6DSOX
I²C/I3C coexistence in LSM6DSOX
DS12814 - Rev 3 page 25/199
5.4 Master I²C interface
If the LSM6DSOX is configured in Mode 2, a master I²C line is available. The master serial interface is mapped in
the following dedicated pins.
Table 16. Master I²C pin details
Pin name Pin description
MSCL I²C serial clock master
MSDA I²C serial data master
MDRDY I²C master external synchronization signal
5.5 Auxiliary SPI interface
If the LSM6DSOX is configured in Mode 3 or Mode 4, the auxiliary SPI is available. The auxiliary SPI interface is
mapped to the following dedicated pins.
Table 17. Auxiliary SPI pin details
Pin name Pin description
OCS_Aux Auxiliary SPI 3/4-wire enable
SDx Auxiliary SPI 3/4-wire data input (SDI_Aux) and SPI 3-wire data output (SDO_Aux)
SCx Auxiliary SPI 3/4-wire interface serial port clock
SDO_Aux Auxiliary SPI 4-wire data output (SDO_Aux)
When the LSM6DSOX is configured in Mode 3 or Mode 4, the auxiliary SPI can be connected to a camera
module for OIS/EIS support.
LSM6DSOX
Master I²C interface
DS12814 - Rev 3 page 26/199
6Functionality
6.1 Operating modes
In the LSM6DSOX, the accelerometer and the gyroscope can be turned on/off independently of each other and
are allowed to have different ODRs and power modes.
The LSM6DSOX has three operating modes available:
• only accelerometer active and gyroscope in power-down
• only gyroscope active and accelerometer in power-down
• both accelerometer and gyroscope sensors active with independent ODR
The accelerometer is activated from power-down by writing ODR_XL[3:0] in CTRL1_XL (10h) while the gyroscope
is activated from power-down by writing ODR_G[3:0] in CTRL2_G (11h). For combo-mode the ODRs are totally
independent.
6.2 Accelerometer power modes
In the LSM6DSOX, the accelerometer can be configured in five different operating modes: power-down, ultra-low-
power, low-power, normal mode and high-performance mode. The operating mode selected depends on the value
of the XL_HM_MODE bit in CTRL6_C (15h). If XL_HM_MODE is set to '0', high-performance mode is valid for all
ODRs (from 12.5 Hz up to 6.66 kHz).
To enable the low-power and normal mode, the XL_HM_MODE bit has to be set to '1'. Low-power mode is
available for lower ODRs (1.6, 12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208
Hz.
6.2.1 Accelerometer ultra-low-power mode
The LSM6DSOX can be configured in ultra-low-power (ULP) mode by setting the XL_ULP_EN bit to 1 in
CTRL5_C (14h) register. This mode can be used in accelerometer-only mode (gyroscope sensor must be
configured in power-down mode) and for ODR_XL values between 1.6 Hz and 208 Hz.
When ULP mode is intended to be used, the bit XL_HM_MODE must be set to 0.
When ULP mode is switched ON/OFF, the accelerometer must be configured in power-down condition.
ULP mode cannot be used in Mode 3 or Mode 4 connection modes.
The embedded functions based on accelerometer data (free-fall, 6D/4D, tap, double tap, wake-up, activity/
inactivity, stationary/motion, step counter, step detection, significant motion, tilt) and the FIFO batching
functionality are still supported when ULP mode is enabled.
6.3 Gyroscope power modes
In the LSM6DSOX, the gyroscope can be configured in four different operating modes: power-down, low-power,
normal mode and high-performance mode. The operating mode selected depends on the value of the
G_HM_MODE bit in CTRL7_G (16h). If G_HM_MODE is set to '0', high-performance mode is valid for all ODRs
(from 12.5 Hz up to 6.66 kHz).
To enable the low-power and normal mode, the G_HM_MODE bit has to be set to '1'. Low-power mode is
available for lower ODRs (12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz.
LSM6DSOX
Functionality
DS12814 - Rev 3 page 27/199
6.4 Block diagram of filters
Figure 16. Block diagram of filters
ADC1
ADC2
Low Pass
UI Gyro
Low Pass
OIS Gyro
Low Pass
OIS XL
Regs
array,
FIFO
interface
Interrupt
mng
Auxiliary
SPI
Voltage and current
references
Trimming circuit
and Test interface
Clock and phase
generator
Power
management FTP
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
CS
SPC_Aux
SDI_Aux
SDO_Aux
INT1
INT2
M
E
M
S
S
E
N
S
O
R
Low Pass
UI XL
Gyro UI/OIS
front-end
XL UI/OIS
front-end
Temperature
sensor
Regs
array
Interrupt
mng
I2C/
/SPI
MIPI I3CSM
6.4.1 Block diagrams of the accelerometer filters
In the LSM6DSOX, the filtering chain for the accelerometer part is composed of the following:
• Analog filter (anti-aliasing)
• Digital filter (LPF1)
• Composite filter
Details of the block diagram appear in the following figure.
Figure 17. Accelerometer UI chain
ADC
Digital
LP Filter
Analog
Anti-aliasing
LP Filter
ODR_XL[3:0]
Composite
Filter
LPF1
LSM6DSOX
Block diagram of filters
DS12814 - Rev 3 page 28/199
Figure 18. Accelerometer composite filter
SLOPE
FILTER
HPCF_XL[2:0]
000
001
010
…
111
SPI /
I2C /
1
0
HP_SLOPE_XL_EN
LPF2_XL_EN
0
1
Digital
HP Filter
HPCF_XL[2:0]
Digital
LP Filter
LPF2
HPCF_XL[2:0]
S/D Tap
6D / 4D
0
1
LOW_PASS_ON_6D
1
0
SLOPE_FDS
Wake-up
Activity /
Inactivity
Free-fall
Advanced
functions
FIFO
USER
OFFSET
0
1
USR_OFF_ON_OUT
USR_OFF_W
OFS_USR[7:0]
1
0
USR_OFF_ON_WU
LPF1
output(1)
MIPI I3CSM
1. The cutoff value of the LPF1 output is ODR/2 when the accelerometer is in high-performance mode. This
value is equal to 700 Hz when the accelerometer is in low-power or normal mode.
Note: Advanced functions include pedometer, step detector and step counter, significant motion detection, and tilt
functions.
The accelerometer filtering chain when Mode 4 is enabled is illustrated in the following figure.
LSM6DSOX
Block diagram of filters
DS12814 - Rev 3 page 29/199
Figure 19. Accelerometer chain with Mode 4 enabled
Digital
LP Filter
LPF_OIS
FILTER_XL_CONF_OIS[2:0]
ADC
Analog
Anti-aliasing
LP Filter
SPI_Aux /
ODR XL
@6.6 kHz
UI chain
SPI / I2C /
MIPI I3CSM
Note: Mode 4 is enabled when Mode4_EN = 1 and OIS_EN_SPI2 = 1 in UI_CTRL1_OIS (70h) / SPI2_CTRL1_OIS
(70h).
The configuration of the accelerometer UI chain is not affected by enabling Mode 4.
Accelerometer output values are available in the following registers with ODR at 6.66 kHz:
•UI_OUTX_L_A_OIS (50h) and UI_OUTX_H_A_OIS (51h) through UI_OUTZ_L_A_OIS (54h) and
UI_OUTZ_H_A_OIS (55h)
•SPI2_OUTX_L_A_OIS (28h) and SPI2_OUTX_H_A_OIS (29h) through SPI2_OUTZ_L_A_OIS (2Ch) and
SPI2_OUTZ_H_A_OIS (2Dh)
Accelerometer full-scale management between the UI chain and OIS chain depends on the setting of the
XL_FS_MODE bit in register CTRL8_XL (17h).
LSM6DSOX
Block diagram of filters
DS12814 - Rev 3 page 30/199
6.4.2 Block diagrams of the gyroscope filters
In the LSM6DSOX, the gyroscope filtering chain depends on the mode configuration:
• Mode 1 (for User Interface (UI) and Electronic Image Stabilization (EIS) functionality through primary
interface) and Mode 2
Figure 20. Gyroscope digital chain - Mode 1 (UI/EIS) and Mode 2
ADC
HPF
HP_EN_G
LPF1
LPF2
LPF1_SEL_G
SPI/
I2C/
FIFO
FTYPE [2:0]
0
1
0
1
ODR_G[3:0]
MIPI I3CSM
In this configuration, the gyroscope ODR is selectable from 12.5 Hz up to 6.66 kHz. A low-pass filter (LPF1) is
available if the auxiliary SPI is disabled, for more details about the filter characteristics see Table 67. Gyroscope
LPF1 bandwidth selection.
The digital LPF2 filter cannot be configured by the user and its cutoff frequency depends on the selected
gyroscope ODR, as indicated in the following table.
Table 18. Gyroscope LPF2 bandwidth selection
Gyroscope ODR [Hz] LPF2 cutoff [Hz]
12.5 4.2
26 8.3
52 16.6
104 33.0
208 66.8
417 135.9
833 295.5
1667 1108.1
3333 1320.7
6667 1441.8
Note: Data can be acquired from the output registers and FIFO over the primary I²C/I³C/SPI interface.
LSM6DSOX
Block diagram of filters
DS12814 - Rev 3 page 31/199
• Mode 3 / Mode 4 (for OIS and EIS functionality)
Figure 21. Gyroscope digital chain - Mode 3 / Mode 4 (OIS/EIS)
ADC
Digital
HP Filter
HP_EN_G
0
1
HP_EN_OIS Digital
LP Filter
FTYPE[1:0]_OIS
LPF1
1
0
SPI / I2C/
MIPI I3CSM
FIFO
Digital
LP Filter
ODR_G[3:0]
LPF2
ODR Gyro
@6.6 kHz
(1) (2)
(3)
(3)
SPI_Aux /
SPI / I2C /
MIPI I3CSM
1. When Mode 3/4 is enabled, the LPF1 filter is not available in the gyroscope UI chain.
2. It is recommended to avoid using the LPF1 filter in Mode1/2 when Mode3/4 is intended to be used.
3. HP_EN_OIS can be used to select the HPF on the OIS path only if the HPF is not used in the UI chain. If
both the HP_EN_G bit and HP_EN_OIS bit are set to 1, the HP filter is applied to the UI chain only.
Note: When S4S is enabled in the UI chain, the HPF is not available in the OIS chain.
The auxiliary interface needs to be enabled in UI_CTRL1_OIS (70h) / SPI2_CTRL1_OIS (70h).
In Mode 3/4 configuration, there are two paths:
• the chain for User Interface (UI) where the ODR is selectable from 12.5 Hz up to 6.66 kHz
• the chain for OIS/EIS where the ODR is at 6.66 kHz and the LPF1 is available. The LPF1 configuration
depends on the setting of the FTYPE_[1;0] _OIS bit in register UI_CTRL2_OIS (71h) / SPI2_CTRL2_OIS
(71h); for more details about the filter characteristics see Table 182. Gyroscope OIS chain digital LPF1 filter
bandwidth selection. Gyroscope output values are in registers 22h to 27h if read from the Auxi_SPI or in
registers 4Ah to 4Fh if read from the primary interface with the selected full scale (FS[1:0]_G_OIS bit in
UI_CTRL1_OIS (70h) / SPI2_CTRL1_OIS (70h)).
LSM6DSOX
Block diagram of filters
DS12814 - Rev 3 page 32/199
6.5 OIS
This paragraph describes OIS functionality. There is a dedicated gyroscope and accelerometer DSP for OIS.
Other features can be configured:
• Self-test on OIS side
• DEN on OIS side
6.5.1 Enabling OIS functionality and connection schemes
There are three different ways in order to enable and configure OIS functionality:
•Auxiliary SPI full control: Enabling and configuration done from Auxiliary SPI
•Enabling primary interface: Enable from primary interface, configuration from Auxiliary SPI
•Primary interface full control: Enabling and configuration done from primary interface
The configurations that allow selecting these three different options are done using the OIS_CTRL_FROM_UI bit
in FUNC_CFG_ACCESS (01h) and the OIS_ON_EN bit in CTRL7_G (16h) as described in the following table.
Table 19. OIS configurations
OIS_CTRL_
FROM_UI OIS_ON_EN OIS configuration option
0 0 Auxiliary SPI full control
0 1 Enabling primary interface
1 x Primary interface full control
6.5.1.1 Auxiliary SPI full control
This is the default condition of the device. The camera module is completely independent from the application
processor as shown in Figure 22.
The Auxiliary SPI can configure OIS functionality through SPI2_INT_OIS (6Fh), SPI2_CTRL1_OIS (70h),
SPI2_CTRL2_OIS (71h), SPI2_CTRL3_OIS (72h).
Reading from the Auxiliary SPI is enabled only when the OIS_EN_SPI2 bit in the SPI2_CTRL1_OIS (70h) register
is set to '1'. This bit also turns on the gyroscope OIS chain.
The Primary Interface can access the OIS control registers (UI_INT_OIS (6Fh), UI_CTRL1_OIS (70h),
UI_CTRL2_OIS (71h), UI_CTRL3_OIS (72h)) in read mode.
Note: If accelerometer Ultra-Low-Power Mode is intended to be used on the Primary chain, it is recommended to use
the Primary IF enabling option instead, in order to make sure that the device is set in Power-Down (from ULP
mode) before enabling the OIS chain.
LSM6DSOX
OIS
DS12814 - Rev 3 page 33/199
Figure 22. Auxiliary SPI full control (a) and enabling primary interface (b)
6x
UI/OIS
AP
I3C/SPI/I2C
Camera Module
OIS Driver
Image
Sensor
Actuator
SPI_Aux 6x
UI/OIS
AP
I3C/SPI/I2C
Camera Module
OIS Driver
Image
Sensor
Actuator
SPI_Aux
(a) (b)
6.5.1.2 Enabling primary interface
This option allows the application processor to enable/disable the OIS functionality from the primary interface. An
example of this option is shown in Figure 22.
In order to enable/disable the OIS chain from the primary interface, the OIS_ON_EN bit in the CTRL7_G (16h)
register must be set to '1' from the primary interface.
Then, enabling OIS functionalities and reading from the Auxiliary SPI can be done from the primary interface by
setting the OIS_ON bit in CTRL7_G (16h) to ‘1’. This bit also turns on the gyroscope OIS chain.
The configuration of the OIS functionalities must be implemented from the Auxiliary SPI through the
SPI2_INT_OIS (6Fh), SPI2_CTRL1_OIS (70h), SPI2_CTRL2_OIS (71h), and SPI2_CTRL3_OIS (72h) registers.
The camera module can verify that the AP has enabled the LSM6DSOX OIS chain by reading the
SPI2_WHO_AM_I (0Fh) register. The bit OIS_EN_SPI2 is kept under reset.
The Primary Interface can access the OIS control registers (UI_INT_OIS (6Fh), UI_CTRL1_OIS (70h),
UI_CTRL2_OIS (71h), UI_CTRL3_OIS (72h)) in read mode.
Note: If the accelerometer Ultra-Low-Power Mode is active when activation of the OIS is required, the device must be
set in Power-Down mode before enabling the OIS chain.
The OIS_ON_EN bit is reset from the SW RESET procedure.
6.5.1.3 Primary interface full control
This option allows the application processor to configure all OIS functionalities from the primary interface. This
option allows using embedded OIS data for both the main and front camera, connecting them to the application
processor (eventually adding a context hub) as shown in Figure 23: the AP can also do some processing on the
data before sending them to the cameras.
In order to place the device in this mode, the OIS_CTRL_FROM_UI bit in the FUNC_CFG_ACCESS (01h)
register must be set to ‘1’ from the primary interface.
LSM6DSOX
OIS
DS12814 - Rev 3 page 34/199
Figure 23. OIS Primary interface full control
Context
Hub
Front camera
6x
UI/OIS
AP
I3C/SPI/I2C
2nd camera Main camera
OIS Driver
Image
Sensor
Actuator
Context
Hub
Front camera
6x
UI/OIS
AP
I3C/SPI/I2C
2nd camera Main camera
OIS Driver
Image
Sensor
Actuator
SPI_Aux
(a) (b)
Then, the AP can configure OIS functionalities through UI_INT_OIS (6Fh), UI_CTRL1_OIS (70h), UI_CTRL2_OIS
(71h), UI_CTRL3_OIS (72h).
The OIS_EN_SPI2 bit in the UI_CTRL1_OIS (70h) register enables the gyroscope OIS chain.
Reading from the Auxiliary SPI can be enabled by setting the SPI2_ READ_EN bit in the UI_INT_OIS (6Fh)
register to ‘1’ in order to directly read OIS data (as shown in Figure 23 (b)). The Auxiliary SPI can access the
SPI2_INT_OIS (6Fh), SPI2_CTRL1_OIS (70h), SPI2_CTRL2_OIS (71h), and SPI2_CTRL3_OIS (72h) registers
in read-only mode.
Note: If the accelerometer Ultra-Low-Power Mode is active when activation of the OIS is required, the device must be
set in Power-Down mode before enabling the OIS chain.
The OIS_CTRL_FROM_UI bit is reset from the SW RESET procedure.
S4S is not available in the primary interface full control mode.
LSM6DSOX
OIS
DS12814 - Rev 3 page 35/199
6.6 FIFO
The presence of a FIFO allows consistent power saving for the system since the host processor does not need
continuously poll data from the sensor, but It can wake up only when needed and burst the significant data out
from the FIFO.
The LSM6DSOX embeds 3 kbytes of data in FIFO to store the following data:
• Gyroscope
• Accelerometer
• External sensors (up to 4)
• Step counter
• Timestamp
• Temperature
Writing data in the FIFO can be configured to be triggered by the:
• Accelerometer / gyroscope data-ready signal
• Sensor hub data-ready signal
• Step detection signal
The applications have maximum flexibility in choosing the rate of batching for physical sensors with FIFO-
dedicated configurations: accelerometer, gyroscope and temperature sensor batching rates can be selected by
the user. External sensor writing in FIFO can be triggered by the accelerometer data-ready signal or by an
external sensor interrupt. The step counter can be stored in FIFO with associated timestamp each time a step is
detected. It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32.
The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows
recognizing the meaning of a word in FIFO.
FIFO allows correct reconstruction of the timestamp information for each sensor stored in FIFO. If a change in the
ODR or BDR (Batching Data Rate) configuration is performed, the application can correctly reconstruct the
timestamp and know exactly when the change was applied without disabling FIFO batching. FIFO stores
information of the new configuration and timestamp in which the change was applied in the device.
Finally, FIFO embeds a compression algorithm that the user can enable in order to have up to 9 kbyte data stored
in FIFO and take advantage of interface communication length for FIFO flushing and communication power
consumption.
The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h) using the
WTM[8:0] bits. To monitor the FIFO status, dedicated registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh))
can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the
number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2 pins of
these status events, the configuration can be set in INT1_CTRL (0Dh) and INT2_CTRL (0Eh).
The FIFO buffer can be configured according to six different modes:
• Bypass mode
• FIFO mode
• Continuous mode
• Continuous-to-FIFO mode
• Bypass-to-continuous mode
• Bypass-to-FIFO mode
Each mode is selected by the FIFO_MODE_[2:0] bits in the FIFO_CTRL4 (0Ah) register.
6.6.1 Bypass mode
In Bypass mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 000), the FIFO is not operational and it remains
empty. Bypass mode is also used to reset the FIFO when in FIFO mode.
6.6.2 FIFO mode
In FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 001) data from the output channels are stored in the
FIFO until it is full.
LSM6DSOX
FIFO
DS12814 - Rev 3 page 36/199
To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0]) to
'000'. After this reset command, it is possible to restart FIFO mode by writing FIFO_CTRL4 (0Ah)
(FIFO_MODE_[2:0]) to '001'.
The FIFO buffer memorizes up to 9 kbytes of data (with compression enabled) but the depth of the FIFO can be
resized by setting the WTM [8:0] bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h). If the STOP_ON_WTM bit in
FIFO_CTRL2 (08h) is set to '1', FIFO depth is limited up to the WTM [8:0] bits in FIFO_CTRL1 (07h) and
FIFO_CTRL2 (08h).
6.6.3 Continuous mode
Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 110) provides a continuous FIFO update: as new
data arrives, the older data is discarded.
A FIFO threshold flag FIFO_STATUS2 (3Bh)(FIFO_WTM_IA) is asserted when the number of unread samples in
FIFO is greater than or equal to FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)(WTM [8:0]).
It is possible to route the FIFO_WTM_IA flag to FIFO_CTRL2 (08h) to the INT1 pin by writing in register
INT1_CTRL (0Dh)(INT1_FIFO_TH) = '1' or to the INT2 pin by writing in register INT2_CTRL (0Eh)
(INT2_FIFO_TH) = '1'.
A full-flag interrupt can be enabled, INT1_CTRL (0Dh)(INT1_FIFO_FULL) = '1' or INT2_CTRL (0Eh)
(INT2_FIFO_FULL) = '1', in order to indicate FIFO saturation and eventually read its content all at once.
If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the FIFO_OVR_IA flag
in FIFO_STATUS2 (3Bh) is asserted.
In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples
available inFIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh)(DIFF_FIFO_[9:0]).
6.6.4 Continuous-to-FIFO mode
In Continuous-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 011), FIFO behavior changes according
to the trigger event detected in one of the following interrupt events:
• Single tap
• Double tap
• Wake-up
• Free-fall
• D6D
When the selected trigger bit is equal to '1', FIFO operates in FIFO mode.
When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.
6.6.5 Bypass-to-Continuous mode
In Bypass-to-Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '100'), data measurement storage
inside FIFO operates in Continuous mode when selected triggers are equal to '1', otherwise FIFO content is reset
(Bypass mode).
FIFO behavior changes according to the trigger event detected in one of the following interrupt events:
• Single tap
• Double tap
• Wake-up
• Free-fall
• D6D
6.6.6 Bypass-to-FIFO mode
In Bypass-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '111'), data measurement storage inside FIFO
operates in FIFO mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode).
FIFO behavior changes according to the trigger event detected in one of the following interrupt events:
• Single tap
• Double tap
• Wake-up
• Free-fall
• D6D
LSM6DSOX
FIFO
DS12814 - Rev 3 page 37/199
6.6.7 FIFO reading procedure
The data stored in FIFO are accessible from dedicated registers and each FIFO word is composed of 7 bytes:
one tag byte (FIFO_DATA_OUT_TAG (78h), in order to identify the sensor, and 6 bytes of fixed data
(FIFO_DATA_OUT registers from (79h) to (7Eh)).
The DIFF_FIFO_[9:0] field in the FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh) registers contains the number
of words (1 byte TAG + 6 bytes DATA) collected in FIFO.
In addition, it is possible to configure a counter of the batch events of accelerometer or gyroscope sensors. The
flag COUNTER_BDR_IA in FIFO_STATUS2 (3Bh) alerts that the counter reaches a selectable threshold
(CNT_BDR_TH_[10:0] field in COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch)). This allows
triggering the reading of FIFO with the desired latency of one single sensor. The sensor is selectable using the
TRIG_COUNTER_BDR bit in COUNTER_BDR_REG1 (0Bh). As for the other FIFO status events, the flag
COUNTER_BDR_IA can be routed on the INT1 or INT2 pins by asserting the corresponding bits
(INT1_CNT_BDR of INT1_CTRL (0Dh) and INT2_CNT_BDR of INT2_CTRL (0Eh)).
In order to maximize the amount of accelerometer and gyroscope data in FIFO, the user can enable the
compression algorithm by setting to 1 both the FIFO_COMPR_EN bit in EMB_FUNC_EN_B (05h) (embedded
functions registers bank) and the FIFO_COMPR_RT_EN bit in FIFO_CTRL2 (08h). When compression is
enabled, it is also possible to force writing non-compressed data at a selectable rate using the
UNCOPTR_RATE_[1:0] field in FIFO_CTRL2 (08h).
Meta information about accelerometer and gyroscope sensor configuration changes can be managed by enabling
the ODR_CHG_EN bit in FIFO_CTRL2 (08h).
LSM6DSOX
FIFO
DS12814 - Rev 3 page 38/199
7Application hints
7.1 LSM6DSOX electrical connections in Mode 1
Figure 24. LSM6DSOX electrical connections in Mode 1
GND or VDDIO
Vdd_IO
GND
100 nF
C2
SDO/SA0
SDx
SCx
INT1
GND
VDDIO
CS
SCL
SDA
11
57
12
TOP
VIEW
VDD
INT2
NC
NC
14
8
4
Vdd
GND
100 nF
C1
GND
1
SCL
SDA
Vdd_IO
Rpu Rpu
Pull-up to be added
Rpu=10kOhm
I2C configuration
HOST
LSM6DSOX
Mode 1
(1)
(1)
I2C
SPI (3/4-w)
/
MIPI I3CSM/
1. Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic)
should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible
through the SPI/I²C/MIPI I3CSM interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely
programmed by the user through the SPI/I²C/MIPI I3CSM interface.
LSM6DSOX
Application hints
DS12814 - Rev 3 page 39/199
7.2 LSM6DSOX electrical connections in Mode 2
Figure 25. LSM6DSOX electrical connections in Mode 2
Vdd_IO
GND
100 nF
C2
SDO/SA0
MSDA
MSCL
INT1
GND
VDDIO
CS
SCL
SDA
11
57
12
TOP
VIEW
VDD
NC
NC
14
8
4
Vdd
GND
100 nF
C1
MDRDY/INT2
GND
1
HOST
LSM6DSOX
LSM6DSM
LSM6DSM
External
sensors
Master I2C
Mode 2
SCL
SDA
Vdd_IO
Rpu Rpu
Pull-up to be added
Rpu=10kOhm
I2C configuration
(1)
(1)
I2C
SPI (3/4-w)
/
MIPI I3CSM/
1. Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic)
should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible
through the SPI/I²C/MIPI I3CSM primary interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely
programmed by the user through the SPI/I²C/MIPI I3CSM primary interface.
LSM6DSOX
LSM6DSOX electrical connections in Mode 2
DS12814 - Rev 3 page 40/199
7.3 LSM6DSOX electrical connections in Mode 3 and Mode 4
Figure 26. LSM6DSOX electrical connections in Mode 3 and Mode 4 (auxiliary 3/4-wire SPI)
Vdd_IO
GND
100 nF
C2
SDO
INT1
GND
VDDIO SDI
11
57
12
TOP
VIEW
VDD
INT2
NC
14
8
4
Vdd
GND
100 nF
C1
SDI_Aux
SPC_Aux
OCS_Aux
1
SPC
CS
GND
HOST
LSM6DSOX
Camera
module
Aux SPI (3/4-wire)
Mode 3
SCL
SDA
Vdd_IO
Rpu Rpu
Pull-up to be added
Rpu=10kOhm
I2C configuration
(1)
HOST
LSM6DSOX
Camera
module
Mode 4
For gyro
data only
For XL and
gyro data
I2C
SPI (3/4-w)
/
MIPI I3CSM/
I2C
SPI (3/4-w)
/
MIPI I3CSM/
Aux SPI (3/4-wire)
1. Leave pin electrically unconnected and soldered to PCB.
Note: When Mode 3 and 4 are used, the pull-up on pins 10 and 11 can be disabled (refer to Table 20. Internal pin
status). To avoid leakage current, it is recommended to not leave the SPI lines floating (also when the OIS
system is off).
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic)
should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device is selectable and accessible through the SPI/I²C/I³C primary interface.
Measured acceleration/angular rate data is selectable and accessible through the SPI/I²C/MIPI I3CSM primary
interface and auxiliary SPI.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely
programmed by the user through the SPI/I²C/MIPI I3CSM interface.
LSM6DSOX
LSM6DSOX electrical connections in Mode 3 and Mode 4
DS12814 - Rev 3 page 41/199
Table 20. Internal pin status
pin# Name Mode 1 function Mode 2 function Mode 3 / Mode 4 function Pin status Mode 1 Pin status Mode 2 Pin status Mode 3/4 (1)
1
SDO SPI 4-wire interface serial
data output (SDO)
SPI 4-wire interface serial
data output (SDO)
SPI 4-wire interface serial
data output (SDO)
Default: input without pull-up.
Pull-up is enabled if bit
SDO_PU_EN = 1 in reg 02h.
Default: input without pull-up.
Pull-up is enabled if bit
SDO_PU_EN = 1 in reg 02h.
Default: Input without pull-up.
Pull-up is enabled if bit
SDO_PU_EN = 1 in reg 02h.
SA0
I²C least significant bit of
the device address (SA0)
MIPI I3CSM least significant
bit of the static address
(SA0)
I²C least significant bit of
the device address (SA0)
MIPI I3CSM least significant
bit of the static address
(SA0)
I²C least significant bit of
the device address (SA0)
MIPI I3CSM least significant
bit of the static address
(SA0)
2 SDx Connect to VDDIO or GND I²C serial data master
(MSDA)
Auxiliary SPI 3/4-wire
interface serial data input
(SDI) and SPI 3-wire serial
data output (SDO)
Default: input without pull-up.
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in
sensor hub registers (see Note to
enable pull-up).
Default: input without pull-up.
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in
sensor hub registers (see Note to
enable pull-up).
Default: input without pull-up.
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in
sensor hub registers (see Note to
enable pull-up).
3 SCx Connect to VDDIO or GND I²C serial clock master
(MSCL)
Auxiliary SPI 3/4-wire
interface serial port clock
(SPC_Aux)
Default: input without pull-up.
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in
sensor hub registers (see Note to
enable pull-up).
Default: input without pull-up.
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in
sensor hub registers (see Note to
enable pull-up).
Default: input without pull-up.
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in
sensor hub registers (see Note to
enable pull-up)
4 INT1
Programmable interrupt 1 /
If device is used as MIPI
I3CSM pure slave, this pin
must be set to ‘1’.
Programmable interrupt 1 /
If device is used as MIPI
I3CSM pure slave, this pin
must be set to ‘1’.
Programmable interrupt 1 /
If device is used as MIPI
I3CSM pure slave, this pin
must be set to ‘1’.
Default: input with pull-down(2) Default: input with pull-down(2) Default: input with pull-down(2)
5 VDDIO Power supply for I/O pins Power supply for I/O pins Power supply for I/O pins
6 GND 0 V supply 0 V supply 0 V supply
7 GND 0 V supply 0 V supply 0 V supply
8 VDD Power supply Power supply Power supply
9 INT2
Programmable interrupt 2
(INT2) / Data enabled
(DEN)
Programmable interrupt 2
(INT2) / Data enabled
(DEN) / I²C master external
synchronization signal
(MDRDY)
Programmable interrupt 2
(INT2) / Data enabled
(DEN)
Default: output forced to ground Default: output forced to ground Default: output forced to ground
10 OCS_Aux Leave unconnected Leave unconnected Auxiliary SPI 3/4-wire
interface enabled
Default: input with pull-up.
Pull-up is disabled if bit
OIS_PU_DIS = 1 in reg 02h.
Default: input with pull-up.
Pull-up is disabled if bit
OIS_PU_DIS = 1 in reg 02h.
Default: input without pull-up
(regardless of the value of bit
OIS_PU_DIS in reg 02h.)
11 SDO_Aux Connect to VDDIO or leave
unconnected
Connect to VDDIO or leave
unconnected
Auxiliary SPI 3-wire
interface: leave
unconnected / Auxiliary SPI
4-wire interface: serial data
output (SDO_Aux)
Default: input with pull-up.
Pull-up is disabled if bit
OIS_PU_DIS = 1 in reg 02h.
Default: input with pull-up.
Pull-up is disabled if bit
OIS_PU_DIS = 1 in reg 02h.
Default: input without pull-up.
Pull-up is enabled if bit SIM_OIS = 1
(Aux_SPI 3-wire) in reg 70h and bit
OIS_PU_DIS = 0 in reg 02h.
12 CS
I²C/SPI mode selection
(1:SPI idle mode / I²C
communication enabled;
0: SPI communication
mode / I²C disabled)
I²C/SPI mode selection
(1:SPI idle mode / I²C
communication enabled;
0: SPI communication
mode / I²C disabled)
I2C/SPI mode selection
(1:SPI idle mode / I²C
communication enabled;
0: SPI communication
mode / I²C disabled)
Default: input with pull-up.
Pull-up is disabled if bit
I2C_disable = 1 in reg 13h and
I3C_disable = 1 in reg 18h.
Default: input with pull-up.
Pull-up is disabled if bit
I2C_disable = 1 in reg 13h and
I3C_disable = 1 in reg 18h.
Default: input with pull-up.
Pull-up is disabled if bit
I2C_disable = 1 in reg 13h and
I3C_disable = 1 in reg 18h.
DS12814 - Rev 3 page 42/199
LSM6DSOX
pin# Name Mode 1 function Mode 2 function Mode 3 / Mode 4 function Pin status Mode 1 Pin status Mode 2 Pin status Mode 3/4 (1)
13 SCL I²C/MIPI I3CSM serial clock
(SCL) / SPI serial port clock
(SPC)
I²C/MIPI I3CSM serial clock
(SCL) / SPI serial port clock
(SPC)
I²C/MIPI I3CSM serial clock
(SCL) / SPI serial port clock
(SPC)
Default: input without pull-up Default: input without pull-up Default: input without pull-up
14 SDA
I²C/MIPI I3CSM serial data
(SDA) / SPI serial data
input (SDI) / 3-wire
interface serial data output
(SDO)
I²C/MIPI I3CSM serial data
(SDA) / SPI serial data
input (SDI) / 3-wire
interface serial data output
(SDO)
I²C/MIPI I3CSM serial data
(SDA) / SPI serial data
input (SDI) / 3-wire
interface serial data output
(SDO)
Default: input without pull-up Default: input without pull-up Default:input without pull-up
1. Mode 3 is enabled when the OIS_EN_SPI2 bit in the UI_CTRL1_OIS (70h) / SPI2_CTRL1_OIS (70h) registers is set to 1. Mode 4 is enabled when
both the OIS_EN_SPI2 bit and the Mode4_EN bit in the UI_CTRL1_OIS (70h) / SPI2_CTRL1_OIS (70h) registers are set to 1.
2. INT1 must be set to '0' or left unconnected during power-on if the I²C/SPI interfaces are used.
Internal pull-up value is from 30 kΩ to 50 kΩ, depending on VDDIO.
Note: The procedure to enable the pull-up on pins 2 and 3 is as follows:
1. From the primary I²C/I³C/SPI interface: write 40h in register at address 01h (enable access to the sensor hub registers)
2. From the primary I²C/I³C/SPI interface: write 08h in register at address 14h (enable the pull-up on pins 2 and 3)
3. From the primary I²C/I³C/SPI interface: write 00h in register at address 01h (disable access to the sensor hub registers)
DS12814 - Rev 3 page 43/199
LSM6DSOX
8Register mapping
The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding
addresses.
All these registers are accessible from the primary SPI/I²C/MIPI I3CSM interface only.
Table 21. Registers address map
Name Type
Register address
Default Comment
Hex Binary
FUNC_CFG_ACCESS RW 01 00000001 00000000
PIN_CTRL RW 02 00000010 00111111
RESERVED - 03 00000011
S4S_TPH_L RW 04 00000100 00000000
S4S_TPH_H RW 05 00000101 00000000
S4S_RR RW 06 00000110 00000000
FIFO_CTRL1 RW 07 00000111 00000000
FIFO_CTRL2 RW 08 00001000 00000000
FIFO_CTRL3 RW 09 00001001 00000000
FIFO_CTRL4 RW 0A 00001010 00000000
COUNTER_BDR_REG1 RW 0B 00001011 00000000
COUNTER_BDR_REG2 RW 0C 00001100 00000000
INT1_CTRL RW 0D 00001101 00000000
INT2_CTRL RW 0E 00001110 00000000
WHO_AM_I R 0F 00001111 01101100 R (SPI2)
CTRL1_XL RW 10 00010000 00000000 R (SPI2)
CTRL2_G RW 11 00010001 00000000 R (SPI2)
CTRL3_C RW 12 00010010 00000100 R (SPI2)
CTRL4_C RW 13 00010011 00000000 R (SPI2)
CTRL5_C RW 14 00010100 00000000 R (SPI2)
CTRL6_C RW 15 00010101 00000000 R (SPI2)
CTRL7_G RW 16 00010110 00000000 R (SPI2)
CTRL8_XL RW 17 0001 0111 00000000 R (SPI2)
CTRL9_XL RW 18 00011000 11100000 R (SPI2)
CTRL10_C RW 19 00011001 00000000 R (SPI2)
ALL_INT_SRC R 1A 00011010 output
WAKE_UP_SRC R 1B 00011011 output
TAP_SRC R 1C 00011100 output
D6D_SRC R 1D 00011101 output
STATUS_REG R 1E 00011110 output
RESERVED - 1F 00011111
OUT_TEMP_L R 20 00100000 output
LSM6DSOX
Register mapping
DS12814 - Rev 3 page 44/199
Name Type
Register address
Default Comment
Hex Binary
OUT_TEMP_H R 21 00100001 output
OUTX_L_G R 22 00100010 output
OUTX_H_G R 23 00100011 output
OUTY_L_G R 24 00100100 output
OUTY_H_G R 25 00100101 output
OUTZ_L_G R 26 00100110 output
OUTZ_H_G R 27 00100111 output
OUTX_L_A R 28 00101000 output
OUTX_H_A R 29 00101001 output
OUTY_L_A R 2A 00101010 output
OUTY_H_A R 2B 00101011 output
OUTZ_L_A R 2C 00101100 output
OUTZ_H_A R 2D 00101101 output
RESERVED - 2E-34
EMB_FUNC_STATUS_MAINPAGE R 35 00110101 output
FSM_STATUS_A_MAINPAGE R 36 00110110 output
FSM_STATUS_B_MAINPAGE R 37 00110111 output
MLC_STATUS_MAINPAGE R 38 00111000 output
STATUS_MASTER_MAINPAGE R 39 00111001 output
FIFO_STATUS1 R 3A 00111010 output
FIFO_STATUS2 R 3B 00111011 output
RESERVED - 3C-3F
TIMESTAMP0 R 40 01000000 output R (SPI2)
TIMESTAMP1 R 41 01000001 output R (SPI2)
TIMESTAMP2 R 42 01000010 output R (SPI2)
TIMESTAMP3 R 43 01000011 output R (SPI2)
RESERVED - 44-48
UI_STATUS_REG_OIS R 49 01001001 output
UI_OUTX_L_G_OIS R 4A 01001010 output
UI_OUTX_H_G_OIS R 4B 01001011 output
UI_OUTY_L_G_OIS R 4C 01001100 output
UI_OUTY_H_G_OIS R 4D 01001101 output
UI_OUTZ_L_G_OIS R 4E 01001110 output
UI_OUTZ_H_G_OIS R 4F 01001111 output
UI_OUTX_L_A_OIS R 50 01010000 output
UI_OUTX_H_A_OIS R 51 01010001 output
UI_OUTY_L_A_OIS R 52 01010010 output
UI_OUTY_H_A_OIS R 53 01010011 output
UI_OUTZ_L_A_OIS R 54 01010100 output
LSM6DSOX
Register mapping
DS12814 - Rev 3 page 45/199
Name Type
Register address
Default Comment
Hex Binary
UI_OUTZ_H_A_OIS R 55 01010101 output
TAP_CFG0 RW 56 01010110 00000000
TAP_CFG1 RW 57 01010111 00000000
TAP_CFG2 RW 58 01011000 00000000
TAP_THS_6D RW 59 01011001 00000000
INT_DUR2 RW 5A 01011010 00000000
WAKE_UP_THS RW 5B 01011011 00000000
WAKE_UP_DUR RW 5C 01011100 00000000
FREE_FALL RW 5D 01011101 00000000
MD1_CFG RW 5E 01011110 00000000
MD2_CFG RW 5F 01011111 00000000
S4S_ST_CMD_CODE RW 60 01100000 00000000
S4S_DT_REG RW 61 01100001 00000000
I3C_BUS_AVB RW 62 01100010 00000000
INTERNAL_FREQ_FINE R 63 01100011 output
RESERVED - 64-6E
UI_INT_OIS R (SPI2 full control mode)
RW (Primary IF full control mode) 6F 01101111 00000000
UI_CTRL1_OIS R (SPI2 full control mode)
RW (Primary IF full control mode) 70 01110000 00000000
UI_CTRL2_OIS R (SPI2 full control mode)
RW (Primary IF full control mode) 71 01110001 00000000
UI_CTRL3_OIS R (SPI2 full control mode)
RW (Primary IF full control mode) 72 01110010 00000000
X_OFS_USR RW 73 01110011 00000000
Y_OFS_USR RW 74 01110100 00000000
Z_OFS_USR RW 75 01110101 00000000
RESERVED - 76-77
FIFO_DATA_OUT_TAG R 78 01111000 output
FIFO_DATA_OUT_X_L R 79 01111001 output
FIFO_DATA_OUT_X_H R 7A 01111010 output
FIFO_DATA_OUT_Y_L R 7B 01111011 output
FIFO_DATA_OUT_Y_H R 7C 01111100 output
FIFO_DATA_OUT_Z_L R 7D 01111101 output
FIFO_DATA_OUT_X_H R 7E 01111110 output
LSM6DSOX
Register mapping
DS12814 - Rev 3 page 46/199
9Register description
The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration,
angular rate and temperature data. The register addresses, made up of 7 bits, are used to identify them and to
write the data through the serial interface.
9.1 FUNC_CFG_ACCESS (01h)
Enable embedded functions register (r/w)
Table 22. FUNC_CFG_ACCESS register
FUNC_CFG_
ACCESS
SHUB_REG
_ACCESS 0(1) 0(1) 0(1) 0(1) 0(1) OIS_CTRL
_FROM_UI
1. This bit must be set to '0' for the correct operation of the device.
Table 23. FUNC_CFG_ACCESS register description
FUNC_CFG_ACCESS
Enable access to the embedded functions configuration
registers. (1)
Default value: 0
SHUB_REG_ACCESS Enable access to the sensor hub (I2C master) registers. (2)
Default value: 0
OIS_CTRL_FROM_UI
Enable the full control from the Primary Interface of OIS
configurations.
Default value: 0
(0: OIS chain full control from Primary Interface disabled;
1: OIS chain full control from Primary Interface enabled)
1. Details concerning the embedded functions configuration registers are available in Section 12 Embedded functions register
mapping and Section 13 Embedded functions register description.
2. Details concerning the sensor hub registers are available in Section 16 Sensor hub register mapping and Section 17 Sensor
hub register description.
LSM6DSOX
Register description
DS12814 - Rev 3 page 47/199
9.2 PIN_CTRL (02h)
SDO, OCS_AUX, SDO_AUX pins pull-up enable/disable register (r/w)
Table 24. PIN_CTRL register
OIS_
PU_DIS
SDO_
PU_EN 1 1 1 1 1 1
Table 25. PIN_CTRL register description
OIS_PU_DIS
Disable pull-up on both OCS_Aux and SDO_Aux pins. Default value: 0
(0: OCS_Aux and SDO_Aux pins with pull-up;
1: OCS_Aux and SDO_Aux pins pull-up disconnected)
SDO_PU_EN Enable pull-up on SDO pin
(0: SDO pin pull-up disconnected (default); 1: SDO pin with pull-up)
9.3 S4S_TPH_L (04h)
Sensor synchronization time frame register (r/w)
Table 26. S4S_TPH_L register
TPH_H_
SEL TPH_L_6 TPH_L_5 TPH_L_4 TPH_L_3 TPH_L_2 TPH_L_1 TPH_L_0
Table 27. S4S_TPH_L register description
TPH_H_SEL Chooses if the TPH formula must be taken into account (see equation below).
TPH_L_[6:0] S4S time frame expressed in number of samples as described in the equation below.
If TPH_H_SEL=0 and TPH_L_[6:0] = d0, S4S is disabled.
When TPH_H_SEL = 0:
TPH [#Samples] = 2 x TPHL
When TPH_H_SEL = 1:
TPH [#Samples] = 2 x (TPH_L + 256 x TPH_H)
LSM6DSOX
PIN_CTRL (02h)
DS12814 - Rev 3 page 48/199
9.4 S4S_TPH_H (05h)
Sensor synchronization time frame register (r/w)
Table 28. S4S_TPH_H register
TPH_H_7 TPH_H_6 TPH_H_5 TPH_H_4 TPH_H_3 TPH_H_2 TPH_H_1 TPH_H_0
Table 29. S4S_TPH_H register description
TPH_H_[7:0] S4S time frame expressed in number of samples. Only if the TPH_H_SEL bit in S4S_TPH_L (04h) is high, is
the value of this register taken into account as described in the equation in S4S_TPH_L (04h)
9.5 S4S_RR (06h)
Sensor synchronization resolution ratio register (r/w)
Table 30. S4S_RR register
0 0 0 0 0 0 RR_1 RR_0
Table 31. S4S_RR register description
RR_[1:0]
(00: S4S, DT resolution 211 ;
01: S4S, DT resolution 212 ;
10: S4S, DT resolution 213 ;
11: S4S, DT resolution 214)
9.6 FIFO_CTRL1 (07h)
FIFO control register 1 (r/w)
Table 32. FIFO_CTRL1 register
WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0
Table 33. FIFO_CTRL1 register description
WTM[7:0]
FIFO watermark threshold, in conjunction with WTM8 in FIFO_CTRL2 (08h)
1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.
LSM6DSOX
S4S_TPH_H (05h)
DS12814 - Rev 3 page 49/199
9.7 FIFO_CTRL2 (08h)
FIFO control register 2 (r/w)
Table 34. FIFO_CTRL2 register
STOP_ON
_WTM
FIFO_
COMPR_RT_
EN
0ODRCHG
_EN 0UNCOPTR
_RATE_1
UNCOPTR
_RATE_0 WTM8
Table 35. FIFO_CTRL2 register description
STOP_ON_WTM
Sensing chain FIFO stop values memorization at threshold level
(0: FIFO depth is not limited (default);
1: FIFO depth is limited to threshold level, defined in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h))
FIFO_COMPR_RT_EN(1) Enables/Disables compression algorithm runtime
ODRCHG_EN Enables ODR CHANGE virtual sensor to be batched in FIFO
UNCOPTR_RATE_[1:0]
This field configures the compression algorithm to write non-compressed data at each rate.
(0: Non-compressed data writing is not forced;
1: Non-compressed data every 8 batch data rate;
2: Non-compressed data every 16 batch data rate;
3: Non-compressed data every 32 batch data rate)
WTM8
FIFO watermark threshold, in conjunction with WTM_FIFO[7:0] in FIFO_CTRL1 (07h)
1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the
threshold level.
1. This bit is effective if the FIFO_COMPR_EN bit of EMB_FUNC_EN_B (05h) is set to 1.
LSM6DSOX
FIFO_CTRL2 (08h)
DS12814 - Rev 3 page 50/199
9.8 FIFO_CTRL3 (09h)
FIFO control register 3 (r/w)
Table 36. FIFO_CTRL3 register
BDR_GY_3 BDR_GY_2 BDR_GY_1 BDR_GY_0 BDR_XL_3 BDR_XL_2 BDR_XL_1 BDR_XL_0
Table 37. FIFO_CTRL3 register description
BDR_GY_[3:0]
Selects Batching Data Rate (writing frequency in FIFO) for gyroscope data.
(0000: Gyro not batched in FIFO (default);
0001: 12.5 Hz;
0010: 26 Hz;
0011: 52 Hz;
0100: 104 Hz;
0101: 208 Hz;
0110: 417 Hz;
0111: 833 Hz;
1000: 1667 Hz;
1001: 3333 Hz;
1010: 6667 Hz;
1011: 6.5 Hz;
1100-1111: not allowed)
BDR_XL_[3:0]
Selects Batching Data Rate (writing frequency in FIFO) for accelerometer data.
(0000: Accelerometer not batched in FIFO (default);
0001: 12.5 Hz;
0010: 26 Hz;
0011: 52 Hz;
0100: 104 Hz;
0101: 208 Hz;
0110: 417 Hz;
0111: 833 Hz;
1000: 1667 Hz;
1001: 3333 Hz;
1010: 6667 Hz;
1011: 1.6 Hz;
1100-1111: not allowed)
LSM6DSOX
FIFO_CTRL3 (09h)
DS12814 - Rev 3 page 51/199
9.9 FIFO_CTRL4 (0Ah)
FIFO control register 4 (r/w)
Table 38. FIFO_CTRL4 register
DEC_TS_
BATCH_1
DEC_TS_
BATCH_0
ODR_T_
BATCH_1
ODR_T_
BATCH_0 0FIFO_
MODE2
FIFO_
MODE1
FIFO_
MODE0
Table 39. FIFO_CTRL4 register description
DEC_TS_BATCH_[1:0]
Selects decimation for timestamp batching in FIFO. Writing rate will be the maximum rate between
XL and GYRO BDR divided by decimation decoder.
(00: Timestamp not batched in FIFO (default);
01: Decimation 1: max(BDR_XL[Hz],BDR_GY[Hz]) [Hz];
10: Decimation 8: max(BDR_XL[Hz],BDR_GY[Hz])/8 [Hz];
11: Decimation 32: max(BDR_XL[Hz],BDR_GY[Hz])/32 [Hz])
ODR_T_BATCH_[1:0]
Selects batching data rate (writing frequency in FIFO) for temperature data
(00: Temperature not batched in FIFO (default);
01: 1.6 Hz;
10: 12.5 Hz;
11: 52 Hz)
FIFO_MODE[2:0]
FIFO mode selection
(000: Bypass mode: FIFO disabled;
001: FIFO mode: stops collecting data when FIFO is full;
010: Reserved;
011: Continuous-to-FIFO mode: Continuous mode until trigger is deasserted, then FIFO mode;
100: Bypass-to-Continuous mode: Bypass mode until trigger is deasserted, then Continuous mode;
101: Reserved;
110: Continuous mode: if the FIFO is full, the new sample overwrites the older one;
111: Bypass-to-FIFO mode: Bypass mode until trigger is deasserted, then FIFO mode.)
LSM6DSOX
FIFO_CTRL4 (0Ah)
DS12814 - Rev 3 page 52/199
9.10 COUNTER_BDR_REG1 (0Bh)
Counter batch data rate register 1 (r/w)
Table 40. COUNTER_BDR_REG1 register
dataready_
pulsed
RST_COUNT
ER_BDR
TRIG_COUN
TER_BDR 0 0 CNT_
BDR_TH_10
CNT_
BDR_TH_9
CNT_
BDR_TH_8
Table 41. COUNTER_BDR_REG1 register description
dataready_pulsed
Enables pulsed data-ready mode
(0: Data-ready latched mode (returns to 0 only after an interface reading) (default);
1: Data-ready pulsed mode (the data ready pulses are 75 µs long)
RST_COUNTER_BDR Resets the internal counter of batching events for a single sensor.
This bit is automatically reset to zero if it was set to ‘1’.
TRIG_COUNTER_BDR
Selects the trigger for the internal counter of batching events between XL and gyro.
(0: XL batching event;
1: GYRO batching event)
CNT_BDR_TH_[10:8]
In conjunction with CNT_BDR_TH_[7:0] in COUNTER_BDR_REG2 (0Ch), sets the threshold for the
internal counter of batching events. When this counter reaches the threshold, the counter is reset
and the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’.
9.11 COUNTER_BDR_REG2 (0Ch)
Counter batch data rate register 2 (r/w)
Table 42. COUNTER_BDR_REG2 register
CNT_
BDR_TH_7
CNT_
BDR_TH_6
CNT_
BDR_TH_5
CNT_
BDR_TH_4
CNT_
BDR_TH_3
CNT_
BDR_TH_2
CNT_
BDR_TH_1
CNT_
BDR_TH_0
Table 43. COUNTER_BDR_REG2 register description
CNT_BDR_TH_[7:0]
In conjunction with CNT_BDR_TH_[10:8] in COUNTER_BDR_REG1 (0Bh), sets the threshold for the
internal counter of batching events. When this counter reaches the threshold, the counter is reset and
the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’.
LSM6DSOX
COUNTER_BDR_REG1 (0Bh)
DS12814 - Rev 3 page 53/199
9.12 INT1_CTRL (0Dh)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried out on INT1 when the MIPI I3CSM dynamic address is not
assigned (I2C or SPI is used). Some bits can be also used to trigger an IBI (In-Band Interrupt) when the MIPI
I3CSM interface is used. The output of the pin will be the OR combination of the signals selected here and in
MD1_CFG (5Eh).
Table 44. INT1_CTRL register
DEN_DRDY
_flag
INT_1
CNT_BDR
INT1_
FIFO_FULL
INT1_
FIFO_OVR
INT1_
FIFO_TH
INT1_
BOOT
INT1_
DRDY_G
INT1_
DRDY_XL
Table 45. INT1_CTRL register description
DEN_DRDY_flag Sends DEN_DRDY (DEN stamped on Sensor Data flag) to INT1 pin
INT1_CNT_BDR Enables COUNTER_BDR_IA interrupt on INT1
INT1_FIFO_FULL Enables FIFO full flag interrupt on INT1 pin. It can be also used to
trigger an IBI when the MIPI I3CSM interface is used.
INT1_FIFO_OVR Enables FIFO overrun interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3CSM
interface is used.
INT1_FIFO_TH Enables FIFO threshold interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3CSM
interface is used.
INT1_BOOT Enables boot status on INT1 pin
INT1_DRDY_G Enables gyroscope data-ready interrupt on INT1 pin. It can be also used to
trigger an IBI when the MIPI I3CSM interface is used.
INT1_DRDY_XL Enables accelerometer data-ready interrupt on INT1 pin. It can be also used to trigger an IBI when the
MIPI I3CSM interface is used.
LSM6DSOX
INT1_CTRL (0Dh)
DS12814 - Rev 3 page 54/199
9.13 INT2_CTRL (0Eh)
INT2 pin control register (r/w)
Each bit in this register enables a signal to be carried out on INT2 when the MIPI I3CSM dynamic address in not
assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI when the I3C interface is used. The
output of the pin will be the OR combination of the signals selected here and in MD2_CFG (5Fh).
Table 46. INT2_CTRL register
0INT2_
CNT_BDR
INT2_
FIFO_FULL
INT2_
FIFO_OVR
INT2_
FIFO_TH
INT2_
DRDY_TEMP
INT2_
DRDY_G
INT2_
DRDY_XL
Table 47. INT2_CTRL register description
INT2_CNT_BDR Enables COUNTER_BDR_IA interrupt on INT2
INT2_FIFO_FULL Enables FIFO full flag interrupt on INT2 pin
INT2_FIFO_OVR Enables FIFO overrun interrupt on INT2 pin
INT_FIFO_TH Enables FIFO threshold interrupt on INT2 pin
INT2_DRDY_TEMP Enables temperature sensor data-ready interrupt on INT2 pin. It can be also used to trigger an IBI when
the MIPI I3CSM interface is used and INT2_ON_INT1 = ‘1’ in CTRL4_C (13h).
INT2_DRDY_G Gyroscope data-ready interrupt on INT2 pin
INT2_DRDY_XL Accelerometer data-ready interrupt on INT2 pin
9.14 WHO_AM_I (0Fh)
WHO_AM_I register (r). This is a read-only register. Its value is fixed at 6Ch.
Table 48. WhoAmI register
01101100
LSM6DSOX
INT2_CTRL (0Eh)
DS12814 - Rev 3 page 55/199
9.15 CTRL1_XL (10h)
Accelerometer control register 1 (r/w)
Table 49. CTRL1_XL register
ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0 FS1_XL FS0_XL LPF2_XL_EN 0
Table 50. CTRL1_XL register description
ODR_XL[3:0] Accelerometer ODR selection (see Table 51)
FS[1:0]_XL Accelerometer full-scale selection (see Table 52)
LPF2_XL_EN
Accelerometer high-resolution selection
(0: output from first stage digital filtering selected (default);
1: output from LPF2 second filtering stage selected)
Table 51. Accelerometer ODR register setting
ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0
ODR selection [Hz] when
XL_HM_MODE = 1 in
CTRL6_C (15h)
ODR selection [Hz] when
XL_HM_MODE = 0 in
CTRL6_C (15h)
0 0 0 0 Power-down Power-down
1 0 1 1 1.6 Hz (low power only) 12.5 Hz (high performance)
0 0 0 1 12.5 Hz (low power) 12.5 Hz (high performance)
0 0 1 0 26 Hz (low power) 26 Hz (high performance)
0 0 1 1 52 Hz (low power) 52 Hz (high performance)
0 1 0 0 104 Hz (normal mode) 104 Hz (high performance)
0 1 0 1 208 Hz (normal mode) 208 Hz (high performance)
0 1 1 0 416 Hz (high performance) 416 Hz (high performance)
0 1 1 1 833 Hz (high performance) 833 Hz (high performance)
1 0 0 0 1.66 kHz (high performance) 1.66 kHz (high performance)
1 0 0 1 3.33 kHz (high performance) 3.33 kHz (high performance)
1 0 1 0 6.66 kHz (high performance) 6.66 kHz (high performance)
1 1 x x Not allowed Not allowed
Table 52. Accelerometer full-scale selection
FS[1:0]_XL XL_FS_MODE = ‘0’
in CTRL8_XL (17h)
XL_FS_MODE = ‘1’
in CTRL8_XL (17h)
00 (default) 2 g2 g
01 16 g2 g
10 4 g4 g
11 8 g8 g
LSM6DSOX
CTRL1_XL (10h)
DS12814 - Rev 3 page 56/199
9.16 CTRL2_G (11h)
Gyroscope control register 2 (r/w)
Table 53. CTRL2_G register
ODR_G3 ODR_G2 ODR_G1 ODR_G0 FS1_G FS0_G FS_125 0
Table 54. CTRL2_G register description
ODR_G[3:0] Gyroscope output data rate selection. Default value: 0000
(Refer to Table 55)
FS[1:0]_G
Gyroscope UI chain full-scale selection
(00: 250 dps;
01: 500 dps;
10: 1000 dps;
11: 2000 dps)
FS_125
Selects gyro UI chain full-scale 125 dps
(0: FS selected through bits FS[1:0]_G;
1: FS set to 125 dps)
Table 55. Gyroscope ODR configuration setting
ODR_G3 ODR_G2 ODR_G1 ODR_G0 ODR [Hz] when G_HM_MODE = 1 in
CTRL7_G (16h)
ODR [Hz] when G_HM_MODE = 0 in
CTRL7_G (16h)
0 0 0 0 Power down Power down
0 0 0 1 12.5 Hz (low power) 12.5 Hz (high performance)
0 0 1 0 26 Hz (low power) 26 Hz (high performance)
0 0 1 1 52 Hz (low power) 52 Hz (high performance)
0 1 0 0 104 Hz (normal mode) 104 Hz (high performance)
0 1 0 1 208 Hz (normal mode) 208 Hz (high performance)
0 1 1 0 416 Hz (high performance) 416 Hz (high performance)
0 1 1 1 833 Hz (high performance) 833 Hz (high performance)
1 0 0 0 1.66 kHz (high performance) 1.66 kHz (high performance)
1 0 0 1 3.33 kHz (high performance 3.33 kHz (high performance)
1 0 1 0 6.66 kHz (high performance 6.66 kHz (high performance)
1 0 1 1 Not available Not available
LSM6DSOX
CTRL2_G (11h)
DS12814 - Rev 3 page 57/199
9.17 CTRL3_C (12h)
Control register 3 (r/w)
Table 56. CTRL3_C register
BOOT BDU H_LACTIVE PP_OD SIM IF_INC 0 SW_RESET
Table 57. CTRL3_C register description
BOOT
Reboots memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
This bit is automatically cleared.
BDU
Block Data Update. Default value: 0
(0: continuous update;
1: output registers are not updated until MSB and LSB have been read)
H_LACTIVE Interrupt activation level. Default value: 0
(0: interrupt output pins active high; 1: interrupt output pins active low)
PP_OD Push-pull/open-drain selection on INT1 and INT2 pins. Default value: 0
(0: push-pull mode; 1: open-drain mode)
SIM SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
IF_INC
Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI).
Default value: 1
(0: disabled; 1: enabled)
SW_RESET
Software reset. Default value: 0
(0: normal mode; 1: reset device)
This bit is automatically cleared.
LSM6DSOX
CTRL3_C (12h)
DS12814 - Rev 3 page 58/199
9.18 CTRL4_C (13h)
Control register 4 (r/w)
Table 58. CTRL4_C register
0 SLEEP_G INT2_on
_INT1 0DRDY_
MASK I2C_disable LPF1_
SEL_G 0
Table 59. CTRL4_C register description
SLEEP_G Enables gyroscope Sleep mode. Default value:0
(0: disabled; 1: enabled)
INT2_on_INT1
All interrupt signals available on INT1 pin enable. Default value: 0
(0: interrupt signals divided between INT1 and INT2 pins;
1: all interrupt signals in logic or on INT1 pin)
DRDY_MASK
Enables data available
(0: disabled;
1: mask DRDY on pin (both XL & Gyro) until filter settling ends (XL and Gyro independently masked).
I2C_disable Disables I2C interface. Default value: 0
(0: SPI, I2C and MIPI I3CSM interfaces enabled (default); 1: I²C interface disabled)
LPF1_SEL_G
Enables gyroscope digital LPF1 if auxiliary SPI is disabled; the bandwidth can be selected through FTYPE
[2:0] in CTRL6_C (15h).
(0: disabled; 1: enabled)
LSM6DSOX
CTRL4_C (13h)
DS12814 - Rev 3 page 59/199
9.19 CTRL5_C (14h)
Control register 5 (r/w)
Table 60. CTRL5_C register
XL_ULP_EN ROUNDING1 ROUNDING0 ROUNDING_
STATUS ST1_G ST0_G ST1_XL ST0_XL
Table 61. CTRL5_C register description
XL_ULP_EN Accelerometer ultra-low-power mode enable. Default value: 0(1)
(0: Ultra-low-power mode disabled; 1: Ultra-low-power mode enabled)
ROUNDING[1:0]
Circular burst-mode (rounding) read from the output registers. Default value: 00
(00: no rounding;
01: accelerometer only;
10: gyroscope only;
11: gyroscope + accelerometer)
ROUNDING_
STATUS
Source register rounding function in ALL_INT_SRC (1Ah), WAKE_UP_SRC (1Bh), TAP_SRC (1Ch),
D6D_SRC (1Dh), STATUS_REG (1Eh) and EMB_FUNC_STATUS_MAINPAGE (35h),
FSM_STATUS_A_MAINPAGE (36h), FSM_STATUS_B_MAINPAGE (37h), MLC_STATUS_MAINPAGE
(38h), STATUS_MASTER_MAINPAGE (39h), FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh).
Default value: 0
(0: Rounding disabled; 1: Rounding enabled)
ST[1:0]_G Angular rate sensor self-test enable. Default value: 00
(00: Self-test disabled; Other: refer to Table 62)
ST[1:0]_XL Linear acceleration sensor self-test enable. Default value: 00
(00: Self-test disabled; Other: refer to Table 63)
1. Further details about the accelerometer ultra-low-power mode are provided in Section 6.2.1 Accelerometer ultra-low-power
mode.
Table 62. Angular rate sensor self-test mode selection
ST1_G ST0_G Self-test mode
0 0 Normal mode
0 1 Positive sign self-test
1 0 Not allowed
1 1 Negative sign self-test
Table 63. Linear acceleration sensor self-test mode selection
ST1_XL ST0_XL Self-test mode
0 0 Normal mode
0 1 Positive sign self-test
1 0 Negative sign self-test
1 1 Not allowed
LSM6DSOX
CTRL5_C (14h)
DS12814 - Rev 3 page 60/199
9.20 CTRL6_C (15h)
Control register 6 (r/w)
Table 64. CTRL6_C register
TRIG_EN LVL1_EN LVL2_EN XL_HM_
MODE
USR_
OFF_W FTYPE_2 FTYPE_1 FTYPE_0
Table 65. CTRL6_C register description
TRIG_EN DEN data edge-sensitive trigger enable. Refer to Table 66.
LVL1_EN DEN data level-sensitive trigger enable. Refer to Table 66.
LVL2_EN DEN level-sensitive latched enable. Refer to Table 66.
XL_HM_MODE
High-performance operating mode disable for accelerometer. Default value: 0
(0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
USR_OFF_W
Weight of XL user offset bits of registers X_OFS_USR (73h), Y_OFS_USR (74h), Z_OFS_USR (75h)
0 = 2-10 g/LSB
1 = 2-6 g/LSB
FTYPE[2:0] Gyroscope low-pass filter (LPF1) bandwidth selection
Table 66 shows the selectable bandwidth values (available if auxiliary SPI is disabled).
Table 66. Trigger mode selection
TRIG_EN, LVL1_EN, LVL2_EN Trigger mode
100 Edge-sensitive trigger mode is selected
010 Level-sensitive trigger mode is selected
011 Level-sensitive latched mode is selected
110 Level-sensitive FIFO enable mode is selected
Table 67. Gyroscope LPF1 bandwidth selection
FTYPE
[2:0] 12.5 Hz 26 Hz 52 Hz 104 Hz 208 Hz 416 Hz 833 Hz 1.67 kHz 3.33 kHz 6.67 kHz
000 4.2 8.3 16.6 33.0 67.0 136.6 239.2 304.2 328.5 335.5
001 4.2 8.3 16.6 33.0 67.0 130.5 192.4 220.7 229.6 232.0
010 4.2 8.3 16.6 33.0 67.0 120.3 154.2 166.6 170.1 171.1
011 4.2 8.3 16.6 33.0 67.0 137.1 281.8 453.2 559.2 609.0
100 4.2 8.3 16.7 33.0 62.4 86.7 96.6 99.6 NA NA
101 4.2 8.3 16.8 31.0 43.2 48.0 49.4 49.8 NA NA
110 4.1 7.8 13.4 19.0 23.1 24.6 25.0 25.1 NA NA
111 3.9 6.7 9.7 11.5 12.2 12.4 12.5 12.5 NA NA
LSM6DSOX
CTRL6_C (15h)
DS12814 - Rev 3 page 61/199
9.21 CTRL7_G (16h)
Control register 7 (r/w)
Table 68. CTRL7_G register
G_HM_
MODE HP_EN_G HPM1_G HPM0_G 0(1) OIS_ON_EN USR_OFF
_ON_OUT OIS_ON
1. This bit must be set to '0' for the correct operation of the device.
Table 69. CTRL7_G register description
G_HM_MODE
Disables high-performance operating mode for gyroscope. Default: 0
(0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
HP_EN_G Enables gyroscope digital high-pass filter. The filter is enabled only if the gyro is in HP mode. Default value: 0
(0: HPF disabled; 1: HPF enabled)
HPM_G[1:0]
Gyroscope digital HP filter cutoff selection. Default: 00
(00: 16 mHz;
01: 65 mHz;
10: 260 mHz;
11: 1.04 Hz)
OIS_ON_EN(1)
Selects how to enable and disable the OIS chain, after first configuration and enabling through SPI2.
(0: OIS chain is enabled/disabled with SPI2 interface;
1: OIS chain is enabled/disabled with primary interface)
USR_OFF_
ON_ OUT
Enables accelerometer user offset correction block; it's valid for the low-pass path - see
Figure 18. Accelerometer composite filter. Default value: 0
(0: accelerometer user offset correction block bypassed;
1: accelerometer user offset correction block enabled)
OIS_ON(1) Enables/disables the OIS chain from primary interface when the OIS_ON_EN bit is '1'.
(0: OIS disabled; 1: OIS enabled)
1. First, enabling OIS and OIS configurations must be done through SPI2, with OIS_ON_EN and OIS_ON set to '0'.
LSM6DSOX
CTRL7_G (16h)
DS12814 - Rev 3 page 62/199
9.22 CTRL8_XL (17h)
Control register 8 (r/w)
Table 70. CTRL8_XL register
HPCF_
XL_2
HPCF_
XL_1
HPCF_
XL_0
HP_REF_
MODE_XL
FASTSETTL_
MODE_XL
HP_SLOPE_
XL_EN
XL_
FS_MODE
LOW_PASS_
ON_6D
Table 71. CTRL8_XL register description
HPCF_XL_[2:0] Accelerometer LPF2 and HP filter configuration and cutoff setting. Refer to Table 72.
HP_REF_MODE_XL
Enables accelerometer high-pass filter reference mode (valid for high-pass path - HP_SLOPE_XL_EN
bit must be ‘1’). Default value: 0(1)
(0: disabled, 1: enabled)
FASTSETTL_
MODE_XL
Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the second samples after
writing this bit. Active only during device exit from power- down mode. Default value: 0
(0: disabled, 1: enabled)
HP_SLOPE_XL_EN Accelerometer slope filter / high-pass filter selection. Refer to Figure 27.
XL_FS_MODE
Accelerometer full-scale management between UI chain and OIS chain
(0: Old full-scale mode. When XL UI is on, the full scale is the same between UI/OIS and is chosen by
the UI CTRL registers; when XL UI is in PD, the OIS can choose the FS.
1: New full-scale mode. Full scales are independent between the UI/OIS chain but both bound to ±8 g.)
LOW_PASS_ON_6D
LPF2 on 6D function selection. Refer to Figure 27. Default value: 0
(0: ODR/2 low-pass filtered data sent to 6D interrupt function;
1: LPF2 output data sent to 6D interrupt function)
1. When enabled, the first output data have to be discarded.
Table 72. Accelerometer bandwidth configurations
Filter type HP_SLOPE_
XL_EN LPF2_XL_EN HPCF_XL_[2:0] Bandwidth
Low pass 0
0 - ODR/2
1
000 ODR/4
001 ODR/10
010 ODR/20
011 ODR/45
100 ODR/100
101 ODR/200
110 ODR/400
111 ODR/800
LSM6DSOX
CTRL8_XL (17h)
DS12814 - Rev 3 page 63/199
Filter type HP_SLOPE_
XL_EN LPF2_XL_EN HPCF_XL_[2:0] Bandwidth
High pass 1 -
000 SLOPE (ODR/4)
001 ODR/10
010 ODR/20
011 ODR/45
100 ODR/100
101 ODR/200
110 ODR/400
111 ODR/800
Figure 27. Accelerometer block diagram
SLOPE
FILTER
HPCF_XL[2:0]
000
001
010
…
111
SPI /
I2C /
1
0
HP_SLOPE_XL_EN
LPF2_XL_EN
0
1
Digital
HP Filter
HPCF_XL[2:0]
Digital
LP Filter
LPF2
HPCF_XL[2:0]
S/D Tap
6D / 4D
0
1
LOW_PASS_ON_6D
1
0
SLOPE_FDS
Wake-up
Activity /
Inactivity
Free-fall
Advanced
functions
FIFO
USER
OFFSET
0
1
USR_OFF_ON_OUT
USR_OFF_W
OFS_USR[7:0]
1
0
USR_OFF_ON_WU
LPF1
output(1)
MIPI I3CSM
LSM6DSOX
CTRL8_XL (17h)
DS12814 - Rev 3 page 64/199
9.23 CTRL9_XL (18h)
Control register 9 (r/w)
Table 73. CTRL9_XL register
DEN_X DEN_Y DEN_Z DEN_XL_G DEN_XL_EN DEN_LH I3C_disable 0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 74. CTRL9_XL register description
DEN_X DEN value stored in LSB of X-axis. Default value: 1
(0: DEN not stored in X-axis LSB; 1: DEN stored in X-axis LSB)
DEN_Y DEN value stored in LSB of Y-axis. Default value: 1
(0: DEN not stored in Y-axis LSB; 1: DEN stored in Y-axis LSB)
DEN_Z DEN value stored in LSB of Z-axis. Default value: 1
(0: DEN not stored in Z-axis LSB; 1: DEN stored in Z-axis LSB)
DEN_XL_G
DEN stamping sensor selection. Default value: 0
(0: DEN pin info stamped in the gyroscope axis selected by bits [7:5];
1: DEN pin info stamped in the accelerometer axis selected by bits [7:5])
DEN_XL_EN Extends DEN functionality to accelerometer sensor. Default value: 0
(0: disabled; 1: enabled)
DEN_LH DEN active level configuration. Default value: 0
(0: active low; 1: active high)
I3C_disable
Disables MIPI I3CSM communication protocol(1)
(0: SPI, I2C, MIPI I3CSM interfaces enabled (default);
1: MIPI I3CSM interface disabled)
1. It is recommended to set this bit to '1' during the initial device configuration phase, when the I3C interface is not used.
9.24 CTRL10_C (19h)
Control register 10 (r/w)
Table 75. CTRL10_C register
0 0 TIMESTAMP
_EN 0 0 0 0 0
Table 76. CTRL10_C register description
TIMESTAMP_EN
Enables timestamp counter. Default value: 0
(0: disabled; 1: enabled)
The counter is readable in TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and
TIMESTAMP3 (43h).
LSM6DSOX
CTRL9_XL (18h)
DS12814 - Rev 3 page 65/199
9.25 ALL_INT_SRC (1Ah)
Source register for all interrupts (r)
Table 77. ALL_INT_SRC register
TIMESTAMP
_ENDCOUNT 0SLEEP_
CHANGE_IA D6D_IA DOUBLE_
TAP
SINGLE_
TAP WU_IA FF_IA
Table 78. ALL_INT_SRC register description
TIMESTAMP_ENDCOUNT Alerts timestamp overflow within 6.4 ms
SLEEP_CHANGE_IA Detects change event in activity/inactivity status. Default value: 0
(0: change status not detected; 1: change status detected)
D6D_IA Interrupt active for change in position of portrait, landscape, face-up, face-down. Default value: 0
(0: change in position not detected; 1: change in position detected)
DOUBLE_TAP Double-tap event status. Default value: 0
(0:event not detected, 1: event detected)
SINGLE_TAP Single-tap event status. Default value:0
(0: event not detected, 1: event detected)
WU_IA Wake-up event status. Default value: 0
(0: event not detected, 1: event detected)
FF_IA Free-fall event status. Default value: 0
(0: event not detected, 1: event detected)
LSM6DSOX
ALL_INT_SRC (1Ah)
DS12814 - Rev 3 page 66/199
9.26 WAKE_UP_SRC (1Bh)
Wake-up interrupt source register (r)
Table 79. WAKE_UP_SRC register
0SLEEP_
CHANGE_IA FF_IA SLEEP_
STATE WU_IA X_WU Y_WU Z_WU
Table 80. WAKE_UP_SRC register description
SLEEP_CHANGE_IA Detects change event in activity/inactivity status. Default value: 0
(0: change status not detected; 1: change status detected)
FF_IA Free-fall event detection status. Default: 0
(0: free-fall event not detected; 1: free-fall event detected)
SLEEP_STATE Sleep status bit. Default value: 0
(0: Activity status; 1: Inactivity status)
WU_IA Wakeup event detection status. Default value: 0
(0: wakeup event not detected; 1: wakeup event detected.)
X_WU Wakeup event detection status on X-axis. Default value: 0
(0: wakeup event on X-axis not detected; 1: wakeup event on X-axis detected)
Y_WU Wakeup event detection status on Y-axis. Default value: 0
(0: wakeup event on Y-axis not detected; 1: wakeup event on Y-axis detected)
Z_WU Wakeup event detection status on Z-axis. Default value: 0
(0: wakeup event on Z-axis not detected; 1: wakeup event on Z-axis detected)
LSM6DSOX
WAKE_UP_SRC (1Bh)
DS12814 - Rev 3 page 67/199
9.27 TAP_SRC (1Ch)
Tap source register (r).
Table 81. TAP_SRC register
0 TAP_IA SINGLE_
TAP
DOUBLE_
_TAP TAP_SIGN X_TAP Y_TAP Z_TAP
Table 82. TAP_SRC register description
TAP_IA Tap event detection status. Default: 0
(0: tap event not detected; 1: tap event detected)
SINGLE_TAP Single-tap event status. Default value: 0
(0: single tap event not detected; 1: single tap event detected)
DOUBLE_TAP Double-tap event detection status. Default value: 0
(0: double-tap event not detected; 1: double-tap event detected.)
TAP_SIGN
Sign of acceleration detected by tap event. Default: 0
(0: positive sign of acceleration detected by tap event;
1: negative sign of acceleration detected by tap event)
X_TAP Tap event detection status on X-axis. Default value: 0
(0: tap event on X-axis not detected; 1: tap event on X-axis detected)
Y_TAP Tap event detection status on Y-axis. Default value: 0
(0: tap event on Y-axis not detected; 1: tap event on Y-axis detected)
Z_TAP Tap event detection status on Z-axis. Default value: 0
(0: tap event on Z-axis not detected; 1: tap event on Z-axis detected)
LSM6DSOX
TAP_SRC (1Ch)
DS12814 - Rev 3 page 68/199
9.28 D6D_SRC (1Dh)
Portrait, landscape, face-up and face-down source register (r)
Table 83. D6D_SRC register
DEN_DRDY D6D_IA ZH ZL YH YL XH XL
Table 84. D6D_SRC register description
DEN_DRDY DEN data-ready signal. It is set high when data output is related to the data coming from a DEN active
condition.(1)
D6D_IA Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0
(0: change position not detected; 1: change position detected)
ZH Z-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
ZL Z-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
YH Y-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over-threshold) detected)
YL Y-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
XH X-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
XL X-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
1. The DEN data-ready signal can be latched or pulsed depending on the value of the dataready_pulsed bit of the
COUNTER_BDR_REG1 (0Bh) register.
9.29 STATUS_REG (1Eh)
The STATUS_REG register is read by the primary interface SPI/I²C & MIPI I3CSM (r).
Table 85. STATUS_REG register
0 0 0 0 0 TDA GDA XLDA
Table 86. STATUS_REG register description
TDA
Temperature new data available. Default: 0
(0: no set of data is available at temperature sensor output;
1: a new set of data is available at temperature sensor output)
GDA
Gyroscope new data available. Default value: 0
(0: no set of data available at gyroscope output;
1: a new set of data is available at gyroscope output)
XLDA
Accelerometer new data available. Default value: 0
(0: no set of data available at accelerometer output;
1: a new set of data is available at accelerometer output)
LSM6DSOX
D6D_SRC (1Dh)
DS12814 - Rev 3 page 69/199
9.30 OUT_TEMP_L (20h), OUT_TEMP_H (21h)
Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement.
Table 87. OUT_TEMP_L register
Temp7 Temp6 Temp5 Temp4 Temp3 Temp2 Temp1 Temp0
Table 88. OUT_TEMP_H register
Temp15 Temp14 Temp13 Temp12 Temp11 Temp10 Temp9 Temp8
Table 89. OUT_TEMP register description
Temp[15:0] Temperature sensor output data
The value is expressed as two’s complement sign extended on the MSB.
9.31 OUTX_L_G (22h) and OUTX_H_G (23h)
Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the full scale and ODR settings (CTRL2_G (11h)) of gyro user interface.
Table 90. OUTX_L_G register
D7 D6 D5 D4 D3 D2 D1 D0
Table 91. OUTX_H_G register
D15 D14 D13 D12 D11 D10 D9 D8
Table 92. OUTX_H_G register description
D[15:0] Gyro UI chain pitch axis (X) angular rate output value
LSM6DSOX
OUT_TEMP_L (20h), OUT_TEMP_H (21h)
DS12814 - Rev 3 page 70/199
9.32 OUTY_L_G (24h) and OUTY_H_G (25h)
Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the full scale and ODR settings (CTRL2_G (11h)) of the gyro user interface.
Table 93. OUTY_L_G register
D7 D6 D5 D4 D3 D2 D1 D0
Table 94. OUTY_H_G register
D15 D14 D13 D12 D11 D10 D9 D8
Table 95. OUTY_H_G register description
D[15:0] Gyro UI chain roll axis (Y) angular rate output value
9.33 OUTZ_L_G (26h) and OUTZ_H_G (27h)
Angular rate sensor yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the full scale and ODR settings (CTRL2_G (11h)) of the gyro user interface.
Table 96. OUTZ_L_G register
D7 D6 D5 D4 D3 D2 D1 D0
Table 97. OUTZ_H_G register
D15 D14 D13 D12 D11 D10 D9 D8
Table 98. OUTZ_H_G register description
D[15:0] Gyro UI chain yaw axis (Z) angular rate output value
LSM6DSOX
OUTY_L_G (24h) and OUTY_H_G (25h)
DS12814 - Rev 3 page 71/199
9.34 OUTX_L_A (28h) and OUTX_H_A (29h)
Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the full-scale and ODR settings (CTRL1_XL (10h)) of the accelerometer user interface.
Table 99. OUTX_L_A register
D7 D6 D5 D4 D3 D2 D1 D0
Table 100. OUTX_H_A register
D15 D14 D13 D12 D11 D10 D9 D8
Table 101. OUTX_H_A register description
D[15:0] Accelerometer UI chain X-axis linear acceleration output value
9.35 OUTY_L_A (2Ah) and OUTY_H_A (2Bh)
Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the full-scale and ODR settings (CTRL1_XL (10h)) of the accelerometer user interface.
Table 102. OUTY_L_A register
D7 D6 D5 D4 D3 D2 D1 D0
Table 103. OUTY_H_A register
D15 D14 D13 D12 D11 D10 D9 D8
Table 104. OUTY_H_A register description
D[15:0] Accelerometer UI chain Y-axis linear acceleration output value
LSM6DSOX
OUTX_L_A (28h) and OUTX_H_A (29h)
DS12814 - Rev 3 page 72/199
9.36 OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)
Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the full-scale and ODR settings (CTRL1_XL (10h)) of the accelerometer user interface.
Table 105. OUTZ_L_A register
D7 D6 D5 D4 D3 D2 D1 D0
Table 106. OUTZ_H_A register
D15 D14 D13 D12 D11 D10 D9 D8
Table 107. OUTZ_H_A register description
D[15:0] Accelerometer UI chain Z-axis linear acceleration output value
9.37 EMB_FUNC_STATUS_MAINPAGE (35h)
Embedded function status register (r).
Table 108. EMB_FUNC_STATUS_MAINPAGE register
IS_FSM_LC 0 IS_
SIGMOT IS_TILT IS_
STEP_DET 0 0 0
Table 109. EMB_FUNC_STATUS_MAINPAGE register description
IS_FSM_LC Interrupt status bit for FSM long counter timeout interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_SIGMOT Interrupt status bit for significant motion detection
(1: interrupt detected; 0: no interrupt)
IS_TILT Interrupt status bit for tilt detection
(1: interrupt detected; 0: no interrupt)
IS_STEP_DET Interrupt status bit for step detection
(1: interrupt detected; 0: no interrupt)
LSM6DSOX
OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)
DS12814 - Rev 3 page 73/199
9.38 FSM_STATUS_A_MAINPAGE (36h)
Finite State Machine status register (r).
Table 110. FSM_STATUS_A_MAINPAGE register
IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1
Table 111. FSM_STATUS_A_MAINPAGE register description
IS_FSM8 Interrupt status bit for FSM8 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM7 Interrupt status bit for FSM7 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM6 Interrupt status bit for FSM6 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM5 Interrupt status bit for FSM5 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM4 Interrupt status bit for FSM4 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM3 Interrupt status bit for FSM3 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM2 Interrupt status bit for FSM2 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM1 Interrupt status bit for FSM1 interrupt event.
(1: interrupt detected; 0: no interrupt)
LSM6DSOX
FSM_STATUS_A_MAINPAGE (36h)
DS12814 - Rev 3 page 74/199
9.39 FSM_STATUS_B_MAINPAGE (37h)
Finite State Machine status register (r).
Table 112. FSM_STATUS_B_MAINPAGE register
IS_FSM16 IS_FSM15 IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9
Table 113. FSM_STATUS_B_MAINPAGE register description
IS_FSM16 Interrupt status bit for FSM16 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM15 Interrupt status bit for FSM15 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM14 Interrupt status bit for FSM14 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM13 Interrupt status bit for FSM13 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM12 Interrupt status bit for FSM12 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM11 Interrupt status bit for FSM11 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM10 Interrupt status bit for FSM10 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM9 Interrupt status bit for FSM9 interrupt event.
(1: interrupt detected; 0: no interrupt)
LSM6DSOX
FSM_STATUS_B_MAINPAGE (37h)
DS12814 - Rev 3 page 75/199
9.40 MLC_STATUS_MAINPAGE (38h)
Machine Learning Core status register (r).
Table 114. MLC_STATUS _MAINPAGE register
IS_MLC8 IS_MLC7 IS_MLC6 IS_MLC5 IS_MLC4 IS_MLC3 IS_MLC2 IS_MLC1
Table 115. MLC_STATUS_MAINPAGE register description
IS_MLC8 Interrupt status bit for MLC8 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC7 Interrupt status bit for MLC7 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC6 Interrupt status bit for MLC6 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC5 Interrupt status bit for MLC5 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC4 Interrupt status bit for MLC4 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC3 Interrupt status bit for MLC3 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC2 Interrupt status bit for MLC2 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC1 Interrupt status bit for MLC1 interrupt event.
(1: interrupt detected; 0: no interrupt)
9.41 STATUS_MASTER_MAINPAGE (39h)
Sensor hub source register (r).
Table 116. STATUS_MASTER_MAINPAGE register
WR_ONCE_
DONE
SLAVE3_
NACK
SLAVE2_
NACK
SLAVE1_
NACK
SLAVE0_
NACK 0 0 SENS_HUB
_ENDOP
Table 117. STATUS_MASTER_MAINPAGE register description
WR_ONCE_DONE When the bit WRITE_ONCE in MASTER_CONFIG (14h) is configured as 1, this bit is set to 1 when the
write operation on slave 0 has been performed and completed. Default value: 0
SLAVE3_NACK This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0
SLAVE2_NACK This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0
SLAVE1_NACK This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0
SLAVE0_NACK This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0
SENS_HUB_ENDOP
Sensor hub communication status. Default value: 0
(0: sensor hub communication not concluded;
1: sensor hub communication concluded)
LSM6DSOX
MLC_STATUS_MAINPAGE (38h)
DS12814 - Rev 3 page 76/199
9.42 FIFO_STATUS1 (3Ah)
FIFO status register 1 (r)
Table 118. FIFO_STATUS1 register
DIFF_
FIFO_7
DIFF_
FIFO_6
DIFF_
FIFO_5
DIFF_
FIFO_4
DIFF_
FIFO_3
DIFF_
FIFO_2
DIFF_
FIFO_1
DIFF_
FIFO_0
Table 119. FIFO_STATUS1 register description
DIFF_FIFO_[7:0] Number of unread sensor data (TAG + 6 bytes) stored in FIFO
In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh).
9.43 FIFO_STATUS2 (3Bh)
FIFO status register 2 (r)
Table 120. FIFO_STATUS2 register
FIFO_
WTM_IA
FIFO_
OVR_IA
FIFO_
FULL_IA
COUNTER_
BDR_IA
FIFO_OVR_
LATCHED 0(1) DIFF_
FIFO_9
DIFF_
FIFO_8
1. This bit must be set to '0' for the correct operation of the device.
Table 121. FIFO_STATUS2 register description
FIFO_WTM_IA
FIFO watermark status. Default value: 0
(0: FIFO filling is lower than WTM;
1: FIFO filling is equal to or greater than WTM)
Watermark is set through bits WTM[8:0] in FIFO_CTRL2 (08h) and FIFO_CTRL1 (07h).
FIFO_OVR_IA FIFO overrun status. Default value: 0
(0: FIFO is not completely filled; 1: FIFO is completely filled)
FIFO_FULL_IA Smart FIFO full status. Default value: 0
(0: FIFO is not full; 1: FIFO will be full at the next ODR)
COUNTER_BDR_IA
Counter BDR reaches the CNT_BDR_TH_[10:0] threshold set in COUNTER_BDR_REG1 (0Bh) and
COUNTER_BDR_REG2 (0Ch). Default value: 0
This bit is reset when these registers are read.
FIFO_OVR_LATCHED Latched FIFO overrun status. Default value: 0
This bit is reset when this register is read.
DIFF_FIFO_[9:8] Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00
In conjunction with DIFF_FIFO[7:0] in FIFO_STATUS1 (3Ah)
LSM6DSOX
FIFO_STATUS1 (3Ah)
DS12814 - Rev 3 page 77/199
9.44 TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3
(43h)
Timestamp first data output register (r). The value is expressed as a 32-bit word and the bit resolution is 25 µs.
Table 122. TIMESTAMP output registers
D31 D30 D29 D28 D27 D26 D25 D24
D23 D22 D21 D20 D19 D18 D17 D16
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Table 123. TIMESTAMP output register description
D[31:0] Timestamp output registers: 1LSB = 25 µs
9.45 UI_STATUS_REG_OIS (49h)
OIS status register (r).
Table 124. UI_STATUS_REG_OIS register
00000GYRO_
SETTLING GDA XLDA
Table 125. UI_STATUS_REG_OIS register description
GYRO_SETTLING High when the gyroscope output is in the settling phase
GDA Gyroscope data available (reset when one of the high parts of the output data is read)
XLDA Accelerometer data available (reset when one of the high parts of the output data is read)
LSM6DSOX
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h),
and TIMESTAMP3 (43h)
DS12814 - Rev 3 page 78/199
9.46 UI_OUTX_L_G_OIS (4Ah) and UI_OUTX_H_G_OIS (4Bh)
Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the gyroscope full scale and ODR (6.66 kHz) settings of the OIS gyro.
Table 126. UI_OUTX_L_G_OIS register
D7 D6 D5 D4 D3 D2 D1 D0
Table 127. UI_OUTX_H_G_OIS register
D15 D14 D13 D12 D11 D10 D9 D8
Table 128. UI_OUTX_H_G_OIS register description
D[15:0] Gyro OIS chain pitch axis (X) angular rate output value
9.47 UI_OUTY_L_G_OIS (4Ch) and UI_OUTY_H_G_OIS (4Dh)
Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the gyroscope full scale and ODR (6.66 kHz) settings of the OIS gyro.
Table 129. UI_OUTY_L_G_OIS register
D7 D6 D5 D4 D3 D2 D1 D0
Table 130. UI_OUTY_H_G_OIS register
D15 D14 D13 D12 D11 D10 D9 D8
Table 131. UI_OUTY_H_G_OIS description
D[15:0] Gyro OIS chain roll axis (Y) angular rate output value
LSM6DSOX
UI_OUTX_L_G_OIS (4Ah) and UI_OUTX_H_G_OIS (4Bh)
DS12814 - Rev 3 page 79/199
9.48 UI_OUTZ_L_G_OIS (4Eh) and UI_OUTZ_H_G_OIS (4Fh)
Angular rate sensor yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the gyroscope full scale and ODR (6.66 kHz) settings of the OIS gyro.
Table 132. UI_OUTZ_L_G_OIS register
D7 D6 D5 D4 D3 D2 D1 D0
Table 133. UI_OUTZ_H_G_OIS register
D15 D14 D13 D12 D11 D10 D9 D8
Table 134. UI_OUTZ_H_G_OIS register description
D[15:0] Gyro OIS chain yaw axis (Z) angular rate output value
9.49 UI_OUTX_L_A_OIS (50h) and UI_OUTX_H_A_OIS (51h)
Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the accelerometer full scale and ODR (6.66 kHz) settings of the OIS accelerometer.
Table 135. UI_OUTX_L_A_OIS register
D7 D6 D5 D4 D3 D2 D1 D0
Table 136. UI_OUTX_H_A_OIS register
D15 D14 D13 D12 D11 D10 D9 D8
Table 137. UI_OUTX_H_A_OIS register description
D[15:0] Accelerometer OIS chain X-axis linear acceleration output value
LSM6DSOX
UI_OUTZ_L_G_OIS (4Eh) and UI_OUTZ_H_G_OIS (4Fh)
DS12814 - Rev 3 page 80/199
9.50 UI_OUTY_L_A_OIS (52h) and UI_OUTY_H_A_OIS (53h)
Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the accelerometer full scale and ODR (6.66 kHz) settings of the OIS accelerometer.
Table 138. UI_OUTY_L_A_OIS register
D7 D6 D5 D4 D3 D2 D1 D0
Table 139. UI_OUTY_H_A_OIS register
D15 D14 D13 D12 D11 D10 D9 D8
Table 140. UI_OUTY_H_A_OIS register description
D[15:0] Accelerometer OIS chain Y-axis linear acceleration output value
9.51 UI_OUTZ_L_A_OIS (54h) and UI_OUTZ_H_A_OIS (55h)
Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the accelerometer full scale and ODR (6.66 kHz) settings of the OIS accelerometer.
Table 141. UI_OUTZ_L_A_OIS register
D7 D6 D5 D4 D3 D2 D1 D0
Table 142. UI_OUTZ_H_A_OIS register
D15 D14 D13 D12 D11 D10 D9 D8
Table 143. UI_OUTZ_H_A_OIS register description
D[15:0] Accelerometer OIS chain Z-axis linear acceleration output value
LSM6DSOX
UI_OUTY_L_A_OIS (52h) and UI_OUTY_H_A_OIS (53h)
DS12814 - Rev 3 page 81/199
9.52 TAP_CFG0 (56h)
Activity/inactivity functions, configuration of filtering, and tap recognition functions (r/w).
Table 144. TAP_CFG0 register
0INT_CLR_
ON_READ
SLEEP_
STATUS_
ON_INT
SLOPE_
FDS TAP_X_EN TAP_Y_EN TAP_Z_EN LIR
Table 145. TAP_CFG0 register description
INT_CLR_ON_READ
This bit allows immediately clearing the latched interrupts of an event detection upon the read of
the corresponding status register. It must be set to 1 together with LIR. Default value: 0
(0: latched interrupt signal cleared at the end of the ODR period;
1: latched interrupt signal immediately cleared)
SLEEP_STATUS_ON_INT
Activity/inactivity interrupt mode configuration.
If INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits are enabled, drives the sleep status or
sleep change on the INT pins. Default value: 0
(0: sleep change notification on INT pins; 1: sleep status reported on INT pins)
SLOPE_FDS HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions. Default value: 0 (
0: SLOPE filter applied; 1: HPF applied)
TAP_X_EN Enable X direction in tap recognition. Default value: 0
(0: X direction disabled; 1: X direction enabled)
TAP_Y_EN Enable Y direction in tap recognition. Default value: 0
(0: Y direction disabled; 1: Y direction enabled)
TAP_Z_EN Enable Z direction in tap recognition. Default value: 0
(0: Z direction disabled; 1: Z direction enabled)
LIR Latched Interrupt. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
LSM6DSOX
TAP_CFG0 (56h)
DS12814 - Rev 3 page 82/199
9.53 TAP_CFG1 (57h)
Tap configuration register (r/w)
Table 146. TAP_CFG1 register
TAP_
PRIORITY_2
TAP_
PRIORITY_1
TAP_
PRIORITY_0
TAP_
THS_X_4
TAP_
THS_X_3
TAP_
THS_X_2
TAP_
THS_X_1
TAP_
THS_X_0
Table 147. TAP_CFG1 register description
TAP_PRIORITY_[2:0] Selection of axis priority for TAP detection (see Table 148)
TAP_THS_X_[4:0] X-axis tap recognition threshold. Default value: 0
1 LSB = FS_XL / (25)
Table 148. TAP priority decoding
TAP_PRIORITY_[2:0] Max. priority Mid. priority Min. priority
000 X Y Z
001 Y X Z
010 X Z Y
011 Z Y X
100 X Y Z
101 Y Z X
110 Z X Y
111 Z Y X
9.54 TAP_CFG2 (58h)
Enables interrupt and inactivity functions, and tap recognition functions (r/w).
Table 149. TAP_CFG2 register
INTERRUPTS
_ENABLE INACT_EN1 INACT_EN0 TAP_
THS_Y_4
TAP_
THS_Y_3
TAP_
THS_Y_2
TAP_
THS_Y_1
TAP_
THS_Y_0
Table 150. TAP_CFG2 register description
INTERRUPTS_ENABLE Enable basic interrupts (6D/4D, free-fall, wake-up, tap, inactivity). Default value: 0
(0: interrupt disabled; 1: interrupt enabled)
INACT_EN[1:0]
Enable activity/inactivity (sleep) function. Default value: 00
(00: stationary/motion-only interrupts generated, XL and gyro do not change;
01: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro does not change;
10: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to sleep mode;
11: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to power-down mode)
TAP_THS_Y_[4:0] Y-axis tap recognition threshold. Default value: 0
1 LSB = FS_XL / (25)
LSM6DSOX
TAP_CFG1 (57h)
DS12814 - Rev 3 page 83/199
9.55 TAP_THS_6D (59h)
Portrait/landscape position and tap function threshold register (r/w).
Table 151. TAP_THS_6D register
D4D_EN SIXD_THS1 SIXD_THS0 TAP_
THS_Z_4
TAP_
THS_Z_3
TAP_
THS_Z_2
TAP_
THS_Z_1
TAP_
THS_Z_0
Table 152. TAP_THS_6D register description
D4D_EN
4D orientation detection enable. Z-axis position detection is disabled.
Default value: 0
(0: enabled; 1: disabled)
SIXD_THS[1:0] Threshold for 4D/6D function. Default value: 00
For details, refer to Table 153.
TAP_THS_Z_[4:0] Z-axis recognition threshold. Default value: 0
1 LSB = FS_XL / (25)
Table 153. Threshold for D4D/D6D function
SIXD_THS[1:0] Threshold value
00 80 degrees
01 70 degrees
10 60 degrees
11 50 degrees
LSM6DSOX
TAP_THS_6D (59h)
DS12814 - Rev 3 page 84/199
9.56 INT_DUR2 (5Ah)
Tap recognition function setting register (r/w).
Table 154. INT_DUR2 register
DUR3 DUR2 DUR1 DUR0 QUIET1 QUIET0 SHOCK1 SHOCK0
Table 155. INT_DUR2 register description
DUR[3:0]
Duration of maximum time gap for double tap recognition. Default: 0000
When double tap recognition is enabled, this register expresses the maximum time between two consecutive
detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to
16*ODR_XL time. If the DUR[3:0] bits are set to a different value, 1LSB corresponds to 32*ODR_XL time.
QUIET[1:0]
Expected quiet time after a tap detection. Default value: 00
Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default
value of these bits is 00b which corresponds to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
value, 1LSB corresponds to 4*ODR_XL time.
SHOCK[1:0]
Maximum duration of overthreshold event. Default value: 00
Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event.
The default value of these bits is 00b which corresponds to 4*ODR_XL time. If the SHOCK[1:0] bits are set to a
different value, 1LSB corresponds to 8*ODR_XL time.
9.57 WAKE_UP_THS (5Bh)
Single/double-tap selection and wake-up configuration (r/w)
Table 156. WAKE_UP_THS register
SINGLE_
DOUBLE_TAP
USR_OFF
_ON_WU WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0
Table 157. WAKE_UP_THS register description
SINGLE_DOUBLE_TAP
Single/double-tap event enable. Default value: 0
(0: only single-tap event enabled;
1: both single and double-tap events enabled)
USR_OFF_ON_WU Drives the low-pass filtered data with user offset correction (instead of high-pass filtered data) to the
wakeup function.
WK_THS[5:0] Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in WAKE_UP_DUR (5Ch).
Default value: 000000
LSM6DSOX
INT_DUR2 (5Ah)
DS12814 - Rev 3 page 85/199
9.58 WAKE_UP_DUR (5Ch)
Free-fall, wakeup and sleep mode functions duration setting register (r/w)
Table 158. WAKE_UP_DUR register
FF_DUR5 WAKE_DUR1 WAKE_DUR0 WAKE_THS_W SLEEP_DUR3 SLEEP_DUR2 SLEEP_DUR1 SLEEP_DUR0
Table 159. WAKE_UP_DUR register description
FF_DUR5
Free fall duration event. Default: 0
For the complete configuration of the free-fall duration, refer to FF_DUR[4:0] in the FREE_FALL (5Dh)
configuration.
1 LSB = 1 ODR_time
WAKE_DUR[1:0] Wake up duration event. Default: 00
1LSB = 1 ODR_time
WAKE_THS_W
Weight of 1 LSB of wakeup threshold. Default: 0
(0: 1 LSB = FS_XL / (26);
1: 1 LSB = FS_XL / (28) )
SLEEP_DUR[3:0] Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR)
1 LSB = 512 ODR
LSM6DSOX
WAKE_UP_DUR (5Ch)
DS12814 - Rev 3 page 86/199
9.59 FREE_FALL (5Dh)
Free-fall function duration setting register (r/w).
Table 160. FREE_FALL register
FF_DUR4 FF_DUR3 FF_DUR2 FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0
Table 161. FREE_FALL register description
FF_DUR[4:0]
Free-fall duration event. Default: 0
For the complete configuration of the free fall duration, refer to FF_DUR5 in the WAKE_UP_DUR (5Ch)
configuration.
FF_THS[2:0] Free fall threshold setting. Default: 000
For details refer to Table 162.
Table 162. Threshold for free-fall function
FF_THS[2:0] Threshold value
000 156 mg
001 219 mg
010 250 mg
011 312 mg
100 344 mg
101 406 mg
110 469 mg
111 500 mg
LSM6DSOX
FREE_FALL (5Dh)
DS12814 - Rev 3 page 87/199
9.60 MD1_CFG (5Eh)
Functions routing on INT1 register (r/w)
Table 163. MD1_CFG register
INT1_
SLEEP_
CHANGE
INT1_
SINGLE_
TAP
INT1_WU INT1_FF
INT1_
DOUBLE_
TAP
INT1_6D INT1_
EMB_FUNC
INT1_
SHUB
Table 164. MD1_CFG register description
INT1_SLEEP_CHANGE(1)
Routing of activity/inactivity recognition event on INT1. Default: 0
(0: routing of activity/inactivity event on INT1 disabled;
1: routing of activity/inactivity event on INT1 enabled)
INT1_SINGLE_TAP
Routing of single-tap recognition event on INT1. Default: 0
(0: routing of single-tap event on INT1 disabled;
1: routing of single-tap event on INT1 enabled)
INT1_WU
Routing of wakeup event on INT1. Default value: 0
(0: routing of wakeup event on INT1 disabled;
1: routing of wakeup event on INT1 enabled)
INT1_FF
Routing of free-fall event on INT1. Default value: 0
(0: routing of free-fall event on INT1 disabled;
1: routing of free-fall event on INT1 enabled)
INT1_DOUBLE_TAP
Routing of tap event on INT1. Default value: 0
(0: routing of double-tap event on INT1 disabled;
1: routing of double-tap event on INT1 enabled)
INT1_6D
Routing of 6D event on INT1. Default value: 0
(0: routing of 6D event on INT1 disabled;
1: routing of 6D event on INT1 enabled)
INT1_EMB_FUNC
Routing of embedded functions event on INT1. Default value: 0
(0: routing of embedded functions event on INT1 disabled;
1: routing embedded functions event on INT1 enabled)
INT1_SHUB
Routing of sensor hub communication concluded event on INT1. Default value: 0
(0: routing of sensor hub communication concluded event on INT1 disabled;
1: routing of sensor hub communication concluded event on INT1 enabled)
1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in TAP_CFG0
(56h) register.
LSM6DSOX
MD1_CFG (5Eh)
DS12814 - Rev 3 page 88/199
9.61 MD2_CFG (5Fh)
Functions routing on INT2 register (r/w)
Table 165. MD2_CFG register
INT2_
SLEEP_
CHANGE
INT2_
SINGLE_
TAP
INT2_WU INT2_FF
INT2_
DOUBLE_
TAP
INT2_6D INT2_
EMB_FUNC
INT2_
TIMESTAMP
Table 166. MD2_CFG register description
INT2_SLEEP_CHANGE(1)
Routing of activity/inactivity recognition event on INT2. Default: 0
(0: routing of activity/inactivity event on INT2 disabled;
1: routing of activity/inactivity event on INT2 enabled)
INT2_SINGLE_TAP
Single-tap recognition routing on INT2. Default: 0
(0: routing of single-tap event on INT2 disabled;
1: routing of single-tap event on INT2 enabled)
INT2_WU
Routing of wakeup event on INT2. Default value: 0
(0: routing of wakeup event on INT2 disabled;
1: routing of wake-up event on INT2 enabled)
INT2_FF
Routing of free-fall event on INT2. Default value: 0
(0: routing of free-fall event on INT2 disabled;
1: routing of free-fall event on INT2 enabled)
INT2_DOUBLE_TAP
Routing of tap event on INT2. Default value: 0
(0: routing of double-tap event on INT2 disabled;
1: routing of double-tap event on INT2 enabled)
INT2_6D
Routing of 6D event on INT2. Default value: 0
(0: routing of 6D event on INT2 disabled;
1: routing of 6D event on INT2 enabled)
INT2_EMB_FUNC
Routing of embedded functions event on INT2. Default value: 0
(0: routing of embedded functions event on INT2 disabled;
1: routing embedded functions event on INT2 enabled)
INT2_TIMESTAMP Enables routing on INT2 pin of the alert for timestamp overflow within 6.4 ms.
1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in TAP_CFG0
(56h) register.
LSM6DSOX
MD2_CFG (5Fh)
DS12814 - Rev 3 page 89/199
9.62 S4S_ST_CMD_CODE (60h)
S4S Master command register (r/w)
Table 167. S4S_ST_CMD_CODE register
ST_CMD_
CODE7
ST_CMD_
CODE6
ST_CMD_
CODE5
ST_CMD_
CODE4
ST_CMD_
CODE3
ST_CMD_
CODE2
ST_CMD_
CODE1
ST_CMD_
CODE0
Table 168. S4S_ST_CMD_CODE register description
ST_CMD_CODE[7:0] Master command code used for S4S. Default value: 0
9.63 S4S_DT_REG (61h)
S4S DT register (r/w)
Table 169. S4S_DT_REG register
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
Table 170. S4S_DT_REG register description
DT[7:0] DT used for S4S. Default value: 0
9.64 I3C_BUS_AVB (62h)
I3C_BUS_AVB register (r/w)
Table 171. I3C_BUS_AVB register
0(1) 0(1) 0(1) I3C_Bus_
Avb_Sel1
I3C_Bus_
Avb_Sel0 0(1) 0(1) PD_DIS_
INT1
1. This bit must be set to '0' for the correct operation of the device.
Table 172. I3C_BUS_AVB register description
PD_DIS_INT1
This bit allows disabling the INT1 pull-down.
(0: Pull-down on INT1 enabled (pull-down is effectively connected only when no interrupts are routed
to the INT1 pin or when I3C dynamic address is assigned);
1: Pull-down on INT1 disabled (pull-down not connected)
I3C_Bus_Avb_Sel[1:0]
These bits are used to select the bus available time when I3C IBI is used.
Default value: 00
(00: bus available time equal to 50 µsec (default);
01: bus available time equal to 2 µsec;
10: bus available time equal to 1 msec;
11: bus available time equal to 25 msec)
LSM6DSOX
S4S_ST_CMD_CODE (60h)
DS12814 - Rev 3 page 90/199
9.65 INTERNAL_FREQ_FINE (63h)
Internal frequency register (r)
Table 173. INTERNAL_FREQ_FINE register
FREQ_
FINE7
FREQ_
FINE6
FREQ_
FINE5
FREQ_
FINE4
FREQ_
FINE3
FREQ_
FINE2
FREQ_
FINE1
FREQ_
FINE0
Table 174. INTERNAL_FREQ_FINE register description
FREQ_FINE[7:0] Difference in percentage of the effective ODR (and Timestamp Rate) with respect to the typical.
Step: 0.15%. 8-bit format, 2's complement.
9.66 UI_INT_OIS (6Fh)
OIS interrupt configuration register and accelerometer self-test enable setting. The primary interface can write this
register when the OIS_CTRL_FROM_UI bit in the FUNC_CFG_ACCESS (01h) register is equal to 1 (Primary IF
Full control mode); this register is read-only when the OIS_CTRL_FROM_UI bit is equal to 0 (SPI2 Full control
mode) and shows the content of the SPI2_INT_OIS (6Fh) register.
Table 175. UI_INT_OIS register
INT2_
DRDY_OIS LVL2_OIS DEN_LH_OIS 0 SPI2_
READ_EN 0 0 0
Table 176. UI_INT_OIS register description
INT2_DRDY_OIS Enables OIS chain DRDY on INT2 pin. This setting has priority over all other INT2 settings.
LVL2_OIS Enables level-sensitive latched mode on the OIS chain. Default value: 0
DEN_LH_OIS
Indicates polarity of DEN signal on OIS chain
(0: DEN pin is active-low;
1: DEN pin is active-high)
SPI2_READ_EN
In Primary IF full control mode, enables Auxiliary SPI for reading OIS data in registers
SPI2_OUTX_L_G_OIS (22h) and SPI2_OUTX_H_G_OIS (23h) through SPI2_OUTZ_L_A_OIS (2Ch) and
SPI2_OUTZ_H_A_OIS (2Dh). Default value: 0
(0: OIS data reading from Auxiliary SPI disabled;
1: OIS data reading from Auxiliary SPI enabled)
LSM6DSOX
INTERNAL_FREQ_FINE (63h)
DS12814 - Rev 3 page 91/199
9.67 UI_CTRL1_OIS (70h)
OIS configuration register. The primary interface can write this register when the OIS_CTRL_FROM_UI bit in the
FUNC_CFG_ACCESS (01h) register is equal to 1 (Primary IF Full control mode); this register is read-only when
the OIS_CTRL_FROM_UI bit is equal to 0 (SPI2 Full control mode) and shows the content of the
SPI2_CTRL1_OIS (70h) register.
Table 177. UI_CTRL1_OIS register
0 LVL1_OIS SIM_OIS Mode4_EN FS1_G_OIS FS0_G_OIS FS_125_OIS OIS_EN_SPI2
Table 178. UI_CTRL1_OIS register description
LVL1_OIS Enables level-sensitive trigger mode on OIS chain. Default value: 0
SIM_OIS
SPI2 3- or 4-wire interface. Default value: 0
(0: 4-wire SPI2;
1: 3-wire SPI2)
Mode4_EN
Enables accelerometer OIS chain. When the OIS_CTRL_FROM_UI bit in the FUNC_CFG_ACCESS (01h)
register is equal to 1 (Primary IF Full control mode enabled), the accelerometer OIS outputs are available
through the primary interface in registers UI_OUTX_L_A_OIS (50h) and UI_OUTX_H_A_OIS (51h) through
UI_OUTZ_L_A_OIS (54h) and UI_OUTZ_H_A_OIS (55h) and UI_STATUS_REG_OIS (49h).
Note: OIS_EN_SPI2 must be enabled (i.e. set to ‘1’) to enable also the XL OIS chain.
FS[1:0]_G_OIS
Selects gyroscope OIS chain full-scale
(00: 250 dps;
01: 500 dps;
10: 1000 dps;
11: 2000 dps)
FS_125_OIS
Selects gyroscope OIS chain full-scale 125 dps
(0: FS selected through bits FS[1:0]_OIS_G;
1: 125 dps)
OIS_EN_SPI2
Enables OIS chain data processing for gyro in Mode 3 and Mode 4 (mode4_en = 1) and accelerometer data
in and Mode 4 (mode4_en = 1).
When the OIS_CTRL_FROM_UI bit in FUNC_CFG_ACCESS (01h) register is equal to 1 (Primary IF Full
control mode enabled), the gyroscope OIS outputs are available through the primary interface in registers
UI_OUTX_L_G_OIS (4Ah) and UI_OUTX_H_G_OIS (4Bh) through UI_OUTZ_L_G_OIS (4Eh) and
UI_OUTZ_H_G_OIS (4Fh)and UI_STATUS_REG_OIS (49h), and LPF1 is dedicated to this chain.
DEN mode selection can be done using the LVL1_OIS bit of register UI_CTRL1_OIS (70h) and the LVL2_OIS bit
of register UI_INT_OIS (6Fh).
DEN mode on the OIS path is active in the gyroscope only.
Table 179. DEN mode selection
LVL1_OIS, LVL2_OIS DEN mode
10 Level-sensitive trigger mode is selected
11 Level-sensitive latched mode is selected
LSM6DSOX
UI_CTRL1_OIS (70h)
DS12814 - Rev 3 page 92/199
9.68 UI_CTRL2_OIS (71h)
OIS configuration register. The primary interface can write this register when the OIS_CTRL_FROM_UI bit in the
FUNC_CFG_ACCESS (01h) register is equal to 1 (Primary IF Full control mode); this register is read-only when
the OIS_CTRL_FROM_UI bit is equal to 0 (SPI2 Full control mode) and shows the content of the
SPI2_CTRL2_OIS (71h) register.
Table 180. UI_CTRL2_OIS register
- - HPM1_OIS HPM0_OIS 0 FTYPE_1_OIS FTYPE_0_OIS HP_EN_OIS
Table 181. UI_CTRL2_OIS register description
HPM[1:0]_OIS
Selects gyroscope OIS chain digital high-pass filter cutoff. Default value: 00
(00: 16 mHz;
01: 65 mHz;
10: 260 mHz;
11: 1.04 Hz)
FTYPE_[1:0]_OIS Selects gyroscope digital LPF1 filter bandwidth. Table 182 shows cutoff and phase values obtained with all
configurations.
HP_EN_OIS Enables gyroscope OIS chain digital high-pass filter.
Table 182. Gyroscope OIS chain digital LPF1 filter bandwidth selection
FTYPE_[1:0]_OIS Cutoff [Hz] Phase @ 20 Hz [°]
00 335.5 -6.69
01 232.0 -8.78
10 171.1 -11.18
11 609.0 -4.91
LSM6DSOX
UI_CTRL2_OIS (71h)
DS12814 - Rev 3 page 93/199
9.69 UI_CTRL3_OIS (72h)
OIS configuration register. The primary interface can write this register when the OIS_CTRL_FROM_UI bit in the
FUNC_CFG_ACCESS (01h) register is equal to 1 (Primary IF Full control mode); this register is read-only when
the OIS_CTRL_FROM_UI bit is equal to 0 (SPI2 Full control mode) and shows the content of the
SPI2_CTRL3_OIS (72h) register.
Table 183. UI_CTRL3_OIS register
FS1_XL_OIS FS0_XL_OIS FILTER_XL_
CONF_OIS_2
FILTER_XL_
CONF_OIS_1
FILTER_XL_
CONF_OIS_0 0 0 ST_OIS_
CLAMPDIS
Table 184. UI_CTRL3_OIS register description
FS[1:0]_XL_OIS Selects accelerometer OIS channel full-scale. See Table 185.
FILTER_XL_CONF_OIS_[2:0] Selects accelerometer OIS channel bandwidth. See Table 186.
ST_OIS_CLAMPDIS
Disables OIS chain clamp
(0: All OIS chain outputs = 8000h during self-test;
1: OIS chain self-test outputs as shown in Table 187.
Table 185. Accelerometer OIS channel full-scale selection
FS[1:0]_XL_OIS
XL_FS_MODE = ‘0’ XL_FS_MODE = ‘1’
XL UI ON XL UI PD -
00 (default) Full-scale selected from user interface 2 g2 g
01 16 g2 g
10 4 g4 g
11 8 g8 g
Note: The XL_FS_MODE bit is in CTRL8_XL (17h).
Note: When the accelerometer full-scale value is selected only from the UI side it is readable also from the OIS side.
Table 186. Accelerometer OIS channel bandwidth and phase
FILTER_XL_CONF_OIS[2:0] Typ. overall bandwidth [Hz] Typ. overall phase [°]
000 289 -5.72 @ 20 Hz
001 258 -6.80 @ 20 Hz
010 120 -13.2 @ 20 Hz
011 65.1 -21.5 @ 20 Hz
100 33.2 -19.1 @ 10 Hz
101 16.6 -33.5 @ 10 Hz
110 8.30 -26.7 @ 4 Hz
111 4.14 -26.2 @ 2 Hz
LSM6DSOX
UI_CTRL3_OIS (72h)
DS12814 - Rev 3 page 94/199
Table 187. Self-test nominal output variation
Full scale Ouput variation [dps]
2000 400
1000 200
500 100
250 50
125 25
LSM6DSOX
UI_CTRL3_OIS (72h)
DS12814 - Rev 3 page 95/199
9.70 X_OFS_USR (73h)
Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is
internally subtracted from the acceleration value measured on the X-axis.
Table 188. X_OFS_USR register
X_OFS_
USR_7
X_OFS_
USR_6
X_OFS_
USR_5
X_OFS_
USR_4
X_OFS_
USR_3
X_OFS_
USR_2
X_OFS_
USR_1
X_OFS_
USR_0
Table 189. X_OFS_USR register description
X_OFS_USR_[7:0] Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on
USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127 127].
9.71 Y_OFS_USR (74h)
Accelerometer Y-axis user offset correction (r/w). The offset value set in the Y_OFS_USR offset register is
internally subtracted from the acceleration value measured on the Y-axis.
Table 190. Y_OFS_USR register
Y_OFS_
USR_7
Y_OFS_
USR_6
Y_OFS_
USR_5
Y_OFS_
USR_4
Y_OFS_
USR_3
Y_OFS_
USR_2
Y_OFS_
USR_1
Y_OFS_
USR_0
Table 191. Y_OFS_USR register description
Y_OFS_USR_[7:0]
Accelerometer Y-axis user offset calibration expressed in 2’s complement, weight depends on
USR_OFF_W in CTRL6_C (15h). The value must be in the range
[-127, +127].
9.72 Z_OFS_USR (75h)
Accelerometer Z-axis user offset correction (r/w). The offset value set in the Z_OFS_USR offset register is
internally subtracted from the acceleration value measured on the Z-axis.
Table 192. Z_OFS_USR register
Z_OFS_
USR_7
Z_OFS_
USR_6
Z_OFS_
USR_5
Z_OFS_
USR_4
Z_OFS_
USR_3
Z_OFS_
USR_2
Z_OFS_
USR_1
Z_OFS_
USR_0
Table 193. Z_OFS_USR register description
Z_OFS_USR_[7:0] Accelerometer Z-axis user offset calibration expressed in 2’s complement, weight depends on
USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127, +127].
LSM6DSOX
X_OFS_USR (73h)
DS12814 - Rev 3 page 96/199
9.73 FIFO_DATA_OUT_TAG (78h)
FIFO tag register (r)
Table 194. FIFO_DATA_OUT_TAG register
TAG_
SENSOR_4
TAG_
SENSOR_3
TAG_
SENSOR_2
TAG_
SENSOR_1
TAG_
SENSOR_0 TAG_CNT_1 TAG_CNT_0 TAG_
PARITY
Table 195. FIFO_DATA_OUT_TAG register description
TAG_SENSOR_[4:0]
FIFO tag. Identifies the sensor in:
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah), FIFO_DATA_OUT_Y_L (7Bh) and
FIFO_DATA_OUT_Y_H (7Ch), and FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)
For details, refer to Table 196
TAG_CNT_[1:0] 2-bit counter which identifies sensor time slot
TAG_PARITY Parity check of TAG content
Table 196. FIFO tag
TAG_SENSOR_[4:0] Sensor name
0x01 Gyroscope NC
0x02 Accelerometer NC
0x03 Temperature
0x04 Timestamp
0x05 CFG_Change
0x06 Accelerometer NC_T_2
0x07 Accelerometer NC_T_1
0x08 Accelerometer 2xC
0x09 Accelerometer 3xC
0x0A Gyroscope NC_T_2
0x0B Gyroscope NC_T_1
0x0C Gyroscope 2xC
0x0D Gyroscope 3xC
0x0E Sensor Hub Slave 0
0x0F Sensor Hub Slave 1
0x10 Sensor Hub Slave 2
0x11 Sensor Hub Slave 3
0x12 Step Counter
0x19 Sensor Hub Nack
LSM6DSOX
FIFO_DATA_OUT_TAG (78h)
DS12814 - Rev 3 page 97/199
9.74 FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)
FIFO data output X (r)
Table 197. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Table 198. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description
D[15:0] FIFO X-axis output
9.75 FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch)
FIFO data output Y (r)
Table 199. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Table 200. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description
D[15:0] FIFO Y-axis output
9.76 FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)
FIFO data output Z (r)
Table 201. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Table 202. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description
D[15:0] FIFO Z-axis output
LSM6DSOX
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)
DS12814 - Rev 3 page 98/199
10 SPI2 register mapping
The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding
addresses.
All these registers are accessible from Auxiliary SPI interface only.
Table 203. SPI2 register address map
Name Type
Register address
Default Comment
Hex Binary
SPI2_WHO_AM_I R 0F 00001111 output
SPI2_STATUS_REG_OIS R 1E 00011110 output
SPI2_OUT_TEMP_L R 20 00100000 output
SPI2_OUT_TEMP_H R 21 00100001 output
SPI2_OUTX_L_G_OIS R 22 00100010 output
SPI2_OUTX_H_G_OIS R 23 00100011 output
SPI2_OUTY_L_G_OIS R 24 00100100 output
SPI2_OUTY_H_G_OIS R 25 00100101 output
SPI2_OUTZ_L_G_OIS R 26 00100110 output
SPI2_OUTZ_H_G_OIS R 27 00100111 output
SPI2_OUTX_L_A_OIS R 28 00101000 output
SPI2_OUTX_H_A_OIS R 29 00101001 output
SPI2_OUTY_L_A_OIS R 2A 00101010 output
SPI2_OUTY_H_A_OIS R 2B 00101011 output
SPI2_OUTZ_L_A_OIS R 2C 00101100 output
SPI2_OUTZ_H_A_OIS R 2D 00101101 output
SPI2_INT_OIS RW (SPI2 full control mode)
R (Primary IF full control mode 6F 01101111 00000000
SPI2_CTRL1_OIS RW (SPI2 full control mode)
R (Primary IF full control mode 70 01110000 00000000
SPI2_CTRL2_OIS RW (SPI2 full control mode)
R (Primary IF full control mode 71 01110001 00000000
SPI2_CTRL3_OIS RW (SPI2 full control mode)
R (Primary IF full control mode 72 01110010 00000000
LSM6DSOX
SPI2 register mapping
DS12814 - Rev 3 page 99/199
11 SPI2 register description
11.1 SPI2_WHO_AM_I (0Fh)
WHO_AM_I register (r). This is a read-only register. Its value is fixed at 6Ch.
Table 204. SPI2_WhoAmI register
01101100
11.2 SPI2_STATUS_REG_OIS (1Eh)
The SPI2_STATUS_REG_OIS register is read by the Auxiliary SPI (r).
Table 205. SPI_STATUS_REG_OIS register
0 0 0 0 0 GYRO_
SETTLING GDA XLDA
Table 206. SPI_STATUS_REG_OIS description
GYRO_SETTLING High when the gyroscope output is in the settling phase
GDA Gyroscope data available (reset when one of the high parts of the output data is read)
XLDA Accelerometer data available (reset when one of the high parts of the output data is read)
11.3 SPI2_OUT_TEMP_L (20h) and SPI2_OUT_TEMP_H (21h)
Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement.
Table 207. SPI2_OUT_TEMP_L register
Temp7 Temp6 Temp5 Temp4 Temp3 Temp2 Temp1 Temp0
Table 208. SPI2_OUT_TEMP_H register
Temp15 Temp14 Temp13 Temp12 Temp11 Temp10 Temp9 Temp8
Table 209. SPI2_OUT_TEMP register description
Temp[15:0] Temperature sensor output data
The value is expressed as two’s complement sign extended on the MSB.
LSM6DSOX
SPI2 register description
DS12814 - Rev 3 page 100/199
11.4 SPI2_OUTX_L_G_OIS (22h) and SPI2_OUTX_H_G_OIS (23h)
Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the gyroscope full scale and ODR (6.66 kHz) settings of the OIS gyro.
Table 210. SPI2_OUTX_L_G_OIS register
D7 D6 D5 D4 D3 D2 D1 D0
Table 211. SPI2_OUTX_H_G_OIS register
D15 D14 D13 D12 D11 D10 D9 D8
Table 212. SPI2_OUTX_H_G_OIS register description
D[15:0] Gyro OIS chain pitch axis (X) angular rate output value
11.5 SPI2_OUTY_L_G_OIS (24h) and SPI2_OUTY_H_G_OIS (25h)
Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the gyroscope full scale and ODR (6.66 kHz) settings of the OIS gyro.
Table 213. SPI2_OUTY_L_G_OIS register
D7 D6 D5 D4 D3 D2 D1 D0
Table 214. SPI2_OUTY_H_G_OIS register
D15 D14 D13 D12 D11 D10 D9 D8
Table 215. SPI2_OUTY_H_G_OIS register description
D[15:0] Gyro OIS chain roll axis (Y) angular rate output value
LSM6DSOX
SPI2_OUTX_L_G_OIS (22h) and SPI2_OUTX_H_G_OIS (23h)
DS12814 - Rev 3 page 101/199
11.6 SPI2_OUTZ_L_G_OIS (26h) and SPI2_OUTZ_H_G_OIS (27h)
Angular rate sensor yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the gyroscope full scale and ODR (6.66 kHz) settings of the OIS gyro.
Table 216. SPI2_OUTZ_L_G_OIS register
D7 D6 D5 D4 D3 D2 D1 D0
Table 217. SPI2_OUTZ_H_G_OIS register
D15 D14 D13 D12 D11 D10 D9 D8
Table 218. SPI2_OUTZ_H_G_OIS register description
D[15:0] Gyro OIS chain yaw axis (Z) angular rate output value
11.7 SPI2_OUTX_L_A_OIS (28h) and SPI2_OUTX_H_A_OIS (29h)
Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the accelerometer full scale and ODR (6.66 kHz) settings of the OIS accelerometer.
Table 219. SPI2_OUTX_L_A_OIS register
D7 D6 D5 D4 D3 D2 D1 D0
Table 220. SPI2_OUTX_H_A_OIS register
D15 D14 D13 D12 D11 D10 D9 D8
Table 221. SPI2_OUTX_H_A_OIS register description
D[15:0] Accelerometer UI chain X-axis linear acceleration output value
LSM6DSOX
SPI2_OUTZ_L_G_OIS (26h) and SPI2_OUTZ_H_G_OIS (27h)
DS12814 - Rev 3 page 102/199
11.8 SPI2_OUTY_L_A_OIS (2Ah) and SPI2_OUTY_H_A_OIS (2Bh)
Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the accelerometer full scale and ODR (6.66 kHz) settings of the OIS accelerometer.
Table 222. SPI2_OUTY_L_A_OIS register
D7 D6 D5 D4 D3 D2 D1 D0
Table 223. SPI2_OUTY_H_A_OIS register
D15 D14 D13 D12 D11 D10 D9 D8
Table 224. SPI2_OUTY_H_A_OIS register description
D[15:0] Accelerometer UI chain Y-axis linear acceleration output value
11.9 SPI2_OUTZ_L_A_OIS (2Ch) and SPI2_OUTZ_H_A_OIS (2Dh)
Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
Data are according to the accelerometer full scale and ODR (6.66 kHz) settings of the OIS accelerometer.
Table 225. SPI2_OUTZ_L_A_OIS register
D7 D6 D5 D4 D3 D2 D1 D0
Table 226. SPI2_OUTZ_H_A_OIS register
D15 D14 D13 D12 D11 D10 D9 D8
Table 227. SPI2_OUTZ_H_A_OIS register description
D[15:0] Accelerometer UI chain Z-axis linear acceleration output value
LSM6DSOX
SPI2_OUTY_L_A_OIS (2Ah) and SPI2_OUTY_H_A_OIS (2Bh)
DS12814 - Rev 3 page 103/199
11.10 SPI2_INT_OIS (6Fh)
OIS interrupt configuration register and accelerometer self-test enable setting. The auxiliary SPI interface can
write this register when the OIS_CTRL_FROM_UI bit in the FUNC_CFG_ACCESS (01h) register is equal to 0
(SPI2 Full control mode); this register is read-only when the OIS_CTRL_FROM_UI bit is equal to 1 (Primary IF
Full control mode) and shows the content of the UI_INT_OIS (6Fh) register.
Table 228. SPI_INT_OIS register
INT2_
DRDY_OIS LVL2_OIS DEN_LH_OIS - - 0 ST1_XL_OIS ST0_XL_OIS
Table 229. SPI_INT_OIS register description
INT2_DRDY_OIS Enables OIS chain DRDY on INT2 pin. This setting has priority over all other INT2 settings.
LVL2_OIS Enables level-sensitive latched mode on the OIS chain. Default value: 0
DEN_LH_OIS
Indicates polarity of DEN signal on OIS chain
(0: DEN pin is active-low;
1: DEN pin is active-high)
ST[1:0]_XL_OIS
Selects accelerometer self-test – effective only if XL OIS chain is enabled. Default value: 00
(00: Normal mode;
01: Positive sign self-test;
10: Negative sign self-test;
11: not allowed)
LSM6DSOX
SPI2_INT_OIS (6Fh)
DS12814 - Rev 3 page 104/199
11.11 SPI2_CTRL1_OIS (70h)
OIS configuration register. The auxiliary SPI interface can write this register when the OIS_CTRL_FROM_UI bit in
the FUNC_CFG_ACCESS (01h) register is equal to 0 (SPI2 Full control mode); this register is read-only when the
OIS_CTRL_FROM_UI bit is equal to 1 (Primary IF Full control mode) and shows the content of the UI_INT_OIS
(6Fh) register.
Table 230. SPI_CTRL1_OIS register
0 LVL1_OIS SIM_OIS Mode4_EN FS1_G_OIS FS0_G_OIS FS_125_OIS OIS_EN_SPI2
Table 231. SPI_CTRL1_OIS register description
LVL1_OIS Enables level-sensitive trigger mode on the OIS chain. Default value: 0
SIM_OIS
SPI2 3- or 4-wire interface. Default value: 0
(0: 4-wire SPI2;
1: 3-wire SPI2)
Mode4_EN
Enables accelerometer OIS chain. OIS outputs are available through SPI2 in registers
SPI2_OUTX_L_A_OIS (28h) and SPI2_OUTX_H_A_OIS (29h) through SPI2_OUTZ_L_A_OIS (2Ch) and
SPI2_OUTZ_H_A_OIS (2Dh) and SPI2_STATUS_REG_OIS (1Eh).
Note: OIS_EN_SPI2 must be enabled (i.e. set to ‘1’) to enable also the XL OIS chain.
FS[1:0]_G_OIS
Selects gyroscope OIS chain full-scale
(00: 250 dps;
01: 500 dps;
10: 1000 dps;
11: 2000 dps)
FS_125_OIS
Selects gyroscope OIS chain full-scale 125 dps
(0: FS selected through bits FS[1:0]_OIS_G;
1: 125 dps)
OIS_EN_SPI2
Enables OIS chain data processing for gyro in Mode 3 and Mode 4 (mode4_en = 1) and accelerometer data
in and Mode 4 (mode4_en = 1).
When the OIS chain is enabled, the OIS outputs are available through the SPI2 in registers
SPI2_OUTX_L_G_OIS (22h) and SPI2_OUTX_H_G_OIS (23h) through SPI2_OUTZ_L_G_OIS (26h) and
SPI2_OUTZ_H_G_OIS (27h) and STATUS_REG (1Eh) and SPI2_STATUS_REG_OIS (1Eh), and LPF1 is
dedicated to this chain.
DEN mode selection can be done using the LVL1_OIS bit of register UI_CTRL1_OIS (70h) and the LVL2_OIS bit
of register UI_INT_OIS (6Fh).
DEN mode on the OIS path is active in the gyroscope only.
Table 232. DEN mode selection
LVL1_OIS, LVL2_OIS DEN mode
10 Level-sensitive trigger mode is selected
11 Level-sensitive latched mode is selected
LSM6DSOX
SPI2_CTRL1_OIS (70h)
DS12814 - Rev 3 page 105/199
11.12 SPI2_CTRL2_OIS (71h)
OIS configuration register. The auxiliary SPI interface can write this register when the OIS_CTRL_FROM_UI bit in
the FUNC_CFG_ACCESS (01h) register is equal to 0 (SPI2 Full control mode); this register is read-only when the
OIS_CTRL_FROM_UI bit is equal to 1 (Primary IF Full control mode) and shows the content of the UI_INT_OIS
(6Fh) register.
Table 233. SPI_CTRL2_OIS register
- - HPM1_OIS HPM0_OIS 0 FTYPE_1_OIS FTYPE_0_OIS HP_EN_OIS
Table 234. SPI_CTRL2_OIS register description
HPM[1:0]_OIS
Selects gyroscope OIS chain digital high-pass filter cutoff. Default value: 00
(00: 16 mHz;
01: 65 mHz;
10: 260 mHz;
11: 1.04 Hz)
FTYPE_[1:0]_OIS Selects gyroscope digital LPF1 filter bandwidth. Table 182 shows cutoff and phase values obtained with all
configurations.
HP_EN_OIS Enables gyroscope OIS chain digital high-pass filter
Table 235. Gyroscope OIS chain digital LPF1 filter bandwidth selection
FTYPE_[1:0]_OIS Cutoff [Hz] Phase @ 20 Hz [°]
00 351.39 -6.88
01 236.63 -8.97
10 172.70 -11.37
11 937.91 -5.10
LSM6DSOX
SPI2_CTRL2_OIS (71h)
DS12814 - Rev 3 page 106/199
11.13 SPI2_CTRL3_OIS (72h)
OIS configuration register. The auxiliary SPI interface can write this register when the OIS_CTRL_FROM_UI bit in
the FUNC_CFG_ACCESS (01h) register is equal to 0 (SPI2 Full control mode); this register is read-only when the
OIS_CTRL_FROM_UI bit is equal to 1 (Primary IF Full control mode) and shows the content of the UI_INT_OIS
(6Fh) register.
Table 236. SPI2_CTRL3_OIS register
FS1_XL_OIS FS0_XL_OIS FILTER_
XL_CONF_OIS_2
FILTER_
XL_CONF_OIS_1
FILTER_
XL_CONF_OIS_0 ST1_OIS ST0_OIS ST_OIS_
CLAMPDIS
Table 237. SPI2_CTRL3_OIS register description
FS[1:0]_XL_OIS Selects accelerometer OIS channel full-scale. See Table 185.
FILTER_XL_CONF_OIS_[2:0] Selects accelerometer OIS channel bandwidth. See Table 186.
ST[1:0]_OIS
Selects gyroscope OIS chain self-test. Default value: 00
Table 187 lists the output variation when the self-test is enabled and
ST_OIS_CLAMPDIS = '1'.
(00: Normal mode;
01: Positive sign self-test;
10: Normal mode;
11: Negative sign self-test)
ST_OIS_CLAMPDIS
Disables OIS chain clamp
(0: All OIS chain outputs = 8000h during self-test;
1: OIS chain self-test outputs as shown in Table 187.
Table 238. Accelerometer OIS channel full-scale selection
FS[1:0]_XL_OIS
XL_FS_MODE = ‘0’ XL_FS_MODE = ‘1’
XL UI ON XL UI PD -
00 (default)
Full-scale selected from user
interface
2 g2 g
01 16 g2 g
10 4 g4 g
11 8 g8 g
Note: XL_FS_MODE bit is in CTRL8_XL (17h).
When the accelerometer full-scale value is selected only from the UI side, it is readable also from the OIS side.
LSM6DSOX
SPI2_CTRL3_OIS (72h)
DS12814 - Rev 3 page 107/199
12 Embedded functions register mapping
The table given below provides a list of the registers for the embedded functions available in the device and the
corresponding addresses. Embedded functions registers are accessible when FUNC_CFG_EN is set to '1' in
FUNC_CFG_ACCESS (01h).
Table 239. Register address map - embedded functions
Name Type
Register address
Default Comment
Hex Binary
PAGE_SEL r/w 02 00000010 00000001
EMB_FUNC_EN_A r/w 04 00000100 00000000
EMB_FUNC_EN_B r/w 05 00000101 00000000
PAGE_ADDRESS r/w 08 00001000 00000000
PAGE_VALUE r/w 09 00001001 00000000
EMB_FUNC_INT1 r/w 0A 00001010 00000000
FSM_INT1_A r/w 0B 00001011 00000000
FSM_INT1_B r/w 0C 00001100 00000000
MLC_INT1 r/w 0D 00001101 00000000
EMB_FUNC_INT2 r/w 0E 00001110 00000000
FSM_INT2_A r/w 0F 00001111 00000000
FSM_INT2_B r/w 10 00010000 00000000
MLC_INT2 r/w 11 00010001 00000000
EMB_FUNC_STATUS r 12 00010010 output
FSM_STATUS_A r 13 00010011 output
FSM_STATUS_B r 14 00010100 output
MLC_STATUS r 15 00010101 output
PAGE_RW r/w 17 00010111 00000000
RESERVED - 18-43 00011000
EMB_FUNC_FIFO_CFG r/w 44 01000100 00000000
FSM_ENABLE_A r/w 46 01000110 00000000
FSM_ENABLE_B r/w 47 01000111 00000000
FSM_LONG_COUNTER_L r/w 48 01001000 00000000
FSM_LONG_COUNTER_H r/w 49 01001001 00000000
FSM_LONG_COUNTER_CLEAR r/w 4A 01001010 00000000
FSM_OUTS1 r 4C 01001100 output
FSM_OUTS2 r 4D 01001101 output
FSM_OUTS3 r 4E 01001110 output
FSM_OUTS4 r 4F 01001111 output
FSM_OUTS5 r 50 01010000 output
FSM_OUTS6 r 51 01010001 output
FSM_OUTS7 r 52 01010010 output
LSM6DSOX
Embedded functions register mapping
DS12814 - Rev 3 page 108/199
Name Type
Register address
Default Comment
Hex Binary
FSM_OUTS8 r 53 01010011 output
FSM_OUTS9 r 54 01010100 output
FSM_OUTS10 r 55 01010101 output
FSM_OUTS11 r 56 01010110 output
FSM_OUTS12 r 57 01010111 output
FSM_OUTS13 r 58 01011000 output
FSM_OUTS14 r 59 01011001 output
FSM_OUTS15 r 5A 01011010 output
FSM_OUTS16 r 5B 01011011 output
RESERVED - 5E 01011110
EMB_FUNC_ODR_CFG_B r/w 5F 01011111 01001011
EMB_FUNC_ODR_CFG_C r/w 60 01100000 00010101
STEP_COUNTER_L r 62 01100010 output
STEP_COUNTER_H r 63 01100011 output
EMB_FUNC_SRC r/w 64 01100100 output
EMB_FUNC_INIT_A r/w 66 01100110 00000000
EMB_FUNC_INIT_B r/w 67 01100111 00000000
MLC0_SRC r 70 01110000 output
MLC1_SRC r 71 01110001 output
MLC2_SRC r 72 01110010 output
MLC3_SRC r 73 01110011 output
MLC4_SRC r 74 01110100 output
MLC5_SRC r 75 01110101 output
MLC6_SRC r 76 01110110 output
MLC7_SRC r 77 01110111 output
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to
the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration
values. Their content is automatically restored when the device is powered up.
LSM6DSOX
Embedded functions register mapping
DS12814 - Rev 3 page 109/199
13 Embedded functions register description
13.1 PAGE_SEL (02h)
Enable advanced features dedicated page (r/w)
Table 240. PAGE_SEL register
PAGE_SEL3 PAGE_SEL2 PAGE_SEL1 PAGE_SEL0 0(1) 0(1) 0(1) 1(2)
1. This bit must be set to '0' for the correct operation of the device.
2. This bit must be set to '1' for the correct operation of the device.
Table 241. PAGE_SEL register description
PAGE_SEL[3:0] Select the advanced features dedicated page
Default value: 0000
13.2 EMB_FUNC_EN_A (04h)
Embedded functions enable register (r/w)
Table 242. EMB_FUNC_EN_A register
0(1) 0(1) SIGN_
MOTION_EN TILT_EN PEDO_EN 0(1) 0(1) 0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 243. EMB_FUNC_EN_A register description
SIGN_MOTION_EN
Enable significant motion detection function. Default value: 0
(0: significant motion detection function disabled;
1: significant motion detection function enabled)
TILT_EN
Enable tilt calculation. Default value: 0
(0: tilt algorithm disabled;
1: tilt algorithm enabled)
PEDO_EN
Enable pedometer algorithm. Default value: 0
(0: pedometer algorithm disabled;
1: pedometer algorithm enabled)
LSM6DSOX
Embedded functions register description
DS12814 - Rev 3 page 110/199
13.3 EMB_FUNC_EN_B (05h)
Embedded functions enable register (r/w)
Table 244. EMB_FUNC_EN_B register
0(1) 0(1) 0(1) MLC_EN FIFO_
COMPR_EN 0(1) 0(1) FSM_EN
1. This bit must be set to '0' for the correct operation of the device.
Table 245. EMB_FUNC_EN_B register description
MLC_EN
Enable Machine Learning Core feature. Default value: 0
(0: Machine Learning Core feature disabled;
1: Machine Learning Core feature enabled)
FIFO_COMPR_EN(1)
Enable FIFO compression feature. Default value: 0
(0: FIFO compression feature disabled;
1: FIFO compression feature enabled)
FSM_EN Enable Finite State Machine (FSM) feature. Default value: 0
(0: FSM feature disabled; 1: FSM feature enabled)
1. This bit is effective if the FIFO_COMPR_RT_EN bit of FIFO_CTRL2 (08h) is set to 1.
13.4 PAGE_ADDRESS (08h)
Page address register (r/w)
Table 246. PAGE_ADDRESS register
PAGE_
ADDR7
PAGE_
ADDR6
PAGE_
ADDR5
PAGE_
ADDR4
PAGE_
ADDR3
PAGE_
ADDR2
PAGE_
ADDR1
PAGE_
ADDR0
Table 247. PAGE_ADDRESS register description
PAGE_ADDR[7:0]
After setting the bit PAGE_WRITE / PAGE_READ in register PAGE_RW (17h), this register is used to set
the address of the register to be written/read in the advanced features page selected through the bits
PAGE_SEL[3:0] in register PAGE_SEL (02h).
LSM6DSOX
EMB_FUNC_EN_B (05h)
DS12814 - Rev 3 page 111/199
13.5 PAGE_VALUE (09h)
Page value register (r/w)
Table 248. PAGE_VALUE register
PAGE_
VALUE7
PAGE_
VALUE6
PAGE_
VALUE5
PAGE_
VALUE4
PAGE_
VALUE3
PAGE_
VALUE2
PAGE_
VALUE1
PAGE_
VALUE0
Table 249. PAGE_VALUE register description
PAGE_VALUE[7:0]
These bits are used to write (if the bit PAGE_WRITE = 1 in register PAGE_RW (17h)) or read (if the bit
PAGE_READ = 1 in register PAGE_RW (17h)) the data at the address PAGE_ADDR[7:0] of the selected
advanced features page.
13.6 EMB_FUNC_INT1 (0Ah)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT1. The pin's output will supply the OR
combination of the selected signals.
Table 250. EMB_FUNC_INT1 register
INT1_
FSM_LC 0(1) INT1_
SIG_MOT INT1_TILT INT1_STEP
_DETECTOR 0(1) 0(1) 0(1)
1. This bit must be set to '0' for the correct operation of the device.
EMB_FUNC_INT1 register description
INT1_FSM_LC(1) Routing of FSM long counter timeout interrupt event on INT1. Default value: 0 (0: routing on
INT1 disabled; 1: routing on INT1 enabled)
INT1_SIG_MOT(1) Routing of significant motion event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_TILT(1) Routing of tilt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_STEP_DETECTOR(1) Routing of pedometer step recognition event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
1. This bit is effective if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1.
LSM6DSOX
PAGE_VALUE (09h)
DS12814 - Rev 3 page 112/199
13.7 FSM_INT1_A (0Bh)
INT1 pin control register (r/w).
Each bit in this register enables a signal to be carried through INT1. The pin's output will supply the OR
combination of the selected signals.
Table 251. FSM_INT1_A register
INT1_FSM8 INT1_FSM7 INT1_FSM6 INT1_FSM5 INT1_FSM4 INT1_FSM3 INT1_FSM2 INT1_FSM1
Table 252. FSM_INT1_A register description
INT1_FSM8(1) Routing of FSM8 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM7(1) Routing of FSM7 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM6(1) Routing of FSM6 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM5(1) Routing of FSM5 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM4(1) Routing of FSM4 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM3(1) Routing of FSM3 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM2(1) Routing of FSM2 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM1(1) Routing of FSM1 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
1. This bit is effective if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1.
LSM6DSOX
FSM_INT1_A (0Bh)
DS12814 - Rev 3 page 113/199
13.8 FSM_INT1_B (0Ch)
INT1 pin control register (r/w).
Each bit in this register enables a signal to be carried through INT1. The pin's output will supply the OR
combination of the selected signals.
Table 253. FSM_INT1_B register
INT1_
FSM16
INT1_
FSM15
INT1_
FSM14
INT1_
FSM13
INT1_
FSM12
INT1_
FSM11
INT1_
FSM10
INT1_
FSM9
Table 254. FSM_INT1_B register description
INT1_FSM16(1) Routing of FSM16 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM15(1) Routing of FSM15 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM14(1) Routing of FSM14 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM13(1) Routing of FSM13 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM12(1) Routing of FSM12 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM11(1) Routing of FSM11 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM10(1) Routing of FSM10 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_FSM9(1) Routing of FSM9 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
1. This bit is effective if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1.
LSM6DSOX
FSM_INT1_B (0Ch)
DS12814 - Rev 3 page 114/199
13.9 MLC_INT1 (0Dh)
Each bit in this register enables a signal to be carried through INT1. The pin's output will supply the OR
combination of the selected signals.
Table 255. MLC_INT1 register
INT1_MLC8 INT1_MLC7 INT1_MLC6 INT1_MLC5 INT1_MLC4 INT1_MLC3 INT1_MLC2 INT1_MLC1
Table 256. MLC_INT1 register description
INT1_MLC8 Routing of MLC8 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_MLC7 Routing of MLC7 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_MLC6 Routing of MLC6 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_MLC5 Routing of MLC5 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_MLC4 Routing of MLC4 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_MLC3 Routing of MLC3 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_MLC2 Routing of MLC2 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_MLC1 Routing of MLC1 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
LSM6DSOX
MLC_INT1 (0Dh)
DS12814 - Rev 3 page 115/199
13.10 EMB_FUNC_INT2 (0Eh)
INT2 pin control register (r/w).
Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR
combination of the selected signals.
Table 257. EMB_FUNC_INT2 register
INT2_
FSM_LC 0(1) INT2_
SIG_MOT INT2_TILT INT2_STEP
_DETECTOR 0(1) 0(1) 0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 258. EMB_FUNC_INT2 register description
INT2_FSM_LC(1) Routing of FSM long counter timeout interrupt event on INT2. Default value: 0 (0: routing on
INT2 disabled; 1: routing on INT2 enabled)
INT2_SIG_MOT(1) Routing of significant motion event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_TILT(1) Routing of tilt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_STEP_DETECTOR(1) Routing of pedometer step recognition event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
1. This bit is effective if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1.
LSM6DSOX
EMB_FUNC_INT2 (0Eh)
DS12814 - Rev 3 page 116/199
13.11 FSM_INT2_A (0Fh)
INT2 pin control register (r/w).
Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR
combination of the selected signals.
Table 259. FSM_INT2_A register
INT2_FSM8 INT2_FSM7 INT2_FSM6 INT2_FSM5 INT2_FSM4 INT2_FSM3 INT2_FSM2 INT2_FSM1
Table 260. FSM_INT2_A register description
INT2_FSM8(1) Routing of FSM8 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM7(1) Routing of FSM7 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM6(1) Routing of FSM6 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM5(1) Routing of FSM5 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM4(1) Routing of FSM4 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM3(1) Routing of FSM3 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM2(1) Routing of FSM2 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM1(1) Routing of FSM1 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
1. This bit is effective if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1.
LSM6DSOX
FSM_INT2_A (0Fh)
DS12814 - Rev 3 page 117/199
13.12 FSM_INT2_B (10h)
INT2 pin control register (r/w).
Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR
combination of the selected signals.
Table 261. FSM_INT2_B register
INT2_FSM16 INT2_FSM15 INT2_FSM14 INT2_FSM13 INT2_FSM12 INT2_FSM11 INT2_FSM10 INT2_FSM9
Table 262. FSM_INT2_B register description
INT2_FSM16(1) Routing of FSM16 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM15(1) Routing of FSM15 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM14(1) Routing of FSM14 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM13(1) Routing of FSM13 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM12(1) Routing of FSM12 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM11(1) Routing of FSM11 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM10(1) Routing of FSM10 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_FSM9(1) Routing of FSM9 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
1. This bit is effective if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1.
LSM6DSOX
FSM_INT2_B (10h)
DS12814 - Rev 3 page 118/199
13.13 MLC_INT2 (11h)
INT2 pin control register (r/w).
Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR
combination of the selected signals.
Table 263. MLC_INT2 register
INT2_MLC8 INT2_MLC7 INT2_MLC6 INT2_MLC5 INT2_MLC4 INT2_MLC3 INT2_MLC2 INT2_MLC1
Table 264. MLC_INT2 register description
INT2_MLC8 Routing of MLC8 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_MLC7 Routing of MLC7 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_MLC6 Routing of MLC6 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_MLC5 Routing of MLC5 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_MLC4 Routing of MLC4 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_MLC3 Routing of MLC3 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_MLC2 Routing of MLC2 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_MLC1 Routing of MLC1 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
LSM6DSOX
MLC_INT2 (11h)
DS12814 - Rev 3 page 119/199
13.14 EMB_FUNC_STATUS (12h)
Embedded function status register (r).
Table 265. EMB_FUNC_STATUS register
IS_FSM_LC 0 IS_SIGMOT IS_TILT IS_STEP_DET 0 0 0
Table 266. EMB_FUNC_STATUS register description
IS_FSM_LC Interrupt status bit for FSM long counter timeout interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_SIGMOT Interrupt status bit for significant motion detection
(1: interrupt detected; 0: no interrupt)
IS_TILT Interrupt status bit for tilt detection
(1: interrupt detected; 0: no interrupt)
IS_STEP_DET Interrupt status bit for step detection
(1: interrupt detected; 0: no interrupt)
LSM6DSOX
EMB_FUNC_STATUS (12h)
DS12814 - Rev 3 page 120/199
13.15 FSM_STATUS_A (13h)
Finite State Machine status register (r).
Table 267. FSM_STATUS_A register
IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1
Table 268. FSM_STATUS_A register description
IS_FSM8 Interrupt status bit for FSM8 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM7 Interrupt status bit for FSM7 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM6 Interrupt status bit for FSM6 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM5 Interrupt status bit for FSM5 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM4 Interrupt status bit for FSM4 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM3 Interrupt status bit for FSM3 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM2 Interrupt status bit for FSM2 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM1 Interrupt status bit for FSM1 interrupt event.
(1: interrupt detected; 0: no interrupt)
LSM6DSOX
FSM_STATUS_A (13h)
DS12814 - Rev 3 page 121/199
13.16 FSM_STATUS_B (14h)
Finite State Machine status register (r).
Table 269. FSM_STATUS_B register
IS_FSM16 IS_FSM15 IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9
Table 270. FSM_STATUS_B register description
IS_FSM16 Interrupt status bit for FSM16 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM15 Interrupt status bit for FSM15 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM14 Interrupt status bit for FSM14 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM13 Interrupt status bit for FSM13 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM12 Interrupt status bit for FSM12 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM11 Interrupt status bit for FSM11 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM10 Interrupt status bit for FSM10 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM9 Interrupt status bit for FSM9 interrupt event.
(1: interrupt detected; 0: no interrupt)
LSM6DSOX
FSM_STATUS_B (14h)
DS12814 - Rev 3 page 122/199
13.17 MLC_STATUS (15h)
Machine Learning Core status register (r).
Table 271. MLC_STATUS register
IS_MLC8 IS_MLC7 IS_MLC6 IS_MLC5 IS_MLC4 IS_MLC3 IS_MLC IS_MLC1
Table 272. MLC_STATUS register description
IS_MLC8 Interrupt status bit for MLC8 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC7 Interrupt status bit for MLC7 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC6 Interrupt status bit for MLC6 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC5 Interrupt status bit for MLC5 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC4 Interrupt status bit for MLC4 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC3 Interrupt status bit for MLC3 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC2 Interrupt status bit for MLC2 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC1 Interrupt status bit for MLC1 interrupt event.
(1: interrupt detected; 0: no interrupt)
LSM6DSOX
MLC_STATUS (15h)
DS12814 - Rev 3 page 123/199
13.18 PAGE_RW (17h)
Enable read and write mode of advanced features dedicated page (r/w)
Table 273. PAGE_RW register
EMB_
FUNC_LIR
PAGE_
WRITE
PAGE_
READ 0(1) 0(1) 0(1) 0(1) 0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 274. PAGE_RW register description
EMB_FUNC_LIR
Latched Interrupt mode for Embedded Functions. Default value: 0
(0: Embedded Functions interrupt request not latched;
1: Embedded Functions interrupt request latched)
PAGE_WRITE
Enable writes to the selected advanced features dedicated page.(1)
Default value: 0
(1: enable; 0: disable)
PAGE_READ
Enable reads from the selected advanced features dedicated page.(1)
Default value: 0
(1: enable; 0: disable)
1. Page selected by PAGE_SEL[3:0] in PAGE_SEL (02h) register.
13.19 EMB_FUNC_FIFO_CFG (44h)
Embedded functions batching configuration register (r/w).
Table 275. EMB_FUNC_FIFO_CFG register
0(1) PEDO_
FIFO_EN 0(1) 0(1) 0(1) 0(1) 0(1) 0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 276. EMB_FUNC_FIFO_CFG register description
PEDO_FIFO_EN Enable FIFO batching of step counter values. Default value: 0
LSM6DSOX
PAGE_RW (17h)
DS12814 - Rev 3 page 124/199
13.20 FSM_ENABLE_A (46h)
FSM enable register (r/w).
Table 277. FSM_ENABLE_A register
FSM8_EN FSM7_EN FSM6_EN FSM5_EN FSM4_EN FSM3_EN FSM2_EN FSM1_EN
Table 278. FSM_ENABLE_A register description
FSM8_EN FSM8 enable. Default value: 0 (0: FSM8 disabled; 1: FSM8 enabled)
FSM7_EN FSM7 enable. Default value: 0 (0: FSM7 disabled; 1: FSM7 enabled)
FSM6_EN FSM6 enable. Default value: 0 (0: FSM6 disabled; 1: FSM6 enabled)
FSM5_EN FSM5 enable. Default value: 0 (0: FSM5 disabled; 1: FSM5 enabled)
FSM4_EN FSM4 enable. Default value: 0 (0: FSM4 disabled; 1: FSM4 enabled)
FSM3_EN FSM3 enable. Default value: 0 (0: FSM3 disabled; 1: FSM3 enabled)
FSM2_EN FSM2 enable. Default value: 0 (0: FSM2 disabled; 1: FSM2 enabled)
FSM1_EN FSM1 enable. Default value: 0 (0: FSM1 disabled; 1: FSM1 enabled)
13.21 FSM_ENABLE_B (47h)
FSM enable register (r/w).
Table 279. FSM_ENABLE_B register
FSM16_EN FSM15_EN FSM14_EN FSM13_EN FSM12_EN FSM11_EN FSM10_EN FSM9_EN
Table 280. FSM_ENABLE_B register description
FSM16_EN FSM16 enable. Default value: 0 (0: FSM16 disabled; 1: FSM16 enabled)
FSM15_EN FSM15 enable. Default value: 0 (0: FSM15 disabled; 1: FSM15 enabled)
FSM14_EN FSM14 enable. Default value: 0 (0: FSM14 disabled; 1: FSM14 enabled)
FSM13_EN FSM13 enable. Default value: 0 (0: FSM13 disabled; 1: FSM13 enabled)
FSM12_EN FSM12 enable. Default value: 0 (0: FSM12 disabled; 1: FSM12 enabled)
FSM11_EN FSM11 enable. Default value: 0 (0: FSM11 disabled; 1: FSM11 enabled)
FSM10_EN FSM10 enable. Default value: 0 (0: FSM10 disabled; 1: FSM10 enabled)
FSM9_EN FSM9 enable. Default value: 0 (0: FSM9 disabled; 1: FSM9 enabled)
LSM6DSOX
FSM_ENABLE_A (46h)
DS12814 - Rev 3 page 125/199
13.22 FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h)
FSM long counter status register (r/w).
Long counter value is an unsigned integer value (16-bit format); this value can be reset using the LC_CLEAR bit
in the FSM_LONG_COUNTER_CLEAR (4Ah) register.
Table 281. FSM_LONG_COUNTER_L register
FSM_LC_7 FSM_LC_6 FSM_LC_5 FSM_LC_4 FSM_LC_3 FSM_LC_2 FSM_LC_1 FSM_LC_0
Table 282. FSM_LONG_COUNTER_L register description
FSM_LC_[7:0] Long counter current value (LSbyte). Default value: 00000000
Table 283. FSM_LONG_COUNTER_H register
FSM_LC_15 FSM_LC_14 FSM_LC_13 FSM_LC_12 FSM_LC_11 FSM_LC_10 FSM_LC_9 FSM_LC_8
Table 284. FSM_LONG_COUNTER_H register description
FSM_LC_[15:8] Long counter current value (MSbyte). Default value: 00000000
13.23 FSM_LONG_COUNTER_CLEAR (4Ah)
FSM long counter reset register (r/w).
Table 285. FSM_LONG_COUNTER_CLEAR register
0(1) 0(1) 0(1) 0(1) 0(1) 0(1) FSM_LC_
CLEARED
FSM_LC_
CLEAR
1. This bit must be set to '0' for the correct operation of the device.
Table 286. FSM_LONG_COUNTER_CLEAR register description
FSM_LC_CLEARED This read-only bit is automatically set to 1 when the long counter reset is done. Default value: 0
FSM_LC_CLEAR Clear FSM long counter value. Default value: 0
LSM6DSOX
FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h)
DS12814 - Rev 3 page 126/199
13.24 FSM_OUTS1 (4Ch)
FSM1 output register (r).
Table 287. FSM_OUTS1 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 288. FSM_OUTS1 register description
P_X FSM1 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM1 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM1 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM1 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM1 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM1 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM1 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM1 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS1 (4Ch)
DS12814 - Rev 3 page 127/199
13.25 FSM_OUTS2 (4Dh)
FSM2 output register (r).
Table 289. FSM_OUTS2 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 290. FSM_OUTS2 register description
P_X FSM2 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM2 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM2 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM2 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM2 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM2 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM2 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM2 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS2 (4Dh)
DS12814 - Rev 3 page 128/199
13.26 FSM_OUTS3 (4Eh)
FSM3 output register (r).
Table 291. FSM_OUTS3 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 292. FSM_OUTS3 register description
P_X FSM3 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM3 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM3 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM3 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM3 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM3 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM3 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM3 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS3 (4Eh)
DS12814 - Rev 3 page 129/199
13.27 FSM_OUTS4 (4Fh)
FSM4 output register (r).
Table 293. FSM_OUTS4 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 294. FSM_OUTS4 register description
P_X FSM4 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM4 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM4 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM4 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM4 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM4 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM4 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM4 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS4 (4Fh)
DS12814 - Rev 3 page 130/199
13.28 FSM_OUTS5 (50h)
FSM5 output register (r).
Table 295. FSM_OUTS5 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 296. FSM_OUTS5 register description
P_X FSM5 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM5 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM5 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM5 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM5 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM5 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM5 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM5 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS5 (50h)
DS12814 - Rev 3 page 131/199
13.29 FSM_OUTS6 (51h)
FSM6 output register (r).
Table 297. FSM_OUTS6 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 298. FSM_OUTS6 register description
P_X FSM6 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM6 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM6 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM6 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM6 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM6 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM6 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM6 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS6 (51h)
DS12814 - Rev 3 page 132/199
13.30 FSM_OUTS7 (52h)
FSM7 output register (r).
Table 299. FSM_OUTS7 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 300. FSM_OUTS7 register description
P_X FSM7 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM7 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM7 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM7 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM7 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM7 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM7 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM7 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS7 (52h)
DS12814 - Rev 3 page 133/199
13.31 FSM_OUTS8 (53h)
FSM8 output register (r).
Table 301. FSM_OUTS8 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 302. FSM_OUTS8 register description
P_X FSM8 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM8 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM8 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM8 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM8 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM8 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM8 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM8 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS8 (53h)
DS12814 - Rev 3 page 134/199
13.32 FSM_OUTS9 (54h)
FSM9 output register (r).
Table 303. FSM_OUTS9 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 304. FSM_OUTS9 register description
P_X FSM9 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM9 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM9 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM9 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM9 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM9 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM9 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM9 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS9 (54h)
DS12814 - Rev 3 page 135/199
13.33 FSM_OUTS10 (55h)
FSM10 output register (r).
Table 305. FSM_OUTS10 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 306. FSM_OUTS10 register description
P_X FSM10 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM10 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM10 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM10 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM10 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM10 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM10 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM10 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS10 (55h)
DS12814 - Rev 3 page 136/199
13.34 FSM_OUTS11 (56h)
FSM11 output register (r).
Table 307. FSM_OUTS11 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 308. FSM_OUTS11 register description
P_X FSM11 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM11 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM11 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM11 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM11 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM11 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM11 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM11 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS11 (56h)
DS12814 - Rev 3 page 137/199
13.35 FSM_OUTS12 (57h)
FSM12 output register (r).
Table 309. FSM_OUTS12 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 310. FSM_OUTS12 register description
P_X FSM12 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM12 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM12 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM12 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM12 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM12 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM12 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM12 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS12 (57h)
DS12814 - Rev 3 page 138/199
13.36 FSM_OUTS13 (58h)
FSM13 output register (r).
Table 311. FSM_OUTS13 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 312. FSM_OUTS13 register description
P_X FSM13 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM13 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM13 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM13 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM13 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM13 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM13 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM13 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS13 (58h)
DS12814 - Rev 3 page 139/199
13.37 FSM_OUTS14 (59h)
FSM14 output register (r).
Table 313. FSM_OUTS14 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 314. FSM_OUTS14 register description
P_X FSM14 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM14 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM14 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM14 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM14 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM14 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM14 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM14 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS14 (59h)
DS12814 - Rev 3 page 140/199
13.38 FSM_OUTS15 (5Ah)
FSM15 output register (r).
Table 315. FSM_OUTS15 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 316. FSM_OUTS15 register description
P_X FSM15 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM15 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM15 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM15 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM15 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM15 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM15 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM15 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS15 (5Ah)
DS12814 - Rev 3 page 141/199
13.39 FSM_OUTS16 (5Bh)
FSM16 output register (r).
Table 317. FSM_OUTS16 register
P_X N_X P_Y N_Y P_Z N_Z P_V N_V
Table 318. FSM_OUTS16 register description
P_X FSM16 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
N_X FSM16 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
P_Y FSM16 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
N_Y FSM16 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
P_Z FSM16 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
N_Z FSM16 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
P_V FSM16 output: positive event detected on the vector.
(0: event not detected; 1: event detected
N_V FSM16 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
LSM6DSOX
FSM_OUTS16 (5Bh)
DS12814 - Rev 3 page 142/199
13.40 EMB_FUNC_ODR_CFG_B (5Fh)
Finite State Machine output data rate configuration register (r/w).
Table 319. EMB_FUNC_ODR_CFG_B register
0(1) 1(2) 0(1) FSM_ODR1 FSM_ODR0 0(1) 1(2) 1(2)
1. This bit must be set to '0' for the correct operation of the device.
2. This bit must be set to '1' for the correct operation of the device.
Table 320. EMB_FUNC_ODR_CFG_B register description
FSM_ODR[1:0]
Finite State Machine ODR configuration:
(00: 12.5 Hz;
01: 26 Hz (default);
10: 52 Hz;
11: 104 Hz)
13.41 EMB_FUNC_ODR_CFG_C (60h)
Machine Learning Core output data rate configuration register (r/w).
Table 321. EMB_FUNC_ODR_CFG_C register
0(1) 0(1) MLC_ODR1 MLC_ODR0 0(1) 1(2) 0(1) 1(2)
1. This bit must be set to '0' for the correct operation of the device.
2. This bit must be set to '1' for the correct operation of the device.
Table 322. EMB_FUNC_ODR_CFG_C register description
MLC_ODR[1:0]
Machine Learning Core ODR configuration:
(00: 12.5 Hz;
01: 26 Hz (default);
10: 52 Hz;
11: 104 Hz)
LSM6DSOX
EMB_FUNC_ODR_CFG_B (5Fh)
DS12814 - Rev 3 page 143/199
13.42 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h)
Step counter output register (r).
Table 323. STEP_COUNTER_L register
STEP_7 STEP_6 STEP_5 STEP_4 STEP_3 STEP_2 STEP_1 STEP_0
Table 324. STEP_COUNTER_L register description
STEP_[7:0] Step counter output (LSbyte)
Table 325. STEP_COUNTER_H register
STEP_15 STEP_14 STEP_13 STEP_12 STEP_11 STEP_10 STEP_9 STEP_8
Table 326. STEP_COUNTER_H register description
STEP_[15:8] Step counter output (MSbyte)
13.43 EMB_FUNC_SRC (64h)
Embedded function source register (r/w)
Table 327. EMB_FUNC_SRC register
PEDO_
RST_STEP 0STEP_
DETECTED
STEP_COUNT
_DELTA_IA
STEP_
OVERFLOW
STEPCOUNTER
_BIT_SET 0 0
Table 328. EMB_FUNC_SRC register description
PEDO_RST_STEP Reset pedometer step counter. Read/write bit.
(0: disabled; 1: enabled)
STEP_DETECTED Step detector event detection status. Read-only bit.
(0: step detection event not detected; 1: step detection event detected)
STEP_COUNT_DELTA_IA
Pedometer step recognition on delta time status. Read-only bit.
(0: no step recognized during delta time;
1: at least one step recognized during delta time)
STEP_OVERFLOW Step counter overflow status. Read-only bit.
(0: step counter value < 216; 1: step counter value reached 216)
STEPCOUNTER_BIT_SET
This bit is equal to 1 when the step count is increased. If a timer period is programmed in
PEDO_SC_DELTAT_L (D0h) and PEDO_SC_DELTAT_H (D1h) embedded advanced features
(page 1) registers, this bit is kept to 0.
Read-only bit.
LSM6DSOX
STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h)
DS12814 - Rev 3 page 144/199
13.44 EMB_FUNC_INIT_A (66h)
Embedded functions initialization register (r/w)
Table 329. EMB_FUNC_INIT_A register
0(1) 0(1) SIG_MOT
_INIT TILT_INIT STEP_DET
_INIT 0(1) 0(1) 0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 330. EMB_FUNC_INIT_A register description
SIG_MOT_INIT Significant Motion Detection algorithm initialization request. Default value: 0
TILT_INIT Tilt algorithm initialization request. Default value: 0
STEP_DET_INIT Pedometer Step Counter/Detector algorithm initialization request. Default value: 0
13.45 EMB_FUNC_INIT_B (67h)
Embedded functions initialization register (r/w)
Table 331. EMB_FUNC_INIT_B register
0(1) 0(1) 0(1) MLC_INIT FIFO_
COMPR_INIT 0(1) 0(1) FSM_INIT
1. This bit must be set to '0' for the correct operation of the device.
Table 332. EMB_FUNC_INIT_B register description
MLC_INIT Machine Learning Core initialization request. Default value: 0
FIFO_COMPR_INIT FIFO compression feature initialization request. Default value: 0
FSM_INIT FSM initialization request. Default value: 0
13.46 MLC0_SRC (70h)
Machine Learning Core source register (r)
Table 333. MLC0_SRC register
MLC0_
SRC_7
MLC0_
SRC_6
MLC0_
SRC_5
MLC0_
SRC_4
MLC0_
SRC_3
MLC0_
SRC_2
MLC0_
SRC_1
MLC0_
SRC_0
Table 334. MLC0_SRC register description
MLC0_SRC_[7:0] Output value of MLC0 decision tree
LSM6DSOX
EMB_FUNC_INIT_A (66h)
DS12814 - Rev 3 page 145/199
13.47 MLC1_SRC (71h)
Machine Learning Core source register (r)
Table 335. MLC1_SRC register
MLC1_
SRC_7
MLC1_
SRC_6
MLC1_
SRC_5
MLC1_
SRC_4
MLC1_
SRC_3
MLCS1_
SRC_2
MLC1_
SRC_1
MLC1_
SRC_0
Table 336. MLC1_SRC register description
MLC1_SRC_[7:0] Output value of MLC1 decision tree
13.48 MLC2_SRC (72h)
Machine Learning Core source register (r)
Table 337. MLC2_SRC register
MLC2_
SRC_7
MLC2_
SRC_6
MLC2_
SRC_5
MLC2_
SRC_4
MLC2_
SRC_3
MLC2_
SRC_2
MLC2_
SRC_1
MLC2_
SRC_0
Table 338. MLC2_SRC register description
MLC2_SRC_[7:0] Output value of MLC2 decision tree
13.49 MLC3_SRC (73h)
Machine Learning Core source register (r)
Table 339. MLC3_SRC register
MLC3_
SRC_7
MLC3_
SRC_6
MLC3_
SRC_5
MLC3_
SRC_4
MLC3_
SRC_3
MLC3_
SRC_2
MLC3_
SRC_1
MLC3_
SRC_0
Table 340. MLC3_SRC register description
MLC3_SRC_[7:0] Output value of MLC3 decision tree
LSM6DSOX
MLC1_SRC (71h)
DS12814 - Rev 3 page 146/199
13.50 MLC4_SRC (74h)
Machine Learning Core source register (r)
Table 341. MLC4_SRC register
MLC4_
SRC_7
MLC4_
SRC_6
MLC4_
SRC_5
MLC4_
SRC_4
MLC4_
SRC_3
MLC4_
SRC_2
MLC4_
SRC_1
MLC4_
SRC_0
Table 342. MLC4_SRC register description
MLC4_SRC_[7:0] Output value of MLC4 decision tree
13.51 MLC5_SRC (75h)
Machine Learning Core source register (r)
Table 343. MLC5_SRC register
MLC5_
SRC_7
MLC5_
SRC_6
MLC5_
SRC_5
MLC5_
SRC_4
MLC5_
SRC_3
MLC5_
SRC_2
MLC5_
SRC_1
MLC5_
SRC_0
Table 344. MLC5_SRC register description
MLC5_SRC_[7:0] Output value of MLC5 decision tree
13.52 MLC6_SRC (76h)
Machine Learning Core source register (r)
Table 345. MLC6_SRC register
MLC6_
SRC_7
MLC6_
SRC_6
MLC6_
SRC_5
MLC6_
SRC_4
MLC6_
SRC_3
MLC6_
SRC_2
MLC6_
SRC_1
MLC6_
SRC_0
Table 346. MLC6_SRC register description
MLC6_SRC_[7:0] Output value of MLC6 decision tree
13.53 MLC7_SRC (77h)
Machine Learning Core source register (r)
Table 347. MLC7_SRC register
MLC7_
SRC_7
MLC7_
SRC_6
MLC7_
SRC_5
MLC7_
SRC_4
MLC7_
SRC_3
MLC7_
SRC_2
MLC7_
SRC_1
MLC7_
SRC_0
Table 348. MLC7_SRC register description
MLC7_SRC_[7:0] Output value of MLC7 decision tree
LSM6DSOX
MLC4_SRC (74h)
DS12814 - Rev 3 page 147/199
14 Embedded advanced features pages
The table given below provides a list of the registers for the embedded advanced features page 0. These
registers are accessible when PAGE_SEL[3:0] are set to 0000 in PAGE_SEL (02h).
Table 349. Register address map - embedded advanced features page 0
Name Type
Register address
Default Comment
Hex Binary
MAG_SENSITIVITY_L r/w BA 10111010 00100100
MAG_SENSITIVITY_H r/w BB 10111011 00010110
MAG_OFFX_L r/w C0 11000000 00000000
MAG_OFFX_H r/w C1 11000001 00000000
MAG_OFFY_L r/w C2 11000010 00000000
MAG_OFFY_H r/w C3 11000011 00000000
MAG_OFFZ_L r/w C4 11000100 00000000
MAG_OFFZ_H r/w C5 11000101 00000000
MAG_SI_XX_L r/w C6 11000110 00000000
MAG_SI_XX_H r/w C7 11000111 00111100
MAG_SI_XY_L r/w C8 11001000 00000000
MAG_SI_XY_H r/w C9 11001001 00000000
MAG_SI_XZ_L r/w CA 11001010 00000000
MAG_SI_XZ_H r/w CB 11001011 00000000
MAG_SI_YY_L r/w CC 11001100 00000000
MAG_SI_YY_H r/w CD 11001101 00111100
MAG_SI_YZ_L r/w CE 11001110 00000000
MAG_SI_YZ_H r/w CF 11001111 00000000
MAG_SI_ZZ_L r/w D0 11010000 00000000
MAG_SI_ZZ_H r/w D1 11010001 00111100
MAG_CFG_A r/w D4 11010100 00000101
MAG_CFG_B r/w D5 11010101 00000010
The following table provides a list of the registers for the embedded advanced features page 1. These registers
are accessible when PAGE_SEL[3:0] are set to 0001 in PAGE_SEL (02h).
Table 350. Register address map - embedded advanced features page 1
Name Type
Register address
Default Comment
Hex Binary
FSM_LC_TIMEOUT_L r/w 7A 01111010 00000000
FSM_LC_TIMEOUT_H r/w 7B 01111011 00000000
FSM_PROGRAMS r/w 7C 01111100 00000000
LSM6DSOX
Embedded advanced features pages
DS12814 - Rev 3 page 148/199
Name Type
Register address
Default Comment
Hex Binary
FSM_START_ADD_L r/w 7E 01111110 00000000
FSM_START_ADD_H r/w 7F 01111111 00000000
PEDO_CMD_REG r/w 83 10000011 00000000
PEDO_DEB_STEPS_CONF r/w 84 10000100 00001010
PEDO_SC_DELTAT_L r/w D0 11010000 00000000
PEDO_SC_DELTAT_H r/w D1 11010001 00000000
MLC_MAG_SENSITIVITY_L r/w E8 11101000 0000000
MLC_MAG_SENSITIVITY_H r/w E9 11101001 00111100
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to
the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration
values. Their content is automatically restored when the device is powered up.
Write procedure example: write value 06h register at address 84h (PEDO_DEB_STEPS_CONF) in Page 1
1. Write bit FUNC_CFG_EN = 1 in FUNC_CFG_ACCESS (01h) // Enable access to embedded functions registers
2. Write bit PAGE_WRITE = 1 in PAGE_RW (17h) register // Select write operation mode
3. Write 0001 in PAGE_SEL[3:0] field of register PAGE_SEL (02h) // Select page 1
4. Write 84h in PAGE_ADDR register (08h) // Set address
5. Write 06h in PAGE_DATA register (09h) // Set value to be written
6. Write bit PAGE_WRITE = 0 in PAGE_RW (17h) register // Write operation disabled
7. Write bit FUNC_CFG_EN = 0 in FUNC_CFG_ACCESS (01h) // Disable access to embedded functions registers
Read procedure example: read value of register at address 84h (PEDO_DEB_STEPS_CONF) in Page 1
1. Write bit FUNC_CFG_EN = 1 in FUNC_CFG_ACCESS (01h) // Enable access to embedded functions registers
2. Write bit PAGE_READ = 1 in PAGE_RW (17h) register // Select read operation mode
3. Write 0001 in PAGE_SEL[3:0] field of register PAGE_SEL (02h) // Select page 1
4. Write 84h in PAGE_ADDR register (08h) // Set address
5. Read value of PAGE_DATA register (09h) // Get register value
6. Write bit PAGE_READ = 0 in PAGE_RW (17h) register // Read operation disabled
7. Write bit FUNC_CFG_EN = 0 in FUNC_CFG_ACCESS (01h) // Disable access to embedded functions registers
Note: Steps 1 and 2 of both procedures are intended to be performed at the beginning of the procedure. Steps 6 and 7
of both procedures are intended to be performed at the end of the procedure. If the procedure involves multiple
operations, only steps 3, 4 and 5 must be repeated for each operation. If, in particular, the multiple operations
involve consecutive registers, only step 5 can be performed.
LSM6DSOX
Embedded advanced features pages
DS12814 - Rev 3 page 149/199
15 Embedded advanced features register description
15.1 Page 0 - Embedded advanced features registers
15.1.1 MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh)
External magnetometer sensitivity value register for the Finite State Machine (r/w).
This register corresponds to the LSB-to-gauss conversion value of the external magnetometer sensor. The
register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5
exponent bits; F: 10 fraction bits).
Default value of MAG_SENS[15:0] is 0x1624, corresponding to 0.0015 gauss/LSB.
Table 351. MAG_SENSITIVITY_L register
MAG_
SENS_7
MAG_
SENS_6
MAG_
SENS_5
MAG_
SENS_4
MAG_
SENS_3
MAG_
SENS_2
MAG_
SENS_1
MAG_
SENS_0
Table 352. MAG_SENSITIVITY_L register description
MAG_SENS_[7:0] External magnetometer sensitivity (LSbyte). Default value: 00100100
Table 353. MAG_SENSITIVITY_H register
MAG_
SENS_15
MAG_
SENS_14
MAG_
SENS_13
MAG_
SENS_12
MAG_
SENS_11
MAG_
SENS_10
MAG_
SENS_9
MAG_
SENS_8
Table 354. MAG_SENSITIVITY_H register description
MAG_SENS_[15:8] External magnetometer sensitivity (MSbyte). Default value: 00010110
LSM6DSOX
Embedded advanced features register description
DS12814 - Rev 3 page 150/199
15.1.2 MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h)
Offset for X-axis hard-iron compensation register (r/w).
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF
(S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 355. MAG_OFFX_L register
MAG_
OFFX_7
MAG_
OFFX_6
MAG_
OFFX_5
MAG_
OFFX_4
MAG_
OFFX_3
MAG_
OFFX_2
MAG_
OFFX_1
MAG_
OFFX_0
Table 356. MAG_OFFX_L register description
MAG_OFFX_[7:0] Offset for X-axis hard-iron compensation (LSbyte). Default value: 00000000
Table 357. MAG_OFFX_H register
MAG_
OFFX_15
MAG_
OFFX_14
MAG_
OFFX_13
MAG_
OFFX_12
MAG_
OFFX_11
MAG_
OFFX_10
MAG_
OFFX_9
MAG_
OFFX_8
Table 358. MAG_OFFX_H register description
MAG_OFFX_[15:8] Offset for X-axis hard-iron compensation (MSbyte). Default value: 00000000
15.1.3 MAG_OFFY_L (C2h) and MAG_OFFY_H (C3h)
Offset for Y-axis hard-iron compensation register (r/w).
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF
(S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 359. MAG_OFFY_L register
MAG_
OFFY_7
MAG_
OFFY_6
MAG_
OFFY_5
MAG_
OFFY_4
MAG_
OFFY_3
MAG_
OFFY_2
MAG_
OFFY_1
MAG_
OFFY_0
Table 360. MAG_OFFY_L register description
MAG_OFFY_[7:0] Offset for Y-axis hard-iron compensation (LSbyte). Default value: 00000000
Table 361. MAG_OFFY_H register
MAG_
OFFY_15
MAG_
OFFY_14
MAG_
OFFY_13
MAG_
OFFY_12
MAG_
OFFY_11
MAG_
OFFY_10
MAG_
OFFY_9
MAG_
OFFY_8
Table 362. MAG_OFFY_H register description
MAG_OFFY_[15:8] Offset for Y-axis hard-iron compensation (MSbyte). Default value: 00000000
LSM6DSOX
Page 0 - Embedded advanced features registers
DS12814 - Rev 3 page 151/199
15.1.4 MAG_OFFZ_L (C4h) and MAG_OFFZ_H (C5h)
Offset for Z-axis hard-iron compensation register (r/w).
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF
(S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 363. MAG_OFFZ_L register
MAG_
OFFZ_7
MAG_
OFFZ_6
MAG_
OFFZ_5
MAG_
OFFZ_4
MAG_
OFFZ_3
MAG_
OFFZ_2
MAG_
OFFZ_1
MAG_
OFFZ_0
Table 364. MAG_OFFZ_L register description
MAG_OFFZ_[7:0] Offset for Z-axis hard-iron compensation (LSbyte). Default value: 00000000
Table 365. MAG_OFFZ_H register
MAG_
OFFZ_15
MAG_
OFFZ_14
MAG_
OFFZ_13
MAG_
OFFZ_12
MAG_
OFFZ_11
MAG_
OFFZ_10
MAG_
OFFZ_9
MAG_
OFFZ_8
Table 366. MAG_OFFZ_H register description
MAG_OFFZ_[15:8] Offset for Z-axis hard-iron compensation (MSbyte). Default value: 00000000
15.1.5 MAG_SI_XX_L (C6h) and MAG_SI_XX_H (C7h)
Soft-iron (3x3 symmetric) matrix correction register (r/w).
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF
(S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 367. MAG_SI_XX_L register
MAG_SI_
XX_7
MAG_SI_
XX_6
MAG_SI_
XX_5
MAG_SI_
XX_4
MAG_SI_
XX_3
MAG_SI_
XX_2
MAG_SI_
XX_1
MAG_SI_
XX_0
Table 368. MAG_SI_XX_L register description
MAG_SI_XX_[7:0] Soft-iron correction row1 col1 coefficient (LSbyte). Default value: 00000000
Table 369. MAG_SI_XX_H register
MAG_SI_
XX_15
MAG_SI_
XX_14
MAG_SI_
XX_13
MAG_SI_
XX_12
MAG_SI_
XX_11
MAG_SI_
XX_10
MAG_SI_
XX_9
MAG_SI_
XX_8
Table 370. MAG_SI_XX_H register description
MAG_SI_XX_[15:8] Soft-iron correction row1 col1 coefficient (MSbyte). Default value: 00111100
LSM6DSOX
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DS12814 - Rev 3 page 152/199
15.1.6 MAG_SI_XY_L (C8h) and MAG_SI_XY_H (C9h)
Soft-iron (3x3 symmetric) matrix correction register (r/w).
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF
(S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 371. MAG_SI_XY_L register
MAG_SI_
XY_7
MAG_SI_
XY_6
MAG_SI_
XY_5
MAG_SI_
XY_4
MAG_SI_
XY_3
MAG_SI_
XY_2
MAG_SI_
XY_1
MAG_SI_
XY_0
Table 372. MAG_SI_XY_L register description
MAG_SI_XY_[7:0] Soft-iron correction row1 col2 (and row2 col1) coefficient (LSbyte). Default value: 00000000
Table 373. MAG_SI_XY_H register
MAG_SI_
XY_15
MAG_SI_
XY_14
MAG_SI_
XY_13
MAG_SI_
XY_12
MAG_SI_
XY_11
MAG_SI_
XY_10
MAG_SI_
XY_9
MAG_SI_
XY_8
Table 374. MAG_SI_XY_H register description
MAG_SI_XY_[15:8] Soft-iron correction row1 col2 (and row2 col1) coefficient (MSbyte). Default value: 00000000
15.1.7 MAG_SI_XZ_L (CAh) and MAG_SI_XZ_H (CBh)
Soft-iron (3x3 symmetric) matrix correction register (r/w).
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF
(S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 375. MAG_SI_XZ_L register
MAG_SI_
XZ_7
MAG_SI_
XZ_6
MAG_SI_
XZ_5
MAG_SI_
XZ_4
MAG_SI_
XZ_3
MAG_SI_
XZ_2
MAG_SI_
XZ_1
MAG_SI_
XZ_0
Table 376. MAG_SI_XZ_L register description
MAG_SI_XZ_[7:0] Soft-iron correction row1 col3 (and row3 col1) coefficient (LSbyte). Default value: 00000000
Table 377. MAG_SI_XZ_H register
MAG_SI_
XZ_15
MAG_SI_
XZ_14
MAG_SI_
XZ_13
MAG_SI_
XZ_12
MAG_SI_
XZ_11
MAG_SI_
XZ_10
MAG_SI_
XZ_9
MAG_SI_
XZ_8
Table 378. MAG_SI_XZ_H register description
MAG_SI_XZ_[15:8] Soft-iron correction row1 col3 (and row3 col1) coefficient (MSbyte). Default value: 00000000
LSM6DSOX
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DS12814 - Rev 3 page 153/199
15.1.8 MAG_SI_YY_L (CCh) and MAG_SI_YY_H (CDh)
Soft-iron (3x3 symmetric) matrix correction register (r/w).
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF
(S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 379. MAG_SI_YY_L register
MAG_SI_
YY_7
MAG_SI_
YY_6
MAG_SI_
YY_5
MAG_SI_
YY_4
MAG_SI_
YY_3
MAG_SI_
YY_2
MAG_SI_
YY_1
MAG_SI_
YY_0
Table 380. MAG_SI_YY_L register description
MAG_SI_YY_[7:0] Soft-iron correction row2 col2 coefficient (LSbyte). Default value: 00000000
Table 381. MAG_SI_YY_H register
MAG_SI_
YY_15
MAG_SI_
YY_14
MAG_SI_
YY_13
MAG_SI_
YY_12
MAG_SI_
YY_11
MAG_SI_
YY_10
MAG_SI_
YY_9
MAG_SI_
YY_8
Table 382. MAG_SI_YY_H register description
MAG_SI_YY_[15:8] Soft-iron correction row2 col2 coefficient (MSbyte). Default value: 00111100
15.1.9 MAG_SI_YZ_L (CEh) and MAG_SI_YZ_H (CFh)
Soft-iron (3x3 symmetric) matrix correction register (r/w).
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF
(S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 383. MAG_SI_YZ_L register
MAG_SI_
YZ_7
MAG_SI_
YZ_6
MAG_SI_
YZ_5
MAG_SI_
YZ_4
MAG_SI_
YZ_3
MAG_SI_
YZ_2
MAG_SI_
YZ_1
MAG_SI_
YZ_0
Table 384. MAG_SI_YZ_L register description
MAG_SI_YZ_[7:0] Soft-iron correction row2 col3 (and row3 col2) coefficient (LSbyte).
Default value: 00000000
Table 385. MAG_SI_YZ_H register
MAG_SI_
YZ_15
MAG_SI_
YZ_14
MAG_SI_
YZ_13
MAG_SI_
YZ_12
MAG_SI_
YZ_11
MAG_SI_
YZ_10
MAG_SI_
YZ_9
MAG_SI_
YZ_8
Table 386. MAG_SI_YZ_H register description
MAG_SI_YZ_[15:8] Soft-iron correction row2 col3 (and row3 col2) coefficient (MSbyte).
Default value: 00000000
LSM6DSOX
Page 0 - Embedded advanced features registers
DS12814 - Rev 3 page 154/199
15.1.10 MAG_SI_ZZ_L (D0h) and MAG_SI_ZZ_H (D1h)
Soft-iron (3x3 symmetric) matrix correction register (r/w).
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF
(S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 387. MAG_SI_ZZ_L register
MAG_SI_
ZZ_7
MAG_SI_
ZZ_6
MAG_SI_
ZZ_5
MAG_SI_
ZZ_4
MAG_SI_
ZZ_3
MAG_SI_
ZZ_2
MAG_SI_
ZZ_1
MAG_SI_
ZZ_0
Table 388. MAG_SI_ZZ_L register description
MAG_SI_ZZ_[7:0] Soft-iron correction row3 col3 coefficient (LSbyte). Default value: 00000000
Table 389. MAG_SI_ZZ_H register
MAG_SI_
ZZ_15
MAG_SI_
ZZ_14
MAG_SI_
ZZ_13
MAG_SI_
ZZ_12
MAG_SI_
ZZ_11
MAG_SI_
ZZ_10
MAG_SI_
ZZ_9
MAG_SI_
ZZ_8
Table 390. MAG_SI_ZZ_H register description
MAG_SI_ZZ_[15:8] Soft-iron correction row3 col3 coefficient (MSbyte). Default value: 00111100
LSM6DSOX
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15.1.11 MAG_CFG_A (D4h)
External magnetometer coordinates (Z and Y axes) rotation register (r/w).
Table 391. MAG_CFG_A register
0(1) MAG_Y_
AXIS2
MAG_Y_
AXIS1
MAG_Y_
AXIS0 0(1) MAG_Z_
AXIS2
MAG_Z_
AXIS1
MAG_Z_
AXIS0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 392. MAG_CFG_A description
MAG_Y_AXIS[2:0]
Magnetometer Y-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation)
(000: Y = Y; (default)
001: Y = -Y;
010: Y = X;
011: Y = -X;
100: Y = -Z;
101: Y = Z;
Others: Y = Y)
MAG_Z_AXIS[2:0]
Magnetometer Z-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation)
(000: Z = Y;
001: Z = -Y;
010: Z = X;
011: Z = -X;
100: Z = -Z;
101: Z = Z; (default)
Others: Z = Y)
15.1.12 MAG_CFG_B (D5h)
External magnetometer coordinates (X-axis) rotation register (r/w).
Table 393. MAG_CFG_B register
0(1) 0(1) 0(1) 0(1) 0(1) MAG_X_
AXIS2
MAG_X_
AXIS1
MAG_X_
AXIS0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 394. MAG_CFG_B description
MAG_X_AXIS[2:0]
Magnetometer X-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation)
(000: X = Y;
001: X = -Y;
010: X = X; (default)
011: X = -X;
100: X = -Z;
101: X = Z;
Others: X = Y)
LSM6DSOX
Page 0 - Embedded advanced features registers
DS12814 - Rev 3 page 156/199
15.2 Page1 - Embedded advanced features registers
15.2.1 FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh)
FSM long counter timeout register (r/w).
The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached
this value, the FSM generates an interrupt.
Table 395. FSM_LC_TIMEOUT_L register
FSM_LC_
TIMEOUT7
FSM_LC_
TIMEOUT6
FSM_LC_
TIMEOUT5
FSM_LC_
TIMEOUT4
FSM_LC_
TIMEOUT3
FSM_LC_
TIMEOUT2
FSM_LC_
TIMEOUT1
FSM_LC_
TIMEOUT0
Table 396. FSM_LC_TIMEOUT_L register description
FSM_LC_TIMEOUT[7:0] FSM long counter timeout value (LSbyte). Default value: 00000000
Table 397. FSM_LC_TIMEOUT_H register
FSM_LC_
TIMEOUT15
FSM_LC_
TIMEOUT14
FSM_LC_
TIMEOUT13
FSM_LC_
TIMEOUT12
FSM_LC_
TIMEOUT11
FSM_LC_
TIMEOUT10
FSM_LC_
TIMEOUT9
FSM_LC_
TIMEOUT8
Table 398. FSM_LC_TIMEOUT_H register description
FSM_LC_TIMEOUT[15:8] FSM long counter timeout value (MSbyte). Default value: 00000000
15.2.2 FSM_PROGRAMS (7Ch)
FSM number of programs register (r/w).
Table 399. FSM_PROGRAMS register
FSM_N_
PROG7
FSM_N_
PROG6
FSM_N_
PROG5
FSM_N_
PROG4
FSM_N_
PROG3
FSM_N_
PROG2
FSM_N_
PROG1
FSM_N_
PROG0
Table 400. FSM_PROGRAMS register description
FSM_N_PROG[7:0] Number of FSM programs; must be less than or equal to 16.
Default value: 00000000
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15.2.3 FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh)
FSM start address register (r/w). First available address is 0x033C.
Table 401. FSM_START_ADD_L register
FSM_
START7
FSM_
START6
FSM_
START5
FSM_
START4
FSM_
START3
FSM_
START2
FSM_
START1
FSM_
START0
Table 402. FSM_START_ADD_L register description
FSM_START[7:0] FSM start address value (LSbyte). Default value: 00000000
Table 403. FSM_START_ADD_H register
FSM_
START15
FSM_
START14
FSM_
START13
FSM_
START12
FSM_
START11
FSM_
START10
FSM_
START9
FSM_
START8
Table 404. FSM_START_ADD_H register description
FSM_START[15:8] FSM start address value (MSbyte). Default value: 00000000
15.2.4 PEDO_CMD_REG (83h)
Pedometer configuration register (r/w)
Table 405. PEDO_CMD_REG register
0(1) 0(1) 0(1) 0(1) CARRY_
COUNT_EN
FP_
REJECTION_EN 0(1) AD_
DET_EN
1. This bit must be set to '0' for the correct operation of the device.
Table 406. PEDO_CMD_REG register description
CARRY_COUNT_EN Set when user wants to generate interrupt only on count overflow event.
FP_REJECTION_EN Enables the false-positive rejection feature
AD_DET_EN Enables the advanced detection feature.
15.2.5 PEDO_DEB_STEPS_CONF (84h)
Pedometer debounce configuration register (r/w)
Table 407. PEDO_DEB_STEPS_CONF register
DEB_
STEP7
DEB_
STEP6
DEB_
STEP5
DEB_
STEP4
DEB_
STEP3
DEB_
STEP2
DEB_
STEP1
DEB_
STEP0
Table 408. PEDO_DEB_STEPS_CONF register description
DEB_STEP[7:0] Debounce threshold. Minimum number of steps to increment the step counter (debounce). Default value:
00001010
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15.2.6 PEDO_SC_DELTAT_L (D0h) and PEDO_SC_DELTAT_H (D1h)
Time period register for step detection on delta time (r/w)
Table 409. PEDO_SC_DELTAT_L register
PD_SC_7 PD_SC_6 PD_SC_5 PD_SC_4 PD_SC_3 PD_SC_2 PD_SC_1 PD_SC_0
Table 410. PEDO_SC_DELTAT_H register
PD_SC_15 PD_SC_14 PD_SC_13 PD_SC_12 PD_SC_11 PD_SC_10 PD_SC_9 PD_SC_8
Table 411. PEDO_SC_DELTAT_H/L register description
PD_SC_[15:0] Time period value (1LSB = 6.4 ms)
15.2.7 MLC_MAG_SENSITIVITY_L (E8h) and MLC_MAG_SENSITIVITY_H (E9h)
External magnetometer sensitivity value register for the Machine Learning Core (r/w).
This register corresponds to the LSB-to-gauss conversion value of the external magnetometer sensor. The
register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5
exponent bits; F: 10 fraction bits). Default value of MLC_MAG_S_[15:0] is 0x3C00, corresponding to 1 gauss/
LSB.
Table 412. MLC_MAG_SENSITIVITY_L register
MLC_
MAG_S_7
MLC_
MAG_S_6
MLC_
MAG_S_5
MLC_
MAG_S_4
MLC_
MAG_S_3
MLC_
MAG_S_2
MLC_
MAG_S_1
MLC_
MAG_S_0
Table 413. MLC_ MAG_SENSITIVITY_L register description
MLC_MAG_S_[7:0] External magnetometer sensitivity (LSbyte). Default value: 00000000
Table 414. MLC_MAG_SENSITIVITY_H register
MLC_
MAG_S_15
MLC_
MAG_S_14
MLC_
MAG_S_13
MLC_
MAG_S_12
MLC_
MAG_S_11
MLC_
MAG_S_10
MLC_
MAG_S_9
MLC_
MAG_S_8
Table 415. MLC_MAG_SENSITIVITY_H register description
MLC_MAG_S_[15:8] External magnetometer sensitivity (MSbyte). Default value: 00111100
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16 Sensor hub register mapping
The table given below provides a list of the registers for the sensor hub functions available in the device and the
corresponding addresses. The sensor hub registers are accessible when bit SHUB_REG_ACCESS is set to '1' in
FUNC_CFG_ACCESS (01h).
Table 416. Register address map - sensor hub registers
Name Type
Register address
Default Comment
Hex Binary
SENSOR_HUB_1 r 02 00000010 output
SENSOR_HUB_2 r 03 00000011 output
SENSOR_HUB_3 r 04 00000100 output
SENSOR_HUB_4 r 05 00000101 output
SENSOR_HUB_5 r 06 00000110 output
SENSOR_HUB_6 r 07 00000111 output
SENSOR_HUB_7 r 08 00001000 output
SENSOR_HUB_8 r 09 00001001 output
SENSOR_HUB_9 r 0A 00001010 output
SENSOR_HUB_10 r 0B 00001011 output
SENSOR_HUB_11 r 0C 00001100 output
SENSOR_HUB_12 r 0D 00001101 output
SENSOR_HUB_13 r 0E 00001110 output
SENSOR_HUB_14 r 0F 00001111 output
SENSOR_HUB_15 r 10 00010000 output
SENSOR_HUB_16 r 11 00010001 output
SENSOR_HUB_17 r 12 00010010 output
SENSOR_HUB_18 r 13 00010011 output
MASTER_CONFIG rw 14 00010100 00000000
SLV0_ADD rw 15 00010101 00000000
SLV0_SUBADD rw 16 00010110 00000000
SLV0_CONFIG rw 17 0001 0111 00000000
SLV1_ADD rw 18 00011000 00000000
SLV1_SUBADD rw 19 00011001 00000000
SLV1_CONFIG rw 1A 00011010 00000000
SLV2_ADD rw 1B 00011011 00000000
SLV2_SUBADD rw 1C 00011100 00000000
SLV2_CONFIG rw 1D 00011101 00000000
SLV3_ADD rw 1E 00011110 00000000
SLV3_SUBADD rw 1F 00011111 00000000
SLV3_CONFIG rw 20 00100000 00000000
DATAWRITE_SLV0 rw 21 00100001 00000000
STATUS_MASTER r 22 00100010 output
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Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to
the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration
values. Their content is automatically restored when the device is powered up.
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Sensor hub register mapping
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17 Sensor hub register description
17.1 SENSOR_HUB_1 (02h)
Sensor hub output register (r)
First byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 417. SENSOR_HUB_1 register
Sensor
Hub1_7
Sensor
Hub1_6
Sensor
Hub1_5
Sensor
Hub1_4
Sensor
Hub1_3
Sensor
Hub1_2
Sensor
Hub1_1
Sensor
Hub1_0
Table 418. SENSOR_HUB_1 register description
SensorHub1[7:0] First byte associated to external sensors
17.2 SENSOR_HUB_2 (03h)
Sensor hub output register (r)
Second byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 419. SENSOR_HUB_2 register
Sensor
Hub2_7
Sensor
Hub2_6
Sensor
Hub2_5
Sensor
Hub2_4
Sensor
Hub2_3
Sensor
Hub2_2
Sensor
Hub2_1
Sensor
Hub2_0
Table 420. SENSOR_HUB_2 register description
SensorHub2[7:0] Second byte associated to external sensors
17.3 SENSOR_HUB_3 (04h)
Sensor hub output register (r)
Third byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 421. SENSOR_HUB_3 register
Sensor
Hub3_7
Sensor
Hub3_6
Sensor
Hub3_5
Sensor
Hub3_4
Sensor
Hub3_3
Sensor
Hub3_2
Sensor
Hub3_1
Sensor
Hub3_0
Table 422. SENSOR_HUB_3 register description
SensorHub3[7:0] Third byte associated to external sensors
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17.4 SENSOR_HUB_4 (05h)
Sensor hub output register (r)
Fourth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 423. SENSOR_HUB_4 register
Sensor
Hub4_7
Sensor
Hub4_6
Sensor
Hub4_5
Sensor
Hub4_4
Sensor
Hub4_3
Sensor
Hub4_2
Sensor
Hub4_1
Sensor
Hub4_0
Table 424. SENSOR_HUB_4 register description
SensorHub4[7:0] Fourth byte associated to external sensors
17.5 SENSOR_HUB_5 (06h)
Sensor hub output register (r)
Fifth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 425. SENSOR_HUB_5 register
Sensor
Hub5_7
Sensor
Hub5_6
Sensor
Hub5_5
Sensor
Hub5_4
Sensor
Hub5_3
Sensor
Hub5_2
Sensor
Hub5_1
Sensor
Hub5_0
Table 426. SENSOR_HUB_5 register description
SensorHub5[7:0] Fifth byte associated to external sensors
17.6 SENSOR_HUB_6 (07h)
Sensor hub output register (r)
Sixth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 427. SENSOR_HUB_6 register
Sensor
Hub6_7
Sensor
Hub6_6
Sensor
Hub6_5
Sensor
Hub6_4
Sensor
Hub6_3
Sensor
Hub6_2
Sensor
Hub6_1
Sensor
Hub6_0
Table 428. SENSOR_HUB_6 register description
SensorHub6[7:0] Sixth byte associated to external sensors
LSM6DSOX
SENSOR_HUB_4 (05h)
DS12814 - Rev 3 page 163/199
17.7 SENSOR_HUB_7 (08h)
Sensor hub output register (r)
Seventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 429. SENSOR_HUB_7 register
Sensor
Hub7_7
Sensor
Hub7_6
Sensor
Hub7_5
Sensor
Hub7_4
Sensor
Hub7_3
Sensor
Hub7_2
Sensor
Hub7_1
Sensor
Hub7_0
Table 430. SENSOR_HUB_7 register description
SensorHub7[7:0] Seventh byte associated to external sensors
17.8 SENSOR_HUB_8 (09h)
Sensor hub output register (r)
Eighth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 431. SENSOR_HUB_8 register
Sensor
Hub8_7
Sensor
Hub8_6
Sensor
Hub8_5
Sensor
Hub8_4
Sensor
Hub8_3
Sensor
Hub8_2
Sensor
Hub8_1
Sensor
Hub8_0
Table 432. SENSOR_HUB_8 register description
SensorHub8[7:0] Eighth byte associated to external sensors
17.9 SENSOR_HUB_9 (0Ah)
Sensor hub output register (r)
Ninth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 433. SENSOR_HUB_9 register
Sensor
Hub9_7
Sensor
Hub9_6
Sensor
Hub9_5
Sensor
Hub9_4
Sensor
Hub9_3
Sensor
Hub9_2
Sensor
Hub9_1
Sensor
Hub9_0
Table 434. SENSOR_HUB_9 register description
SensorHub9[7:0] Ninth byte associated to external sensors
LSM6DSOX
SENSOR_HUB_7 (08h)
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17.10 SENSOR_HUB_10 (0Bh)
Sensor hub output register (r)
Tenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 435. SENSOR_HUB_10 register
Sensor
Hub10_7
Sensor
Hub10_6
Sensor
Hub10_5
Sensor
Hub10_4
Sensor
Hub10_3
Sensor
Hub10_2
Sensor
Hub10_1
Sensor
Hub10_0
Table 436. SENSOR_HUB_10 register description
SensorHub10[7:0] Tenth byte associated to external sensors
17.11 SENSOR_HUB_11 (0Ch)
Sensor hub output register (r)
Eleventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 437. SENSOR_HUB_11 register
Sensor
Hub11_7
Sensor
Hub11_6
Sensor
Hub11_5
Sensor
Hub11_4
Sensor
Hub11_3
Sensor
Hub11_2
Sensor
Hub11_1
Sensor
Hub11_0
Table 438. SENSOR_HUB_11 register description
SensorHub11[7:0] Eleventh byte associated to external sensors
17.12 SENSOR_HUB_12 (0Dh)
Sensor hub output register (r)
Twelfth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 439. SENSOR_HUB_12 register
Sensor
Hub12_7
Sensor
Hub12_6
Sensor
Hub12_5
Sensor
Hub12_4
Sensor
Hub12_3
Sensor
Hub12_2
Sensor
Hub12_1
Sensor
Hub12_0
Table 440. SENSOR_HUB_12 register description
SensorHub12[7:0] Twelfth byte associated to external sensors
LSM6DSOX
SENSOR_HUB_10 (0Bh)
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17.13 SENSOR_HUB_13 (0Eh)
Sensor hub output register (r)
Thirteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 441. SENSOR_HUB_13 register
Sensor
Hub13_7
Sensor
Hub13_6
Sensor
Hub13_5
Sensor
Hub13_4
Sensor
Hub13_3
Sensor
Hub13_2
Sensor
Hub13_1
Sensor
Hub13_0
Table 442. SENSOR_HUB_13 register description
SensorHub13[7:0] Thirteenth byte associated to external sensors
17.14 SENSOR_HUB_14 (0Fh)
Sensor hub output register (r)
Fourteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 443. SENSOR_HUB_14 register
Sensor
Hub14_7
Sensor
Hub14_6
Sensor
Hub14_5
Sensor
Hub14_4
Sensor
Hub14_3
Sensor
Hub14_2
Sensor
Hub14_1
Sensor
Hub14_0
Table 444. SENSOR_HUB_14 register description
SensorHub14[7:0] Fourteenth byte associated to external sensors
17.15 SENSOR_HUB_15 (10h)
Sensor hub output register (r)
Fifteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 445. SENSOR_HUB_15 register
Sensor
Hub15_7
Sensor
Hub15_6
Sensor
Hub15_5
Sensor
Hub15_4
Sensor
Hub15_3
Sensor
Hub15_2
Sensor
Hub15_1
Sensor
Hub15_0
Table 446. SENSOR_HUB_15 register description
SensorHub15[7:0] Fifteenth byte associated to external sensors
LSM6DSOX
SENSOR_HUB_13 (0Eh)
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17.16 SENSOR_HUB_16 (11h)
Sensor hub output register (r)
Sixteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 447. SENSOR_HUB_16 register
Sensor
Hub16_7
Sensor
Hub16_6
Sensor
Hub16_5
Sensor
Hub16_4
Sensor
Hub16_3
Sensor
Hub16_2
Sensor
Hub16_1
Sensor
Hub16_0
Table 448. SENSOR_HUB_16 register description
SensorHub16[7:0] Sixteenth byte associated to external sensors
17.17 SENSOR_HUB_17 (12h)
Sensor hub output register (r)
Seventeenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 449. SENSOR_HUB_17 register
Sensor
Hub17_7
Sensor
Hub17_6
Sensor
Hub17_5
Sensor
Hub17_4
Sensor
Hub17_3
Sensor
Hub17_2
Sensor
Hub17_1
Sensor
Hub17_0
Table 450. SENSOR_HUB_17 register description
SensorHub17[7:0] Seventeenth byte associated to external sensors
17.18 SENSOR_HUB_18 (13h)
Sensor hub output register (r)
Eighteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 451. SENSOR_HUB_17 register
Sensor
Hub18_7
Sensor
Hub18_6
Sensor
Hub18_5
Sensor
Hub18_4
Sensor
Hub18_3
Sensor
Hub18_2
Sensor
Hub18_1
Sensor
Hub18_0
Table 452. SENSOR_HUB_17 register description
SensorHub18[7:0] Eighteenth byte associated to external sensors
LSM6DSOX
SENSOR_HUB_16 (11h)
DS12814 - Rev 3 page 167/199
17.19 MASTER_CONFIG (14h)
Master configuration register (r/w)
Table 453. MASTER_CONFIG register
RST_MASTER
_REGS
WRITE_
ONCE
START_
CONFIG
PASS_
THROUGH_
MODE
SHUB_
PU_EN MASTER_ON AUX_
SENS_ON1
AUX_
SENS_ON0
Table 454. MASTER_CONFIG register description
RST_MASTER_REGS Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. Default value: 0
WRITE_ONCE
Slave 0 write operation is performed only at the first sensor hub cycle.
Default value: 0
(0: write operation for each sensor hub cycle;
1: write operation only for the first sensor hub cycle)
START_CONFIG
Sensor hub trigger signal selection. Default value: 0
(0: sensor hub trigger signal is the accelerometer/gyro data-ready;
1: sensor hub trigger signal external from INT2 pin)
PASS_THROUGH_MODE
I²C interface pass-through. Default value: 0
(0: pass-through disabled;
1: pass-through enabled, main I²C line is short-circuited with the auxiliary line)
SHUB_PU_EN
Master I²C pull-up enable. Default value: 0
(0: internal pull-up on auxiliary I²C line disabled;
1: internal pull-up on auxiliary I²C line enabled)
MASTER_ON Sensor hub I2C master enable. Default: 0
(0: master I2C of sensor hub disabled; 1: master I2C of sensor hub enabled)
AUX_SENS_ON[1:0]
Number of external sensors to be read by the sensor hub.
(00: one sensor (default);
01: two sensors;
10: three sensors;
11: four sensors)
LSM6DSOX
MASTER_CONFIG (14h)
DS12814 - Rev 3 page 168/199
17.20 SLV0_ADD (15h)
I2C slave address of the first external sensor (Sensor 1) register (r/w).
Table 455. SLV0_ADD register
slave0_add6 slave0_add5 slave0_add4 slave0_add3 slave0_add2 slave0_add1 slave0_add0 rw_0
Table 456. SLV_ADD register description
slave0_add[6:0] I2C slave address of Sensor1 that can be read by the sensor hub.
Default value: 0000000
rw_0 Read/write operation on Sensor 1. Default value: 0
(0: write operation; 1: read operation)
17.21 SLV0_SUBADD (16h)
Address of register on the first external sensor (Sensor 1) register (r/w).
Table 457. SLV0_SUBADD register
slave0_reg7 slave0_reg6 slave0_reg5 slave0_reg4 slave0_reg3 slave0_reg2 slave0_reg1 slave0_reg0
Table 458. SLV0_SUBADD register description
slave0_reg[7:0] Address of register on Sensor1 that has to be read/written according to the rw_0 bit value in SLV0_ADD
(15h). Default value: 00000000
17.22 SLAVE0_CONFIG (17h)
First external sensor (Sensor1) configuration and sensor hub settings register (r/w).
Table 459. SLAVE0_CONFIG register
SHUB_
ODR_1
SHUB_
ODR_0 0(1) 0(1) BATCH_EXT_
SENS_0_EN
Slave0_
numop2
Slave0_
numop1
Slave0_
numop0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 460. SLAVE0_CONFIG register description
SHUB_ODR_[1:0]
Rate at which the master communicates. Default value: 00
(00: 104 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 104
Hz);
01: 52 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 52 Hz);
10: 26 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 26 Hz);
11: 12.5 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 12.5
Hz)
BATCH_EXT_SENS_0_EN Enable FIFO batching data of first slave. Default value: 0
Slave0_numop[2:0] Number of read operations on Sensor 1. Default value: 000
LSM6DSOX
SLV0_ADD (15h)
DS12814 - Rev 3 page 169/199
17.23 SLV1_ADD (18h)
I²C slave address of the second external sensor (Sensor 2) register (r/w).
Table 461. SLV1_ADD register
Slave1_add6 Slave1_add5 Slave1_add4 Slave1_add3 Slave1_add2 Slave1_add1 Slave1_add0 r_1
Table 462. SLV1_ADD register description
Slave1_add[6:0] I²C slave address of Sensor 2 that can be read by the sensor hub.
Default value: 0000000
r_1 Read operation on Sensor 2 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
17.24 SLV1_SUBADD (19h)
Address of register on the second external sensor (Sensor 2) register (r/w).
Table 463. SLV1_SUBADD register
Slave1_reg7 Slave1_reg6 Slave1_reg5 Slave1_reg4 Slave1_reg3 Slave1_reg2 Slave1_reg1 Slave1_reg0
Table 464. SLV1_SUBADD register description
Slave1_reg[7:0] Address of register on Sensor 2 that has to be read/written according to the r_1 bit value in SLV1_ADD
(18h).
17.25 SLAVE1_CONFIG (1Ah)
Second external sensor (Sensor 2) configuration register (r/w).
Table 465. SLAVE1_CONFIG register
0(1) 0(1) 0(1) 0(1) BATCH_EXT_
SENS_1_EN
Slave1_
numop2
Slave1_
numop1
Slave1_
numop0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 466. SLAVE1_CONFIG register description
BATCH_EXT_SENS_1_EN Enable FIFO batching data of second slave. Default value: 0
Slave1_numop[2:0] Number of read operations on Sensor 2. Default value: 000
LSM6DSOX
SLV1_ADD (18h)
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17.26 SLV2_ADD (1Bh)
I2C slave address of the third external sensor (Sensor 3) register (r/w).
Table 467. SLV2_ADD register
Slave2_add6 Slave2_add5 Slave2_add4 Slave2_add3 Slave2_add2 Slave2_add1 Slave2_add0 r_2
Table 468. SLV2_ADD register description
Slave2_add[6:0] I2C slave address of Sensor 3 that can be read by the sensor hub.
r_2 Read operation on Sensor 3 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
17.27 SLV2_SUBADD (1Ch)
Address of register on the third external sensor (Sensor 3) register (r/w).
Table 469. SLV2_SUBADD register
Slave2_reg7 Slave2_reg6 Slave2_reg5 Slave2_reg4 Slave2_reg3 Slave2_reg2 Slave2_reg1 Slave2_reg0
Table 470. SLV2_SUBADD register description
Slave2_reg[7:0] Address of register on Sensor 3 that has to be read/written according to the r_2 bit value in SLV2_ADD
(1Bh).
17.28 SLAVE2_CONFIG (1Dh)
Third external sensor (Sensor 3) configuration register (r/w).
Table 471. SLAVE2_CONFIG register
0(1) 0(1) 0(1) 0(1) BATCH_EXT_
SENS_2_EN
Slave2_
numop2
Slave2_
numop1
Slave2_
numop0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 472. SLAVE2_CONFIG register description
BATCH_EXT_SENS_2_EN Enable FIFO batching data of third slave. Default value: 0
Slave2_numop[2:0] Number of read operations on Sensor 3. Default value: 000
LSM6DSOX
SLV2_ADD (1Bh)
DS12814 - Rev 3 page 171/199
17.29 SLV3_ADD (1Eh)
I²C slave address of the fourth external sensor (Sensor 4) register (r/w).
Table 473. SLV3_ADD register
Slave3_add6 Slave3_add5 Slave3_add4 Slave3_add3 Slave3_add2 Slave3_add1 Slave3_add0 r_3
Table 474. SLV3_ADD register description
Slave3_add[6:0] I2C slave address of Sensor 4 that can be read by the sensor hub.
r_3 Read operation on Sensor 4 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
17.30 SLV3_SUBADD (1Fh)
Address of register on the fourth external sensor (Sensor 4) register (r/w).
Table 475. SLV3_SUBADD register
Slave3_reg7 Slave3_reg6 Slave3_reg5 Slave3_reg4 Slave3_reg3 Slave3_reg2 Slave3_reg1 Slave3_reg0
Table 476. SLV3_SUBADD register description
Slave3_reg[7:0] Address of register on Sensor 4 that has to be read according to the r_3 bit value in SLV3_ADD (1Eh).
17.31 SLAVE3_CONFIG (20h)
Fourth external sensor (Sensor 4) configuration register (r/w).
Table 477. SLAVE3_CONFIG register
0(1) 0(1) 0(1) 0(1) BATCH_EXT
_SENS_3_EN
Slave3_
numop2
Slave3_
numop1
Slave3_
numop0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 478. SLAVE3_CONFIG register description
BATCH_EXT_SENS_3_EN Enable FIFO batching data of fourth slave. Default value: 0
Slave3_numop[2:0] Number of read operations on Sensor 4. Default value: 000
LSM6DSOX
SLV3_ADD (1Eh)
DS12814 - Rev 3 page 172/199
17.32 DATAWRITE_SLV0 (21h)
Data to be written into the slave device register (r/w).
Table 479. DATAWRITE_SLV0 register
Slave0_
dataw7
Slave0_
dataw6
Slave0_
dataw5
Slave0_
dataw4
Slave0_
dataw3
Slave0_
dataw2
Slave0_
dataw1
Slave0_
dataw0
Table 480. DATAWRITE_SLV0 register description
Slave0_dataw[7:0] Data to be written into the slave 0 device according to the rw_0 bit in register SLV0_ADD (15h).
Default value: 00000000
17.33 STATUS_MASTER (22h)
Sensor hub source register (r).
Table 481. STATUS_MASTER register
WR_ONCE
_DONE
SLAVE3_
NACK
SLAVE2_
NACK
SLAVE1_
NACK
SLAVE0_
NACK 0 0 SENS_HUB
_ENDOP
Table 482. STATUS_MASTER register description
WR_ONCE_DONE When the bit WRITE_ONCE in MASTER_CONFIG (14h) is configured as 1, this bit is set to 1 when the
write operation on slave 0 has been performed and completed. Default value: 0
SLAVE3_NACK This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0
SLAVE2_NACK This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0
SLAVE1_NACK This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0
SLAVE0_NACK This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0
SENS_HUB_ENDOP
Sensor hub communication status. Default value: 0
(0: sensor hub communication not concluded;
1: sensor hub communication concluded)
LSM6DSOX
DATAWRITE_SLV0 (21h)
DS12814 - Rev 3 page 173/199
18 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and "Green" standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Land pattern and soldering recommendations are available at www.st.com/mems.
LSM6DSOX
Soldering information
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19 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
19.1 LGA-14L package information
Figure 28. LGA-14L 2.5x3x0.86 mm package outline and mechanical data
W
L
H4x (0.1)
14x 0.475±0.05
14x 0.25±0.05
0.5
0.5
Pin1 indicator
Pin1 indicator
BOTTOM VIEWTOP VIEW
1.5
1
Dimensions are in millimeter unless otherwise specified
General tolerance is +/-0.1mm unless otherwise specified
OUTER DIMENSIONS
ITEM
DIMENSION [mm]
TOLERANCE [mm]
1.0± 05.2 ]L[ htgneL
1.0± 00.3 ]W[ htdiW
XAM 68.0 ]H[ thgieH
DM00249496_1
LSM6DSOX
Package information
DS12814 - Rev 3 page 175/199
19.2 LGA-14 packing information
Figure 29. Carrier tape information for LGA-14 package
Figure 30. LGA-14 package orientation in carrier tape
LSM6DSOX
LGA-14 packing information
DS12814 - Rev 3 page 176/199
Figure 31. Reel information for carrier tape of LGA-14 package
AD
B
Fu ll rad ius Tape slot
in core for
tape start
2.5mm min. width
G measured at hub
C
N
40mm min.
Access hole at
slot location
T
Table 483. Reel dimensions for carrier tape of LGA-14 package
Reel dimensions (mm)
A (max) 330
B (min) 1.5
C 13 ±0.25
D (min) 20.2
N (min) 60
G 12.4 +2/-0
T (max) 18.4
LSM6DSOX
LGA-14 packing information
DS12814 - Rev 3 page 177/199
Revision history
Table 484. Document revision history
Date Revision Changes
30-Oct-2018 1 Initial release
12-Dec-2018 2 First public release
25-Jan-2019 3
Added product label indicating ST's commitment to sustainable technology
Added Section 2.4 Machine Learning Core
Updated footnotes in Table 4. Temperature sensor characteristics
Added registers concerning Machine Learning Core
Updated EMB_FUNC_ODR_CFG_B (5Fh)
Updated EMB_FUNC_ODR_CFG_C (60h)
LSM6DSOX
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Contents
1Overview ..........................................................................3
2Embedded low-power features .....................................................4
2.1 Tilt detection...................................................................4
2.2 Significant Motion Detection .....................................................4
2.3 Finite State Machine ............................................................5
2.4 Machine Learning Core .........................................................5
3Pin description ....................................................................7
3.1 Pin connections ................................................................8
4Module specifications ............................................................10
4.1 Mechanical characteristics......................................................10
4.2 Electrical characteristics........................................................13
4.3 Temperature sensor characteristics ..............................................13
4.4 Communication interface characteristics ..........................................14
4.4.1 SPI - serial peripheral interface .............................................14
4.4.2 I²C - inter-IC control interface ..............................................15
4.5 Absolute maximum ratings......................................................16
4.6 Terminology ..................................................................17
4.6.1 Sensitivity .............................................................17
4.6.2 Zero-g and zero-rate level.................................................17
5Digital interfaces .................................................................18
5.1 I²C/SPI interface ..............................................................18
5.1.1 I²C serial interface.......................................................18
5.1.2 I²C operation ...........................................................18
5.1.3 SPI bus interface........................................................20
5.2 MIPI I3CSM interface ..........................................................22
5.2.1 MIPI I3CSM slave interface................................................23
5.2.2 MIPI I3CSM CCC supported commands......................................23
5.3 I²C/I3C coexistence in LSM6DSOX ..............................................25
5.4 Master I²C interface ...........................................................26
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5.5 Auxiliary SPI interface..........................................................26
6Functionality .....................................................................27
6.1 Operating modes..............................................................27
6.2 Accelerometer power modes ....................................................27
6.2.1 Accelerometer ultra-low-power mode ........................................27
6.3 Gyroscope power modes .......................................................27
6.4 Block diagram of filters .........................................................27
6.4.1 Block diagrams of the accelerometer filters....................................28
6.4.2 Block diagrams of the gyroscope filters.......................................31
6.5 OIS .........................................................................33
6.5.1 Enabling OIS functionality and connection schemes .............................33
6.6 FIFO ........................................................................36
6.6.1 Bypass mode ..........................................................36
6.6.2 FIFO mode ............................................................36
6.6.3 Continuous mode .......................................................37
6.6.4 Continuous-to-FIFO mode.................................................37
6.6.5 Bypass-to-Continuous mode...............................................37
6.6.6 Bypass-to-FIFO mode....................................................37
6.6.7 FIFO reading procedure ..................................................38
7Application hints .................................................................39
7.1 LSM6DSOX electrical connections in Mode 1 ......................................39
7.2 LSM6DSOX electrical connections in Mode 2 ......................................39
7.3 LSM6DSOX electrical connections in Mode 3 and Mode 4 ...........................40
8Register mapping.................................................................44
9Register description ..............................................................47
9.1 FUNC_CFG_ACCESS (01h) ....................................................47
9.2 PIN_CTRL (02h) ..............................................................48
9.3 S4S_TPH_L (04h).............................................................48
9.4 S4S_TPH_H (05h) ............................................................49
9.5 S4S_RR (06h) ................................................................49
9.6 FIFO_CTRL1 (07h) ............................................................49
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9.7 FIFO_CTRL2 (08h) ............................................................50
9.8 FIFO_CTRL3 (09h) ............................................................51
9.9 FIFO_CTRL4 (0Ah)............................................................52
9.10 COUNTER_BDR_REG1 (0Bh) ..................................................53
9.11 COUNTER_BDR_REG2 (0Ch) ..................................................53
9.12 INT1_CTRL (0Dh).............................................................54
9.13 INT2_CTRL (0Eh) .............................................................55
9.14 WHO_AM_I (0Fh) .............................................................55
9.15 CTRL1_XL (10h) ..............................................................56
9.16 CTRL2_G (11h) ...............................................................57
9.17 CTRL3_C (12h) ...............................................................58
9.18 CTRL4_C (13h) ...............................................................59
9.19 CTRL5_C (14h) ...............................................................60
9.20 CTRL6_C (15h) ...............................................................60
9.21 CTRL7_G (16h)...............................................................61
9.22 CTRL8_XL (17h) ..............................................................63
9.23 CTRL9_XL (18h) ..............................................................65
9.24 CTRL10_C (19h)..............................................................65
9.25 ALL_INT_SRC (1Ah) ..........................................................66
9.26 WAKE_UP_SRC (1Bh).........................................................67
9.27 TAP_SRC (1Ch) ..............................................................68
9.28 D6D_SRC (1Dh) ..............................................................69
9.29 STATUS_REG (1Eh)...........................................................69
9.30 OUT_TEMP_L (20h), OUT_TEMP_H (21h)........................................70
9.31 OUTX_L_G (22h) and OUTX_H_G (23h) .........................................70
9.32 OUTY_L_G (24h) and OUTY_H_G (25h) .........................................71
9.33 OUTZ_L_G (26h) and OUTZ_H_G (27h)..........................................71
9.34 OUTX_L_A (28h) and OUTX_H_A (29h) ..........................................72
9.35 OUTY_L_A (2Ah) and OUTY_H_A (2Bh) .........................................72
9.36 OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) .........................................73
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9.37 EMB_FUNC_STATUS_MAINPAGE (35h) .........................................73
9.38 FSM_STATUS_A_MAINPAGE (36h) .............................................74
9.39 FSM_STATUS_B_MAINPAGE (37h) .............................................75
9.40 MLC_STATUS_MAINPAGE (38h)................................................76
9.41 STATUS_MASTER_MAINPAGE (39h)............................................76
9.42 FIFO_STATUS1 (3Ah) .........................................................76
9.43 FIFO_STATUS2 (3Bh) .........................................................77
9.44 TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 78
9.45 UI_STATUS_REG_OIS (49h) ...................................................78
9.46 UI_OUTX_L_G_OIS (4Ah) and UI_OUTX_H_G_OIS (4Bh) ..........................79
9.47 UI_OUTY_L_G_OIS (4Ch) and UI_OUTY_H_G_OIS (4Dh) ..........................79
9.48 UI_OUTZ_L_G_OIS (4Eh) and UI_OUTZ_H_G_OIS (4Fh) ..........................80
9.49 UI_OUTX_L_A_OIS (50h) and UI_OUTX_H_A_OIS (51h) ...........................80
9.50 UI_OUTY_L_A_OIS (52h) and UI_OUTY_H_A_OIS (53h) ...........................81
9.51 UI_OUTZ_L_A_OIS (54h) and UI_OUTZ_H_A_OIS (55h) ...........................81
9.52 TAP_CFG0 (56h)..............................................................82
9.53 TAP_CFG1 (57h)..............................................................83
9.54 TAP_CFG2 (58h)..............................................................83
9.55 TAP_THS_6D (59h) ...........................................................83
9.56 INT_DUR2 (5Ah)..............................................................85
9.57 WAKE_UP_THS (5Bh) .........................................................85
9.58 WAKE_UP_DUR (5Ch) ........................................................86
9.59 FREE_FALL (5Dh) ............................................................87
9.60 MD1_CFG (5Eh) ..............................................................88
9.61 MD2_CFG (5Fh) ..............................................................89
9.62 S4S_ST_CMD_CODE (60h) ....................................................90
9.63 S4S_DT_REG (61h) ...........................................................90
9.64 I3C_BUS_AVB (62h)...........................................................90
9.65 INTERNAL_FREQ_FINE (63h) ..................................................91
9.66 UI_INT_OIS (6Fh).............................................................91
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9.67 UI_CTRL1_OIS (70h) ..........................................................92
9.68 UI_CTRL2_OIS (71h) ..........................................................93
9.69 UI_CTRL3_OIS (72h) ..........................................................94
9.70 X_OFS_USR (73h) ............................................................96
9.71 Y_OFS_USR (74h) ............................................................96
9.72 Z_OFS_USR (75h) ............................................................96
9.73 FIFO_DATA_OUT_TAG (78h) ...................................................97
9.74 FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) .....................98
9.75 FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch) .....................98
9.76 FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh) .....................98
10 SPI2 register mapping ............................................................99
11 SPI2 register description........................................................ 100
11.1 SPI2_WHO_AM_I (0Fh).......................................................100
11.2 SPI2_STATUS_REG_OIS (1Eh) ................................................100
11.3 SPI2_OUT_TEMP_L (20h) and SPI2_OUT_TEMP_H (21h).........................100
11.4 SPI2_OUTX_L_G_OIS (22h) and SPI2_OUTX_H_G_OIS (23h) .....................101
11.5 SPI2_OUTY_L_G_OIS (24h) and SPI2_OUTY_H_G_OIS (25h) .....................101
11.6 SPI2_OUTZ_L_G_OIS (26h) and SPI2_OUTZ_H_G_OIS (27h) .....................102
11.7 SPI2_OUTX_L_A_OIS (28h) and SPI2_OUTX_H_A_OIS (29h) .....................102
11.8 SPI2_OUTY_L_A_OIS (2Ah) and SPI2_OUTY_H_A_OIS (2Bh) .....................103
11.9 SPI2_OUTZ_L_A_OIS (2Ch) and SPI2_OUTZ_H_A_OIS (2Dh) .....................103
11.10 SPI2_INT_OIS (6Fh) .........................................................104
11.11 SPI2_CTRL1_OIS (70h).......................................................105
11.12 SPI2_CTRL2_OIS (71h).......................................................106
11.13 SPI2_CTRL3_OIS (72h).......................................................107
12 Embedded functions register mapping .......................................... 108
13 Embedded functions register description ....................................... 110
13.1 PAGE_SEL (02h) ............................................................110
13.2 EMB_FUNC_EN_A (04h)......................................................110
13.3 EMB_FUNC_EN_B (05h)......................................................111
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13.4 PAGE_ADDRESS (08h).......................................................111
13.5 PAGE_VALUE (09h) ..........................................................112
13.6 EMB_FUNC_INT1 (0Ah) ......................................................112
13.7 FSM_INT1_A (0Bh) ..........................................................113
13.8 FSM_INT1_B (0Ch) ..........................................................114
13.9 MLC_INT1 (0Dh).............................................................115
13.10 EMB_FUNC_INT2 (0Eh) ......................................................116
13.11 FSM_INT2_A (0Fh)...........................................................117
13.12 FSM_INT2_B (10h)...........................................................118
13.13 MLC_INT2 (11h) .............................................................119
13.14 EMB_FUNC_STATUS (12h) ...................................................120
13.15 FSM_STATUS_A (13h)........................................................121
13.16 FSM_STATUS_B (14h)........................................................122
13.17 MLC_STATUS (15h) ..........................................................123
13.18 PAGE_RW (17h) .............................................................124
13.19 EMB_FUNC_FIFO_CFG (44h) .................................................124
13.20 FSM_ENABLE_A (46h) .......................................................125
13.21 FSM_ENABLE_B (47h) .......................................................125
13.22 FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h)..............126
13.23 FSM_LONG_COUNTER_CLEAR (4Ah) .........................................126
13.24 FSM_OUTS1 (4Ch) ..........................................................127
13.25 FSM_OUTS2 (4Dh) ..........................................................128
13.26 FSM_OUTS3 (4Eh)...........................................................129
13.27 FSM_OUTS4 (4Fh)...........................................................130
13.28 FSM_OUTS5 (50h) ...........................................................131
13.29 FSM_OUTS6 (51h) ...........................................................132
13.30 FSM_OUTS7 (52h) ...........................................................133
13.31 FSM_OUTS8 (53h) ...........................................................134
13.32 FSM_OUTS9 (54h) ...........................................................135
13.33 FSM_OUTS10 (55h)..........................................................136
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13.34 FSM_OUTS11 (56h) ..........................................................137
13.35 FSM_OUTS12 (57h)..........................................................138
13.36 FSM_OUTS13 (58h)..........................................................139
13.37 FSM_OUTS14 (59h)..........................................................140
13.38 FSM_OUTS15 (5Ah) .........................................................141
13.39 FSM_OUTS16 (5Bh) .........................................................142
13.40 EMB_FUNC_ODR_CFG_B (5Fh)...............................................143
13.41 EMB_FUNC_ODR_CFG_C (60h)...............................................143
13.42 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h) .........................144
13.43 EMB_FUNC_SRC (64h).......................................................144
13.44 EMB_FUNC_INIT_A (66h).....................................................145
13.45 EMB_FUNC_INIT_B (67h).....................................................145
13.46 MLC0_SRC (70h) ............................................................145
13.47 MLC1_SRC (71h) ............................................................146
13.48 MLC2_SRC (72h) ............................................................146
13.49 MLC3_SRC (73h) ............................................................146
13.50 MLC4_SRC (74h) ............................................................147
13.51 MLC5_SRC (75h) ............................................................147
13.52 MLC6_SRC (76h) ............................................................147
13.53 MLC7_SRC (77h) ............................................................147
14 Embedded advanced features pages ............................................ 148
15 Embedded advanced features register description .............................. 150
15.1 Page 0 - Embedded advanced features registers..................................150
15.1.1 MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh) ..................150
15.1.2 MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h)...............................151
15.1.3 MAG_OFFY_L (C2h) and MAG_OFFY_H (C3h)...............................151
15.1.4 MAG_OFFZ_L (C4h) and MAG_OFFZ_H (C5h) ...............................152
15.1.5 MAG_SI_XX_L (C6h) and MAG_SI_XX_H (C7h) ..............................152
15.1.6 MAG_SI_XY_L (C8h) and MAG_SI_XY_H (C9h) ..............................153
15.1.7 MAG_SI_XZ_L (CAh) and MAG_SI_XZ_H (CBh) ..............................153
15.1.8 MAG_SI_YY_L (CCh) and MAG_SI_YY_H (CDh) .............................154
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15.1.9 MAG_SI_YZ_L (CEh) and MAG_SI_YZ_H (CFh) ..............................154
15.1.10 MAG_SI_ZZ_L (D0h) and MAG_SI_ZZ_H (D1h) ..............................155
15.1.11 MAG_CFG_A (D4h) ....................................................156
15.1.12 MAG_CFG_B (D5h) ....................................................156
15.2 Page1 - Embedded advanced features registers ..................................156
15.2.1 FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh)...................157
15.2.2 FSM_PROGRAMS (7Ch) ................................................157
15.2.3 FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh) ....................158
15.2.4 PEDO_CMD_REG (83h).................................................158
15.2.5 PEDO_DEB_STEPS_CONF (84h) .........................................158
15.2.6 PEDO_SC_DELTAT_L (D0h) and PEDO_SC_DELTAT_H (D1h) ..................158
15.2.7 MLC_MAG_SENSITIVITY_L (E8h) and MLC_MAG_SENSITIVITY_H (E9h) .........159
16 Sensor hub register mapping ................................................... 160
17 Sensor hub register description................................................. 162
17.1 SENSOR_HUB_1 (02h) .......................................................162
17.2 SENSOR_HUB_2 (03h) .......................................................162
17.3 SENSOR_HUB_3 (04h) .......................................................162
17.4 SENSOR_HUB_4 (05h) .......................................................163
17.5 SENSOR_HUB_5 (06h) .......................................................163
17.6 SENSOR_HUB_6 (07h) .......................................................163
17.7 SENSOR_HUB_7 (08h) .......................................................164
17.8 SENSOR_HUB_8 (09h) .......................................................164
17.9 SENSOR_HUB_9 (0Ah).......................................................164
17.10 SENSOR_HUB_10 (0Bh)......................................................165
17.11 SENSOR_HUB_11 (0Ch)......................................................165
17.12 SENSOR_HUB_12 (0Dh)......................................................165
17.13 SENSOR_HUB_13 (0Eh)......................................................166
17.14 SENSOR_HUB_14 (0Fh)......................................................166
17.15 SENSOR_HUB_15 (10h) ......................................................166
17.16 SENSOR_HUB_16 (11h) ......................................................167
17.17 SENSOR_HUB_17 (12h) ......................................................167
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17.18 SENSOR_HUB_18 (13h) ......................................................167
17.19 MASTER_CONFIG (14h)......................................................168
17.20 SLV0_ADD (15h).............................................................169
17.21 SLV0_SUBADD (16h).........................................................169
17.22 SLAVE0_CONFIG (17h).......................................................169
17.23 SLV1_ADD (18h).............................................................170
17.24 SLV1_SUBADD (19h).........................................................170
17.25 SLAVE1_CONFIG (1Ah) ......................................................170
17.26 SLV2_ADD (1Bh) ............................................................171
17.27 SLV2_SUBADD (1Ch) ........................................................171
17.28 SLAVE2_CONFIG (1Dh) ......................................................171
17.29 SLV3_ADD (1Eh) ............................................................172
17.30 SLV3_SUBADD (1Fh).........................................................172
17.31 SLAVE3_CONFIG (20h).......................................................172
17.32 DATAWRITE_SLV0 (21h)......................................................173
17.33 STATUS_MASTER (22h) ......................................................173
18 Soldering information........................................................... 174
19 Package information............................................................ 175
19.1 LGA-14L package information..................................................175
19.2 LGA-14 packing information ...................................................175
Revision history ..................................................................... 178
Contents ............................................................................ 179
List of tables ........................................................................ 188
List of figures........................................................................ 198
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List of tables
Table 1. Pin description .....................................................................8
Table 2. Mechanical characteristics ............................................................ 10
Table 3. Electrical characteristics .............................................................. 13
Table 4. Temperature sensor characteristics ...................................................... 13
Table 5. SPI slave timing values (in mode 3) ...................................................... 14
Table 6. I²C slave timing values ............................................................... 15
Table 7. Absolute maximum ratings ............................................................16
Table 8. Serial interface pin description ..........................................................18
Table 9. I²C terminology ....................................................................18
Table 10. SAD+Read/Write patterns............................................................. 19
Table 11. Transfer when master is writing one byte to slave.............................................19
Table 12. Transfer when master is writing multiple bytes to slave ......................................... 19
Table 13. Transfer when master is receiving (reading) one byte of data from slave ............................. 19
Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave ......................... 19
Table 15. MIPI I3CSM CCC commands ........................................................... 23
Table 16. Master I²C pin details ................................................................26
Table 17. Auxiliary SPI pin details .............................................................. 26
Table 18. Gyroscope LPF2 bandwidth selection..................................................... 31
Table 19. OIS configurations .................................................................. 33
Table 20. Internal pin status .................................................................. 42
Table 21. Registers address map............................................................... 44
Table 22. FUNC_CFG_ACCESS register .........................................................47
Table 23. FUNC_CFG_ACCESS register description ................................................. 47
Table 24. PIN_CTRL register..................................................................48
Table 25. PIN_CTRL register description ......................................................... 48
Table 26. S4S_TPH_L register ................................................................48
Table 27. S4S_TPH_L register description ........................................................ 48
Table 28. S4S_TPH_H register ................................................................ 49
Table 29. S4S_TPH_H register description ........................................................ 49
Table 30. S4S_RR register ...................................................................49
Table 31. S4S_RR register description ........................................................... 49
Table 32. FIFO_CTRL1 register ................................................................49
Table 33. FIFO_CTRL1 register description........................................................ 49
Table 34. FIFO_CTRL2 register ................................................................50
Table 35. FIFO_CTRL2 register description........................................................ 50
Table 36. FIFO_CTRL3 register ................................................................51
Table 37. FIFO_CTRL3 register description........................................................ 51
Table 38. FIFO_CTRL4 register ................................................................52
Table 39. FIFO_CTRL4 register description........................................................ 52
Table 40. COUNTER_BDR_REG1 register ........................................................ 53
Table 41. COUNTER_BDR_REG1 register description ................................................53
Table 42. COUNTER_BDR_REG2 register ........................................................ 53
Table 43. COUNTER_BDR_REG2 register description ................................................53
Table 44. INT1_CTRL register .................................................................54
Table 45. INT1_CTRL register description.........................................................54
Table 46. INT2_CTRL register .................................................................55
Table 47. INT2_CTRL register description.........................................................55
Table 48. WhoAmI register ................................................................... 55
Table 49. CTRL1_XL register ................................................................. 56
Table 50. CTRL1_XL register description .........................................................56
Table 51. Accelerometer ODR register setting ...................................................... 56
LSM6DSOX
List of tables
DS12814 - Rev 3 page 188/199
Table 52. Accelerometer full-scale selection .......................................................56
Table 53. CTRL2_G register .................................................................. 57
Table 54. CTRL2_G register description ..........................................................57
Table 55. Gyroscope ODR configuration setting..................................................... 57
Table 56. CTRL3_C register .................................................................. 58
Table 57. CTRL3_C register description ..........................................................58
Table 58. CTRL4_C register .................................................................. 59
Table 59. CTRL4_C register description ..........................................................59
Table 60. CTRL5_C register .................................................................. 60
Table 61. CTRL5_C register description ..........................................................60
Table 62. Angular rate sensor self-test mode selection ................................................ 60
Table 63. Linear acceleration sensor self-test mode selection ........................................... 60
Table 64. CTRL6_C register .................................................................. 61
Table 65. CTRL6_C register description ..........................................................61
Table 66. Trigger mode selection ............................................................... 61
Table 67. Gyroscope LPF1 bandwidth selection..................................................... 61
Table 68. CTRL7_G register .................................................................. 62
Table 69. CTRL7_G register description ..........................................................62
Table 70. CTRL8_XL register ................................................................. 63
Table 71. CTRL8_XL register description .........................................................63
Table 72. Accelerometer bandwidth configurations ................................................... 63
Table 73. CTRL9_XL register ................................................................. 65
Table 74. CTRL9_XL register description .........................................................65
Table 75. CTRL10_C register ................................................................. 65
Table 76. CTRL10_C register description ......................................................... 65
Table 77. ALL_INT_SRC register ............................................................... 66
Table 78. ALL_INT_SRC register description....................................................... 66
Table 79. WAKE_UP_SRC register .............................................................67
Table 80. WAKE_UP_SRC register description ..................................................... 67
Table 81. TAP_SRC register ..................................................................68
Table 82. TAP_SRC register description .......................................................... 68
Table 83. D6D_SRC register ..................................................................69
Table 84. D6D_SRC register description ..........................................................69
Table 85. STATUS_REG register ...............................................................69
Table 86. STATUS_REG register description .......................................................69
Table 87. OUT_TEMP_L register ...............................................................70
Table 88. OUT_TEMP_H register............................................................... 70
Table 89. OUT_TEMP register description......................................................... 70
Table 90. OUTX_L_G register ................................................................. 70
Table 91. OUTX_H_G register................................................................. 70
Table 92. OUTX_H_G register description......................................................... 70
Table 93. OUTY_L_G register ................................................................. 71
Table 94. OUTY_H_G register................................................................. 71
Table 95. OUTY_H_G register description......................................................... 71
Table 96. OUTZ_L_G register ................................................................. 71
Table 97. OUTZ_H_G register .................................................................71
Table 98. OUTZ_H_G register description.........................................................71
Table 99. OUTX_L_A register .................................................................72
Table 100. OUTX_H_A register .................................................................72
Table 101. OUTX_H_A register description .........................................................72
Table 102. OUTY_L_A register .................................................................72
Table 103. OUTY_H_A register .................................................................72
Table 104. OUTY_H_A register description .........................................................72
Table 105. OUTZ_L_A register ................................................................. 73
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List of tables
DS12814 - Rev 3 page 189/199
Table 106. OUTZ_H_A register .................................................................73
Table 107. OUTZ_H_A register description .........................................................73
Table 108. EMB_FUNC_STATUS_MAINPAGE register ................................................ 73
Table 109. EMB_FUNC_STATUS_MAINPAGE register description ........................................ 73
Table 110. FSM_STATUS_A_MAINPAGE register .................................................... 74
Table 111. FSM_STATUS_A_MAINPAGE register description ............................................ 74
Table 112. FSM_STATUS_B_MAINPAGE register .................................................... 75
Table 113. FSM_STATUS_B_MAINPAGE register description ............................................ 75
Table 114. MLC_STATUS _MAINPAGE register ..................................................... 76
Table 115. MLC_STATUS_MAINPAGE register description .............................................. 76
Table 116. STATUS_MASTER_MAINPAGE register................................................... 76
Table 117. STATUS_MASTER_MAINPAGE register description .......................................... 76
Table 118. FIFO_STATUS1 register ..............................................................77
Table 119. FIFO_STATUS1 register description ...................................................... 77
Table 120. FIFO_STATUS2 register ..............................................................77
Table 121. FIFO_STATUS2 register description ...................................................... 77
Table 122. TIMESTAMP output registers .......................................................... 78
Table 123. TIMESTAMP output register description ...................................................78
Table 124. UI_STATUS_REG_OIS register .........................................................78
Table 125. UI_STATUS_REG_OIS register description .................................................78
Table 126. UI_OUTX_L_G_OIS register ...........................................................79
Table 127. UI_OUTX_H_G_OIS register........................................................... 79
Table 128. UI_OUTX_H_G_OIS register description................................................... 79
Table 129. UI_OUTY_L_G_OIS register ...........................................................79
Table 130. UI_OUTY_H_G_OIS register........................................................... 79
Table 131. UI_OUTY_H_G_OIS description ........................................................ 79
Table 132. UI_OUTZ_L_G_OIS register ...........................................................80
Table 133. UI_OUTZ_H_G_OIS register ...........................................................80
Table 134. UI_OUTZ_H_G_OIS register description................................................... 80
Table 135. UI_OUTX_L_A_OIS register ...........................................................80
Table 136. UI_OUTX_H_A_OIS register ........................................................... 80
Table 137. UI_OUTX_H_A_OIS register description................................................... 80
Table 138. UI_OUTY_L_A_OIS register ...........................................................81
Table 139. UI_OUTY_H_A_OIS register ........................................................... 81
Table 140. UI_OUTY_H_A_OIS register description................................................... 81
Table 141. UI_OUTZ_L_A_OIS register ........................................................... 81
Table 142. UI_OUTZ_H_A_OIS register ...........................................................81
Table 143. UI_OUTZ_H_A_OIS register description ...................................................81
Table 144. TAP_CFG0 register ................................................................. 82
Table 145. TAP_CFG0 register description ......................................................... 82
Table 146. TAP_CFG1 register ................................................................. 83
Table 147. TAP_CFG1 register description ......................................................... 83
Table 148. TAP priority decoding ................................................................ 83
Table 149. TAP_CFG2 register .................................................................83
Table 150. TAP_CFG2 register description ......................................................... 83
Table 151. TAP_THS_6D register ............................................................... 84
Table 152. TAP_THS_6D register description ....................................................... 84
Table 153. Threshold for D4D/D6D function ........................................................84
Table 154. INT_DUR2 register.................................................................. 85
Table 155. INT_DUR2 register description ......................................................... 85
Table 156. WAKE_UP_THS register..............................................................85
Table 157. WAKE_UP_THS register description ..................................................... 85
Table 158. WAKE_UP_DUR register ............................................................. 86
Table 159. WAKE_UP_DUR register description .....................................................86
LSM6DSOX
List of tables
DS12814 - Rev 3 page 190/199
Table 160. FREE_FALL register ................................................................ 87
Table 161. FREE_FALL register description ........................................................ 87
Table 162. Threshold for free-fall function .......................................................... 87
Table 163. MD1_CFG register.................................................................. 88
Table 164. MD1_CFG register description..........................................................88
Table 165. MD2_CFG register.................................................................. 89
Table 166. MD2_CFG register description..........................................................89
Table 167. S4S_ST_CMD_CODE register ......................................................... 90
Table 168. S4S_ST_CMD_CODE register description .................................................90
Table 169. S4S_DT_REG register ............................................................... 90
Table 170. S4S_DT_REG register description .......................................................90
Table 171. I3C_BUS_AVB register............................................................... 90
Table 172. I3C_BUS_AVB register description.......................................................90
Table 173. INTERNAL_FREQ_FINE register........................................................ 91
Table 174. INTERNAL_FREQ_FINE register description................................................ 91
Table 175. UI_INT_OIS register................................................................. 91
Table 176. UI_INT_OIS register description......................................................... 91
Table 177. UI_CTRL1_OIS register .............................................................. 92
Table 178. UI_CTRL1_OIS register description ...................................................... 92
Table 179. DEN mode selection................................................................. 92
Table 180. UI_CTRL2_OIS register .............................................................. 93
Table 181. UI_CTRL2_OIS register description ...................................................... 93
Table 182. Gyroscope OIS chain digital LPF1 filter bandwidth selection ..................................... 93
Table 183. UI_CTRL3_OIS register .............................................................. 94
Table 184. UI_CTRL3_OIS register description ...................................................... 94
Table 185. Accelerometer OIS channel full-scale selection .............................................. 94
Table 186. Accelerometer OIS channel bandwidth and phase ............................................ 94
Table 187. Self-test nominal output variation ........................................................95
Table 188. X_OFS_USR register ................................................................96
Table 189. X_OFS_USR register description ........................................................96
Table 190. Y_OFS_USR register ................................................................96
Table 191. Y_OFS_USR register description ........................................................96
Table 192. Z_OFS_USR register ................................................................ 96
Table 193. Z_OFS_USR register description ........................................................ 96
Table 194. FIFO_DATA_OUT_TAG register......................................................... 97
Table 195. FIFO_DATA_OUT_TAG register description ................................................97
Table 196. FIFO tag ......................................................................... 97
Table 197. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers .................................... 98
Table 198. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description ............................ 98
Table 199. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers .................................... 98
Table 200. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description ............................ 98
Table 201. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers .................................... 98
Table 202. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description............................. 98
Table 203. SPI2 register address map ............................................................99
Table 204. SPI2_WhoAmI register .............................................................. 100
Table 205. SPI_STATUS_REG_OIS register ....................................................... 100
Table 206. SPI_STATUS_REG_OIS description .................................................... 100
Table 207. SPI2_OUT_TEMP_L register.......................................................... 100
Table 208. SPI2_OUT_TEMP_H register ......................................................... 100
Table 209. SPI2_OUT_TEMP register description ................................................... 100
Table 210. SPI2_OUTX_L_G_OIS register ........................................................ 101
Table 211. SPI2_OUTX_H_G_OIS register ........................................................ 101
Table 212. SPI2_OUTX_H_G_OIS register description................................................ 101
Table 213. SPI2_OUTY_L_G_OIS register ........................................................ 101
LSM6DSOX
List of tables
DS12814 - Rev 3 page 191/199
Table 214. SPI2_OUTY_H_G_OIS register ........................................................ 101
Table 215. SPI2_OUTY_H_G_OIS register description................................................ 101
Table 216. SPI2_OUTZ_L_G_OIS register ........................................................ 102
Table 217. SPI2_OUTZ_H_G_OIS register ........................................................ 102
Table 218. SPI2_OUTZ_H_G_OIS register description ................................................ 102
Table 219. SPI2_OUTX_L_A_OIS register ........................................................ 102
Table 220. SPI2_OUTX_H_A_OIS register ........................................................ 102
Table 221. SPI2_OUTX_H_A_OIS register description ................................................ 102
Table 222. SPI2_OUTY_L_A_OIS register ........................................................ 103
Table 223. SPI2_OUTY_H_A_OIS register ........................................................ 103
Table 224. SPI2_OUTY_H_A_OIS register description ................................................ 103
Table 225. SPI2_OUTZ_L_A_OIS register ........................................................ 103
Table 226. SPI2_OUTZ_H_A_OIS register ........................................................ 103
Table 227. SPI2_OUTZ_H_A_OIS register description ................................................ 103
Table 228. SPI_INT_OIS register............................................................... 104
Table 229. SPI_INT_OIS register description....................................................... 104
Table 230. SPI_CTRL1_OIS register ............................................................ 105
Table 231. SPI_CTRL1_OIS register description .................................................... 105
Table 232. DEN mode selection................................................................ 105
Table 233. SPI_CTRL2_OIS register ............................................................ 106
Table 234. SPI_CTRL2_OIS register description .................................................... 106
Table 235. Gyroscope OIS chain digital LPF1 filter bandwidth selection .................................... 106
Table 236. SPI2_CTRL3_OIS register ........................................................... 107
Table 237. SPI2_CTRL3_OIS register description ................................................... 107
Table 238. Accelerometer OIS channel full-scale selection ............................................. 107
Table 239. Register address map - embedded functions ............................................... 108
Table 240. PAGE_SEL register .................................................................110
Table 241. PAGE_SEL register description .........................................................110
Table 242. EMB_FUNC_EN_A register............................................................110
Table 243. EMB_FUNC_EN_A register description ...................................................110
Table 244. EMB_FUNC_EN_B register............................................................111
Table 245. EMB_FUNC_EN_B register description ...................................................111
Table 246. PAGE_ADDRESS register ............................................................111
Table 247. PAGE_ADDRESS register description ....................................................111
Table 248. PAGE_VALUE register ...............................................................112
Table 249. PAGE_VALUE register description .......................................................112
Table 250. EMB_FUNC_INT1 register ............................................................112
Table 251. FSM_INT1_A register................................................................113
Table 252. FSM_INT1_A register description........................................................113
Table 253. FSM_INT1_B register................................................................114
Table 254. FSM_INT1_B register description........................................................114
Table 255. MLC_INT1 register..................................................................115
Table 256. MLC_INT1 register description .........................................................115
Table 257. EMB_FUNC_INT2 register ............................................................116
Table 258. EMB_FUNC_INT2 register description ....................................................116
Table 259. FSM_INT2_A register................................................................117
Table 260. FSM_INT2_A register description........................................................117
Table 261. FSM_INT2_B register................................................................118
Table 262. FSM_INT2_B register description........................................................118
Table 263. MLC_INT2 register..................................................................119
Table 264. MLC_INT2 register description .........................................................119
Table 265. EMB_FUNC_STATUS register......................................................... 120
Table 266. EMB_FUNC_STATUS register description................................................. 120
Table 267. FSM_STATUS_A register ............................................................ 121
LSM6DSOX
List of tables
DS12814 - Rev 3 page 192/199
Table 268. FSM_STATUS_A register description .................................................... 121
Table 269. FSM_STATUS_B register ............................................................ 122
Table 270. FSM_STATUS_B register description .................................................... 122
Table 271. MLC_STATUS register .............................................................. 123
Table 272. MLC_STATUS register description ...................................................... 123
Table 273. PAGE_RW register ................................................................ 124
Table 274. PAGE_RW register description ........................................................ 124
Table 275. EMB_FUNC_FIFO_CFG register ....................................................... 124
Table 276. EMB_FUNC_FIFO_CFG register description............................................... 124
Table 277. FSM_ENABLE_A register ............................................................ 125
Table 278. FSM_ENABLE_A register description .................................................... 125
Table 279. FSM_ENABLE_B register ............................................................ 125
Table 280. FSM_ENABLE_B register description .................................................... 125
Table 281. FSM_LONG_COUNTER_L register ..................................................... 126
Table 282. FSM_LONG_COUNTER_L register description ............................................. 126
Table 283. FSM_LONG_COUNTER_H register ..................................................... 126
Table 284. FSM_LONG_COUNTER_H register description............................................. 126
Table 285. FSM_LONG_COUNTER_CLEAR register................................................. 126
Table 286. FSM_LONG_COUNTER_CLEAR register description......................................... 126
Table 287. FSM_OUTS1 register ............................................................... 127
Table 288. FSM_OUTS1 register description....................................................... 127
Table 289. FSM_OUTS2 register ............................................................... 128
Table 290. FSM_OUTS2 register description....................................................... 128
Table 291. FSM_OUTS3 register ............................................................... 129
Table 292. FSM_OUTS3 register description....................................................... 129
Table 293. FSM_OUTS4 register ............................................................... 130
Table 294. FSM_OUTS4 register description....................................................... 130
Table 295. FSM_OUTS5 register ............................................................... 131
Table 296. FSM_OUTS5 register description....................................................... 131
Table 297. FSM_OUTS6 register ............................................................... 132
Table 298. FSM_OUTS6 register description....................................................... 132
Table 299. FSM_OUTS7 register ............................................................... 133
Table 300. FSM_OUTS7 register description....................................................... 133
Table 301. FSM_OUTS8 register ............................................................... 134
Table 302. FSM_OUTS8 register description....................................................... 134
Table 303. FSM_OUTS9 register ............................................................... 135
Table 304. FSM_OUTS9 register description....................................................... 135
Table 305. FSM_OUTS10 register .............................................................. 136
Table 306. FSM_OUTS10 register description ...................................................... 136
Table 307. FSM_OUTS11 register .............................................................. 137
Table 308. FSM_OUTS11 register description ...................................................... 137
Table 309. FSM_OUTS12 register .............................................................. 138
Table 310. FSM_OUTS12 register description ...................................................... 138
Table 311. FSM_OUTS13 register .............................................................. 139
Table 312. FSM_OUTS13 register description ...................................................... 139
Table 313. FSM_OUTS14 register .............................................................. 140
Table 314. FSM_OUTS14 register description ...................................................... 140
Table 315. FSM_OUTS15 register .............................................................. 141
Table 316. FSM_OUTS15 register description ...................................................... 141
Table 317. FSM_OUTS16 register .............................................................. 142
Table 318. FSM_OUTS16 register description ...................................................... 142
Table 319. EMB_FUNC_ODR_CFG_B register ..................................................... 143
Table 320. EMB_FUNC_ODR_CFG_B register description ............................................. 143
Table 321. EMB_FUNC_ODR_CFG_C register ..................................................... 143
LSM6DSOX
List of tables
DS12814 - Rev 3 page 193/199
Table 322. EMB_FUNC_ODR_CFG_C register description ............................................. 143
Table 323. STEP_COUNTER_L register.......................................................... 144
Table 324. STEP_COUNTER_L register description.................................................. 144
Table 325. STEP_COUNTER_H register ......................................................... 144
Table 326. STEP_COUNTER_H register description ................................................. 144
Table 327. EMB_FUNC_SRC register ........................................................... 144
Table 328. EMB_FUNC_SRC register description ................................................... 144
Table 329. EMB_FUNC_INIT_A register .......................................................... 145
Table 330. EMB_FUNC_INIT_A register description.................................................. 145
Table 331. EMB_FUNC_INIT_B register .......................................................... 145
Table 332. EMB_FUNC_INIT_B register description.................................................. 145
Table 333. MLC0_SRC register ................................................................ 145
Table 334. MLC0_SRC register description........................................................ 145
Table 335. MLC1_SRC register ................................................................ 146
Table 336. MLC1_SRC register description........................................................ 146
Table 337. MLC2_SRC register ................................................................ 146
Table 338. MLC2_SRC register description........................................................ 146
Table 339. MLC3_SRC register ................................................................ 146
Table 340. MLC3_SRC register description........................................................ 146
Table 341. MLC4_SRC register ................................................................ 147
Table 342. MLC4_SRC register description........................................................ 147
Table 343. MLC5_SRC register ................................................................ 147
Table 344. MLC5_SRC register description........................................................ 147
Table 345. MLC6_SRC register ................................................................ 147
Table 346. MLC6_SRC register description........................................................ 147
Table 347. MLC7_SRC register ................................................................ 147
Table 348. MLC7_SRC register description........................................................ 147
Table 349. Register address map - embedded advanced features page 0 ................................... 148
Table 350. Register address map - embedded advanced features page 1 ................................... 148
Table 351. MAG_SENSITIVITY_L register ........................................................ 150
Table 352. MAG_SENSITIVITY_L register description ................................................ 150
Table 353. MAG_SENSITIVITY_H register ........................................................ 150
Table 354. MAG_SENSITIVITY_H register description ................................................ 150
Table 355. MAG_OFFX_L register .............................................................. 151
Table 356. MAG_OFFX_L register description...................................................... 151
Table 357. MAG_OFFX_H register.............................................................. 151
Table 358. MAG_OFFX_H register description ..................................................... 151
Table 359. MAG_OFFY_L register .............................................................. 151
Table 360. MAG_OFFY_L register description...................................................... 151
Table 361. MAG_OFFY_H register.............................................................. 151
Table 362. MAG_OFFY_H register description ..................................................... 151
Table 363. MAG_OFFZ_L register .............................................................. 152
Table 364. MAG_OFFZ_L register description ...................................................... 152
Table 365. MAG_OFFZ_H register.............................................................. 152
Table 366. MAG_OFFZ_H register description ..................................................... 152
Table 367. MAG_SI_XX_L register.............................................................. 152
Table 368. MAG_SI_XX_L register description ..................................................... 152
Table 369. MAG_SI_XX_H register ............................................................. 152
Table 370. MAG_SI_XX_H register description ..................................................... 152
Table 371. MAG_SI_XY_L register.............................................................. 153
Table 372. MAG_SI_XY_L register description ..................................................... 153
Table 373. MAG_SI_XY_H register ............................................................. 153
Table 374. MAG_SI_XY_H register description ..................................................... 153
Table 375. MAG_SI_XZ_L register.............................................................. 153
LSM6DSOX
List of tables
DS12814 - Rev 3 page 194/199
Table 376. MAG_SI_XZ_L register description ..................................................... 153
Table 377. MAG_SI_XZ_H register ............................................................. 153
Table 378. MAG_SI_XZ_H register description ..................................................... 153
Table 379. MAG_SI_YY_L register.............................................................. 154
Table 380. MAG_SI_YY_L register description ..................................................... 154
Table 381. MAG_SI_YY_H register ............................................................. 154
Table 382. MAG_SI_YY_H register description ..................................................... 154
Table 383. MAG_SI_YZ_L register.............................................................. 154
Table 384. MAG_SI_YZ_L register description ..................................................... 154
Table 385. MAG_SI_YZ_H register ............................................................. 154
Table 386. MAG_SI_YZ_H register description ..................................................... 154
Table 387. MAG_SI_ZZ_L register.............................................................. 155
Table 388. MAG_SI_ZZ_L register description...................................................... 155
Table 389. MAG_SI_ZZ_H register ............................................................. 155
Table 390. MAG_SI_ZZ_H register description ..................................................... 155
Table 391. MAG_CFG_A register .............................................................. 156
Table 392. MAG_CFG_A description ............................................................ 156
Table 393. MAG_CFG_B register .............................................................. 156
Table 394. MAG_CFG_B description ............................................................ 156
Table 395. FSM_LC_TIMEOUT_L register ........................................................ 157
Table 396. FSM_LC_TIMEOUT_L register description ................................................ 157
Table 397. FSM_LC_TIMEOUT_H register ........................................................ 157
Table 398. FSM_LC_TIMEOUT_H register description ................................................ 157
Table 399. FSM_PROGRAMS register ........................................................... 157
Table 400. FSM_PROGRAMS register description................................................... 157
Table 401. FSM_START_ADD_L register ......................................................... 158
Table 402. FSM_START_ADD_L register description ................................................. 158
Table 403. FSM_START_ADD_H register......................................................... 158
Table 404. FSM_START_ADD_H register description................................................. 158
Table 405. PEDO_CMD_REG register ........................................................... 158
Table 406. PEDO_CMD_REG register description ................................................... 158
Table 407. PEDO_DEB_STEPS_CONF register .................................................... 158
Table 408. PEDO_DEB_STEPS_CONF register description ............................................ 158
Table 409. PEDO_SC_DELTAT_L register ........................................................ 159
Table 410. PEDO_SC_DELTAT_H register ........................................................ 159
Table 411. PEDO_SC_DELTAT_H/L register description............................................... 159
Table 412. MLC_MAG_SENSITIVITY_L register .................................................... 159
Table 413. MLC_ MAG_SENSITIVITY_L register description............................................ 159
Table 414. MLC_MAG_SENSITIVITY_H register .................................................... 159
Table 415. MLC_MAG_SENSITIVITY_H register description............................................ 159
Table 416. Register address map - sensor hub registers............................................... 160
Table 417. SENSOR_HUB_1 register............................................................ 162
Table 418. SENSOR_HUB_1 register description ................................................... 162
Table 419. SENSOR_HUB_2 register............................................................ 162
Table 420. SENSOR_HUB_2 register description ................................................... 162
Table 421. SENSOR_HUB_3 register............................................................ 162
Table 422. SENSOR_HUB_3 register description ................................................... 162
Table 423. SENSOR_HUB_4 register............................................................ 163
Table 424. SENSOR_HUB_4 register description ................................................... 163
Table 425. SENSOR_HUB_5 register............................................................ 163
Table 426. SENSOR_HUB_5 register description ................................................... 163
Table 427. SENSOR_HUB_6 register............................................................ 163
Table 428. SENSOR_HUB_6 register description ................................................... 163
Table 429. SENSOR_HUB_7 register............................................................ 164
LSM6DSOX
List of tables
DS12814 - Rev 3 page 195/199
Table 430. SENSOR_HUB_7 register description ................................................... 164
Table 431. SENSOR_HUB_8 register............................................................ 164
Table 432. SENSOR_HUB_8 register description ................................................... 164
Table 433. SENSOR_HUB_9 register............................................................ 164
Table 434. SENSOR_HUB_9 register description ................................................... 164
Table 435. SENSOR_HUB_10 register........................................................... 165
Table 436. SENSOR_HUB_10 register description................................................... 165
Table 437. SENSOR_HUB_11 register ........................................................... 165
Table 438. SENSOR_HUB_11 register description................................................... 165
Table 439. SENSOR_HUB_12 register........................................................... 165
Table 440. SENSOR_HUB_12 register description................................................... 165
Table 441. SENSOR_HUB_13 register........................................................... 166
Table 442. SENSOR_HUB_13 register description................................................... 166
Table 443. SENSOR_HUB_14 register........................................................... 166
Table 444. SENSOR_HUB_14 register description................................................... 166
Table 445. SENSOR_HUB_15 register........................................................... 166
Table 446. SENSOR_HUB_15 register description................................................... 166
Table 447. SENSOR_HUB_16 register........................................................... 167
Table 448. SENSOR_HUB_16 register description................................................... 167
Table 449. SENSOR_HUB_17 register........................................................... 167
Table 450. SENSOR_HUB_17 register description................................................... 167
Table 451. SENSOR_HUB_17 register........................................................... 167
Table 452. SENSOR_HUB_17 register description................................................... 167
Table 453. MASTER_CONFIG register........................................................... 168
Table 454. MASTER_CONFIG register description .................................................. 168
Table 455. SLV0_ADD register ................................................................ 169
Table 456. SLV_ADD register description ......................................................... 169
Table 457. SLV0_SUBADD register ............................................................. 169
Table 458. SLV0_SUBADD register description ..................................................... 169
Table 459. SLAVE0_CONFIG register ........................................................... 169
Table 460. SLAVE0_CONFIG register description ................................................... 169
Table 461. SLV1_ADD register ................................................................ 170
Table 462. SLV1_ADD register description ........................................................ 170
Table 463. SLV1_SUBADD register ............................................................. 170
Table 464. SLV1_SUBADD register description ..................................................... 170
Table 465. SLAVE1_CONFIG register ........................................................... 170
Table 466. SLAVE1_CONFIG register description ................................................... 170
Table 467. SLV2_ADD register ................................................................ 171
Table 468. SLV2_ADD register description ........................................................ 171
Table 469. SLV2_SUBADD register ............................................................. 171
Table 470. SLV2_SUBADD register description ..................................................... 171
Table 471. SLAVE2_CONFIG register ........................................................... 171
Table 472. SLAVE2_CONFIG register description ................................................... 171
Table 473. SLV3_ADD register ................................................................ 172
Table 474. SLV3_ADD register description ........................................................ 172
Table 475. SLV3_SUBADD register ............................................................. 172
Table 476. SLV3_SUBADD register description ..................................................... 172
Table 477. SLAVE3_CONFIG register ........................................................... 172
Table 478. SLAVE3_CONFIG register description ................................................... 172
Table 479. DATAWRITE_SLV0 register........................................................... 173
Table 480. DATAWRITE_SLV0 register description .................................................. 173
Table 481. STATUS_MASTER register ........................................................... 173
Table 482. STATUS_MASTER register description................................................... 173
Table 483. Reel dimensions for carrier tape of LGA-14 package ......................................... 177
LSM6DSOX
List of tables
DS12814 - Rev 3 page 196/199
Table 484. Document revision history ............................................................ 178
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List of tables
DS12814 - Rev 3 page 197/199
List of figures
Figure 1. Generic state machine...............................................................5
Figure 2. State machine in the LSM6DSOX .......................................................5
Figure 3. Machine Learning Core in the LSM6DSOX ................................................6
Figure 4. Pin connections ...................................................................7
Figure 5. LSM6DSOX connection modes ........................................................8
Figure 6. SPI slave timing diagram (in mode 3) ................................................... 14
Figure 7. I²C slave timing diagram ............................................................15
Figure 8. Read and write protocol (in mode 3) .................................................... 20
Figure 9. SPI read protocol (in mode 3) ......................................................... 21
Figure 10. Multiple byte SPI read protocol (2-byte example) (in mode 3) ................................... 21
Figure 11. SPI write protocol (in mode 3)......................................................... 22
Figure 12. Multiple byte SPI write protocol (2-byte example) (in mode 3) ................................... 22
Figure 13. SPI read protocol in 3-wire mode (in mode 3) .............................................. 22
Figure 14. I²C and I3C both active (INT1 pin not connected) ........................................... 25
Figure 15. Only I3C active (INT1 pin connected to VDD_IO) ........................................... 25
Figure 16. Block diagram of filters ............................................................. 28
Figure 17. Accelerometer UI chain .............................................................28
Figure 18. Accelerometer composite filter ........................................................ 29
Figure 19. Accelerometer chain with Mode 4 enabled ................................................ 30
Figure 20. Gyroscope digital chain - Mode 1 (UI/EIS) and Mode 2 ....................................... 31
Figure 21. Gyroscope digital chain - Mode 3 / Mode 4 (OIS/EIS) ........................................ 32
Figure 22. Auxiliary SPI full control (a) and enabling primary interface (b) .................................. 34
Figure 23. OIS Primary interface full control....................................................... 35
Figure 24. LSM6DSOX electrical connections in Mode 1 .............................................. 39
Figure 25. LSM6DSOX electrical connections in Mode 2 .............................................. 40
Figure 26. LSM6DSOX electrical connections in Mode 3 and Mode 4 (auxiliary 3/4-wire SPI)..................... 41
Figure 27. Accelerometer block diagram ......................................................... 64
Figure 28. LGA-14L 2.5x3x0.86 mm package outline and mechanical data ................................ 175
Figure 29. Carrier tape information for LGA-14 package ............................................. 176
Figure 30. LGA-14 package orientation in carrier tape............................................... 176
Figure 31. Reel information for carrier tape of LGA-14 package ........................................ 177
LSM6DSOX
List of figures
DS12814 - Rev 3 page 198/199
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LSM6DSOX
DS12814 - Rev 3 page 199/199