© Semiconductor Components Industries, LLC, 2016
July, 2019 − Rev. 3
1Publication Order Number:
NVMFS5C682NL/D
NVMFS5C682NL
MOSFET – Power, Single
N-Channel
60 V, 21 mW, 25 A
Features
•Small Footprint (5x6 mm) for Compact Design
•Low RDS(on) to Minimize Conduction Losses
•Low QG and Capacitance to Minimize Driver Losses
•NVMFS5C682NLWF − Wettable Flank Option for Enhanced Optical
Inspection
•AEC−Q101 Qualified and PPAP Capable
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS 60 V
Gate−to−Source Voltage VGS ±20 V
Continuous Drain
Current RqJC
(Notes 1, 3) Steady
State
TC = 25°CID25 A
TC = 100°C 18
Power Dissipation
RqJC (Note 1)
TC = 25°CPD28 W
TC = 100°C 14
Continuous Drain
Current RqJA
(Notes 1, 2, 3) Steady
State
TA = 25°CID8.8 A
TA = 100°C 6.2
Power Dissipation
RqJA (Notes 1 & 2)
TA = 25°CPD3.5 W
TA = 100°C 1.7
Pulsed Drain Current TA = 25°C, tp = 10 msIDM 130 A
Operating Junction and Storage Temperature TJ, Tstg −55 to
+ 175
°C
Source Current (Body Diode) IS31 A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 1.1 A)
EAS 43 mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
Junction−to−Case − Steady State RqJC 5.3 °C/W
Junction−to−Ambient − Steady State (Note 2) RqJA 43
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
MARKING
DIAGRAM
www.onsemi.com
XXXXXX
AYWZZ
G (4)
S (1,2,3)
N−CHANNEL MOSFET
D (5)
S
S
S
G
D
D
D
D
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
1
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
XXXXXX = 5C682L
XXXXXX = (NVMFS5C682NL) or
XXXXXX = 682LWF
XXXXXX = (NVMFS5C682NLWF)
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
V(BR)DSS RDS(ON) MAX ID MAX
60 V
21 mW @ 10 V
25 A
31.5 mW @ 4.5 V
NVMFS5C682NL
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA60 V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
28 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V,
VDS = 60 V
TJ = 25 °C 10
mA
TJ = 125°C 250
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = 20 V 100 nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 16 mA1.2 2.0 V
Threshold Temperature Coefficient VGS(TH)/TJ−4.5 mV/°C
Drain−to−Source On Resistance RDS(on) VGS = 10 V ID = 10 A 18 21
mW
VGS = 4.5 V ID = 10 A 26 31.5
Forward Transconductance gFS VDS =15 V, ID = 10 A 17 S
CHARGES AND CAPACITANCES
Input Capacitance CISS
VGS = 0 V, f = 1 MHz, VDS = 25 V
410
pF
Output Capacitance COSS 210
Reverse Transfer Capacitance CRSS 7.0
Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 48 V; ID = 10 A 2.5 nC
Total Gate Charge QG(TOT) VGS = 10 V, VDS = 48 V; ID = 10 A 5.0 nC
Threshold Gate Charge QG(TH)
VGS = 10 V, VDS = 48 V; ID = 10 A
0.6
nC
Gate−to−Source Charge QGS 1.0
Gate−to−Drain Charge QGD 0.5
Plateau Voltage VGP 2.7 V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time td(ON)
VGS = 10 V, VDS = 48 V,
ID = 10 A, RG = 2.5 W
4.0
ns
Rise Time tr12
Turn−Off Delay Time td(OFF) 12
Fall Time tf1.5
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V,
IS = 10 A
TJ = 25°C 0.9 1.2
V
TJ = 125°C 0.8
Reverse Recovery Time tRR
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 10 A
18
ns
Charge Time ta9.0
Discharge Time tb9.0
Reverse Recovery Charge QRR 7.0 nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
NVMFS5C682NL
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3
TYPICAL CHARACTERISTICS
10 V to
4.5 V
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
2.52.01.51.00.50
0
5
10
15
20
25
4.03.02.52.01.51.00.50
0
5
10
15
20
25
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
109876543
15
20
25
30
4540 503025201510
10
15
20
30
50
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
15012510075250−25−50
0.5
1.0
1.5
2.0
2.5
605040302010
1
100
1000
10,000
100,000
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
IDSS, LEAKAGE (nA)
2.4 V
2.6 V
2.8 V
3.0 V
3.2 V
3.4 V
3.5
TJ = 125°C
TJ = 25°C
TJ = −55°C
TJ = 25°C
ID = 10 A
TJ = 25°C
VGS = 4.5 V
VGS = 10 V
VGS = 10 V
ID = 10 A
50 175
TJ = 125°C
TJ = 85°C
45
50
35
40
VGS = 2.2 V
VDS = 3 V
35
25
45
TJ = 150°C
TJ = 175°C
10
NVMFS5C682NL
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4
TYPICAL CHARACTERISTICS
Figure 7. Capacitance Variation Figure 8. Gate−to−Source vs. Total Charge
VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC)
6050403020100
1
10
100
1000
43210
0
2
4
6
8
10
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
RG, GATE RESISTANCE (W)VSD, SOURCE−TO−DRAIN VOLTAGE (V)
100101
1
10
100
0.90.8 1.00.70.60.50.40.3
0.1
1
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
VDS, DRAIN−TO−SOURCE VOLTAGE (V) TAV, TIME IN AVALANCHE (s)
1001010.1
0.1
10
100
1000
0.1
1
10
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
t, TIME (ns)
IS, SOURCE CURRENT (A)
ID, DRAIN CURRENT(A)
IPEAK, DRAIN CURRENT(A)
VGS = 0 V
TJ = 25°C
f = 1 MHz
CISS
COSS
CRSS
5
VDS = 48 V
TJ = 25°C
ID = 10 A
QT
QGS QGD
VGS = 10 V
VDS = 48 V
ID = 10 A
td(off)
td(on)
tf
tr
TJ = 125°C TJ = 25°C TJ = −55°C
10
1E−02
RDS(on) Limit
Thermal Limit
Package Limit
500 ms
1 ms
10 ms
TC = 25°C
Single Pulse
VGS ≤ 10 V
TJ(initial) = 100°C
TJ(initial) = 25°C
1E−05
1
3
5
7
9
0.1
1
1E−04 1E−03
VGS = 0 V
dc
NVMFS5C682NL
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5
Figure 13. Thermal Characteristics
PULSE TIME (sec)
0.010.001 10.0001 0.10.00001 100.000001
0.01
0.1
1
10
100
RqJA(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE(°C/W)
100 1000
Single Pulse
50% Duty Cycle
20%
10%
5%
2%
1%
DEVICE ORDERING INFORMATION
Device Marking Package Shipping†
NVMFS5C682NLT1G 5C682L DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS5C682NLWFT1G 682LWF DFN5
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
NVMFS5C682NLT3G 5C682L DFN5
(Pb−Free)
5000 / Tape & Reel
NVMFS5C682NLWFT3G 682LWF DFN5
(Pb−Free, Wettable Flanks)
5000 / Tape & Reel
NVMFS5C682NLAFT1G 5C682L DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS5C682NLWFAFT1G 682LWF DFN5
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
M3.00 3.40
q0 −−−
_
3.80
12
_
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE N DATE 25 JUN 201
8
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
1234
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D1
E1 q
D
E
2
2
B
A
0.20 C
0.20 C
2 X
2 X
DIM MIN NOM
MILLIMETERS
A0.90 1.00
A1 0.00 −−−
b0.33 0.41
c0.23 0.28
D5.15
D1 4.70 4.90
D2 3.80 4.00
E6.15
E1 5.70 5.90
E2 3.45 3.65
e1.27 BSC
G0.51 0.575
K1.20 1.35
L0.51 0.575
L1 0.125 REF
A
0.10 C
0.10 C
DETAIL A
14
L1
e/2
8X
D2
G
E2
K
b
A0.10 B
C
0.05 cL
DETAIL A
A1
c
4 X
C
SEATING
PLANE
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
1
MAX
1.10
0.05
0.51
0.33
5.10
4.20
6.10
3.85
0.71
1.50
0.71
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
M
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1.270
2X
0.750
1.000
0.905
4.530
1.530
4.5600.495
3.200
1.330
0.965
2X
2X
4X
4X
PIN 5
(EXPOSED PAD)
STYLE 2:
PIN 1. ANODE
2. ANODE
3. ANODE
4. NO CONNECT
5. CATHODE
5.00 5.30
6.00 6.30
PITCH
DIMENSIONS: MILLIMETERS
1
RECOMMENDED
e
2X
0.475
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some product
s
may not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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98AON14036D
DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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DFN5 5x6, 1.27P (SO−8FL)
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