DS90LV001
DS90LV001 800 Mbps LVDS Buffer
Literature Number: SNLS067D
February 19, 2008
DS90LV001
800 Mbps LVDS Buffer
General Description
The DS90LV001 LVDS-LVDS Buffer takes an LVDS input
signal and provides an LVDS output signal. In many large
systems, signals are distributed across backplanes, and one
of the limiting factors for system speed is the "stub length" or
the distance between the transmission line and the untermi-
nated receivers on individual cards. Although it is generally
recognized that this distance should be as short as possible
to maximize system performance, real-world packaging con-
cerns often make it difficult to make the stubs as short as the
designer would like.
The DS90LV001, available in the LLP (Leadless Leadframe
Package) package, will allow the receiver to be placed very
close to the main transmission line, thus improving system
performance.
A wide input dynamic range will allow the DS90LV001 to re-
ceive differential signals from LVPECL as well as LVDS
sources. This will allow the device to also fill the role of an
LVPECL-LVDS translator.
An output enable pin is provided, which allows the user to
place the LVDS output in TRI-STATE.
The DS90LV001 is offered in two package options, an 8 pin
LLP and SOIC.
Features
■Single +3.3 V Supply
■LVDS receiver inputs accept LVPECL signals
■TRI-STATE outputs
■Receiver input threshold < ±100 mV
■Fast propagation delay of 1.4 ns (typ)
■Low jitter 800 Mbps fully differential data path
■100 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern
at 800 Mbps
■Compatible with ANSI/TIA/EIA-644-A LVDS standard
■8 pin SOIC and space saving (70%) LLP package
■Industrial Temperature Range
Connection Diagram
Top View
10133805
Order Number DS90LV001TM, DS90LV001TLD
See NS Package Number M08A, LDA08A
Block Diagram
10133802
© 2008 National Semiconductor Corporation 101338 www.national.com
DS90LV001 800 Mbps LVDS Buffer
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)−0.3V to +4V
LVCMOS/LVTTL Input Voltage
(EN) −0.3V to (VCC + 0.3V)
LVDS Receiver Input Voltage (IN
+, IN−) −0.3V to +4V
LVDS Driver Output Voltage (OUT
+, OUT−) −0.3V to +4V
LVDS Output Short Circuit Current Continuous
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
Soldering (4 sec.) +260°C
Maximum Package Power Dissipation at 25°C
M Package 726 mW
Derate M Package 5.8 mW/°C above +25°C
LDA Package 2.44 W
Derate LDA Package 19.49 mW/°C above +25°C
ESD Ratings
(HBM, 1.5kΩ, 100pF) ≥2.5kV
(EIAJ, 0Ω, 200pF) ≥250V
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Receiver Input Voltage 0 VCC V
Operating Free Air
Temperature
−40 +25 +85 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS/LVTTL DC SPECIFICATIONS (EN)
VIH High Level Input Voltage 2.0 VCC V
VIL Low Level Input Voltage GND 0.8 V
IIH High Level Input Current VIN = 3.6V or 2.0V, VCC = 3.6V +7 +20 μA
IIL Low Level Input Current VIN = GND or 0.8V, VCC = 3.6V ±1 ±10 μA
VCL Input Clamp Voltage ICL = −18 mA −0.6 −1.5 V
LVDS OUTPUT DC SPECIFICATIONS (OUT)
VOD Differential Output Voltage RL = 100Ω 250 325 450 mV
ΔVOD Change in Magnitude of VOD for Complimentary
Output States
Figure 1 and Figure 2 20 mV
VOS Offset Voltage RL = 100Ω 1.080 1.19 1.375 V
ΔVOS Change in Magnitude of VOS for Complimentary
Output States
Figure 1 20 mV
IOZ Output TRI-STATE Current EN = 0V, VOUT = VCC or GND ±1 ±10 μA
IOFF Power-Off Leakage Current VCC = 0V, VOUT = 3.6V or GND ±1 ±10 μA
IOS Output Short Circuit Current (Note 4) EN = VCC, VOUT+ and VOUT− = 0V −16 −24 mA
IOSD Differential Output Short Circuit Current (Note 4) EN = VCC, VOD = 0V −7 −12 mA
LVDS RECEIVER DC SPECIFICATIONS (IN)
VTH Differential Input High Threshold VCM = +0.05V, +1.2V or +3.25V 0 +100 mV
VTL Differential Input Low Threshold −100 0 mV
VCMR Common Mode Voltage Range VID = 100mV, VCC = 3.3V 0.05 3.25 V
IIN Input Current VIN = +3.0V VCC = 3.6V or 0V ±1 ±10 μA
VIN = 0V ±1 ±10 μA
ΔIIN Change in Magnitude of IIN VIN = +3.0V VCC = 3.6V or 0V 1 6 μA
VIN = 0V 1 6 μA
SUPPLY CURRENT
ICCD Total Supply Current EN = VCC, RL = 100Ω, CL = 5 pF 47 70 mA
ICCZ TRI-STATE Supply Current EN = 0V 22 35 mA
www.national.com 2
DS90LV001
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)
Symbol Parameter Conditions Min Typ Max Units
tPHLD Differential Propagation Delay High to Low RL = 100Ω, CL = 5pF 1.0 1.4 2.0 ns
tPLHD Differential Propagation Delay Low to High Figure 3 and Figure 4 1.0 1.4 2.0 ns
tSKD1 Pulse Skew |tPLHD − tPHLD| (Notes 5, 6) 20 200 ps
tSKD3 Part to Part Skew (Notes 5, 7) 0 60 ps
tSKD4 Part to Part Skew (Notes 5, 8) 400 ps
tLHT Rise Time (Note 5) RL = 100Ω, CL = 5pF 200 320 450 ps
tHLT Fall Time (Note 5) Figure 3 and Figure 5 200 310 450 ps
tPHZ Disable Time (Active High to Z) RL = 100Ω, CL = 5pF 3 25 ns
tPLZ Disable Time (Active Low to Z) Figure 6 and Figure 7 3 25 ns
tPZH Enable Time (Z to Active High) 25 45 ns
tPZL Enable Time (Z to Active Low) 25 45 ns
tDJ LVDS Data Jitter, Deterministic (Peak-to-Peak)
(Note 9)
VID = 300mV; PRBS = 223 − 1 data; VCM
= 1.2V at 800Mbps (NRZ) 100 135 ps
tRJ LVDS Clock Jitter, Random (Note 9) VID = 300mV; VCM = 1.2V at 400MHz
clock 2.2 3.5 ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 3: All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.
Note 4: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and
temperature) range.
Note 6: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel.
Note 7: tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 8: tSKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended
operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.
Note 9: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT range with the following
test equipment setup: HP8133A (pattern pulse generator), 5 feet of RG142B cable with DUT test board and HP83480A (digital scope mainframe) with HP83484A
(50GHz scope module). The HP8133A with RG142B cable exhibit a tDJ = 21ps and tRJ = 1.8ps.
3 www.national.com
DS90LV001
DC Test Circuits
10133803
FIGURE 1. Differential Driver DC Test Circuit
10133808
FIGURE 2. Differential Driver Full Load DC Test Circuit
AC Test Circuits and Timing Diagrams
10133806
FIGURE 3. LVDS Output Load
10133807
FIGURE 4. Propagation Delay Low-to-High and High-to-Low
www.national.com 4
DS90LV001
10133809
FIGURE 5. LVDS Output Transition Time
10133801
FIGURE 6. TRI-STATE Delay Test Circuit
10133804
FIGURE 7. Output active to TRI-STATE and TRI-STATE to active output time
5 www.national.com
DS90LV001
DS90LV001 Pin Descriptions (SOIC and LLP)
Pin Name Pin # Input/Output Description
GND 1 P Ground
IN − 2 I Inverting receiver LVDS input pin
IN+ 3 I Non-inverting receiver LVDS input pin
NC 4 No Connect
VCC 5 P Power Supply, 3.3V ± 0.3V.
OUT+ 6 O Non-inverting driver LVDS output pin
OUT - 7 O Inverting driver LVDS output pin
EN 8 I Enable pin. When EN is LOW, the driver is disabled and the LVDS
outputs are in TRI-STATE. When EN is HIGH, the driver is enabled.
LVCMOS/LVTTL levels.
DAP NA NA Die Attach Pad or DAP (LLP Package only). The DAP is NOT connected
to the device GND nor any other pin. It is still recommended to connect
the DAP to a GND plane of a PCB for enhenced heat dissipation.
Typical Applications
Backplane Stub-Hider Application
10133811
www.national.com 6
DS90LV001
Cable Repeater Application
10133810
Application Information
MODE OF OPERATION
The DS90LV001 can be used as a "stub-hider." In many sys-
tems, signals are distributed across backplanes, and one of
the limiting factors for system speed is the "stub length" or the
distance between the transmission line and the unterminated
receivers on the individual cards. Although it is generally rec-
ognized that this distance should be as short as possible to
maximize system performance, real-world packaging con-
cerns and PCB designs often make it difficult to make the
stubs as short as the designer would like. The DS90LV001,
available in the LLP (Leadless Leadframe Package) package,
can improve system performance by allowing the receiver to
be placed very close to the main transmission line either on
the backplane itself or very close to the connector on the card.
Longer traces to the LVDS receiver may be placed after the
DS90LV001. This very small LLP package is a 75% space
savings over the SOIC package.
INPUT FAILSAFE
The receiver inputs of the DS90LV001 do not have internal
failsafe biasing. For point-to-point and multidrop applications
with a single source, failsafe biasing may not be required.
When the driver is off, the link is in-active. If failsafe biasing
is required, this can be accomplished with external high value
resistors. Using the equations in the LVDS Owner"s Manual
Chapter 4, the IN+ should be pull to VCC (3.3V) with 20kΩ and
the IN− should be pull to GND with 12kΩ. This provides a
slight positive differential bias, and sets a known HIGH state
on the link with a minimum amount of distortion.
10133815
PCB LAYOUT AND POWER SYSTEM BYPASS
Circuit board layout and stack-up for the DS90LV001 should
be designed to provide noise-free power to the device. Good
layout practice also will separate high frequency or high level
inputs and outputs to minimize unwanted stray noise pickup,
feedback and interference. Power system performance may
be greatly improved by using thin dielectrics (4 to 10 mils) for
power/ground sandwiches. This increases the intrinsic ca-
pacitance of the PCB power system which improves power
supply filtering, especially at high frequencies, and makes the
value and placement of external bypass capacitors less criti-
cal. External bypass capacitors should include both RF ce-
ramic and tantalum electrolytic types. RF capacitors may use
values in the range 0.01 µF to 0.1 µF. Tantalum capacitors
may be in the range 2.2 µF to 10 µF. Voltage rating for tan-
talum capacitors should be at least 5X the power supply
voltage being used. It is recommended practice to use two
vias at each power pin of the DS90LV001 as well as all RF
bypass capacitor terminals. Dual vias reduce the interconnect
inductance by up to half, thereby reducing interconnect in-
ductance and extending the effective frequency range of the
bypass components.
The outer layers of the PCB may be flooded with additional
ground plane. These planes will improve shielding and isola-
tion as well as increase the intrinsic capacitance of the power
supply plane system. Naturally, to be effective, these planes
must be tied to the ground supply plane at frequent intervals
with vias. Frequent via placement also improves signal in-
tegrity on signal transmission lines by providing short paths
for image currents which reduces signal distortion. The
planes should be pulled back from all transmission lines and
component mounting pads a distance equal to the width of
the widest transmission line or the thickness of the dielectric
separating the transmission line from the internal power or
ground plane(s) whichever is greater. Doing so minimizes ef-
fects on transmission line impedances and reduces unwanted
parasitic capacitances at component mounting pads.
There are more common practices which should be followed
when designing PCBs for LVDS signaling. Please see appli-
cation note AN-1108 for guidelines. In addition, application
note AN-1187 has additional information specifically related
to LLP recommendations.
7 www.national.com
DS90LV001
Typical Performance Curves
Output High Voltage vs
Power Supply Voltage
10133816
Output Low Voltage vs
Power Supply Voltage
10133817
Output Short Circuit Current vs
Power Supply Voltage
10133818
Differential Output Short Circuit Current vs
Power Supply Voltage
10133819
www.national.com 8
DS90LV001
Output TRI-STATE Current vs
Power Supply Voltage
10133820
Offset Voltage vs
Power Supply Voltage
10133821
Differential Output Voltage
vs Power Supply Voltage
10133822
Differential Output Voltage
vs Load Resistor
10133823
Power Supply Current
vs Frequency
10133824
Power Supply Current vs
Power Supply Voltage
10133825
9 www.national.com
DS90LV001
TRI-STATE Power Supply Current vs
Power Supply Voltage
10133826
Differential Transition Voltage vs
Power Supply Voltage
10133827
Differential Propagation Delay vs
Power Supply Voltage
10133828
Differential Propagation Delay vs
Ambient Temperature
10133836
www.national.com 10
DS90LV001
Differential Skew vs
Power Supply Voltage
10133829
Differential Skew vs
Ambient Temperature
10133837
Transition Time vs
Power Supply Voltage
10133830
Transition Time vs
Ambient Temperature
10133838
11 www.national.com
DS90LV001
Differential Propagation Delay vs
Differential Input Voltage
10133831
Differential Propagation Delay vs
Common-Mode Voltage
10133832
Peak-to-Peak Output Jitter at VCM = 0.4V vs
Differential Input Voltage
10133833
Peak-to-Peak Output Jitter at VCM = 2.9V vs
Differential Input Voltage
10133835
www.national.com 12
DS90LV001
Peak-to-Peak Output Jitter at VCM = 1.2V vs
Differential Input Voltage
10133834
Peak-to-Peak Output Jitter at VCM = 1.2V vs
Ambient Temperature
10133839
13 www.national.com
DS90LV001
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS90LV001TM
See NS Package Number M08A
Order Number DS90LV001TLD
See NS Package Number LDA08A
www.national.com 14
DS90LV001
Notes
15 www.national.com
DS90LV001
Notes
DS90LV001 800 Mbps LVDS Buffer
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
Products Design Support
Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench
Audio www.national.com/audio Analog University www.national.com/AU
Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes
Data Converters www.national.com/adc Distributors www.national.com/contacts
Displays www.national.com/displays Green Compliance www.national.com/quality/green
Ethernet www.national.com/ethernet Packaging www.national.com/packaging
Interface www.national.com/interface Quality and Reliability www.national.com/quality
LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns
Power Management www.national.com/power Feedback www.national.com/feedback
Switching Regulators www.national.com/switchers
LDOs www.national.com/ldo
LED Lighting www.national.com/led
PowerWise www.national.com/powerwise
Serial Digital Interface (SDI) www.national.com/sdi
Temperature Sensors www.national.com/tempsensors
Wireless (PLL/VCO) www.national.com/wireless
THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION
(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,
IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT.
TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT
NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL
PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR
APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND
APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE
NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.
EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO
LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY
RIGHT.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other
brand or product names may be trademarks or registered trademarks of their respective holders.
Copyright© 2008 National Semiconductor Corporation
For the most current product information visit us at www.national.com
National Semiconductor
Americas Technical
Support Center
Email:
new.feedback@nsc.com
Tel: 1-800-272-9959
National Semiconductor Europe
Technical Support Center
Email: europe.support@nsc.com
German Tel: +49 (0) 180 5010 771
English Tel: +44 (0) 870 850 4288
National Semiconductor Asia
Pacific Technical Support Center
Email: ap.support@nsc.com
National Semiconductor Japan
Technical Support Center
Email: jpn.feedback@nsc.com
www.national.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Communications and Telecom www.ti.com/communications
Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers
Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps
DLP®Products www.dlp.com Energy and Lighting www.ti.com/energy
DSP dsp.ti.com Industrial www.ti.com/industrial
Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical
Interface interface.ti.com Security www.ti.com/security
Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright ©2011, Texas Instruments Incorporated
