12-Bit Serial Input Multiplying CMOS
Digital-to-Analog Converter
DAC8043
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
FEATURES
12-bit accuracy in an 8-lead PDIP and SOIC package
Fast serial data input
Double data buffers
Low ±½ LSB maximum INL and ±1 LSB maximum DNL
Maximum gain error: 2 LSB
Low ±5 ppm/°C maximum tempco
ESD resistant
Low cost
Available in die form
APPLICATIONS
Autocalibration systems
Process control and industrial automation
Programmable amplifiers and attenuators
Digitally controlled filters
FUNCTIONAL BLOCK DIAGRAM
12-BI T DAC
12-BIT
DAC REG IST E R
12-BIT
SHIFT REGISTER
12
12
DAC8043
R
FB
V
REF
LD
CLK
SRI GND
V
DD
I
OUT
R
FB
00271-001
Figure 1.
GENERAL DESCRIPTION
The DAC8043 is a high accuracy 12-bit CMOS multiplying
DAC in a space-saving 8-lead PDIP package. Featuring serial
data input, double buffering, and excellent analog performance,
the DAC8043 is ideal for applications where PC board space is
at a premium. In addition, improved linearity and gain error
performance permit reduced parts count through the elimination
of trimming components. Separate input clock and load DAC
control lines allow full user control of data loading and analog
output.
The circuit consists of a 12-bit serial-in, parallel-out shift register,
a 12-bit DAC register, a 12-bit CMOS DAC, and control logic.
Serial data is clocked into the input register on the rising edge
of the CLK pulse. When the new data word has been clocked
in, it is loaded into the DAC register with the LD input pin.
Data in the DAC register is converted to an output current by
the digital-to-analog converter (DAC).
The fast interface timing of the DAC8043 may reduce timing
design considerations while minimizing microprocessor wait
states. For applications requiring an asynchronous clear function
or more versatile microprocessor interface logic, refer to the
AD5443.
Operating from a single 5 V power supply, the DAC8043 is the
ideal low power, small size, high performance solution to many
application problems. It is available in a PDIP package that is
compatible with auto-insertion equipment. There is also a
16-lead SOIC package available.
DAC8043
Rev. E | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Wafe r Test Lim it s .......................................................................... 4
Absolute Maximum Ratings ............................................................ 5
Caution .......................................................................................... 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ..............................................7
Terminology .......................................................................................9
Digital Section ................................................................................. 10
General Circuit Information ..................................................... 10
Equivalent Circuit Analysis ...................................................... 11
Dynamic Performance ............................................................... 11
Applications Information .............................................................. 12
Application Tips ......................................................................... 12
Interfacing to the MC6800 ........................................................ 14
DAC8043 Interface to the 8085 ................................................ 14
DAC8043 to the 68000 Interface .............................................. 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
1/11—Rev. D to Rev. E
Updated Format .................................................................. Universal
Added SOIC_W Models .................................................... Universal
Added Table 5 .................................................................................... 6
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 15
3/03—Data Sheet Changed from Rev. C to Rev. D.
Deleted 8-Lead CIRDIP and 16-Lead Wide-Body SOL ...... Universal
Figures renumbered ........................................................... Universal
Changes to Absolute Maximum Ratings ....................................... 4
Changes to Ordering Guide ............................................................ 4
Deleted to Dice Characteristics ...................................................... 4
Updated Outline Dimensions ....................................................... 11
DAC8043
Rev. E | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 5 V; VREF = 10 V; IOUT = GND = 0 V; TA = full temperature range specified under the Absolute Maximum Ratings, unless otherwise
noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
STATIC ACCURACY
Resolution N 12 Bits
Nonlinearity1INL DAC8043G ±½ LSB
DAC8043F 1 LSB
Differential Nonlinearity2DNL ±1 LSB
Gain Error3GFSE TA = 25°C 2 LSB
T
A
= full temperature range, all grades 2 LSB
Gain Tempco (ΔGain/∆Temp)4TCGFS ±5 ppm/°C
Power Supply Rejection Ratio
(ΔGain/ΔVDD)
PSRR ΔVDD = ±5% ±0.0006 ±0.002 %/%
Output Leakage Current5ILKG TA = 25°C ±5 nA
TA = full temperature range ±25 nA
Zero Scale Error6, 7I
ZSE
T
A
= 25°C 0.03 LSB
TA = full temperature range 0.15 LSB
Input Resistance8RIN 7 11 15 kΩ
AC PERFORMANCE
Output Current
Settling Time4, 9tS TA = 25°C, VREF = 0 V 0.25 1 μs
Digital-to-Analog Glitch Energy4, 10 Q IOUT load = 100 Ω, CEXT = 13 pF, DAC register loaded
alternately with all 0s and all 1s
2 20 nVs
Feedthrough Error (VREF to IOUT)4, 11 FT VREF = 20 V p-p @ f = 10 kHz, digital input = 0000
0000 0000
0.7 1 mV p-p
TA = 25°C
Total Harmonic Distortion4 THD VREF = 6 V rms @ 1 kHz, DAC register loaded with
all 1s
–85 dB
Output Noise Voltage Density4, 12 en 10 Hz to 100 kHz between RFB and IOUT 17 nV/√Hz
DIGITAL INPUTS
Digital Input
High V
IN
2.4 V
Low VIL 0.8 V
Input Leakage Current13 IIL VIN = 0 V to +5 V ±1 μA
Input Capacitance4, 11 CIN VIN = 0 V 8 pF
ANALOG OUTPUTS
Output Capacitance4 COUT Digital inputs = VIH 110 pF
Digital inputs = VIL 80 pF
TIMING CHARACTERISTICS4, 14
Data Setup Time tDS TA = full temperature range 40 ns
Data Hold Time tDH TA = full temperature range 80 ns
Clock Pulsewidth High tCH TA = full temperature range 90 ns
Clock Pulsewidth Low t
CL
T
A
= full temperature range 120 ns
Load Pulsewidth t
LD
T
A
= full temperature range 120 ns
LSB Clock Into Input Register to
Load DAC Register Time
tASB TA = full temperature range 0 ns
DAC8043
Rev. E | Page 4 of 16
Parameter Symbol Conditions Min Typ Max Unit
POWER SUPPLY
Supply Voltage VDD 4.75 5 5.25 V
Supply Current IDD Digital inputs = VIH or VIL 500 μA
Digital inputs = 0 V or VDD 100 μA
1 ±1/2 LSB = ±0.012% of full scale.
2 All grades are monotonic to 12 bits over temperature.
3 Using internal feedback resistor.
4 Guaranteed by design and not tested.
5 Applies to IOUT; all digital inputs = 0 V.
6 VREF = 10 V; all digital inputs = 0 V.
7 Calculated from worst-case RREF: IZSE (in LSBs) = (RREF × ILKG × 4096)/VREF.
8 Absolute temperature coefficient is less than 300 ppm/°C.
9 IOUT load = 100 Ω , CEXT = 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to ½ LSB; tS = propagation delay (tPD) + 9τ
where τ = measured time constant of the final RC decay.
10 VREF = 0 V, all digital inputs = 0 V to VDD or VDD to 0 V.
11 All digit inputs = 0 V.
12 Calculations from en = √4K TRB
where:
K = Boltzmann constant, J/°K,
R = resistance, Ω,
T = resistor temperature, °K,
B = bandwidth, Hz.
13 Digital inputs are CMOS gates; IIN is typically 1 nA at 25°C.
14 Tested at VIN = 0 V or VDD.
WAFER TEST LIMITS
VDD = 5 V, VREF = 10 V; IOUT = GND = 0 V, TA = 25°C.
Table 2.
DAC8043GBC Limit
Parameter1 Symbol Conditions Min Typ Max Unit
STATIC ACCURACY
Resolution N 12 Bits
Integral Nonlinearity INL ±1 LSB
Differential Nonlinearity DNL ±1 LSB
Gain Error GFSE Using internal feedback resistor ±2 LSB
Power Supply Rejection Ratio PSRR ΔVDD = ±5% ±0.002 %/%
Output Leakage Current (IOUT) ILKG Digital inputs = VIL ±5 nA
REFERENCE INPUT
Input Resistance RIN 7
15 kΩ
DIGITAL INPUTS
Digital Input High VIH 2.4 V
Digital Input Low VIL 0.8 V
Input Leakage Current IIL VIN = 0 V to VDD ±1 μA
POWER SUPPLY
Supply Current IDD Digital inputs = VIN or VIL 500 μA
Digital inputs = 0 V or VDD 100 μA
1 Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult a factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
DAC8043
Rev. E | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND −0.3 V to +8 V
VREF to GND ±18 V
VRFB to GND ±18 V
Digital Input Voltage Range −0.3 V to VDD + 0.3 V
VIOUT to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range
FP Version −40°C to +85°C
GP Version 0°C to 70°C
Junction Temperature 150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
CAUTION
1. Do not apply voltages higher than VDD or less than GND
potential on any terminal except VREF and RFB.
2. The digital control inputs are Zener-protected; however,
permanent damage may occur on unprotected units from
high energy electrostatic fields. Keep units in conductive
foam at all times until ready to use.
3. Use proper antistatic handling procedures.
4. Absolute Maximum Ratings apply to both packaged devices
and dice. Stresses above those listed under the Absolute
Maximum Ratings may cause permanent damage to the
device.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA
θJC Unit
8-Lead PDIP 96 37 °C/W
16-Lead SOIC 92 27 °C/W
ESD CAUTION
DAC8043
Rev. E | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
00271-002
VREF 1
RFB 2
IOUT 3
GND 4
VDD
8
CLK
7
SRI
6
LD
5
DAC8043
TOP VIEW
(Not to Scale)
Figure 2. 8-Lead PDIP
00271-003
DAC8043
TOP VIEW
(Not to Scale)
NC 1
NC 2
VREF 3
RFB 4
NC
16
NC
15
VDD
14
CLK
13
IOUT 5SRI
12
GND 6LD
11
GND 7NC
10
NC 8NC
9
NC = NO CONNECT. DO NO T
CONNECT TO THIS PIN.
Figure 3. 16-Lead Wide-Body SOIC
Table 5. Pin Function Descriptions
Pin No.
8-Lead PDIP 16-Lead SOIC Mnemonic Description
1 3 VREF DAC Reference Voltage Input Pin.
2 4 RFB DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by
connecting to an external amplifier output.
3 5 IOUT DAC Current Output.
4 6, 7 GND Ground Pin.
5 11 LD Load Strobe, Level-Sensitive Digital Input. Transfers shift-register data to DAC register
while active low.
6 12 SRI 12-Bit Serial Register Input. Data loads directly into the shift register MSB first. Extra
leading bits are ignored.
7 13 CLK Serial Clock Input. Positive-edge clocks data into shift register.
8 14 V
Positive Power Supply Input.
1, 2, 8, 9, 10, 15, 16 NC Do Not Connect to These Pins.
DAC8043
Rev. E | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
0
–12
–24
–36
–48
–60
–72
–84
–96
–108
–1201k 10k 100k 1M 10M
FRE QUENCY ( Hz )
GAIN (d B)
00271-004
VDD = 5V
VREF = 100mV
TA = 25° C
DIGITAL INPUT =
1111 1111 1111
DIGITAL INPUT =
0000 0000 0000
Figure 4. Gain vs. Frequency (Output Amplifier: OP42)
0
–20
–40
–60
–80
–100
–12010 100 1k 10k 100k
FRE QUENCY ( Hz )
THD ( dB)
00271-005
V
DD
= 5V
V
IN
= 6V rms
OUTPUT AMPLIFIER: OP42
T
A
= 25° C
Figure 5. Total Harmonic Distortion vs. Frequency (Multiplying Mode)
1.0
0.8
0.6
0.4
0.2
00 1 2 3 4
V
IN
(V)
I
DD
(mA)
00271-006
Figure 6. Supply Current vs. Logic Input Voltage
0.5
0.3
0.1
–0.1
–0.3
–0.4
0.4
0.2
0
–0.2
–0.501024512 20481536 30722560 40953584
DIGITAL INPUT CO DE ( Decimal)
LINEARI TY E RROR (LSB)
00271-007
Figure 7. Linearity Error vs. Digital Input Code
DAC8043
Rev. E | Page 8 of 16
0.50
0.25
0
–0.25
–0.50
2 4 6 8 10
VREF (V)
INL (LSB)
00271-008
Figure 8. Linearity Error vs. Reference Voltage
4.0
3.0
2.0
2.4
1.0
–0.8
1 3 5 7 9 11 13 15
VDD (V)
THRESHOLD VOLTAGE (V)
00271-009
Figure 9. Logic Threshold Voltage vs. Supply Voltage
0.50
0.25
0
–0.25
–0.50
2 4 6 8 10
VREF (V)
DNL ( LSB)
00271-010
Figure 10. DNL Error vs. Reference Voltage
DAC8043
Rev. E | Page 9 of 16
TERMINOLOGY
Integral Nonlinearity (INL)
This is the single most important DAC specification. Analog
Devices, Inc., measures INL as the maximum deviation of
the analog output (from the ideal) from a straight line drawn
between the end points. It is expressed as a percent of full-scale
range or in terms of LSBs.
Refer to the Analog Devices Glossary of EE Terms for
additional digital-to-analog converter definitions.
Interface Logic Information
The DAC8043 has been designed for ease of operation. The
timing diagram (see Figure 12) illustrates the input register
loading sequence. Note that the most significant bit (MSB)
is loaded first.
Once the input register is full, the data is transferred to the
DAC register by taking LD
momentarily low.
DAC8043
Rev. E | Page 10 of 16
DIGITAL SECTION
The digital inputs of the DAC8043 (SRI, LD, and CLK) are TTL
compatible. The input voltage levels affect the amount of current
drawn from the supply; peak supply current occurs as the digital
input (VIN) passes through the transition region (see Figure 6).
Maintaining the digital input voltage levels as close as possible
to the VDD and GND supplies minimizes supply current
consumption.
The digital inputs of the DAC8043 have been designed with
ESD resistance incorporated through careful layout and the
inclusion of input protection circuitry. Figure 11 shows the input
protection diodes and series resistor; this input structure is
duplicated on each digital input. High voltage static charges
applied to the inputs are shunted to the supply and ground rails
through forward biased diodes. These protection diodes were
designed to clamp the inputs to well below dangerous levels
during static discharge conditions.
GENERAL CIRCUIT INFORMATION
The DAC8043 is a 12-bit multiplying digital-to-analog
converter (DAC) with a very low temperature coefficient.
It contains an R-2R resistor ladder network, data input,
control logic, and two data registers.
00271-011
TL/TTL/CMOS
INPUTS
VDD
Figure 11. Digital Input Protection
The digital circuitry forms an interface in which serial data
can be loaded under microprocessor control into a 12-bit shift
register and then transferred, in parallel, to the 12-bit DAC
register.
A simplified circuit of the DAC8043 is shown in Figure 13,
which has an inverted R-2R ladder network consisting of silicon-
chrome, highly stable (50 ppm/°C) thin-film resistors, and
twelve pairs of NMOS current-steering switches.
These switches steer binarily weighted currents into either IOUT
or GND; this yields a constant current in each ladder leg, regardless
of digital input code. This constant current results in a constant
input resistance at VREF equal to R. The VREF input may be driven by
any reference voltage or current, ac or dc, that is within the limits
stated in the Absolute Maximum Ratings section.
The twelve output current-steering NMOS FET switches are in
series with each R-2R resistor; they can introduce bit errors if all
are of the same RON resistance value. They were designed so that
the switch on resistance is binarily scaled so that the voltage drop
across each switch remains constant. If, for example, Switch S1 of
Figure 13 was designed with an on resistance of 10 Ω, Switch S2 for
20 Ω, and so on, a constant 5 mV drop would be maintained across
each switch.
BIT 12 LS B
BIT 1 MSB
1
BIT 11
SRI
CLK INPUT
1
DATA LOADE D M S B FI RST.
BIT 2
LD
tDS tDH
tASB
tLD
tCH
tCL
1 2 11
LOAD SERIAL DATA
INTO INPUT REGISTER
LOAD INPUT REGISTER’S
DATA INTO DAC REGI S TER
00271-012
Figure 12. Write Cycle Timing Diagram
DAC8043
Rev. E | Page 11 of 16
To further ensure accuracy across the full temperature range,
permanently on MOS switches were included in series with
the feedback resistor and the terminating resistor of the R-2R
ladder. The simplified DAC circuit, Figure 13, shows the location
of the series switches. These series switches are equivalently
scaled to two times Switch S1 (MSB) and to Switch S12 (LSB),
respectively, to maintain constant relative voltage drops with
varying temperature. During any testing of the resistor ladder
or RFEEDBACK (such as incoming inspection), VDD must be present
to turn on these series switches.
00271-013
20kΩ
20kΩ20kΩ
GND
IOUT
RFEEDBACK
S12S3
20kΩ
S2
20kΩ
S1
VREF 10kΩ10kΩ
*THESE SWITCHES PERMANENTLY ON.
10kΩ
10kΩ
BIT 1 (MS B) BIT 2
DIGITAL INP UTS
(SWITCHES SHOWN FOR DIGITAL INP UTS (HIG H) )
BIT 3 BIT 12 (L S B)
*
*
Figure 13. Simplified DAC Circuit
EQUIVALENT CIRCUIT ANALYSIS
Figure 14 shows an equivalent analog circuit for the DAC8043.
The (D × VREF)/R current source is code dependent and is the
current generated by the DAC. The current source, ILKG, consists
of surface and junction leakages and doubles approximately
every 10°C. COUT is the output capacitance; it is the result of
the N-channel MOS switches and varies from 80 pF to 110 pF,
depending on the digital input code. RO is the equivalent out-
put resistance that also varies with digital input code. R is the
nominal R-2R resistor ladder resistance.
00271-014
RCOUT
RFB
IOUT
VREF
GND
ILKG
D × VREF
R
R
R
Figure 14. Equivalent Analog Circuit
DYNAMIC PERFORMANCE
Output Impedance
The output resistance of the DAC8043, as in the case of the
output capacitance, varies with the digital input code. This
resistance, looking back into the IOUT terminal, may be between
10 kΩ (the feedback resistor alone when all digital inputs are low)
and 7.5 kΩ (the feedback resistor in parallel with approximately
30 kΩ of the R-2R ladder network resistance when any single bit
logic is high). Static accuracy and dynamic performance will be
affected by these variations. This variation is best illustrated by
using the circuit of Figure 15 and the following equation:
+=
O
FB
OSERROR
R
R
VV 1
where:
RO is a function of the digital code and
= 10 kΩ for more than four bits of Logic 1.
= 30 kΩ for any single bit of Logic 1.
Therefore, the offset gain varies as follows:
At Code 0011 1111 1111,
OSOS
1
ERROR
VVV 2
kΩ10
kΩ10
1=
+=
At Code 0100 0000 0000,
OSOS
2
ERROR VVV 3/4
kΩ30
kΩ10
1=
+=
The error difference is 2/3 VOS.
Because one LSB has a weight (for VREF = 10 V) of 2.4 mV for
the DAC8043, it is clearly important that VOS be minimized,
either by using the amplifier’s nulling pins or an external nulling
network or by selecting an amplifier with inherently low VOS.
Amplifiers with sufficiently low VOS include OP77, OP07, OP27,
and OP42.
00271-015
R
FB
V
REF
2R 2R 2R
ETC
RRR
OP77
V
OS
Figure 15. Simplified Circuit
The gain and phase stability of the output amplifier, board
layout, and power supply decoupling all affect the dynamic
performance. The use of a small compensation capacitor may
be required when high speed operational amplifiers are used. It
may be connected across the feedback resistor of the amplifier
to provide the necessary phase compensation to critically damp
the output. The output capacitance of the DAC8043 and the RFB
resistor form a pole that must be outside the amplifier’s unity
gain crossover frequency.
The considerations when using high speed amplifiers are:
1. Phase compensation (see Figure 16 and Figure 17).
2. Power supply decoupling at the device socket and the use
of proper grounding techniques.
DAC8043
Rev. E | Page 12 of 16
APPLICATIONS INFORMATION
APPLICATION TIPS
In most applications, linearity depends upon the potential
of the IOUT and GND pins being equal to each other. In most
applications, the DAC is connected to an external op amp
with its noninverting input tied to ground (see Figure 16 and
Figure 17). The amplifier selected should have a low input bias
current and low drift over temperature. The amplifier’s input offset
voltage should be nulled to less than 200 μV (less than 10% of
1 LSB).
The noninverting input of the operational amplifier should have
a minimum resistance connection to ground; the usual bias
current compensation resistor should not be used. This resistor
can cause a variable offset voltage appearing as a varying output
error. All grounded pins should tie to a single common ground
point, avoiding ground loops. The VDD power supply should
have a low noise level with no transients greater than 17 V.
Unipolar Operation (2-Quadrant)
The circuits shown in Figure 16 and Figure 17 may be used with
an ac or dc reference voltage. The output of the circuit ranges
between 0 V and approximately −VREF (4095/4096), depending
upon the digital input code. The relationship between the
digital input and the analog output is shown in Table 6. The
limiting parameters for the VREF range are the maximum input
voltage range of the op amp or ±25 V, whichever is lowest.
00271-016
OP77
DAC8043
3
26
4
7
+15V
5V
15pF
VOUT
RFB
VDD
VREF
IOUT
GND
SERIAL
DATA
INPUT
CLK
VREF
10V
–15V
LD
Figure 16. Unipolar Operation with High Accuracy Op Amp (2-Quadrant)
00271-017
OP42
DAC8043 2
36
4
7
+15V
5V
15pF
VOUT
RFB
VDD
VREF
IOUT
GND
SERIAL
DATA
INPUT
CLK
VREF
10V
R2
50Ω
R1
100Ω
–15V
LD
Figure 17. Unipolar Operation with Fast Op Amp and Gain Error Trimming
(2-Quadrant)
Gain error may be trimmed by adjusting R1, as shown in Figure 17.
The DAC register must first be loaded with all 1s. R1 may then
be adjusted until VOUT = −VREF (4095/4096). In the case of an
adjustable VREF, R1 and R2 may be omitted, with VREF adjusted
to yield the desired full-scale output.
In most applications, the DAC8043’s negligible zero-scale error
and very low gain error permit the elimination of the trimming
components (R1 and the external R2) without adversely affecting
on circuit performance.
Table 6. Unipolar Code Table1, 2
Digital Input Nominal Analog Output
MSB LSB (VOUT as Shown in Figure 16 and Figure 17)
1111 1111 1111
−4096
4095
REF
V
1000 0000 0001
−4096
2049
REF
V
1000 0000 0000
24096
2048 REF
REF
V
V−=
−
0111 1111 1111
−4096
2047
REF
V
0000 0000 0001
−4096
1
REF
V
0000 0000 0000
0
4096
0=
−
REF
V
1 Nominal full scale for Figure 16 and Figure 17 circuits is given by
−= 4096
4095
REF
VFS
2 Nominal LSB magnitude for Figure 16 and Figure 17 circuits is given by
( )
n
REFREF VVLSB −
=2or
4096
1
DAC8043
Rev. E | Page 13 of 16
Bipolar Operation (4-Quadrant)
Figure 19 details a suggested circuit for bipolar, or offset binary,
operation. Table 7 shows the digital input to analog output
relationship. The circuit uses offset binary coding. Twos comple-
ment code can be converted to offset binary by software
inversion of the MSB or by the addition of an external inverter
to the MSB input.
Table 7. Bipolar (Offset Binary) Code Table1, 2
Digital Input Nominal Analog Output
MSB LSB (VOUT as Shown in Figure 19)
1111 1111 1111
2048
2047
REF
V
1000 0000 0001
2048
1
REF
V
1000 0000 0000 0
0111 1111 1111
2048
1
REF
V
0000 0000 0001
2048
2047
REF
V
0000 0000 0000
2048
2048
REF
V
1 Nominal full scale for Figure 19 circuits is given by
2048
2047
REF
VFS
2 Nominal LSB magnitude for Figure 19 circuits is given by
2048
1
REF
VLSB
Resistors R3, R4, and R5 must be selected to match within 0.01%,
and they all must be of the same (preferably metal foil) type to
ensure temperature coefficient matching. Mismatching between
R3 and R4 causes offset and full-scale errors, while an R5 to R4
and R3 mismatch results in full-scale error.
Calibration is performed by loading the DAC register with 1000
0000 0000 and adjusting R1 until VOUT = 0 V. R1 and R2 may be
omitted, adjusting the ratio of R3 to R4 to yield VOUT = 0 V. Full
scale can be adjusted by loading the DAC register with 1111
1111 1111 and either adjusting the amplitude of VREF or the
value of R5 until the desired VOUT is achieved.
Analog/Digital Division
The transfer function for the DAC8043 connected in the
multiplying mode, as shown in Figure 16, Figure 17, and
Figure 19, is
12321 2
...
222
12321
IN
O
AAAA
VV
where AX assumes a value of 1 for an on bit and 0 for an off bit.
The transfer function is modified when the DAC is connected
in the feedback of an operational amplifier, as shown in Figure 18
and becomes
4321 2
...
222
12321
IN
OAAAA
V
V
The previous transfer function is the division of an analog
voltage (VREF) by a digital word. The amplifier goes to the rails
with all bits off because division by zero is infinity. With all bits
on the gain is 1 (±1 LSB). The gain becomes 4096 with the LSB,
Bit 12, on.
DAC8043
RFB VDD 5V
LD SRI CLK
VREF
IOUT
GND
DIGITAL
INPUT
V
IN
00271-019
OP42
2
3
6VOUT
Figure 18. Analog/Digital Divider
00271-018
V
OUT
CONTROL
INPUTS
SERIAL
DATA
INPUT
ANALOG
COMMON
V
IN
R
2
50Ω
R
3
10kΩ
5V
R
4
20kΩ
R
5
20kΩ
R
1
100Ω
C
1
10.33pF
1/2
OP200
A
2
DAC8043
R
FB
V
DD
V
REF
I
OUT
GND
CONTROL
BITS SRI
1/2
OP200
A
1
Figure 19. Bipolar Operation (4-Quadrant, Offset Binary)
DAC8043
Rev. E | Page 14 of 16
INTERFACING TO THE MC6800
As shown in Figure 20, the DAC8043 may be interfaced to the
MC6800 by successively executing memory write instructions
while manipulating the data between writes, so that each write
presents the next bit.
In this example, the most significant bits are found in the 0000
and 0001 memory locations. The four MSBs are found in the
lower half of 0000 and the eight LSBs in 0001. The data is taken
from the DB7 line.
The serial data loading is triggered by the CLK pulse, which
is asserted by a decoded memory write to the 2000 memory
location, R/W, and Φ2. A write to address location 4000
transfers data from the input register to the DAC register.
00271-020
74LS138
ADDRESS
DECODER
A
0
A
0
A
15
DB
0
DB
7
E
1
E
3
E
2
A
2
SRI
CLK
LD
DAC8043*
16-BI T DATA BUS
R/W
Φ2
8-BI T DATA BUS
MC6800
*ANALOG CIRCUITRY OMITTED
FOR SIMPLICITY.
Figure 20. DAC8043 to MC6800 Interface
DAC8043 INTERFACE TO THE 8085
The interface of the DAC8043 to the 8085 microprocessor
is shown in Figure 21. Note that the SOD line of the micro-
processor is used to present data serially to the DAC.
Data is clocked into the DAC8043 by executing memory write
instructions. The clock input is generated by decoding Address
8000 and WR. Data is loaded into the DAC register with a
memory write instruction to Address A000.
Serial data supplied to the DAC8043 must be present in
the right-justified format in Register H and Register L of the
microprocessor.
00271-021
A
0
A
15
AD
0
AD
7
(8)
(8)
ALE
SOD SRI
*ANALOG CIRCUITRY OMITTED FOR
SIMPLICITY.
CLK
LD
DAC8043*
ADDRESS BUS ( 16)
DATA
8085
8212
WR
74LS138
ADDRESS
DECODER
A
0
E
1
E
3
5V
E
2
A
2
Figure 21. DAC8043 to 8085 Interface
DAC8043 TO THE 68000 INTERFACE
The interface of the DAC8043 to the 68000 microprocessor is
shown in Figure 22. Serial data to the DAC is taken from one
of the microprocessor’s data bus lines.
00271-022
A1
A23
AS
VMA
VPA
UDS
DB0
DB15
SRI
CLK LD
DAC8043*
ADDRESS BUS
DATA BUS
1/4 74HC125
68000
MICRO-
PROCESSOR
*ANALOG CIRCUITRY OMITTED FOR SIMPLICITY.
ADDRESS
DECODE
CS
+
Figure 22. DAC8043 to 68000 Microprocessor Interface
DAC8043
Rev. E | Page 15 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JE DE C S TANDARDS MS - 001
CONTROLLING DIMENSIONSARE IN INCHES; MILLI MET ER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED- OFF I NCH E QUIVALENTS FOR
REF E RE NCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNE R LEADS MAY BE CONF IG URE D AS WHOLE OR HALF L E ADS .
070606-A
0.022 ( 0.56)
0.018 ( 0.46)
0.014 ( 0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 ( 5.33)
MAX
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2.92)
0.070 ( 1.78)
0.060 ( 1.52)
0.045 ( 1.14)
8
14
5
0.280 ( 7.11)
0.250 ( 6.35)
0.240 ( 6.10)
0.100 ( 2.54)
BSC
0.400 ( 10.16)
0.365 ( 9.27)
0.355 ( 9.02)
0.060 ( 1.52)
MAX
0.430 ( 10.92)
MAX
0.014 ( 0.36)
0.010 ( 0.25)
0.008 ( 0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.195 ( 4.95)
0.130 ( 3.30)
0.115 (2.92)
0.015 ( 0.38)
GAUGE
PLANE
0.005 ( 0.13)
MIN
Figure 23. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENT
HESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
DAC8043
Rev. E | Page 16 of 16
ORDERING GUIDE
Model1, 2Relative Accuracy
Temperature Range Package Description Package Option
DAC8043FP ±1 LSB −40°C to +85°C 8-Lead PDIP N-8
DAC8043FPZ ±1 LSB −40°C to +85°C 8-Lead PDIP N-8
DAC8043FSZ ±1 LSB −40°C to +85°C 16-Lead SOIC_W RW-16
DAC8043GP ±½ LSB 0°C to 70°C 8-Lead PDIP N-8
DAC8043GPZ ±½ LSB 0°C to 70°C 8-Lead PDIP N-8
1 Z = RoHS Compliant Part.
2 All commercial and industrial temperature range parts are available with burn-in.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00271-0-1/11(E)