CORPORATION log N-Channel JFET Switch FEATURES e Low Cost e Automated Insertion Package e Low Insertion Loss @ No Offset or Error Voltage Generated By Closed Switch ~ Purely Resistive = High Isolation Resistance From Driver J717 - J113/SST111 SST113 APPLICATIONS e Analog Switches e Choppers e Commutators ABSOLUTE MAXIMUM RATINGS (Ta = 25C unless otherwise specified) e Fast Switching Gata-Drain or Gate-Source Voltage ................ -35V e Short Sample and Hold Aperture Time Gate Current .. 0.2... eee eee 50mA Storage Temperature Range ............. 55C to+1 50C Operating Temperature Range ........... 55C to +135C PIN CONFIGURATION Lead Temperature (Soldering, 10sec) ............. +300C Power Dissipation .......... 0... cece eee eee 360mW SoT-23 Derate above 25C 2... cece cee eee 3.3mW/C ga G NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or TO.92 any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING INFORMATION Part Package Temperature Range J111-113 Plastic SOT-23 -~55C to +135C 5G PRODUCT MARKING (SOT-23) $ST111-113 Plastic SOT-23 -55C to +135C 9 For Sorted Chips in Carriers see 2N4391 series. SST111 111 5001 SST112 112 SST113 113 ELECTRICAL CHARACTERISTICS (Ta = 25C unless otherwise specified) 111 W2 113 SYMBOL PARAMET TEST CONDITION ER MIN | TYP [MAX] MIN | TYP | MAX] MIN | TYP | MAX UNITS C TIONS lessa Gate Reverse Current (Note 1) 1 1 -1 nA | Vos = OV, Vas = -15V Vesi(ott} Gate Source Cutoff Voltage -3 -10 | -1 -5 | -0.5 3 Vv Vos = 5V, lo = 1A BVess Gate Source Breakdown Voltage | -35 -35 -35 Vos = OV, Iq =-1pA loss Drain Saturation Current (Note 2) | 20 5 2 mA_| Vos = 18V, Vas = OV Ipyoth Drain Cutoff Current (Note 1) 1 1 1 nA Vos = 5V, Vas = -10V TDS(on) Drain Source ON Resistance 30 50 100 Q Vos = 0.1V, Vas = 0V Cagiott) Drain Gate OFF Capacitance 5 5 5 yes = i} ov - Gs = - Cesgiot Source Gate OFF Capacitance 5 5 5 pF | (Note 3) f= 1MHz Cagcon} Drain Gate Pius Source Gate ON 2B 28 28 Vos = Vas = 0 + Cegion)_| Capacitance (Note 3) tyfon) Turn On Delay Time 7 7 7 Switching Time Test i Conditions (Note 3) t Rise Time 6 6 6 Wi die Jttg ta(ott) Turn Off Delay Time 20 20 20 "S lVoo 10V 10V. 10V 4 Fail Time 15 15 15 Reo aka Veo 9ko NOTES: 1. Approximately doubles for every 10C increase in Ta. 2. Pulse test duration 300ps; duty cycle <3%. 3. For design reference only, not 100% tested. 8-41