Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 LM6181 100 mA, 100 MHz Current Feedback Amplifier 1 Features(1) 3 Description * * * The LM6181 current-feedback amplifier offers an unparalleled combination of bandwidth, slew-rate, and output current. The amplifier can directly drive up to 100 pF capacitive loads without oscillating and a 10-V signal into a 50- or 75- back-terminated coax cable system over the full industrial temperature range. This represents a radical enhancement in output drive capability for an 8-pin PDIP high-speed amplifier making it ideal for video applications. 1 * * * * Slew Rate: 2000 V/s Settling Time (0.1%): 50 ns Characterized for Supply Ranges: 5 V and 15 V Low Differential Gain and Phase Error: 0.05%, 0.04 High Output Drive: 10 V into 100 Ensured Bandwidth and Slew Rate Improved Performance Over EL2020, OP160, AD844, LT1223 and HA5004 (1) Typical, unless otherwise noted 2 Applications * * * * * Coax Cable Driver Video Amplifier Flash ADC Buffer High Frequency Filter Scanner and Imaging Systems Cable Driver Built on TI's advanced high-speed VIPTM II (Vertically Integrated PNP) process, the LM6181 employs current-feedback providing bandwidth that does not vary dramatically with gain; 100 MHz at AV = -1, 60 MHz at AV = -10. With a slew rate of 2000V/s, 2nd harmonic distortion of -50 dBc at 10 MHz and settling time of 50 ns (0.1%) the LM6181 dynamic performance makes it ideal for data acquisition, high speed ATE, and precision pulse amplifier applications. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM6181 PDIP (8) 9.81 mm x 6.35 mm LM6181 CDIP (8) 10.16 mm x 6.502 mm LM6181 SOIC (16) 9.90 mm x 3.91 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Step Response VIN (2 V/div) VOUT (2 V/div) Time (50 ns/div) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 4 4 4 4 5 6 7 8 9 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. 15V DC Electrical Characteristics ........................... 15V AC Electrical Characteristics ........................... 5V DC Electrical Characteristics ............................. 5V AC Electrical Characteristics ............................. Typical Performance Characteristics ........................ 7 Typical Applications ............................................ 22 7.1 Current Feedback Topology ................................... 7.2 Power Supply Bypassing and Layout Considerations ......................................................... 7.3 Feedback Resistor Selection: Rf............................. 7.4 Slew Rate Considerations....................................... 7.5 Driving Capacitive Loads ........................................ 7.6 Capacitive Feedback............................................... 22 23 23 24 25 27 8 Application and Implementation ........................ 28 9 Device and Documentation Support.................. 32 8.1 Typical Application ................................................. 28 9.1 Trademarks ............................................................. 32 9.2 Electrostatic Discharge Caution .............................. 32 9.3 Glossary .................................................................. 32 10 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (May 2013) to Revision C Page * Changed data sheet structure and organization. Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions, Application and Implementation; Device and Documentation Support; Mechanical, Packaging, and Ordering Information. Updated selected plots for readability. .................................. 1 * Changed "Junction Temperature Range" to " Operating Temperature Range" and deleted TJ ............................................ 4 * Deleted TJ = 25C for Electrical Characteristics tables .......................................................................................................... 5 Changes from Revision A (May 2013) to Revision B * 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 5 Pin Configuration and Functions * indicates heat sinking pins (1) 8-Pin CDIP, PDIP, or SOIC Package NAB, P, or D (Top View) 16-Pin SOIC Package D (Top View) Pin Functions PIN NAME NUMBER I/O DESCRIPTION NAB, P, D (8) D (16) -IN 2 2 I Inverting Input +IN 3 3 I Non-inverting Input 1, 5, 8 5, 6, 7 12, 13, 14, 15 -- No Connection N/C OUTPUT 6 10 O Output V- 4 1, 4, 8, 9, 16 I Negative Supply V+ 7 11 I Positive Supply (1) The typical junction-to-ambient thermal resistance of the molded PDIP package soldered directly into a PC board is 102C/W. The junction-to-ambient thermal resistance of the SOIC package mounted flush to the PC board is 70C/W when pins 1, 4, 8, 9 and 16 are soldered to a total 2 in2 1 oz. copper trace. The 16-pin SOIC package must have pin 4 and at least one of pins 1, 8, 9, or 16 connected to V- for proper operation. The typical junction-to-ambient thermal resistance of the SOIC package soldered directly into a PC board is 153C/W. Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 3 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) MIN Supply Voltage Differential Input Voltage Input Voltage Soldering Information SOIC Package V V 15 mA Soldering (10 sec) 260 C Vapor Phase (60 seconds) 215 C 220 C Infrared (15 seconds) See (3) Maximum Junction Temperature (2) (3) V 6 Output Short Circuit (1) UNIT 18 Supply Voltage Inverting Input Current PDIP Package MAX 150 C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions the device is intended to be functional, but device parameter specifications may not be ensured under these conditions. For ensured specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. Output currents in excess of 130 mA over a long term basis may adversely affect reliability. 6.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) Electrostatic discharge MIN MAX UNIT -65 +150 C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 3000 V JEDEC document JEP155 states that 3000-V HBM allows safe manufacturing with a standard ESD control process. Human body model 100 pF and 1.5 k. 6.3 Recommended Operating Conditions (1) over operating free-air temperature range (unless otherwise noted) MIN MAX 7 32 V LM6181AM -55 +125 C LM6181AI, LM6181I -40 +85 C Supply Voltage Range Operating Temperature Range (1) UNIT For ensured Military Temperature Range parameters see RETS6181X. 6.4 Thermal Information THERMAL METRIC (1) (2) P (PDIP) D (SOIC) D (SOIC) 8 PINS 8 PINS 16 PINS RJA Junction-to-ambient thermal resistance 102 153 70 RJC(top) Junction-to-case (top) thermal resistance 42 42 38 (1) (2) 4 UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The typical junction-to-ambient thermal resistance of the molded PDIP package soldered directly into a PC board is 102C/W. The junction-to-ambient thermal resistance of the SOIC package mounted flush to the PC board is 70C/W when pins 1, 4, 8, 9 and 16 are soldered to a total 2 in2 1 oz. copper trace. The 16-pin SOIC package must have pin 4 and at least one of pins 1, 8, 9, or 16 connected to V- for proper operation. The typical junction-to-ambient thermal resistance of the SOIC package soldered directly into a PC board is 153C/W." Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 6.5 15V DC Electrical Characteristics The following specifications apply for Supply Voltage = 15V, RF = 820 , and RL = 1 k unless otherwise noted. Boldface limits apply at the temperature extremes. PARAMETER TEST CONDITIONS LM6181AM TYP (1) VOS Input Offset Voltage TC VOS Input Offset Voltage Drift IB Inverting Input Bias Current TC IB IB PSR 2.0 LM6181AI LIMIT (2) 3.0 4.0 5.0 TYP (1) 2.0 LM6181I LIMIT (2) 3.0 3.5 5.0 TYP (1) 3.5 LIMIT (2) 5.0 5.5 2.0 5.0 12.0 2.0 Non-Inverting Input Bias Current 0.5 1.5 3.0 0.5 1.5 3.0 Inverting Input Bias Current Drift 30 30 30 Non-Inverting Input Bias Current Drift 10 10 10 mV max V/C 5.0 5.0 12.0 UNIT 5.0 10 17.0 2.0 3.0 5.0 A max nA/C Inverting Input Bias Current Power Supply Rejection VS = 4.5V, 16V Non-Inverting Input Bias Current Power Supply Rejection VS = 4.5V, 16V Inverting Input Bias Current Common Mode Rejection -10V VCM +10V Non-Inverting Input Bias Current Common Mode Rejection -10V VCM +10V CMRR Common Mode Rejection Ratio PSRR 0.3 0.5 3.0 0.3 0.5 3.0 0.3 0.75 4.5 0.05 0.5 1.5 0.05 0.5 1.5 0.05 0.5 3.0 0.3 0.5 0.75 0.3 0.5 0.75 0.3 0.75 1.0 0.1 0.5 0.5 0.1 0.5 0.5 0.1 0.5 0.5 -10V VCM +10V 60 50 50 60 50 50 60 50 50 dB min Power Supply Rejection Ratio VS = 4.5V, 16V 80 70 70 80 70 70 80 70 65 dB min RO Output Resistance AV = -1, f = 300 kHz 0.2 RIN Non-Inverting Input Resistance VO Output Voltage Swing IB CMR ISC Output Short Circuit Current ZT Transimpedance IS Supply Current VCM Input Common Mode Voltage Range (1) (2) 0.2 10 10 0.2 10 M min RL = 1 k 12 11 11 12 11 11 12 11 11 RL = 100 11 10 7.5 11 10 8.0 11 10 8.0 130 100 75 130 100 85 130 100 85 1.8 1.0 0.5 1.8 1.0 0.5 1.8 0.8 0.4 RL = 100 1.4 0.8 0.4 1.4 0.8 0.4 1.4 0.7 0.35 No Load, VO = 0V 7.5 10 10 7.5 10 10 7.5 10 10 RL = 1 k V+ - 1.7 V- + 1.7 V+ - 1.7 V- + 1.7 A/V max V+ - 1.7 V- + 1.7 V min mA min M min mA max V Typical values represent the most likely parametric norm. All limits ensured at room temperature (standard type face) or at operating temperature extremes (bold face type). Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 5 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com 6.6 15V AC Electrical Characteristics The following specifications apply for Supply Voltage = 15V, RF = 820 , RL = 1 k unless otherwise noted. Boldface limits apply at the temperature extremes. PARAMETER TEST CONDITIONS LM6181AM TYP (1) Closed Loop Bandwidth -3 dB BW PBW Power Bandwidth 100 100 80 80 AV = -1 100 AV = -10 60 AV = -1, VO = 5 VPP 80 LM6181I LIMIT (2) AV = +10 100 TYP (1) 100 80 80 60 100 60 60 60 2000 2000 1400 ts Settling Time (0.1%) AV = -1, VO = 5V RL = 150 tr, tf Rise and Fall Time tp Propagation Delay Time in(+) Non-Inverting Input f = 1 kHz Noise Current Density Inverting Input Noise Current Density f = 1 kHz in(-) Input Noise Voltage Density f = 1 kHz en Second Harmonic Distortion 1000 1400 80 MHz min 60 2000 AV = -1, VO = 10V, RL = 150 (3) UNIT LIMIT (2) Overdriven Slew Rate 6 TYP (1) AV = +2 SR (1) (2) (3) LM6181AI LIMIT (2) 1000 1400 1000 V/s min 50 50 50 VO = 1 VPP 5 5 5 VO = 1 VPP 6 6 6 3 3 3 pA/Hz 16 16 16 pA/Hz 4 4 4 pA/Hz 2 VPP, 10 MHz -50 -50 -50 Third Harmonic Distortion 2 VPP, 10 MHz -55 -55 -50 Differential Gain RL = 150, AV = +2, NTSC 0.05% 0.05% 0.05% Differential Phase RL = 150, AV = +2, NTSC 0.04 0.04 0.04 ns dBc Deg Typical values represent the most likely parametric norm. All limits ensured at room temperature (standard type face) or at operating temperature extremes (bold face type). Measured from +25% to +75% of output waveform. Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 6.7 5V DC Electrical Characteristics The following specifications apply for Supply Voltage = 5V, RF = 820 , and RL = 1 k unless otherwise noted. Boldface limits apply at the temperature extremes. PARAMETER TEST CONDITIONS LM6181AM TYP (1) VOS Input Offset Voltage TC VOS Input Offset Voltage Drift IB Inverting Input Bias Current TC IB IB PSR LM6181AI LIMIT (2) 1.0 2.0 3.0 2.5 TYP (1) LM6181I LIMIT (2) 1.0 2.0 2.5 2.5 TYP (1) LIMIT (2) 1.0 3.0 3.5 5.0 10 22 5.0 Non-Inverting Input Bias Current 0.25 1.5 1.5 0.25 1.5 1.5 Inverting Input Bias Current Drift 50 50 50 Non-Inverting Input Bias Current Drift 3.0 3.0 3.0 5.0 17.5 27.0 0.25 3.0 5.0 VS = 4.0V, 6.0V Non-Inverting Input Bias Current Power Supply Rejection VS = 4.0V, 6.0V Inverting Input Bias Current Common Mode Rejection -2.5V VCM +2.5V Non-Inverting Input Bias Current Common Mode Rejection -2.5V VCM +2.5V CMRR Common Mode Rejection Ratio PSRR 0.3 0.5 0.5 0.3 0.5 0.5 0.3 1.0 1.0 0.05 0.5 0.5 0.05 0.5 0.5 0.05 0.5 0.5 0.3 0.5 1.0 0.3 0.5 1.0 0.3 1.0 1.5 0.12 0.5 1.0 0.12 0.5 0.5 0.12 0.5 0.5 -2.5V VCM +2.5V 57 50 47 57 50 47 57 50 47 Power Supply Rejection Ratio VS = 4.0V, 6.0V 80 70 70 80 70 70 80 64 64 RO Output Resistance AV = -1, f = 300 kHz RIN Non-Inverting Input Resistance VO Output Voltage Swing ISC Output Short Circuit Current ZT Transimpedance IS Supply Current VCM Input Common Mode Voltage Range (1) (2) A max nA/C Inverting Input Bias Current Power Supply Rejection IB CMR mV max V/C 2.5 10 22 UNIT 0.25 0.25 8 M min 8 RL = 1 k 2.6 2.25 2.2 2.6 2.25 2.25 2.6 2.25 2.25 RL = 100 2.2 2.0 2.0 2.2 2.0 2.0 2.2 2.0 2.0 100 75 70 100 75 70 100 75 70 1.4 0.75 0.35 1.4 0.75 0.4 1.0 0.6 0.3 RL = 100 1.0 0.5 0.25 1.0 0.5 0.25 1.0 0.4 0.2 No Load, VO = 0V 6.5 8.5 8.5 6.5 8.5 8.5 6.5 8.5 8.5 RL = 1 k V+ - 1.7 V- + 1.7 V+ - 1.7 V- + 1.7 dB min 0.25 8 A/V max V+ - 1.7 V- + 1.7 V min mA min M min mA max V Typical values represent the most likely parametric norm. All limits ensured at room temperature (standard type face) or at operating temperature extremes (bold face type). Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 7 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com 6.8 5V AC Electrical Characteristics The following specifications apply for Supply Voltage = 5V, RF = 820 , and RL = 1 k unless otherwise noted. Boldface limits apply at the temperature extremes. PARAMETER TEST CONDITIONS LM6181AM TYP (1) BW Closed Loop Bandwidth -3 dB LM6181AI LIMIT (2) TYP (1) LM6181I LIMIT (2) TYP (1) AV = +2 50 50 AV = +10 40 40 AV = -1 55 AV = -10 35 35 35 40 40 35 55 LIMIT (2) UNIT 50 40 35 55 35 MHz min 375 V/s min PBW Power Bandwidth AV = -1, VO = 4 VPP 40 SR Slew Rate AV = -1, VO = 2V, RL = 150 (3) 500 ts Settling Time (0.1%) AV = -1, VO = 2V RL = 150 50 50 50 tr, tf Rise and Fall Time VO = 1 VPP 8.5 8.5 8.5 tp Propagation Delay Time VO = 1 VPP 8 8 8 in(+) Non-Inverting Input Noise Current Density f = 1 kHz 3 3 3 pA/Hz in(-) Inverting Input Noise Current Density f = 1 kHz 16 16 16 pA/Hz en Input Noise Voltage Density f = 1 kHz 4 4 4 pA/Hz Second Harmonic Distortion 2 VPP, 10 MHz -45 -45 -45 Third Harmonic Distortion 2 VPP, 10 MHz -55 -55 -55 Differential Gain RL = 150 , AV = +2, NTSC 0.063% 0.063% 0.063% Differential Phase RL = 150 , AV = +2, NTSC 0.16 0.16 0.16 (1) (2) (3) 8 375 500 375 500 ns dBc Deg Typical values represent the most likely parametric norm. All limits ensured at room temperature (standard type face) or at operating temperature extremes (bold face type). Measured from +25% to +75% of output waveform. Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 6.9 Typical Performance Characteristics TA = 25C unless otherwise noted Figure 1. Closed-loop Frequency Response VS = 15V; Rf = 820 ; RL = 1 k Figure 2. Closed-loop Frequency Response VS = 15V; Rf = 820 ; RL = 150 Figure 3. Unity Gain Frequency Response VS = 15V; AV = +1; Rf = 820 Figure 4. Unit Gain Frequency Response VS = 5V; AV = +1; Rf = 820 Figure 5. Frequency Response Vs Supply Voltage AV = -1; Rf = 820 ; RL = 1 k Figure 6. Frequency Response vs. Supply Voltage AV = -1; Rf = 820 ; RL = 150 Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 9 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) TA = 25C unless otherwise noted 10 Figure 7. Inverting Gain Frequency Response VS = 15V; AV = -1; Rf = 820 Figure 8. Inverting Gain Frequency Response VS = 5V; AV = -1; Rf = 82 0 Figure 9. Non-inverting Gain Frequency Response VS = 15V; AV = +2; Rf = 820 Figure 10. Non-inverting Gain Frequency Response VS = 5V; AV = +2; Rf = 820 Figure 11. Inverting Gain Frequency Response VS = 15V; AV = -10; Rf = 820 Figure 12. Inverting Gain Frequency Response VS = 5V; AV = -10; Rf = 820 Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) TA = 25C unless otherwise noted Figure 13. Non-inverting Gain Frequency Response VS = 15V; AV = +10; Rf = 820 Figure 15. Non-inverting Gain Frequency Compensation VS = 15V; AV = +2; RL = 150 Figure 14. Non-inverting Gain Frequency Response VS = 5V; AV = +10; Rf = 820 Figure 16. Bandwidth vs Rf & RS AV = -1, RL = 1 k Figure 17. Output Swing vs RLOAD Pulsed, VS = 15V, IIN = 200 A, VIN+ = 0V Figure 18. Transimpedance vs Frequency VS = 15V RL = 1 k Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 11 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) TA = 25C unless otherwise noted Figure 19. Transimpedance vs Frequency VS = 15V RL = 100 Figure 20. Transimpedance vs Frequency VS = 5V RL = 1 k Figure 21. Settling Response VS = 15V; RL = 150; VO = 5V; AV = -1 Figure 22. Settling Response VS = 5V; RL = 150 ; VO = 2V; AV = -1 Figure 23. Suggested Rf and RS for CL AV = - 1; RL = 150 12 Submit Documentation Feedback Figure 24. Transimpedance vs Frequency VS = 5V RL = 100 Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) TA = 25C unless otherwise noted Figure 25. Suggested Rf and RS for CL AV = -1 Figure 26. Suggested Rf and RS for CL AV = +2; RL = 150 Figure 27. Suggested Rf and RS for CL AV = +2 Figure 28. Output Impedance vs Freq VS = 15V; AV = -1 Rf = 820 Figure 29. Output Impedance vs Freq VS = 5V; AV = -1 Rf = 820 Figure 30. PSRR (VS+) vs Frequency Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 13 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) TA = 25C unless otherwise noted 14 Figure 31. PSRR (VS-) vs Frequency Figure 32. CMRR vs Frequency Figure 33. Input Voltage Noise vs Frequency Figure 34. Input Current Noise vs Frequency Figure 35. Slew Rate vs Temperature AV = -1; RL = 150 , VS = 15V Figure 36. Slew Rate vs Temperature AV = -1; RL = 150 , VS = 5V Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) TA = 25C unless otherwise noted Figure 37. -3 dB Bandwidth vs Temperature AV = -1 Figure 38. Small Signal Pulse response vs Temp, AV = +1 VS = 15V; RL = 1 k Figure 39. Small Signal Pulse Response vs Temp, AV = +1 VS = 15V; RL = 100 Figure 40. Small Signal Pulse Response vs Temp, AV = +1 VS = 5V; RL = 1 k Figure 41. Small Signal Pulse Response vs Temp, AV = +1 VS = 5V; RL = 100 Figure 42. Small Signal Pulse Response vs Temp, AV = -1 VS = 15V; RL = 1 k Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 15 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) TA = 25C unless otherwise noted 16 Figure 43. Small Signal Pulse Response vs Temp, AV = -1 VS = 15V; RL = 100 Figure 44. Small Signal Pulse Response vs Temp, AV = -1 VS = 5V; RL = 1 k Figure 45. Small Signal Pulse Response vs Temp, AV = -1 VS = 5V; RL = 100 Figure 46. Small Signal Pulse Response vs Temp, AV = +2 VS = 15V; RL = 1 k Figure 47. Small Signal Pulse Response vs Temp, AV = +2 VS = 15V; RL = 100 Figure 48. Small Signal Pulse Response vs Temp, AV = +2 VS = 5V; RL = 1 k Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) TA = 25C unless otherwise noted Figure 49. Small Signal Pulse Response vs Temp, AV = +2 VS = 5V; RL = 100 Figure 50. Small Signal Pulse Response vs Temp, AV = -10 VS = 15V; RL = 1 k Figure 51. Small Signal Pulse Response vs Temp, AV = -10 VS = 15V; RL = 100 Figure 52. Small Signal Pulse Response vs Temp, AV = -10 VS = 5V; RL = 1 k Figure 53. Small Signal Pulse Response vs Temp, AV = -10 VS = 5V; RL = 100 Figure 54. Small Signal Pulse Response Vs Temp, AV = +10 VS = 15V; RL = 1 k Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 17 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) TA = 25C unless otherwise noted 18 Figure 55. Small Signal Pulse Response vs Temp, AV = +10 VS = 15V; RL = 100 Figure 56. Small Signal Pulse Response vs Temp, AV = +10 VS = 5V; RL = 1 k Figure 57. Small Signal Pulse Response vs Temp, AV = +10 VS = 5V; RL = 100 Figure 58. Offset Voltage vs temperature Figure 59. Offset Voltage vs Temperature Figure 60. Transimpedance vs Temperature Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) TA = 25C unless otherwise noted Figure 61. Transimpedance vs Temperature Figure 62. Quiescent Current vs Temperature Figure 63. PSRR vs Temperature Figure 64. CMRR vs Temperature Figure 65. Non-inverting Bias Current vs Temperature Figure 66. Inverting Bias Current vs Temperature Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 19 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) TA = 25C unless otherwise noted 20 Figure 67. PSR IB(+) vs Temperature Figure 68. PSR IB(-) vs Temperature Figure 69. CMR IB(+) vs Temperature Figure 70. CMR IB(-) vs Temperature Figure 71. ISC(+) vs Temperature Figure 72. ISC(-) vs Temperature Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) TA = 25C unless otherwise noted *JA = Thermal Resistance with 2 square inches of 1 ounce Copper tied to Pins 1, 8, 9 and 16. Figure 73. Absolute Maximum Power Derating: PDIP Package Figure 74. Absolute Maximum Power Derating: SOIC-16 package Figure 75. Absolute Maximum Power Derating: SOIC-8 package Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 21 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com 7 Typical Applications 7.1 Current Feedback Topology For a conventional voltage feedback amplifier the resulting small-signal bandwidth is inversely proportional to the desired gain to a first order approximation based on the gain-bandwidth concept. In contrast, the current feedback amplifier topology, such as the LM6181, transcends this limitation to offer a signal bandwidth that is relatively independent of the closed-loop gain. Figure 76 and Figure 77 illustrate that for closed loop gains of -1 and -5 the resulting pulse fidelity suggests quite similar bandwidths for both configurations. VOUT (0.1 V/div) Time (5 ns/div) Figure 76. Step Response, Av = -1V/V VOUT (0.1 V/div) Time (5 ns/div) Variation of Closed Loop Gain from -1 to -5 Yields Similar Responses Figure 77. Step Response, Av = -5V/V 22 Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 Current Feedback Topology (continued) The closed-loop bandwidth of the LM6181 depends on the feedback resistance, Rf. Therefore, RS and not Rf, must be varied to adjust for the desired closed-loop gain as in Figure 78. Figure 78. RS Is Adjusted to Obtain the Desired Closed Loop Gain, AVCL 7.2 Power Supply Bypassing and Layout Considerations A fundamental requirement for high-speed amplifier design is adequate bypassing of the power supply. It is critical to maintain a wideband low-impedance to ground at the amplifiers supply pins to insure the fidelity of high speed amplifier transient signals. 10 F tantalum and 0.1 F ceramic bypass capacitors are recommended for each supply pin. The bypass capacitors should be placed as close to the amplifier pins as possible (0.5 or less). 7.3 Feedback Resistor Selection: Rf Selecting the feedback resistor, Rf, is a dominant factor in compensating the LM6181. For general applications the LM6181 will maintain specified performance with an 820 feedback resistor. Although this value will provide good results for most applications, it may be advantageous to adjust this value slightly. Consider, for instance, the effect on pulse responses with two different configurations where both the closed-loop gains are 2 and the feedback resistors are 820 and 1640, respectively. Figure 79 and Figure 80 illustrate the effect of increasing Rf while maintaining the same closed-loop gain--the amplifier bandwidth decreases. Accordingly, larger feedback resistors can be used to slow down the LM6181 (see -3 dB bandwidth vs Rftypical curves) and reduce overshoot in the time domain response. Conversely, smaller feedback resistance values than 820 can be used to compensate for the reduction of bandwidth at high closed loop gains, due to 2nd order effects. For example Figure 81 illustrates reducing Rf to 500 to establish the desired small signal response in an amplifier configured for a closed loop gain of 25. VOUT (0.5 V/div) VIN (0.5 V/div) Time (20 ns/div) Figure 79. Step Response with Rf = 820 Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 23 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com Feedback Resistor Selection: Rf (continued) VOUT (0.5 V/div) VIN (0.5 V/div) Time (20 ns/div) Increasing Compensation with Increasing Rf Figure 80. Step Response with Rf = 1640 VOUT (0.5 V/div) VIN (0.05 V/div) Time (20 ns/div) Figure 81. Reducing Rf for Large Closed Loop Gains, Rf = 500 7.4 Slew Rate Considerations The slew rate characteristics of current feedback amplifiers are different than traditional voltage feedback amplifiers. In voltage feedback amplifiers slew rate limiting or non-linear amplifier behavior is dominated by the finite availability of the 1st stage tail current charging the compensation capacitor. The slew rate of current feedback amplifiers, in contrast, is not constant. Transient current at the inverting input determines slew rate for both inverting and non-inverting gains. The non-inverting configuration slew rate is also determined by input stage limitations. Accordingly, variations of slew rates occur for different circuit topologies. 24 Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 7.5 Driving Capacitive Loads The LM6181 can drive significantly larger capacitive loads than many current feedback amplifiers. Although the LM6181 can directly drive as much as 100 pF without oscillating, the resulting response will be a function of the feedback resistor value. Figure 83 illustrates the small-signal pulse response of the LM6181 while driving a 50 pF load. Ringing persists for approximately 70 ns. To achieve pulse responses with less ringing either the feedback resistor can be increased (see Figure 23, Figure 25, and Figure 26), or resistive isolation can be used (10 -51 typically works well). Either technique, however, results in lowering the system bandwidth. Figure 85 illustrates the improvement obtained with using a 47 isolation resistor. Figure 82. Cap Load Direct Drive VOUT (0.2 V/div) VIN (0.2 V/div) Time (20 ns/div) Figure 83. AV = -1, LM6181 Can Directly Drive 50 pF of Load Capacitance with 70 ns of Ringing Resulting in Pulse Response Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 25 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com Driving Capacitive Loads (continued) Figure 84. Cap Load Drive with Isolation Resistor VOUT (0.2 V/div) VIN (0.2 V/div) Time (20 ns/div) Rf and RS Could Be Increased to Maintain AV = -1 and Improve Pulse Response Characteristics. Figure 85. Resistive Isolation of CL Provides Higher Fidelity Pulse Response 26 Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 7.6 Capacitive Feedback For voltage feedback amplifiers it is quite common to place a small lead compensation capacitor in parallel with feedback resistance, Rf. This compensation serves to reduce the amplifier's peaking in the frequency domain which equivalently tames the transient response. To limit the bandwidth of current feedback amplifiers, do not use a capacitor across Rf. The dynamic impedance of capacitors in the feedback loop reduces the amplifier's stability. Instead, reduced peaking in the frequency response, and bandwidth limiting can be accomplished by adding an RC circuit, as illustrated in Figure 87. Figure 86. Using RC on Input to Affect Frequency Response (1) VOUT (0.2 V/div) Time (50 ns/div) Figure 87. RC Limits Amplifier Bandwidth to 50 MHz, Eliminating Peaking in the Resulting Pulse Response Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 27 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Typical Application Figure 88. LM6181 Simplified Schematic 28 Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 Typical Application (continued) 8.1.1 Typical Performance Characteristics 8.1.1.1 Overdrive Recovery When the output or input voltage range of a high speed amplifier is exceeded, the amplifier must recover from an overdrive condition. The typical recovery times for open-loop, closed-loop, and input common-mode voltage range overdrive conditions are illustrated in Figure 90, Figure 92, and Figure 93, respectively. The open-loop circuit of Figure 89 generates an overdrive response by allowing the 0.5V input to exceed the linear input range of the amplifier. Typical positive and negative overdrive recovery times shown in Figure 90 are 5 ns and 25 ns, respectively. Figure 89. Open Loop Input Overdrive Test Circuit VIN (0.5 V/div) VOUT (2 V/div) Time (50 ns/div) Figure 90. Open-Loop Overdrive Recovery Time of 5 ns, and 25 ns from Test Circuit in Figure 89 Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 29 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com Typical Application (continued) The large closed-loop gain configuration in Figure 91 forces the amplifier output into overdrive. Figure 92 displays the typical 30 ns recovery time to a linear output value. Figure 91. Overdrive Recovery Circuit under Large Closed Loop Gain Condition VOUT (5 V/div) VIN (0.5 V/div) Time (50 ns/div) Figure 92. Closed-Loop Overdrive Recovery Time of 30 ns from Exceeding Output Voltage Range from Circuit in Figure 91 30 Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 LM6181 www.ti.com SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 Typical Application (continued) The common-mode input of the circuit in Figure 91 is exceeded by a 5V pulse resulting in a typical recovery time of 310 ns shown in Figure 93. The LM6181 supply voltage is 5V. VOUT (2 V/div) VIN (2 V/div) Time (100 ns/div) Figure 93. Exceptional Output Recovery from an Input that Exceeds the Common-Mode Range Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 31 LM6181 SNOS634C - MAY 1998 - REVISED SEPTEMBER 2014 www.ti.com 9 Device and Documentation Support 9.1 Trademarks VIP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 9.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 9.3 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 10 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 32 Submit Documentation Feedback Copyright (c) 1998-2014, Texas Instruments Incorporated Product Folder Links: LM6181 PACKAGE OPTION ADDENDUM www.ti.com 15-Aug-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM6181IM-8/NOPB LIFEBUY SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM618 1IM8 LM6181IMX-8/NOPB LIFEBUY SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM618 1IM8 LM6181IN/NOPB LIFEBUY PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LM6181IN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Aug-2017 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Sep-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM6181IMX-8/NOPB Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 5.4 2.0 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Sep-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM6181IMX-8/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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