NTE7473
Integrated Circuit
TTL − Dual J−K Flip−Flop with Clear
Description:
The NTE7473 is a dual J−K flip−flop in a 14−Lead plastic DIP type package that contains two
independent positive pulse−triggered J−K flip−flops with individual J−K clock, and direct clear
inputs. J−K input is loaded into the master while the clock is high and transferred to the slave
on the high−to−low transition. For this device the J and K inputs must be stable while the clock
is high.
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC 7V.................................................................
Input Voltage 5.5V.....................................................................
Operating Temperature Range, TA0C to +70C............................................
Storage Temperature Range, Tstg −65C to +150C........................................
Note 1. Unless otherwise specified, all voltages are referenced to GND.
Recommended Operating Conditions:
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.75 5.0 5.25 V
High−Level Input Voltage VIH 2− − V
Low−Level Input Voltage VIL − − 0.8 V
High−Level Output Current IOH − − −0.4 mA
Low−Level Output Current IOL − − 16 mA
Pulse Duration
CLK High
tw20 − − ns
CLK Low 47 − − ns
CLR Low 25 − − ns
Input Setup Time Before CLK tsu 0− − ns
Input Hold Time Data After CLK th0− − ns
Operating Temperature Range TA0−+70 C
Electrical Characteristics: (Note 2, Note 3)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Clamp Voltage VIK VCC = MIN, II = −12mA − − −1.5 V
High Level Output Voltage VOH VCC = MIN, VIH = 2V, VIL = 0.8V, IOH = -0.4mA 2.4 3.4 −V
Low Level Output Voltage VOL VCC = MIN, VIH = 2V, VIL = 0.8V, IOL = 16mA −0.2 0.4 V
Input Current IIVCC = MAX, VI = 5.5V − − 1 mA
High−Level Input Current
J or K
IIH VCC = MAX, VI = 2.4V
− − 40 A
CLR or CLK − − 80 A
Low−Level Input Current
J or K
IIL VCC = MAX, VI = 0.4V
− − −1.6 mA
CLR − − −3.2 mA
CLK − − −3.3 mA
Short−Circuit Output Current IOS VCC = MAX, Note 4 −18 − −57 mA
Supply Current ICC VCC = MAX, Note 5 −10 20 mA
Note 2. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 3. All typical values are at VCC = 5V, TA = +25C.
Note 4. Not more than one output should be shorted at a time.
Note 5. With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of
measurement, the clock input is grounded.
Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Maximum Clock Frequency fmax RL = 400, CL = 15pF 15 20 −MHz
Propagation Delay Time
(From CLR Input to Q Output) tPLH −16 25 ns
(From CLR Input to Q Output) tPHL −25 40 ns
Propagation Delay Time
(From CLK Input to Q or Q Output)
tPLH −16 25 ns
tPHL −25 40 ns
Function Table:
Inputs Outputs
CLR CLK J K Q Q
L X X X L H
H L L Q0Q0
H H L H L
H L H L H
H H H Toggle
2Q
1Q
2CLR
1CLR
1J
VCC
Pin Connection Diagram
2J
1
2
3
4
1CLK
1K
52CLK
6
7
14
13
12
11
1Q
GND
10 2K
92Q
8
17
14 8
.300 (7.62)
.200
(5.08)
Max
.100 (2.45) .099 (2.5) Min
.785 (19.95) Max
.600 (15.24)
