1
LTC1285/LTC1288
3V Micropower Sampling
12-Bit A/D Converters in
SO-8 Packages
■
12-Bit Resolution
■
8-Pin SO Plastic Package
■
Low Cost
■
Low Supply Current: 160µA Typ
■
Auto Shutdown to 1nA Typ
■
Guaranteed ±3/4LSB Max DNL
■
Single Supply 3V to 6V Operation
■
Differential Inputs (LTC1285)
■
2-Channel MUX (LTC1288)
■
On-Chip Sample-and-Hold
■
100µs Conversion Time
■
Sampling Rates:
7.5ksps (LTC1285)
6.6ksps (LTC1288)
■
I/O Compatible with SPI, Microwire, etc.
The LTC
®
1285/LTC1288 are 3V micropower, 12-bit, suc-
cessive approximation sampling A/D converters. They
typically draw only 160µA of supply current when con-
verting and automatically power down to a typical supply
current of 1nA whenever they are not performing conver-
sions. They are packaged in 8-pin SO packages and
operate on 3V to 6V supplies. These 12-bit, switched-
capacitor, successive approximation ADCs include
sample-and-holds. The LTC1285 has a single differential
analog input. The LTC1288 offers a software selectable
2-channel MUX.
On-chip serial ports allow efficient data transfer to a wide
range of microprocessors and microcontrollers over three
wires. This, coupled with micropower consumption, makes
remote location possible and facilitates transmitting data
through isolation barriers.
These circuits can be used in ratiometric applications or
with an external reference. The high impedance analog
inputs and the ability to operate with reduced spans (to
1.5V full scale) allow direct connection to sensors and
transducers in many applications, eliminating the need for
gain stages.
APPLICATIONS
U
SAMPLE FREQUENCY (kHz)
0.1
1
SUPPLY CURRENT (µA)
10
100
1000
1 10 100
LTC1285/88 • TA02
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
f
CLK
= 120kHz
Supply Current vs Sample Rate
■
Pen Screen Digitizing
■
Battery-Operated Systems
■
Remote Data Acquisition
■
Isolated Data Acquisition
■
Battery Monitoring
■
Temperature Measurement
12µW, S0-8 Package, 12-Bit ADC
Samples at 200Hz and Runs Off a 3V Supply
3V1µF
ANALOG INPUT
0V TO 3V RANGE –IN
GND
V
CC
CLK
D
OUT
V
REF
LTC1285
MPU
(e.g., 8051)
P1.4
P1.3
P1.2
+IN
LTC1285/88 • TA01
CS/SHDN
6
5
8
7
3
4
1
2
SERIAL DATA LINK
FEATURES
DESCRIPTION
U
TYPICAL APPLICATIONS N
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
2
LTC1285/LTC1288
(Notes 1 and 2)
Power Dissipation.............................................. 500mW
Operating Temperature Range .................... 0°C to 70°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
PART MARKING
T
JMAX
= 150°C, θ
JA
= 130°C/W
Consult factory for Industrial and Military grade parts.
ORDER PART
NUMBER
LTC1285CN8
ORDER PART
NUMBER
LTC1285CS8
1285C
PART MARKING
ORDER PART
NUMBER
LTC1288CN8
ORDER PART
NUMBER
LTC1288CS8
1288C
T
JMAX
= 150°C, θ
JA
= 130°C/W T
JMAX
= 150°C, θ
JA
= 175°C/W
T
JMAX
= 150°C, θ
JA
= 175°C/W
PACKAGE/ORDER INFORMATION
W
UU
Supply Voltage (V
CC
) to GND................................... 12V
Voltage
Analog and Reference ................ –0.3V to V
CC
+ 0.3V
Digital Inputs.........................................–0.3V to 12V
Digital Output ............................. –0.3V to V
CC
+ 0.3V
ABSOLUTE MAXIMUM RATINGS
W
WW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Supply Voltage (Note 3) LTC1285 2.7 6 V
LTC1288 2.7 6 V
f
CLK
Clock Frequency V
CC
= 2.7V (Note 4) 120 kHz
t
CYC
Total Cycle Time LTC1285, f
CLK
= 120kHz 125.0 µs
LTC1288, f
CLK
= 120kHz 141.5 µs
t
hDI
Hold Time, D
IN
After CLK↑V
CC
= 2.7V 450 ns
t
suCS
Setup Time CS↓ Before First CLK↑ (See Operating Sequence) LTC1285, V
CC
= 2.7V 2 µs
LTC1288, V
CC
= 2.7V 2 µs
t
suDI
Setup Time, D
IN
Stable Before CLK↑V
CC
= 2.7V 600 ns
t
WHCLK
CLK High Time V
CC
= 2.7V 3.5 µs
t
WLCLK
CLK Low Time V
CC
= 2.7V 3.5 µs
t
WHCS
CS High Time Between Data Transfer Cycles V
CC
= 2.7V 2 µs
t
WLCS
CS Low Time During Data Transfer LTC1285, f
CLK
= 120kHz 123.0 µs
LTC1288, f
CLK
= 120kHz 139.5 µs
RECOM ENDED OPERATING CONDITIONS
UUUU W
W
1
2
3
4
8
7
6
5
TOP VIEW
VREF
+IN
–IN
GND
VCC
CLK
DOUT
N8 PACKAGE
8-LEAD PDIP
CS/SHDN
1
2
3
4
8
7
6
5
TOP VIEW
CH0
CH1
GND
VCC (VREF)
CLK
DOUT
DIN
N8 PACKAGE
8-LEAD PDIP
CS/SHDN
1
2
3
4
8
7
6
5
TOP VIEW
V
CC
CLK
D
OUT
V
REF
+IN
–IN
GND
S8 PACKAGE
8-LEAD PLASTIC SO
CS/SHDN
1
2
3
4
8
7
6
5
TOP VIEW
V
CC
(V
REF
)
CLK
D
OUT
D
IN
CH0
CH1
GND
S8 PACKAGE
8-LEAD PLASTIC SO
CS/SHDN
3
LTC1285/LTC1288
LTC1285 LTC1288
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Resolution (No Missing Codes) ●12 12 Bits
Integral Linearity Error (Note 6) ●±3/4 ±2±3/4 ±2 LSB
Differential Linearity Error ●±1/4 ±3/4 ±1/4 ±3/4 LSB
Offset Error ●±3/4 ±3±3/4 ±3 LSB
Gain Error ●±2±8±2±8 LSB
Analog Input Range (Note 7 and 8) ●V
REF Input Range (LTC1285) 2.7 ≤ V
CC
≤ 6V V
(Notes 7, 8, and 9) V
Analog Input Leakage Current (Note 10) ●±1±1µA
1.5V to V
CC
+ 0.05V
–0.05V to V
CC
+ 0.05V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
S/(N +D) Signal-to-Noise Plus Distortion Ratio 1kHz Input Signal 67 dB
THD Total Harmonic Distortion (Up to 5th Harmonic) 1kHz Input Signal –80 dB
SFDR Spurious-Free Dynamic Range 1kHz Input Signal 88 dB
Peak Harmonic or Spurious Noise 1kHz Input Signal –88 dB
DYNAMIC ACCURACY
UW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
CC
= 3.6V ●2V
V
IL
Low Level Input Voltage V
CC
= 2.7V ●0.8 V
I
IH
High Level Input Current V
IN
= V
CC
●2.5 µA
I
IL
Low Level Input Current V
IN
= 0V ●–2.5 µA
V
OH
High Level Output Voltage V
CC
= 2.7V, I
O
= 10µA●2.4 2.64 V
V
CC
= 2.7V, I
O
= 360µA●2.1 2.30 V
V
OL
Low Level Output Voltage V
CC
= 2.7V, I
O
= 400µA●0.4 V
I
OZ
Hi-Z Output Leakage CS = High ●±3µA
I
SOURCE
Output Source Current V
OUT
= 0V –10 mA
I
SINK
Output Sink Current V
OUT
= V
CC
15 mA
R
REF
Reference Input Resistance CS = V
IH
2700 MΩ
(LTC1285) CS = V
IL
54 kΩ
I
REF
Reference Current (LTC1285) CS = V
CC
●0.001 2.5 µA
t
CYC
≥ 640µs, f
CLK
≤ 25kHz 50 µA
t
CYC
= 134µs, f
CLK
= 120kHz ●50 70 µA
I
CC
Supply Current CS = V
CC
●0.001 ±3.0 µA
LTC1285, t
CYC
≥ 640µs, f
CLK
≤ 25kHz 150 µA
LTC1285, t
CYC
= 134µs, f
CLK
= 120kHz ●160 320 µA
LTC1288, t
CYC
≥ 720µs, f
CLK
≤ 25kHz 200 µA
LTC1288, t
CYC
= 150µs, f
CLK
= 120kHz ●210 390 µA
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
U
CONVERTER AND MULTIPLEXER CHARACTERISTICS
UW U
(Note 5)
(Note 5)
fSMPL = 7.5kHz (LTC1285), fSMPL = 6.6kHz (LTC1288) (Note 5)
4
LTC1285/LTC1288
TYPICAL PERFORMANCE CHARACTERISTICS
UW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
SMPL
Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles
f
SMPL(MAX)
Maximum Sampling Frequency LTC1285 ●7.5 kHz
LTC1288 ●6.6 kHz
t
CONV
Conversion Time See Operating Sequence 12 CLK Cycles
t
dDO
Delay Time, CLK↓ to D
OUT
Data Valid See Test Circuits ●600 1500 ns
t
dis
Delay Time, CS↑ to D
OUT
Hi-Z See Test Circuits ●220 660 ns
t
en
Delay Time, CLK↓ to D
OUT
Enable See Test Circuits ●180 500 ns
t
hDO
Time Output Data Remains Valid After CLK↓C
LOAD
= 100pF 520 ns
t
f
D
OUT
Fall Time See Test Circuits ●60 180 ns
t
r
D
OUT
Rise Time See Test Circuits ●80 180 ns
C
IN
Input Capacitance Analog Inputs, On Channel 20 pF
Analog Inputs, Off Channel 5 pF
Digital Input 5 pF
(Note 5)
AC CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: These devices are specified at 3V. For 5V specified devices, see
LTC1286 and LTC1298.
Note 4: Increased leakage currents at elevated temperatures cause the
sample-and-hold to droop, therefore it is recommended that f
CLK
≥ 75kHz
at 70° andf
CLK
≥ 1kHz at 25°C.
Note 5: V
CC
= 2.7V, V
REF
= 2.5V and CLK = 120kHz unless otherwise
specified.
Note 6: Linearity error is specified between the actual end points of the
A/D transfer curve.
Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below GND or one diode drop above V
CC
. This spec allows 50mV forward
bias of either diode for 2.7V ≤ V
CC
≤ 6V. This means that as long as the
reference or analog input does not exceed the supply voltage by more than
50mV the output code will be correct. To achieve an absolute 0V to 2.7V
input voltage range will therefore require a minimum supply voltage of
2.650V over initial tolerance, temperature variations and loading. For 2.7V
< V
CC
≤ 6V, reference and analog input range cannot exceed 6.05V. If
reference and analog input range are greater than 6.05V, the output code
will not be guaranteed to be correct.
Note 8: The supply voltage range for the LTC1285 and the LTC1288 is
from 2.7V to 6V.
Note 9: Recommended operating conditions
Note 10: Channel leakage current is measured after the channel selection.
SAMPLE RATE (kHz)
0.1
1
SUPPLY CURRENT (µA)
10
1000
100
110
LTC1285/88 • TPC01
LTC1288
LTC1285
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
f
CLK
= 120kHz
Supply Current vs Sample Rate
FREQUENCY (kHz)
1
0
SUPPLY CURRENT (µA)
1
2
3
4
5
6
20 40 60 80
LTC1285/88 • TPC03
100
7
8
9
0.002
120
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
CS = 0
(AFTER CONVERSION)
CS = V
CC
Shutdown Supply Current vs Clock
Rate with CS High and CS Low
TEMPERATURE (°C)
–55
SUPPLY CURRENT (µA)
150
200
250
105
LTC1285/88 • TPC02
100
50
0–15 25 65
–35 125
545 85
V
CC
= 2.7V
V
REF
= 2.5V
f
CLK
= 120kHz
LTC1285
f
SMPL
= 7.5kHz
LTC1288
f
SMPL
= 6.6kHz
Supply Current vs Temperature
5
LTC1285/LTC1288
TEMPERATURE (°C)
0
CHANGE IN OFFSET (LSB)
0.15
30
LTC1285/88 • TPC07
0
–0.10
10 20 40
–0.15
–0.20
0.20
0.10
0.05
–0.05
50 60 70
V
CC
= 2.7V
V
REF
= 2.5V
f
CLK
= 120kHz
f
SMPL
= f
SMPL(MAX)
Change in Offset vs Temperature
Reference Current vs
Sample Rate (LTC1285)
SAMPLE RATE (kHz)
0
0
REFERENCE CURRENT (µA)
5
15
20
25
50
35
245
LTC1285/88 • TPC04
10
40
45
30
13 6
7
8
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
f
CLK
= 120kHz
TYPICAL PERFORMANCE CHARACTERISTICS
UW
REFERENCE VOLTAGE (V)
1.0
0
CHANGE IN GAIN (LSB)
–1
–3
–4
–5
–10
–7
1.4 1.8 2.0 2.8
LTC1285/88 • TPC09
–2
–8
–9
–6
1.2 1.6 2.2 2.4 2.6
T
A
= 25°C
V
CC
= 2.7V
f
CLK
= 120kHz
f
SMPL
= 7.5kHz
Change in Gain
vs Reference Voltage
Change in Offset
vs Reference Voltage
TEMPERATURE (°C)
–55
43
REFERENCE CURRENT (µA)
44
46
47
48
53
50
–15 25 45 125
LTC1285/88 • TPC05
45
51
52
49
–35 5 65 85 105
V
CC
= 2.7V
V
REF
= 2.5V
f
CLK
= 120kHz
f
SMPL
= 7.5kHz
Reference Current vs Temperature
Change in Linearity
vs Reference Voltage
REFERENCE VOLTAGE (V)
1.0
0
CHANGE IN LINEARITY (LSB)
0.05
0.15
0.20
0.25
0.50
0.35
1.4 1.8 2.0 2.8
LTC1285/88 • TPC08
0.10
0.40
0.45
0.30
1.2 1.6 2.2 2.4 2.6
TA = 25°C
VCC = 2.7V
fCLK = 120kHz
fSMPL = 7.5kHz
REFERENCE VOLTAGE (V)
0.5
0
CHANGE IN OFFSET (LSB = 1/4096 × V
REF
)
0.5
1.0
1.5
2.0
2.5
3.0
1.0 1.5 2.0 2.5
LTC1285/88 • TPC06
3.0
T
A
= 25°C
V
CC
= 2.7V
f
CLK
= 120kHz
f
SMPL
= 7.5kHz
Effective Bits and S/(N + D)
vs Input Frequency
INPUT FREQUENCY (kHz)
1
0
EFFECTIVE NUMBER OF BITS (ENOBs)
S/(N + D) (dB)
3
5
7
10
10 100
LTC1285/88 • TPC12
1
4
6
9
12
11
8
62
56
74
68
50
2TA = 25°C
VCC = 2.7V
fCLK = 120kHz
Differential Nonlinearity vs Code
CODE
0
–1
DIFFERENTIAL NONLINEARITY ERROR (LSB)
–0.5
0
0.5
1
512 1024 1536 2048
LTC1285/88 • TPC11
2560 3072 3584 4096
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
f
CLK
= 120kHz
6
LTC1285/LTC1288
TYPICAL PERFORMANCE CHARACTERISTICS
UW
INPUT FREQUENCY (Hz)
80
ATTENUATION (%)
60
40
50
20
0
90
70
30
10
1k 100k 1M 10M
LTC1285/86 • TPC15
100 10k
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
f
SMPL
= f
SMPL(MAX)
Attenuation vs Input Frequency
Power Supply Feedthrough
vs Ripple Frequency
Intermodulation Distortion
Maximum Clock Frequency
vs Supply Voltage
FREQUENCY (kHz)
0
–120
MAGNITUDE (dB)
–100
–80
–60
–40
1.0 2.0 3.0 4.0
LTC1285/88 • TPC17
–20
0
0.5 1.5 2.5 3.5
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
f1 = 2.05kHz
f2 = 3.05kHz
f
SMPL
= 7.5kHz
RIPPLE FREQUENCY (Hz)
–80
FEEDTHROUGH (dB)
–60
–40
–50
–20
0
–90
–70
–30
–10
1k 100k 1M 10M
LTC1285/86 • TPC18
–100 10k
T
A
= 25°C
V
CC
= 2.7V (V
RIPPLE
= 1mV)
V
REF
= 2.5V
f
CLK
= 120kHZ
SUPPLY VOLTAGE (V)
2.5
100
CLOCK FREQUENCY (kHz)
120
160
180
200
300
240
3.5 4.5 5.0
LTC1285/88 • TPC21
140
260
280
220
3.0 4.0 5.5 6.0
T
A
= 25°C
V
REF
= 2.5V
4096 Point FFT Plot
FREQUENCY (kHz)
0
–120
MAGNITUDE (dB)
–100
–80
–60
–40
1.0 2.0 3.0 4.0
LTC1285/88 • TPC16
–20
0
0.5 1.5 2.5 3.5
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
f
IN
= 3.05kHz
f
CLK
= 120kHz
f
SMPL
= 7.5kHz
Spurious-Free Dynamic Range
vs Input Frequency
INPUT FREQUENCY (kHz)
1
0
SPURIOUS-FREE DYNAMIC RANGE (dB)
20
40
60
80
10 100
LTC1285/88 • G13
100
10
30
50
70
90
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
f
SMPL
= f
SMPL(MAX)
Maximum Clock Frequency
vs Source Resistance
SOURCE RESISTANCE (kΩ)
0.1
0
CLOCK FREQUENCY (kHz)
40
80
120
160
110
LTC1285/88 • G19
200
20
60
100
140
180 T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
–INPUT
+INPUTV
IN
R
SOURCE–
S/(N + D) vs Input Level
INPUT LEVEL (dB)
–45
SIGNAL-TO-NOISE PLUS DISTORTION (dB)
40
50
60
–5
LTC1285/88 • TPC14
30
20
0–35 –25 –15
–40 0
–30 –20 –10
10
80
70
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
f
IN
= 1kHz
f
SMPL
= f
SMPL(MAX)
Sample-and-Hold Acquisition
Time vs Source Resistance
SOURCE RESISTANCE (Ω)
1
100
S & H ACQUISITION TIME (ns)
1000
10000
100 100010 10000
LTC1285/88 • TPC20
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
–INPUT
+INPUTV
IN
R
SOURCE+
7
LTC1285/LTC1288
LTC1285
V
REF
(Pin 1): Reference Input. The reference input defines
the span of the A/D converter.
IN
+
(Pin 2): Positive Analog Input.
IN
–
(Pin 3): Negative Analog Input.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CS/SHDN (Pin 5): Chip Select Input. A logic low on this
input enables the LTC1285. A logic high on this input
disables and powers down the LTC1285.
D
OUT
(Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the serial
data transfer and determines conversion speed.
V
CC
(Pin 8): Power Supply Voltage. This pin provides
power to the A/D converter. It must be kept free of noise
and ripple by bypassing directly to the analog ground
plane.
TYPICAL PERFORMANCE CHARACTERISTICS
UW
Minimum Clock Frequency
for 0.1 LSB Error vs Temperature
TEMPERATURE (°C)
0
CLOCK FREQUENCY (kHz)
80
100
120
40
LTC1285/88 • TPC22
60
40
010 20 30 60 70
50
20
2
V
CC
= 2.7V
V
REF
= 2.5V
TEMPERATURE (°C)
–55
LEAKAGE CURRENT (nA)
10
100
1000
105
LTC1285/88 • TPC24
1
0.1
0.01 –15 25 65
–35 125
545 85
V
CC
= 2.7V
V
REF
= 2.5V
ON CHANNEL OFF CHANNEL
Input Channel Leakage Current
vs Temperature
Digital Input Logic Threshold
vs Supply Voltage
SUPPLY VOLTAGE (V)
2.5
DIGITAL INPUT LOGIC THRESHOLD VOLTAGE (V)
2.0
2.5
3.0
4.0 5.0
LTC1285/88 • TPC23
1.5
1.0
3.0 3.5 4.5 5.5 6.0
0.5
0
T
A
= 25°C
PIN FUNCTIONS
UUU
LTC1288
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
input enables the LTC1288. A logic high on this input
disables and powers down the LTC1288.
CH0 (Pin 2): Analog Input.
CH1 (Pin 3): Analog Input.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
D
IN
(Pin 5): Digital Data Input. The multiplexer address is
shifted into this input.
D
OUT
(Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the
serial data transfer and determines conversion speed.
V
CC
/V
REF
(Pin 8): Power Supply and Reference Voltage.
This pin provides power and defines the span of the A/D
converter. It must be kept free of noise and ripple by
bypassing directly to the analog ground plane.
8
LTC1285/LTC1288
BLOCK DIAGRAM
W
–
+
C
SAMPLE
V
CC
(V
CC
/V
REF
)
CS/SHDN
CLK
D
OUT
IN
+
(CH0)
IN
–
(CH1)
MICROPOWER
COMPARATOR
CAPACITIVE DAC
V
REF
GND
PIN NAMES IN PARENTHESES REFER TO THE LTC1288
LTC1285/88 • BD
(D
IN
)
BIAS AND 
SHUTDOWN CIRCUIT
SAR
SERIAL PORT
TEST CIRCUITS
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Load Circuit for tdis and ten
D
OUT
1.4V
3k
100pF
TEST POINT
LTC1285/88 • TC01
D
OUT
V
OL
V
OH
t
r
t
f
LTC1285/88 • TC02
Voltage Waveforms for DOUT Delay Times, tdDO
Load Circuit for tdDO, tr and tf
CLK
D
OUT
V
IL
t
dDO
V
OL
V
OH
LTC1285/88 • TC03
D
OUT
3k
100pF
TEST POINT
V
CC
t
dis
WAVEFORM 2, t
en
t
dis
WAVEFORM 1
LTC1285/88 • TC04
9
LTC1285/LTC1288
TEST CIRCUITS
Voltage Waveforms for tdis Voltage Waveforms for ten
D
OUT
WAVEFORM 1
(SEE NOTE 1)
V
IH
t
dis
90%
10%
D
OUT
WAVEFORM 2
(SEE NOTE 2)
CS
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1285/88 • TC05
LTC1285/88 • TC06
CS
LTC1285
1
CLK
D
OUT
t
en
B11
V
OL
2
Voltage Waveforms for ten
1234
LTC1288
D
IN
CLK
D
OUT
START
t
en
B11
V
OL
LTC1285/88 • TC07
CS
10
LTC1285/LTC1288
APPLICATION INFORMATION
WUU U
OVERVIEW
The LTC1285 and LTC1288 are 3V micropower, 12-bit,
successive approximation sampling A/D converters. The
LTC1285 typically draws 160µA of supply current when
sampling at 7.5kHz while the LTC1288 nominally con-
sumes 210µA of supply current when sampling at 6.6 kHz.
The extra 50µA of supply current on the LTC1288 comes
from the reference input which is intentionally tied to the
supply. Supply current drops linearly as the sample rate is
reduced (see Supply Current vs Sample Rate). The ADCs
automatically power down when not performing conver-
sions, drawing only leakage current. They are packaged in
8-pin SO and DIP packages. The LTC1285 and LTC1288
operate on a single supply from 2.7V to 6V.
Both the LTC1285 and the LTC1288 contain a 12-bit,
switched-capacitor ADC, a sample-and-hold, and a serial
port (see Block Diagram). Although they share the same
basic design, the LTC1285 and LTC1288 differ in some
respects. The LTC1285 has a differential input and has an
external reference input pin. It can measure signals float-
ing on a DC common-mode voltage and can operate with
reduced spans to 1.5V. Reducing the spans allows it to
achieve 366µV resolution. The LTC1288 has a two-chan-
nel input multiplexer and can convert either channel with
respect to ground or the difference between the two. The
reference input is tied to the supply pin.
SERIAL INTERFACE
The 2-channel LTC1288 communicates with micropro-
cessors and other external circuitry via a synchronous,
half duplex, 4-wire serial interface. The single channel
LTC1285 uses a 3-wire interface (see Operating Sequence
in Figures 1 and 2).
Figure 1. LTC1285 Operating Sequence
CLK
CS
t
CYC
B11
B5
B6
B7
B8B9
B10B11 HI-Z
D
OUT
t
CONV
t
DATA
HI-Z
t
suCS
NULL 
BIT B4 B3 B2 B1
POWER
DOWN
POWER DOWN
B0* NULL 
BIT B10 B9 B8
t
SMPL
(MSB)
(MSB)
CLK
CS
t
CYC
B11*
B5
B6
B7
B8B9
B10B11 HI-Z
D
OUT
t
CONV
t
DATA
HI-Z
t
suCS
NULL
BIT
LTC1285/88 • F01
B4 B3 B3 B4 B5 B6 B7
B2 B2B1 B0 B1 B10
B9B8
t
SMPL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, 
THE ADC WILL OUTPUT ZEROS INDEFINITELY.
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, 
THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY.
t
DATA
: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT
 BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
11
LTC1285/LTC1288
APPLICATION INFORMATION
WUU U
CLK
CS
t
CYC
B5
B6
B7
B8B9
B10B11 HI-Z
D
OUT
t
CONV
t
DATA
HI-Z
t
suCS
NULL
BIT B4 B3 B2 B1
POWER
DOWN
B0*
t
SMPL
(MSB)
(MSB)
CLK
START ODD/
SIGN
SGL/
DIFF
CS
t
CYC
B11
B5
B6
B7
B8B9
B10B11 HI-Z
D
OUT
D
IN
t
CONV
t
DATA
HI-Z
t
suCS
NULL
BIT
MSBF
LTC1285/88 • F02
B4 B3 B3 B4 B5 B6 B7
B2 B2
B1 B0 B1 B10
B9B8
t
SMPL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, 
THE ADC WILL OUTPUT ZEROS INDEFINITELY.
DON’T CARE
START ODD/
SIGN
D
IN
DON’T CARE
t
DATA
: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT
 BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
SGL/
DIFF
MSBF
*
POWER DOWN
Figure 2. LTC1288 Operating Sequence Example: Differential Inputs (CH+, CH–)
MSB-First Data (MSBF = 1)
MSB-First Data (MSBF = 0)
12
LTC1285/LTC1288
Start Bit
The first “logical one” clocked into the D
IN
input after CS
goes low is the start bit. The start bit initiates the data
transfer. The LTC1288 will ignore all leading zeros which
precede this logical one. After the start bit is received, the
remaining bits of the input word will be clocked in. Further
inputs on the D
IN
pin are then ignored until the next CS
cycle.
Multiplexer (MUX) Address
The bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following tables.
In single-ended mode, all input channels are measured
with respect to GND.
APPLICATION INFORMATION
WUU U
Data Transfer
The CLK synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured
on the rising CLK edge in both transmitting and receiving
systems.
The LTC1285 does not require a configuration input word
and has no D
IN
pin. A falling CS initiates data transfer as
shown in the LTC1285 operating sequence. After CS falls
the second CLK pulse enables D
OUT
. After one null bit the
A/D conversion result is output on the D
OUT
line. Bringing
CS high resets the LTC1285 for the next data exchange.
The LTC1288 first receives input data and then transmits
back the A/D conversion result (half duplex). Because of
the half duplex operation, D
IN
and D
OUT
may be tied
together allowing transmission over just 3 wires: CS, CLK
and DATA (D
IN
/D
OUT
).
Data transfer is initiated by a falling chip select (CS) signal.
After CS falls the LTC1288 looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
D
IN
input which configures the LTC1288 and starts the
conversion. After one null bit, the result of the conversion
is output on the D
OUT
line. At the end of the data exchange
CS should be brought high. This resets the LTC1288 in
preparation for the next data exchange.
D
IN
1 D
IN
2
D
OUT
1 D
OUT
2
CS
SHIFT MUX
ADDRESS IN
1 NULL BIT SHIFT A/D CONVERSION
RESULT OUT
LTC1285/88 • AI01
the rising edge of the clock. The input data words are
defined as follows:
ODD/
SIGN MSBFSTART
MUX
ADDRESS MSB FIRST/
LSB FIRST
LTC1285/88 • AI02
SGL/
DIFF
LTC1288 Channel Selection
MUX ADDRESS
ODD/SIGN
0
1
0
1
CHANNEL #
0
+
+
–
1
+
–
+
GND
–
–
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
LTC1285/88 • AI03
SGL/DIFF
1
1
0
0
MSB First/LSB First (MSBF)
The output data of the LTC1288 is programmed for
MSB first or LSB first sequence using the MSBF bit.
When the MSBF bit is a logical one, data will appear on
the DOUT line in MSB first format. Logical zeros will be
filled in indefinitely following the last data bit. When the
MSBF bit is a logical zero, LSB first data will follow the
normal MSB first data on the DOUT line (see Operating
Sequence).
Input Data Word
The LTC1285 requires no D
IN
word. It is permanently
configured to have a single differential input. The conver-
sion result appears on the D
OUT
line. The data format is
MSB first followed by the LSB sequence. This provides
easy interface to MSB or LSB first serial ports. For MSB
first data the CS signal can be taken high after B0 (see
Figure 1). The LTC1288 clocks data into the D
IN
input on
13
LTC1285/LTC1288
APPLICATION INFORMATION
WUU U
Transfer Curve
The LTC1285/LTC1288 are permanently configured for
unipolar only. The input span and code assignment for
this conversion type are shown in the following figures.
0V
1LSB
V
REF
–2LSB
V
REF
4096
V
REF
–1LSB
V
REF
V
IN
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
LTC1285/88 • AI04
1LSB =
Transfer Curve
OUTPUT CODE
•
•
•
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
INPUT VOLTAGE
V
REF
– 1LSB
V
REF
– 2LSB
•
•
•
1LSB
0V
INPUT VOLTAGE
(V
REF
= 5.000V)
4.99878V
4.99756V
•
•
•
0.00122V
0V
LTC1285/88 • AI05
Output Code
Operation with D
IN
and D
OUT
Tied Together
The LTC1288 can be operated with D
IN
and D
OUT
tied
together. This eliminates one of the lines required to
communicate to the microprocessor (MPU). Data is trans-
mitted in both directions on a single wire. The processor
pin connected to this data line should be configurable as
either an input or an output. The LTC1288 will take control
of the data line and drive it low on the 4th falling CLK edge
after the start bit is received (see Figure 3). Therefore the
processor port line must be switched to an input before
this happens to avoid a conflict.
In the Typical Applications section, there is an example of
interfacing the LTC1288 with D
IN
and D
OUT
tied together to
the Intel 8051 MPU.
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 160µA and automatic
shutdown between conversions, the LTC1285/LTC1288
achieves extremely low power consumption over a wide
range of sample rates (see Figure 4). The auto-shutdown
allows the supply curve to drop with reduced sample rate.
Figure 3. LTC1288 Operation with DIN and DOUT Tied Together
1234
CS
CLK
DATA
(D
IN
/D
OUT
)START SGL/DIFF ODD/SIGN MSBF B11 B10
•••
MSBF BIT LATCHED
BY LTC1288
LTC1288 CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO MPU
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1288
PROCESSOR MUST RELEASE DATA LINE AFTER 
4TH RISING CLK AND BEFORE THE 4TH FALLING CLK LTC1288 TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
LTC1285/88 F03
SAMPLE FREQUENCY (kHz)
0.1
1
SUPPLY CURRENT (µA)
10
100
1000
1 10 100
LTC1285/88 • F04
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
f
CLK
= 120kHz
Figure 4. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate
14
LTC1285/LTC1288
APPLICATION INFORMATION
WUU U
Figure 5. Shutdown Current with CS High is 1nA Typically,
Regardless of the Clock. Shutdown Current with CS = Ground
Varies From 1µA at 1kHz to 9µA at 120kHz
Several things must be taken into account to achieve such
a low power consumption.
Shutdown
The LTC1285/LTC1288 are equipped with automatic shut-
down features. They draw power when the CS pin is low
and shut down completely when that pin is high. The bias
circuit and comparator powers down and the reference
input becomes high impedance at the end of each conver-
sion leaving the CLK running to clock out the LSB first data
or zeroes (see Figures 1 and 2). If the CS is not running rail-
to-rail, the input logic buffer will draw current. This current
may be large compared to the typical supply current. To
obtain the lowest supply current, bring the CS pin to
ground when it is low and to supply voltage when it is high.
When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the D
IN
and CLK input have no effect on supply
current during this time. There is no need to stop D
IN
and
CLK with CS = high; they can continue to run without
drawing current.
Minimize CS Low Time
In systems that have significant time between conver-
sions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, transferring data as quickly as
possible, and then bringing it back high will result in the
lowest current drain. This minimizes the amount of time
the device draws power. After a conversion the ADC
automatically shuts down even if CS is held low (see
Figures 1 and 2). If the clock is left running to clock out
LSB-data or zero, the logic will draw a small current.
Figure 5 shows that the typical supply current with CS =
ground varies from 1µA at 1kHz to 9µA at 120kHz. When
CS = V
CC
, the logic is gated off and no supply current is
drawn regardless of the clock frequency.
D
OUT
Loading
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the D
OUT
pin
can add more than 16.2µA to the supply current at a
120kHz clock frequency. An extra 16.2µA or so of current
goes into charging and discharging the load capacitor. The
same goes for digital lines driven at a high frequency by
any logic. The C × V × f currents must be evaluated and the
troublesome ones minimized.
OPERATING ON OTHER THAN 3V SUPPLIES
Both the LTC1285 and the LTC1288 operate from a 2.7V
to 6V supply. To operate the LTC1285/LTC1288 on other
than 3V supplies a few things must be kept in mind.
Input Logic Levels
The input logic levels of CS, CLK and D
IN
are made to
meet TTL on a 3V supply. When the supply voltage varies,
the input logic levels also change. For the LTC1285/
LTC1288 to sample and convert correctly, the digital
inputs have to be in the proper logical low and high levels
relative to the operating supply voltage (see typical curve
of Digital Input Logic Threshold vs Supply Voltage). If
achieving micropower consumption is desirable, the
digital inputs must go rail-to-rail between supply voltage
and ground (see ACHIEVING MICROPOWER PERFOR-
MANCE section).
Clock Frequency
The maximum recommended clock frequency is 120kHz
for the LTC1285/LTC1288 running off a 3V supply. With
the supply voltage changing, the maximum clock fre-
quency for the devices also changes (see the typical curve
FREQUENCY (kHz)
1
0
SUPPLY CURRENT (µA)
1
2
3
4
5
6
20 40 60 80
LTC1285/88 • TPC03
100
7
8
9
0.002
120
T
A
= 25°C
V
CC
= 2.7V
V
REF
= 2.5V
CS = 0
(AFTER CONVERSION)
CS = V
CC
15
LTC1285/LTC1288
APPLICATION INFORMATION
WUU U
Figure 7. LTC1288 “+” and “–” Input Settling Windows
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1285/LTC1288 are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.
The V
CC
pin should be bypassed to the ground plane with
a 10µF tantalum capacitor with leads as short as possible.
If the power supply is clean, the LTC1285/LTC1288 can
also operate with smaller 1µF or less surface mount or
ceramic bypass capacitors. All analog inputs should be
referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or routed
away from the reference and analog circuitry.
SAMPLE-AND-HOLD
Both the LTC1285 and the LTC1288 provide a built-in
sample-and-hold (S&H) function to acquire signals. The
S&H of the LTC1285 acquires input signals from “+” input
relative to “–” input during the t
SMPL
time (see Figure 1).
However, the S&H of the LTC1288 can sample input
signals in the single-ended mode or in the differential
inputs during the t
SMPL
time (see Figure 7).
CLK
DIN
DOUT
"+" INPUT
"–" INPUT
SAMPLE HOLD
"+" INPUT MUST
SETTLE DURING
THIS TIME
tSMPL tCONV
CS
SGL/DIFFSTART MSBF DON’T CARE
1ST BIT TEST "–" INPUT MUST
SETTLE DURING THIS TIME
B11
LTC1285/88 • F07
Figure 6. Interfacing a 3V Powered LTC1285 to a 5V System
+IN
–IN
GND
V
CC
CLK
D
OUT
V
REF
3V
4.7µF
MPU
(e.g. 8051) 5V
P1.4
P1.3
P1.2
LTC1285/88 • F06
DIFFERENTIAL INPUTS
COMMON-MODE RANGE
0V TO 3V
3V
LTC1285
CS
of Maximum Clock Rate vs Supply Voltage). If the maxi-
mum clock frequency is used, care must be taken to
ensure that the device converts correctly.
Mixed Supplies
It is possible to have a microprocessor running off a 5V
supply and communicate with the LTC1285/LTC1288
operating on a 3V supply. The inputs of CS, CLK and D
IN
of the LTC1285/LTC1288 have no problem to take a
voltage swing from 0V to 5V. With the LTC1285 operating
on a 3V supply, the output of D
OUT
may only go between
0V and 3V. The 3V output level is higher enough to trip a
TTL input of the MPU. Figure 6 shows a 3V powered
LTC1285 interfacing a 5V system.
16
LTC1285/LTC1288
APPLICATION INFORMATION
WUU U
Single-Ended Inputs
The sample-and-hold of the LTC1288 allows conversion
of rapidly varying signals. The input voltage is sampled
during the t
SMPL
time as shown in Figure 7. The sampling
interval begins as the bit preceding the MSBF bit is shifted
in and continues until the falling CLK edge after the MSBF
bit is received. On this falling edge, the S&H goes into hold
mode and the conversion begins.
Differential Inputs
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the volt-
age on the selected “–” input must remain constant and be
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be per-
formed accurately. The conversion time is 12 CLK cycles.
Therefore, a change in the “–” input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the “–” input this error would be:
V
ERROR (MAX)
= V
PEAK
× 2 × π × f(“–”) × 12/f
CLK
Where f(“–”) is the frequency of the “–” input voltage,
V
PEAK
is its peak amplitude and f
CLK
is the frequency of the
CLK. In most cases V
ERROR
will not be significant. For a
60Hz signal on the “–” input to generate a 1/4LSB error
(152µV) with the converter running at CLK = 120kHz, its
peak value would have to be 4.03mV.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1285/
LTC1288 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used or
if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.
“+” Input Settling
The input capacitor of the LTC1285 is switched onto “+”
input during the t
SMPL
time (see Figure 1) and samples
the input signal within that time. However, the input
capacitor of the LTC1288 is switched onto “+” input
during the sample phase (t
SMPL
, see Figure 7). The
sample phase is 1 1/2 CLK cycles before conversion
starts. The voltage on the “+” input must settle com-
pletely within t
SMPLE
for the LTC1285 and the LTC1288
respectively. Minimizing R
SOURCE+
and C1 will improve
the input settling time. If a large “+” input source resis-
tance must be used, the sample time can be increased by
using a slower CLK frequency.
“–” Input Settling
At the end of the t
SMPL
, the input capacitor switches to the
“–” input and conversion starts (see Figures 1 and 7).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage settles completely during the first CLK cycle of the
conversion time and be free of noise. Minimizing R
SOURCE–
and C2 will improve settling time. If a large “–” input
source resistance must be used, the time allowed for
settling can be extended by using a slower CLK frequency.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the“+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps, including the LT1006 and
LT1413 single supply op amps, can be made to settle well
even with the minimum settling windows of 12.5µs (“+”
input) which occur at the maximum clock rate of 120kHz.
Source Resistance
The analog inputs of the LTC1285/LTC1288 look like a
20pF capacitor (C
IN
) in series with a 500Ω resistor (R
ON
)
as shown in Figure 8. C
IN
gets switched between the
17
LTC1285/LTC1288
APPLICATION INFORMATION
WUU U
Input Leakage Current
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum
input leakage specification of 1µA (at 125°C) flowing
through a source resistance of 240Ω will cause a voltage
drop of 240µV or 0.4LSB. This error will be much
reduced at lower temperatures because leakage drops
rapidly (see typical curve of Input Channel Leakage
Current vs Temperature).
REFERENCE INPUTS
The reference input of the LTC1285 is effectively a 50kΩ
resistor from the time CS goes low to the end of the
conversion. The reference input becomes a high impedence
node at any other time (see Figure 10). Since the voltage
on the reference input defines the voltage span of the A/D
converter, the reference input should be driven by a
reference with low R
OUT
(ex. LT1004, LT1019 and LT1021)
or a voltage source with low R
OUT
.
selected “+” and “–” inputs once during each conversion
cycle. Large external source resistors and capacitances
will slow the settling of the inputs. It is important that the
overall RC time constants be short enough to allow the
analog inputs to completely settle within the allowed time.
LTC1285
REF
+
R
OUT
V
REF
1
4
GND
LTC1285/88 • F10
Figure 10. Reference Input Equivalent Circuit
Reduced Reference Operation
The minimum reference voltage of the LTC1288 is limited
to 2.7V because the V
CC
supply and reference are inter-
nally tied together. However, the LTC1285 can operate
with reference voltages below 1.5V.
The effective resolution of the LTC1285 can be increased
by reducing the input span of the converter. The LTC1285
exhibits good linearity and gain over a wide range of
reference voltages (see typical curves of Change in Linear-
ity vs Reference Voltage and Change in Gain vs Reference
R
ON
= 500Ω
C
IN
= 20pF
LTC1285
LTC1288
“+”
INPUT
R
SOURCE
+
V
IN
+
C1
“–”
INPUT
R
SOURCE
–
V
IN
–
C2
LTC1285/88 • F08
Figure 8. Analog Input Equivalent Circuit
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 9. For large values of C
F
(e.g., 1µF), the
capacitive input switching currents are averaged into a
net DC current. Therefore, a filter should be chosen with
a small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately I
DC
= 20pF × V
IN
/t
CYC
and is roughly
proportional to V
IN
. When running at the minimum cycle
time of 133.3µs, the input current equals 0.375µA at V
IN
= 2.5V. In this case, a filter resistor of 160Ω will cause
0.1LSB of full-scale error. If a larger filter resistor must
be used, errors can be eliminated by increasing the cycle
time.
RFILTER
VIN
CFILTER
LTC1285/88 • F09
LTC1285
“+”
“–”
IDC
Figure 9. RC Input Filtering
18
LTC1285/LTC1288
APPLICATION INFORMATION
WUU U
Figure 11. LTC1285 Non-Averaged, 4096 Point FFT Plot
Voltage). However, care must be taken when operating at
low values of V
REF
because of the reduced LSB step size
and the resulting higher accuracy requirement placed on
the converter. The following factors must be considered
when operating at low V
REF
values:
1. Offset
2. Noise
3. Conversion speed (CLK frequency)
Offset with Reduced V
REF
The offset of the LTC1285 has a larger effect on the output
code. When the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The typical curve of Change in Offset vs
Reference Voltage shows how offset in LSBs is related to
reference voltage for a typical value of V
OS
. For example,
a V
OS
of 122µV which is 0.2LSB with a 2.5V reference
becomes 1LSB with a 1V reference and 5LSBs with a 0.2V
reference. If this offset is unacceptable, it can be corrected
digitally by the receiving system or by offsetting the “–”
input of the LTC1285.
Noise with Reduced V
REF
The total input referred noise of the LTC1285 can be
reduced to approximately 400µV peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This noise
is insignificant with a 2.5V reference but will become a
larger fraction of an LSB as the size of the LSB is reduced.
For operation with a 2.5V reference, the 400µV noise is
only 0.66LSB peak-to-peak. In this case, the LTC1285
noise will contribute a little bit of uncertainty to the
output code. However, for reduced references the noise
may become a significant fraction of an LSB and cause
undesirable jitter in the output code. For example, with
a 1.25V reference this same 400µV noise is 1.32LSB
peak-to-peak. This will reduce the range of input volt-
ages over which a stable output code can be achieved by
1LSB. If the reference is further reduced to 1V, the 400µV
noise becomes equal to 3.3LSBs and a stable code may
be difficult to achieve. In this case averaging multiple
readings may be necessary.
This noise data was taken in a very clean setup. Any setup
induced noise (noise or ripple on V
CC
, V
REF
or V
IN
) will add
to the internal noise. The lower the reference voltage to be
used the more critical it becomes to have a clean, noise free
setup.
Conversion Speed with Reduced V
REF
With reduced reference voltages, the LSB step size is
reduced and the LTC1285 internal comparator over-
drive is reduced. Therefore, it may be necessary to
reduce the maximum CLK frequency when low values
of VREF are used.
DYNAMIC PERFORMANCE
The LTC1285/LTC1288 have exceptional sampling capa-
bility. Fast Fourier Transform (FFT) test techniques are
used to characterize the ADC’s frequency response, dis-
tortion and noise at the rated throughput. By applying a
low distortion sine wave and analyzing the digital output
using an FFT algorithm, the ADC’s spectral content can be
examined for frequencies outside the fundamental. Figure
11 shows a typical LTC1285 plot.
19
LTC1285/LTC1288
APPLICATION INFORMATION
WUU U
Figure 12. Effective Bits and S/(N + D) vs Input Frequency
Signal-to-Noise Ratio
T
he Signal-to-Noise plus Distortion Ratio (S/N + D) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the ADC’s output. The output is
band limited to frequencies above DC and below one half
the sampling frequency. Figure 12 shows a typical spec-
tral content with a 7.5kHz sampling rate.
INPUT FREQUENCY (kHz)
1
0
EFFECTIVE NUMBER OF BITS (ENOBs)
S/(N + D) (dB)
3
5
7
10
10 100
LTC1285/88 • TPC12
1
4
6
9
12
11
8
62
56
74
68
50
2T
A
= 25°C
V
CC
= 2.7V
f
CLK
= 120kHz
THD =++++
20log VVV V
V
2
23
24
2N
2
1
...
where V
1
is the RMS amplitude of the fundamental fre-
quency and V
2
through V
N
are the amplitudes of the
second through the N
th
harmonics. The typical THD speci-
fication in the Dynamic Accuracy table includes the 2nd
through 5th harmonics. With a 1kHz input signal, the
LTC1285/LTC1288 have typical THD of 80dB with
V
CC
= 2.7V.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition
to THD. IMD is the change in one sinusoidal input
caused by the presence of another sinusoidal input at a
different frequency.
If two pure sine waves of frequencies f
a
and f
b
are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at sum and difference
frequencies of mf
a
± nf
b
, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (f
a
+ f
b
) and
(f
a
– f
b
) while 3rd order IMD terms include (2f
a
+ f
b
),
(2f
a
– f
b
), (f
a
+ 2f
b
), and (f
a
– 2f
b
). If the two input sine
waves are equal in magnitudes, the value (in dB) of the 2nd
order IMD products can be expressed by the following
formula:
IMD f f mplitude f f
ab
ab
±
()
=±
()
20log a
amplitude at f
a
For input frequencies of 2.05kHz and 3.05kHz, the IMD of
the LTC1285/LTC1288 is 72dB with a 2.7V supply.
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in dBs relative to the RMS value of a full-
scale input signal.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to S/(N+D)
by the equation:
ENOB = [S/(N + D) – 1.76]/6.02
where S/(N + D) is expressed in dB. At the maximum
sampling rate of 7.5kHz with a 2.7V supply, the LTC1285
maintains above 10.7 ENOBs at 10kHz input frequency.
Above 10kHz the ENOBs gradually decline, as shown in
Figure 12, due to increasing second harmonic distortion.
The noise floor remains low.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half of the sampling frequency. THD
is defined as:
20
LTC1285/LTC1288
TYPICAL APPLICATIONS N
U
MICROPROCESSOR INTERFACES
The LTC1285/LTC1288 can interface directly without ex-
ternal hardware to most popular microprocessor (MPU)
synchronous serial formats (see Table 1). If an MPU
without a dedicated serial port is used, then 3 or 4 of the
MPU's parallel port lines can be programmed to form the
serial link to the LTC1285/LTC1288. Included here is one
serial interface example and one example showing a
parallel port programmed to form the serial interface.
Motorola SPI (MC68HC11)
The MC68HC11 has been chosen as an example of an MPU
with a dedicated serial port. This MPU transfers data MSB
-first and in 8-bit increments. The D
IN
word sent to the data
register starts with the SPI process. With three 8-bit
transfers, the A/D result is read into the MPU. The second
8-bit transfer clocks B11 through B8 of the A/D conversion
result into the processor. The third 8-bit transfer clocks
the remaining bits, B7 through B0, into the MPU. The data
is right justified into two memory locations. ANDing the
second byte with OF
HEX
clears the four most significant
bits. This operation was not included in the code. It can be
inserted in the data gathering loop or outside the loop
when the data is processed.
MC68HC11 Code
In this example the D
IN
word configures the input MUX for
a single-ended input to be applied to CHO. The conversion
result is output MSB-first.
PART NUMBER TYPE OF INTERFACE
Motorola
MC6805S2,S3 SPI
MC68HC11 SPI
MC68HC05 SPI
RCA
CDP68HC05 SPI
Hitachi
HD6305 SCI Synchronous
HD63705 SCI Synchronous
HD6301 SCI Synchronous
HD63701 SCI Synchronous
HD6303 SCI Synchronous
HD64180 CSI/O
National Semiconductor
COP400 Family MICROWIRE†
COP800 Family MICROWIRE/PLUS†
NS8050U MICROWIRE/PLUS†
HPC16000 Family MICROWIRE/PLUS†
Texas Instruments
TMS7002 Serial Port
TMS7042 Serial Port
TMS70C02 Serial Port
TMS70C42 Serial Port
TMS32011* Serial Port
TMS32020 Serial Port
Intel
8051 Bit Manipulation on Parallel Port
* Requires external hardware
†MICROWIRE and MICROWIRE/PLUS are trademarks of
National Semiconductor Corp.
Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1286/LTC1298
21
LTC1285/LTC1288
LABEL MNEMONIC OPERAND COMMENTS
LDAA #$50 CONFIGURATION DATA FOR SPCR
STAA $1028 LOAD DATA INTO SPCR ($1028)
LDAA #$1B CONFIG. DATA FOR PORT D DDR
STAA $1009 LOAD DATA INTO PORT D DDR
LDAA #$01 LOAD DIN WORD INTO ACC A
STAA $50 LOAD DIN DATA INTO $50
LDAA #$A0 LOAD DIN WORD INTO ACC A
STAA $51 LOAD DIN DATA INTO $51
LDAA #$00 LOAD DUMMY DIN WORD INTO
ACC A
STAA $52 LOAD DUMMY DIN DATA INTO $52
LDX #$1000 LOAD INDEX REGISTER X WITH
$1000
LOOP BCLR $08,X,#$01 D0 GOES LOW (CS GOES LOW)
LDAA $50 LOAD DIN INTO ACC A FROM $50
STAA $102A LOAD DIN INTO SPI, START SCK
LDAA $1029 CHECK SPI STATUS REG
WAIT1 BPL WAIT1 CHECK IF TRANSFER IS DONE
LDAA $51 LOAD DIN INTO ACC A FROM $51
STAA $102A LOAD DIN INTO SPI, START SCK
WAIT2 LDAA $1029 CHECK SPI STATUS REG
BPL WAIT2 CHECK IF TRANSFER IS DONE
LDAA $102A LOAD LTC1288 MSBs INTO ACC A
STAA $62 STORE MSBs IN $62
LDAA $52 LOAD DUMMY INTO ACC A
FROM $52
STAA $102A LOAD DUMMY DIN INTO SPI,
START SCK
WAIT3 LDAA $1029 CHECK SPI STATUS REG
BPL WAIT3 CHECK IF TRANSFER IS DONE
BSET $08,X#$01 DO GOES HIGH (CS GOES HIGH)
LDAA $102A LOAD LTC1288 LSBs IN ACC
STAA $63 STORE LSBs IN $63
JMP LOOP START NEXT CONVERSION
LABEL MNEMONIC OPERAND COMMENTS
Timing Diagram for Interface to the MC68HC11
Hardware and Software Interface to the MC68HC11
CS
CLK
D
OUT
MPU
RECEIVED
WORD
LTC1285/88 • TA03
SGL/
DIFF
START
B3B7 B6 B5 B4 B2 B0B1B11 B10 B9 B8
D
IN
MPU
TRANSMIT
WORD
BYTE 3 (DUMMY)
BYTE 2
0000
SGL/
DIFF
1
BYTE 1
X
ODD/
SIGN MSBF XXX
X
000 XXX
XX
XX
X
BYTE 3
BYTE 2
BYTE 1
B11
???0B10 B8
B9 B7 B6 B4
B5 B3 B2 B0
B1
DON'T CARE
ODD/
SIGN
????????
MSBF
LTC1285/88 • TA04
DOUT FROM LTC1298 STORED IN MC68HC11 RAM
B2 B1 B0
B3
B4
B6
B7 B5
0
0
LSB
MSB
#62
#63
00 B11 B10 B9 B8
CLK
D
OUT
CS
ANALOG
INPUTS
D0
SCK
MC68HC11
D
IN
MISO
LTC1288
CH0
CH1
BYTE 1
BYTE 2 MOSI
TYPICAL APPLICATIONS N
U
22
LTC1285/LTC1288
DOUT FROM 1288 STORED IN 8501 RAM
MSB
R2 B11 B10 B9 B8 B7 B6 B5 B4
LSB
R3 B3 B2 B1 B0 0 0 0 0
TYPICAL APPLICATIONS N
U
Interfacing to the Parallel Port of the INTEL 8051
Family
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1288 and parallel port micro-
processors. Normally the CS, CLK and D
IN
signals would
be generated on 3 port lines and the D
OUT
signal read on
a 4th port line. This works very well. However, we will
demonstrate here an interface with the D
IN
and D
OUT
of the
LTC1288 tied together as described in the SERIAL INTER-
FACE section. This saves one wire.
The 8051 first sends the start bit and MUX address to the
LTC1288 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and the
8051 reads back the 12-bit A/D result over the same data
line.
LABEL MNEMONIC OPERAND COMMENTS
MOV A, #FFH D
IN
word for LTC1288
SETB P1.4 Make sure CS is high
CLR P1.4 CS goes low
MOV R4, #04 Load counter
LOOP 1 RLC A Rotate D
IN
bit into Carry
CLR P1.3 SCLK goes low
MOV P1.2, C Output D
IN
bit to LTC1288
SETB P1.3 SCLK goes high
DJNZ R4, LOOP 1 Next bit
MOV P1, #04 Bit 2 becomes an input
CLR P1.3 SCLK goes low
MOV R4, #09 Load counter
LOOP 2 MOV C, P1.2 Read data bit into Carry
RLC A Rotate data bit into Acc.
SETB P1.3 SCLK goes high
CLR P1.3 SCLK goes low
DJNZ R4, LOOP 2 Next bit
MOV R2, A Store MSBs in R2
CLR A Clear Acc.
MOV R4, #04 Load counter
LOOP 3 MOV C, P1.2 Read data bit into Carry
RLC A Rotate data bit into Acc.
SETB P1.3 SCLK goes high
CLR P1.3 SCLK goes low
DJNZ R4, LOOP 3 Next bit
MOV R4, #04 Load counter
LOOP 4 RRC A Rotate right into Acc.
DJNZ R4, LOOP 4 Next Rotate
MOV R3, A Store LSBs in R3
SETB P1.4 CS goes high
CS
CLK
D
OUT
D
IN
LTC1288
ANALOG
INPUTS
P1.4
P1.3
P1.2
8051
MUX ADDRESS
A/D RESULT
LTC1285/88 • TA01
CLK
MSBF BIT LATCHED 
INTO LTC1288
8051 P1.2 OUTPUTS DATA 
TO LTC1288 LTC1288 SENDS A/D RESULT
BACK TO 8051 P1.2
LTC1288 TAKES CONTROL OF DATA
LINE ON 4TH FALLING CLK
8051 P1.2 RECONFIGURED
AS IN INPUT AFTER THE 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
MSBF B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
SGL/
DIFFSTART
DATA 
(
DIN
/D
OUT
)
LTC1285/88 • TA07
CS
ODD/ 
SIGN
23
LTC1285/LTC1288
TYPICAL APPLICATIONS N
U
39k
2.7V
LT1004-1.2
220k
39k
3Ω
BATTERY MONITOR 
INPUT 8V TO 16V
1µF
0.1µF
CS
CLK
D
OUT
LTC1285
LTC1285/88 • F15
–IN
V
CC
V
REF
GND
+IN
Figure 15. Micropower Battery Voltage Monitor
Figure 13. “Quick Look” Circuit for the LTC1285
A “Quick Look” Circuit for the LTC1285
Users can get a quick look at the function and timing of the
LT1285 by using the following simple circuit (Figure 13).
V
REF
is tied to V
CC
. V
IN
is applied to the +IN input and the
–IN input is tied to the ground. CS is driven at 1/16 the
clock rate by the 74C161 and D
OUT
outputs the data. The
output data from the D
OUT
pin can be viewed on an
oscilloscope that is set up to trigger on the falling edge of
CS (Figure 14). Note the LSB data is partially clocked out
before CS goes high.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Micropower Battery Voltage Monitor
A common problem in battery systems is battery voltage
monitoring. This circuit monitors the 10 cell stack of NiCad
or NiMH batteries found in laptop computers. It draws only
40µA from the 2.7V supply at f
SMPL
= 0.1kHz and 30µA to
62µA from the battery. The 12-bits of resolution of the
LTC1285 are positioned over the desired range of 8V to
16V. This is easily accomplished by using the ADC’s
differential inputs. Tying the –input to the reference gives
an ADC input span of V
REF
to 2V
REF
(1.2V to 2.4V). The
resistor divider then scales the input voltage for 8V to 16V.
CLR
CLK
A
B
C
D
P
GND
V
CC
RC
QA
QB
QC
QD
T
LOAD
74HC161
V
IN
TO OSCILLOSCOPE
CLOCK IN 120kHz
LTC1285/88 • F13
V
CC
CLK
D
OUT
LTC1285
+IN
–IN
GND
4.7µF2.7V
V
REF
CS
MSB
(B11)
VERTICAL: 2V/DIV
HORIZONTAL: 20µs/DIV
LSB
(B0)
NULL
BIT
Figure 14. Scope Trace the LTC1285 “Quick Look” Circuit
Showing A/D Output 101010101010 (AAAHEX)
24
LTC1285/LTC1288
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900
●
FAX
: (408) 434-0507
●
TELEX
: 499-3977
LINEAR TECHNOLOGY CORPORATION 1994
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTION
U
N8 Package
8-Lead Plastic DIP
LT/GP 0894 10K • PRINTED IN USA
N8 0695
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.015
(0.380)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.125
(3.175)
MIN
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.325 +0.025
–0.015
+0.635
–0.381
8.255
()
12 34
8765
0.255 ± 0.015*
(6.477 ± 0.381)
0.400*
(10.160)
MAX
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package
8-Lead Plastic SOIC
0.016 – 0.050
0.406 – 1.270
0.010 – 0.020
(0.254 – 0.508)× 45°
0°– 8° TYP
0.008 – 0.010
(0.203 – 0.254)
SO8 0695
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
1234
0.150 – 0.157**
(3.810 – 3.988)
8765
0.189 – 0.197*
(4.801 – 5.004)
0.228 – 0.244
(5.791 – 6.197)
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH 
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD 
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
PART NUMBER DESCRIPTION COMMENTS
LTC1096/LTC1098 8-Pin SOIC, Micropower 8-Bit ADC Low Power, Small Size, Low Cost
LTC1196/LTC1198 8-Pin SOIC, 1Msps 8-bit ADC Low Power, Small Size, Low Cost
LTC1282 3V High Speed Parallel 12-Bit ADC Complete, V
REF
, CLK, Sample-and-Hold, 140ksps
LTC1289 Multiplexed 3V, 1A 12-Bit ADC 8-Channel, 12-Bit Serial I/O
LTC1522 16-Pin SOIC, 3V Micropower 12-Bit ADC 4-Channel, 12-Bit Serial I/O
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