ADC10064CIWM - Texas Instruments High-Performance Analog

ADC10061, ADC10062, ADC10064

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SNAS069E –JUNE 1999–REVISED MARCH 2013

ADC10061/ADC10062/ADC10064 10-Bit 600 ns A/D Converter with Input Multiplexer and

Sample/Hold

Check for Samples: ADC10061,ADC10062,ADC10064

1FEATURES DESCRIPTION

NOTE: The ADC10061 and ADC10062 are obsolete.

2• Built-in Sample-and-Hold They are described here for reference only.

• Single +5V Supply Using an innovative, patented multistep* conversion

• No External Clock Required technique, these CMOS analog-to-digital converters

• Speed Adjust Pin for Faster Conversions offer sub-microsecond conversion times yet dissipate

(ADC10062 and ADC10064). See ADC10662/4 a maximum of only 235 mW. These converters

for High Speed Ensured Performance. perform 10-bit conversions in two lower-resolution

“flashes”, yielding a fast A/D without the cost, power

APPLICATIONS consumption, and other problems associated with

true flash approaches.

• Digital Signal Processor Front Ends The analog input voltage is sampled and held by an

• Instrumentation internal sampling circuit. Input signals at frequencies

• Disk Drives from DC to over 200 kHz can, therefore, be digitized

• Mobile Telecommunications accurately without the need for an external sample-

and-hold circuit.

KEY SPECIFICATIONS The ADC10062 and ADC10064 include a “speed-up”

• Conversion Time 600 ns Typical, 900 ns Max pin. Connecting an external resistor between this pin

and ground reduces the typical conversion time to as

• Sampling Rate 800 kHz little as 350 ns with only a small increase in linearity

• Low Power Dissipation 235 mW (Max) error.

• Total Unadjusted Error ±1.0 LSB (Max) For ease of interface to microprocessors, the

• No Missing Codes Over Temperature ADC10061, ADC10062, and ADC10064 have been

designed to appear as a memory location or I/O port

without the need for external interface logic.

*U.S. Patent Number 4918449

Simplified Block Diagram

*ADC10061 Only, **ADC10062 and ADC10064 Only, ***ADC10064 Only

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC10061, ADC10062, ADC10064

SNAS069E –JUNE 1999–REVISED MARCH 2013

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Connection Diagram

This device is obsolete; shown for reference only.

Figure 1. Top View

This device is obsolete; shown for reference only.

Figure 2. Top View

Figure 3. Top View

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NOTE: The ADC10061 and ADC10062 are obsolete; shown for reference only.

PIN DESCRIPTIONS

Pin Function Description

DVCC, AVCC Digital and analog positive supply voltage inputs. Connect both to the same voltage source, but bypass separately with

a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor to ground at each pin.

INT Active low interrupt output. INT goes low at the end of each conversion, and returns high following the rising edge of

RD.

S/H Sample/Hold control input. When this pin is forced low (and CS is low), the analog input signal is sampled and a new

conversion is initiated.

RD Active low read control input. When this RD and CS are low, any data present in the output registers will be placed

onto the data bus.

CS Active low Chip Select control input. When low, this pin enables the RD and S/H pins.

S0, S1 On the multiple-input devices (ADC10062 and ADC10064), these pins select the analog input that will be connected to

the A/D during the conversion. The input is selected based on the state of S0 and S1 when S/H makes its High-to-Low

transition (See Timing Diagrams). The ADC10064 includes both S0 and S1. The ADC10062 includes just S0, and the

ADC10061 has neither.

VREF−, VREF+ Reference voltage inputs. They may be placed at any voltage between GND and VCC, but VREF+ must be greater than

VREF−. An input voltage equal to VREF−produces an output code of 0, and an input voltage equal to (VREF+ −1 LSB)

produces an output code of 1023.

VIN, VIN0, VIN1, Analog input pins. The ADC10061 has one input (VIN), the ADC10062 has two inputs (VIN0 and VIN1), and the

VIN2, VIN3 ADC10064 has four inputs (VIN0, VIN1, VIN2 and VIN3). The impedance of the input source should be less than 500Ωfor

best accuracy and conversion speed. For accurate conversions, no input pin (even one that is not selected) should be

driven more than 50 mV above VCC or 50 mV below ground.

GND, AGND, Power supply ground pins. The ADC10061 has a single ground pin (GND), and the ADC10062 and ADC10064 have

DGND separate analog and digital ground pins (AGND and DGND) for separate bypassing of the analog and digital supplies.

The ground pins should be connected to a stable, noise-free system ground. For the devices with two ground pins,

both pins should be returned to the same potential.

DB0–DB9 TRI-STATE data output pins.

SPEED ADJ (ADC10062 and ADC10064 only). This pin is normally left unconnected, but by connecting a resistor between this pin

and ground, the conversion time can be reduced. See Typical Performance Characteristics and the table of Electrical

Characteristics.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings(1)(2)(3)

Supply Voltage (V+= AVCC = DVCC)−0.3V to +6V

Voltage at Any Input or Output −0.3V to V++ 0.3V

Input Current at Any Pin(4) 5 mA

Package Input Current(4) 20 mA

Power Consumption(5) 875 mW

ESD Susceptibility(6) 2000V

Vapor Phase (60 Sec) 215°C

Soldering Information Infrared (15 Sec) 220°C

Storage Temperature Range −65°C to +150°C

Junction Temperature 150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional. These ratings do not ensure specific performance limits, however. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND, unless otherwise specified.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(4) When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > V+) the absolute value of current at that pin

should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies

with an input current of 5 mA to four.

(5) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA and the ambient temperature,

TA. The maximum allowable power dissipation at any temperature is PD= (TJMAX −TA)/θJA or the number given in the Absolute

Maximum Ratings, whichever is lower. In most cases, the maximum derated power dissipation will be reached only during fault

conditions. For these devices, TJMAX for a board-mounted device are as indicated in Package Thermal Resistance.

(6) Human body model, 100 pF discharged through a 1.5 kΩresistor.

Operating Ratings(1)(2)

TMIN ≤TA≤TMAX =

Temperature Range −40°C ≤TA≤+85°C

Supply Voltage Range +4.5V to +5.5V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional. These ratings do not ensure specific performance limits, however. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND, unless otherwise specified.

Package Thermal Resistance

Device θJA (°C/W)

ADC10061CIWM 85

ADC10062CIWM 82

ADC10064CIWM 78

Converter Characteristics

The following specifications apply for V+= +5V, VREF(+) = +5V, VREF(−)= GND, and Speed Adjust pin unconnected unless

otherwise specified. Boldface limits apply for TA= TJ= TMin to TMax;all other limits TA= TJ= +25°C. Units

Symbol Parameter Conditions Typical(1) Limit(2) (Limit)

Resolution 10 Bits

Integral Linearity Error RSA = 18 kΩ±0.5 ±1.0/±1.5 LSB (max)

Offset Error ±1.5 LSB (max)

Full-Scale Error ±1 LSB (max)

Total Unadjusted Error All Suffixes, RSA = 18 kΩ±0.5 ±1.5/±2.2 LSB (max)

Missing Codes] 0(max)

(1) Typical numbers are at +25°C and represent must likely parametric norm.

(2) Limits are specified to TI's AOQL (Average Outgoing Quality Level).

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Converter Characteristics (continued)

The following specifications apply for V+= +5V, VREF(+) = +5V, VREF(−)= GND, and Speed Adjust pin unconnected unless

otherwise specified. Boldface limits apply for TA= TJ= TMin to TMax;all other limits TA= TJ= +25°C. Units

Symbol Parameter Conditions Typical(1) Limit(2) (Limit)

V+= 5V ±5%, VREF = 4.5V ±1/16 LSB

Power Supply Sensitivity V+= 5V ±10%, VREF = 4.5V ±⅜LSB (max)

fIN = 10 kHz, 4.85 VP-P 0.06 %

THD Total Harmonic Distortion fIN = 160 kHz, 4.85 VP-P 0.08 %

fIN = 10 kHz, 4.85 VP-P 61 dB

SNR Signal-to-Noise Ratio fIN = 160 kHz, 4.85 VP-P 60 dB

fIN = 10 kHz, 4.85 VP-P 9.6 Bits

Effective Number of Bits fIN = 160 kHz, 4.85 VP-P 9.4 Bits

RREF Reference Resistance 650 400 Ω(min)

RREF Reference Resistance 650 900 Ω(max)

VREF(+) VREF(+) Input Voltage V++ 0.05 V (max)

VREF(−)VREF(−)Input Voltage GND −0.05 V (min)

VREF(+) VREF(+) Input Voltage VREF(−)V (min)

VREF(−)VREF(−)Input Voltage VREF(+) V (max)

VIN Input Voltage V++ 0.05 V (max)

VIN Input Voltage GND −0.05 V (min)

OFF Channel Input Leakage Current CS = V+, VIN = V+0.01 3µA (max)

ON Channel Input Leakage Current CS = V+, VIN = V+±1 −3µA (max)

DC Electrical Characteristics

The following specifications apply for V+= +5V, VREF(+) = 5V VREF(−)= GND, and Speed Adjust pin unconnected unless

otherwise specified. Boldface limits apply for TA= TJ= TMIN to TMAX;all other limits TA= TJ= +25°C. Units

Symbol Parameter Conditions Typical(1) Limit(2) (Limit)

VIN(1) Logical “1” Input Voltage V+= 5.5V 2.0 V (min)

VIN(0) Logical “0” Input Voltage V+= 4.5V 0.8 V (max)

IIN(1) Logical “1” Input Current VIN(1) = 5V 0.005 3.0 µA (max)

IIN(0) Logical “0” Input Current VIN(0) 0V −0.005 −3.0 µA (max)

V+= 4.5V, IOUT =−360 µA 2.4 V (min)

VOUT(1) Logical “1” Output Voltage V+= 4.5V, IOUT =−10 µA 4.25 V (min)

VOUT(0) Logical “0” Output Voltage V+= 4.5V, IOUT = 1.6 mA 0.4 V (max)

VOUT = 5V 0.1 50 µA (max)

IOUT TRI-STATE Output Current VOUT = 0V −0.1 −50 µA (max)

CS = S/H = RD = 0, RSA =∞1.0 2mA (max)

DICC DVCC Supply Current CS = S/H = RD = 0, RSA = 18 kΩ1.0 2mA (max)

CS = S/H = RD = 0, RSA =∞30 45 mA (max)

AICC AVCC Supply Current CS = S/H = RD = 0, RSA = 18 kΩ30 45 mA (max)

(1) Typical numbers are at +25°C and represent must likely parametric norm.

(2) Limits are specified to TI's AOQL (Average Outgoing Quality Level).

AC Electrical Characteristics

The following specifications apply for V+= +5V, tr= tf= 20 ns, VREF(+) = 5V, VREF(−)= GND, and Speed Adjust pin unconnected

unless otherwise specified. Boldface limits apply for TA= TJ= TMIN to TMAX;all other limits TA= TJ= +25°C. Units

Symbol Parameter Conditions Typical(1) Limit(2) (Limit)

Mode 1 Conversion Time from Rising RSA =∞600 750/900 ns (max)

tCONV Edge of S/H to Falling Edge of INT RSA = 18k 375 ns

(1) Typical numbers are at +25°C and represent must likely parametric norm.

(2) Limits are specified to TI's AOQL (Average Outgoing Quality Level).

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AC Electrical Characteristics (continued)

The following specifications apply for V+= +5V, tr= tf= 20 ns, VREF(+) = 5V, VREF(−)= GND, and Speed Adjust pin unconnected

unless otherwise specified. Boldface limits apply for TA= TJ= TMIN to TMAX;all other limits TA= TJ= +25°C. Units

Symbol Parameter Conditions Typical(1) Limit(2) (Limit)

RSA =∞850 1400 ns (max)

tCRD Mode 2 Conversion Time Mode 2, RSA = 18k 530 ns

Access Time (Delay from Falling Edge of

tACC1 Mode 1; CL= 100 pF 30 60 ns (max)

RD to Output Valid)

Access Time (Delay from Falling Edge of

tACC2 Mode 2; CL= 100 pF 900 tCRD + 50 ns (max)

RD to Output Valid)

tSH Minimum Sample Time(3) Figure 4(2) 250 ns (max)

TRI-STATE Control (Delay from Rising

t1H, t0H RL= 1k, CL= 10 pF 30 60 ns (max)

Edge of RD to High-Z State)

Delay from Rising Edge of RD to Rising

tINTH CL= 100 pF 25 50 ns (max)

Edge of INT

Delay from End of Conversion to Next

tP50 ns (max)

Conversion

tMS Multiplexer Control Setup Time 10 75 ns (max)

tMH Multiplexer Hold Time 10 40 ns (max)

CVIN Analog Input Capacitance 35 pF (max)

COUT Logic Output Capacitance 5 pF (max)

CIN Logic Input Capacitance 5 pF (max)

(3) Accuracy may degrade if tSH is shorter than the value specified. See curves of Accuracy vs. tSH.

TRI-STATE Test Circuits and Waveforms

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Timing Diagrams

The conversion time (tCONV) is set by the internal timer.

Figure 4. Mode 1

The conversion time (tCRD) includes the

sampling time and is determined by the internal timer.

Figure 5. Mode 2 (RD Mode)

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Typical Performance Characteristics

Zero (Offset) Error Linearity Error

vs. Reference Voltage vs. Reference Voltage

Figure 6. Figure 7.

Analog Supply Current Digital Supply Current

vs. Temperature vs. Temperature

Figure 8. Figure 9.

Conversion Time Conversion Time

vs. Temperature vs. Temperature

Figure 10. Figure 11.

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Typical Performance Characteristics (continued)

Conversion Time Conversion Time

vs. Speed-Up Resistor vs. Speed-Up Resistor

(ADC10062 and ADC10064 Only) (ADC10062 and ADC10064 Only)

Figure 12. Figure 13.

Spectral Response

with100 kHz Sine Spectral Response with

Wave Input 100 kHz Sine Wave Input

Figure 14. Figure 15.

Linearity Change

Signal-to-Noise + THD Ratio vs. Speed-Up Resistor

vs. Signal Frequency (ADC10062 and ADC10064 Only)

Figure 16. Figure 17.

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Typical Performance Characteristics (continued)

Linearity Change

vs. Speed-Up Resistor Linearity Error Change

(ADC10062 and ADC10064 Only) vs. Sample Time

Figure 18. Figure 19.

Functional Description

The ADC10061 and the ADC10062 are obsolete. They are discussed here for reference only.

The ADC10061, ADC10062 and ADC10064 digitize an analog input signal to 10 bits accuracy by performing two

lower-resolution “flash” conversions. The first flash conversion provides the six most significant bits (MSBs) of

data, and the second flash conversion provides the four least significant bits LSBs).

Figure 20 is a simplified block diagram of the converter. Near the center of the diagram is a string of resistors. At

the bottom of the string of resistors are 16 resistors, each of which has a value 1/1024 the resistance of the

whole resistor string. These lower 16 resistors (the LSB Ladder) therefore have a voltage drop of 16/1024, or

1/64 of the total reference voltage (VREF+ −VREF−) across them. The remainder of the resistor string is made up

of eight groups of eight resistors connected in series. These comprise the MSB Ladder. Each section of the

MSB Ladder has ⅛of the total reference voltage across it, and each of the LSB resistors has 1/64 of the total

reference voltage across it. Tap points across these resistors can be connected, in groups of sixteen, to the

sixteen comparators at the right of the diagram.

On the left side of the diagram is a string of seven resistors connected between VREF+ and VREF−. Six

comparators compare the input voltage with the tap voltages on this resistor string to provide a low-resolution

“estimate” of the input voltage. This estimate is then used to control the multiplexer that connects the MSB

Ladder to the sixteen comparators on the right. Note that the comparators on the left needn't be very accurate;

they simply provide an estimate of the input voltage. Only the sixteen comparators on the right and the six on the

left are necessary to perform the initial six-bit flash conversion, instead of the 64 comparators that would be

required using conventional half-flash methods.

To perform a conversion, the estimator compares the input voltage with the tap voltages on the seven resistors

on the left. The estimator decoder then determines which MSB Ladder tap points will be connected to the sixteen

comparators on the right. For example, assume that the estimator determines that VIN is between 11/16 and

13/16 of VREF. The estimator decoder will instruct the comparator MUX to connect the 16 comparators to the taps

on the MSB ladder between 10/16 and 14/16 of VREF. The 16 comparators will then perform the first flash

conversion. Note that since the comparators are connected to ladder voltages that extend beyond the range

indicated by the estimator circuit, errors in the estimator as large as 1/16 of the reference voltage (64 LSBs) will

be corrected. This first flash conversion produces the six most significant bits of data—four bits in the flash itself,

and 2 bits in the estimator.

The remaining four LSBs are now determined using the same sixteen comparators that were used for the first

flash conversion. The MSB Ladder tap voltage just below the input voltage (as determined by the first flash) is

subtracted from the input voltage and compared with the tap points on the sixteen LSB Ladder resistors. The

result of this second, four-bit flash conversion is then decoded, and the full 10-bit result is latched.

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Note that the sixteen comparators used in the first flash conversion are reused for the second flash. Thus, the

multistep conversion technique used in the ADC10061, ADC10062, and ADC10064 needs only a small fraction

of the number of comparators that would be required for a traditional flash converter, and far fewer than would be

used in a conventional half-flash approach. This allows the ADC10061, ADC10062, and ADC10064 to perform

high-speed conversions without excessive power drain.

Figure 20. Block Diagram of the Multistep Converter Architecture

SIMILAR PRODUCT DIFFERENCES

The ADC1006x, ADC1046x and ADC1066x (where "x" indicates the number of multiplexer inputs) are similar

devices with different specification limits. The differences in these device families are summarized below.

Device Family ILE, TUE, PSS THD, SNR, ENOB Max. Conversion Time

ADC1006x Ensured - 900ns

ADC1046x - Ensured 900ns

ADC1066x - Ensured 466ns

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APPLICATIONS INFORMATION

MODES OF OPERATION

The ADC10061, ADC10062, and ADC10064 have two basic digital interface modes. Figure 4 and Figure 5 are

timing diagrams for the two modes. The ADC10062 and ADC10064 have input multiplexers that are controlled by

the logic levels on pins S0and S1when S/H goes low. Table 1 is a truth table showing how the input channels

are assigned.

Mode 1

In this mode, the S/H pin controls the start of conversion. S/H is pulled low for a minimum of 250 ns. This causes

the comparators in the “coarse” flash converter to become active. When S/H goes high, the result of the coarse

conversion is latched and the “fine” conversion begins. After 600 ns (typical), INT goes low, indicating that the

conversion results are latched and can be read by pulling RD low. Note that CS must be low to enable S/H or

RD. CS is internally “ANDed” with S/H and RD; the input voltage is sampled when CS and S/H are low, and data

is read when CS and RD are low. INT is reset high on the rising edge of RD.

Table 1. Input Multiplexer Programming

ADC10064 (a)

S1S0Channel

0 0 VIN0

0 1 VIN1

1 0 VIN2

1 1 VIN3

ADC10062 (b)

S0Channel

0 VIN0

1 VIN1

Mode 2

In Mode 2, also called “RD mode”, the S/H and RD pins are tied together. A conversion is initiated by pulling both

pins low. The A/D converter samples the input voltage and causes the coarse comparators to become active. An

internal timer then terminates the coarse conversion and begins the fine conversion. 850 ns (typical) after S/H

and RD are pull low, INT goes low, indicating that the conversion is completed. Approximately 20 ns later the

data appearing on the TRI-STATE output pins will be valid. Note that data will appear on these pins throughout

the conversion, but until INT goes low the data at the output pins will be the result of the previous conversion.

REFERENCE CONSIDERATIONS

The ADC10061, ADC10062, and ADC10064 each have two reference inputs. These inputs, VREF+ and VREF−, are

fully differential and define the zero to full-scale range of the input signal. The reference inputs can be connected

to span the entire supply voltage range (VREF−= 0V, VREF+ = VCC) for ratiometric applications, or they can be

connected to different voltages (as long as they are between ground and VCC) when other input spans are

required.

Reducing the overall VREF span to less than 5V increases the sensitivity of the converter (e.g., if VREF = 2V, then

1 LSB = 1.953 mV). Note, however, that linearity and offset errors become larger when lower reference voltages

are used. See Typical Performance Characteristics for more information. For this reason, reference voltages less

than 2V are not recommended.

In most applications, VREF−will simply be connected to ground, but it is often useful to have an input span that is

offset from ground. This situation is easily accommodated by the reference configuration used in the ADC10061,

ADC10062, and ADC10064. VREF−can be connected to a voltage other than ground as long as the voltage

source connected to this pin is capable of sinking the converter's reference current (12.5 mA Max @ VREF = 5V).

If VREF−is connected to a voltage other than ground, bypass it with multiple capacitors.

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Since the resistance between the two reference inputs can be as low as 400Ω, the voltage source driving the

reference inputs should have low output impedance. Any noise on either reference input is a potential cause of

conversion errors, so each of these pins must be supplied with a clean, low noise voltage source. Each reference

pin should be bypassed with a 10 µF tantalum and a 0.1 µF ceramic.

THE ANALOG INPUT

The ADC10061, ADC10062, and ADC10064 sample the analog input voltage once every conversion cycle.

When this happens, the input is briefly connected to an impedance approximately equal to 600Ωin series with 35

pF. Short-duration current spikes can be observed at the analog input during normal operation. These spikes are

normal and do not degrade the converter's performance.

Large source impedances can slow the charging of the sampling capacitors and degrade conversion accuracy.

Therefore, only signal sources with output impedances less than 500Ωshould be used if rated accuracy is to be

achieved at the minimum sample time (250 ns maximum). If the sampling time is increased, the source

impedance can be larger. If a signal source has a high output impedance, its output should be buffered with an

operational amplifier. The operational amplifier's output should be well-behaved when driving a switched 35

pF/600Ωload. Any ringing or voltage shifts at the op-amp's output during the sampling period can result in

conversion errors.

Correct conversion results will be obtained for input voltages greater than GND −50 mV and less than V++

50 mV. Do not allow the signal source to drive the analog input pin beyond the Absolute Maximum Rating. If an

analog input pin is forced beyond these voltages, the current flowing through the pin should be limited to 5 mA or

less to avoid permanent damage to the IC. The sum of all the overdrive currents into all pins must be less than

the Absolute Maximum Rating for Package Input Current. When the input signal is expected to extend beyond

this limit, an input protection scheme should be used. A simple input protection network using diodes and

resistors is shown in Figure 21. Note the multiple bypass capacitors on the reference and power supply pins. If

VREF−is not grounded, it should also be bypassed to analog ground using multiple capacitors (see POWER

SUPPLY CONSIDERATIONS). AGND and DGND should be at the same potential. VIN0 is shown with an input

protection network. Pin 17 is normally left open, but optional “speedup” resistor RSA can be used to reduce the

conversion time.

Figure 21. Typical Connection

INHERENT SAMPLE-AND-HOLD

Because the ADC10061, ADC10062, and ADC10064 sample the input signal once during each conversion, they

are capable of measuring relatively fast input signals without the help of an external sample-hold. In a non-

sampling successive-approximation A/D converter, regardless of speed, the input signal must be stable to better

than ±1/2 LSB during each conversion cycle or significant errors will result. Consequently, even for many

relatively slow input signals, the signals must be externally sampled and held constant during each conversion if

a SAR with no internal sample-and-hold is used.

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Because they incorporate a direct sample/hold control input, the ADC10061, ADC10062, and ADC10064 are

suitable for use in DSP-based systems. The S/H input allows synchronization of the A/D converter to the DSP

system's sampling rate and to other ADC10061s, ADC10062s, and ADC10064s.

POWER SUPPLY CONSIDERATIONS

The ADC10061, ADC10062, and ADC10064 are designed to operate from a +5V (nominal) power supply. There

are two supply pins, AVCC and DVCC. These pins allow separate external bypass capacitors for the analog and

digital portions of the circuit. To ensure accurate conversions, the two supply pins should be connected to the

same voltage source, and each should be bypassed with a 0.1 µF ceramic capacitor in parallel with a 10 µF

tantalum capacitor. Depending upon the circuit board layout and other system considerations, more bypassing

may be necessary.

The ADC10061 has a single ground pin, and the ADC10062 and ADC10064 each have separate analog and

digital ground pins for separate bypassing of the analog and digital supplies. The devices with separate analog

and digital ground pins should have their ground pins connected to the same potential, and all grounds should be

“clean” and free of noise.

In systems with multiple power supplies, careful attention to power supply sequencing may be necessary to avoid

over-driving inputs. The A/D converter's power supply pins should be at the proper voltage before digital or

analog signals are applied to any of the other pins.

LAYOUT AND GROUNDING

In order to ensure fast, accurate conversions from the ADC10061, ADC10062, and ADC10064, it is necessary to

use appropriate circuit board layout techniques. The analog ground return path should be low-impedance and

free of noise from other parts of the system. Noise from digital circuitry can be especially troublesome.

All bypass capacitors should be located as close to the converter as possible and should connect to the

converter and to ground with short traces. The analog input should be isolated from noisy signal traces to avoid

having spurious signals couple to the input. Any external component (e.g., a filter capacitor) connected across

the converter's input should be connected to a very clean ground return point. Grounding the component at the

wrong point will result in reduced conversion accuracy.

DYNAMIC PERFORMANCE

Many applications require the A/D converter to digitize AC signals, but conventional DC integral and differential

nonlinearity specifications don't accurately predict the A/D converter's performance with AC input signals. The

important specifications for AC applications reflect the converter's ability to digitize AC signals without significant

spectral errors and without adding noise to the digitized signal. Dynamic characteristics such as signal-to-noise

ratio (SNR) and total harmonic distortion (THD), are quantitative measures of this capability.

An A/D converter's AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal

waveform is applied to the A/D converter's input, and the transform is then performed on the digitized waveform.

The resulting spectral plot might look like the ones shown in Typical Performance Characteristics. The large peak

is the fundamental frequency, and the noise and distortion components (if any are present) are visible above and

below the fundamental frequency. Harmonic distortion components appear at whole multiples of the input

frequency. Their amplitudes are combined as the square root of the sum of the squares and compared to the

fundamental amplitude to yield the THD specification. Typical values for THD are given in the table of Electrical

Characteristics.

Signal-to-noise ratio is the ratio of the amplitude at the fundamental frequency to the rms value at all other

frequencies, excluding any harmonic distortion components. Typical values are given in the Electrical

Characteristics table. An alternative definition of signal-to-noise ratio includes the distortion components along

with the random noise to yield a signal-to-noise-plus-distortion ratio, or S/(N + D).

The THD and noise performance of the A/D converter will change with the frequency of the input signal, with

more distortion and noise occurring at higher signal frequencies. One way of describing the A/D's performance

as a function of signal frequency is to make a plot of “effective bits” versus frequency. An ideal A/D converter

with no linearity errors or self-generated noise will have a signal-to-noise ratio equal to (6.02n + 1.76) dB, where

n is the resolution in bits of the A/D converter. A real A/D converter will have some amount of noise and

distortion, and the effective bits can be found by:

Product Folder Links: ADC10061 ADC10062 ADC10064

ADC10061, ADC10062, ADC10064

www.ti.com

SNAS069E –JUNE 1999–REVISED MARCH 2013

where

• S/(N + D) is the ratio of signal to noise and distortion, which can vary with frequency (1)

As an example, an ADC10061 with a 5 VP-P, 100 kHz sine wave input signal will typically have a signal-to-noise-

plus-distortion ratio of 59.2 dB, which is equivalent to 9.54 effective bits. As the input frequency increases, noise

and distortion gradually increase, yielding a plot of effective bits or S/(N + D) as shown in Typical Performance

Characteristics.

SPEED ADJUST

In applications that require faster conversion times, the Speed Adjust pin (pin 14 on the ADC10062, pin 17 on the

ADC10064) can significantly reduce the conversion time. The speed adjust pin is connected to an on-chip current

source that determines the converter's internal timing. By connecting a resistor between the speed adjust pin and

ground as shown in Figure 21, the internal programming current is increased, which reduces the conversion time.

As an example, an 18k resistor reduces the conversion time of a typical part from 600 ns to 350 ns with no

significant effect on linearity. Using smaller resistors to further decrease the conversion time is possible as well,

although the linearity will begin to degrade somewhat (see Typical Performance Characteristics). Note that the

resistor value needed to obtain a given conversion time will vary from part to part, so this technique will generally

require some “tweaking” to obtain satisfactory results.

Product Folder Links: ADC10061 ADC10062 ADC10064

ADC10061, ADC10062, ADC10064

SNAS069E –JUNE 1999–REVISED MARCH 2013

www.ti.com

REVISION HISTORY

Changes from Revision D (March 2013) to Revision E Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 15

Product Folder Links: ADC10061 ADC10062 ADC10064

PACKAGE OPTION ADDENDUM

www.ti.com 1-Nov-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC10064CIWM NRND SOIC DW 28 26 TBD Call TI Call TI -40 to 85 ADC10064

CIWM

ADC10064CIWM/NOPB ACTIVE SOIC DW 28 26 Green (RoHS

& no Sb/Br) SN | CU SN Level-2-260C-1 YEAR -40 to 85 ADC10064

CIWM

ADC10064CIWMX/NOPB ACTIVE SOIC DW 28 1000 Green (RoHS

& no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC10064

CIWM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 1-Nov-2013

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADC10064CIWMX/NOPB SOIC DW 28 1000 330.0 24.4 10.8 18.4 3.2 12.0 24.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADC10064CIWMX/NOPB SOIC DW 28 1000 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 2

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