a FEATURES Monolithic Design for Reliability and Low Cost High Slew Rate: 0.5 V/s Low Droop Rate TA = 25C: 0.1 mV/ms T A = 125C: 10 mV/ms Low Zero-Scale Error: 4 mV Digitally Selected Hold and Reset Modes Reset to Positive or Negative Voltage Levels Logic Signals TTL and CMOS Compatible Uncommitted Comparator On-Chip Available in Die Form Monolithic Peak Detector with Reset-and-Hold Mode PKD01 FUNCTIONAL BLOCK DIAGRAM +IN -IN OUTPUT V+ V- - CMP + LOGIC GND V- OUTPUT BUFFER DET GATED "gm" AMP - -IN - D1 C OUTPUT + A + +IN -IN - +IN + GATED "gm" AMP B PKD01 GENERAL DESCRIPTION The PKD01 tracks an analog input signal until a maximum amplitude is reached. The maximum value is then retained as a peak voltage on a hold capacitor. Being a monolithic circuit, the PKD01 offers significant performance and package density advantages over hybrid modules and discrete designs without sacrificing system versatility. The matching characteristics attained in a monolithic circuit provide inherent advantages when charge injection and droop rate error reduction are primary goals. Innovative design techniques maximize the advantages of monolithic technology. Transconductance (gm) amplifiers were chosen over conventional voltage amplifier circuit building blocks. The gm amplifiers simplify internal frequency compensation, minimize acquisition time and maximize circuit accuracy. Their outputs are easily switched by low glitch current steering circuits. The steered outputs are clamped to reduce charge injection errors upon entering the hold mode or exiting the reset mode. The inherently low zero-scale error is further reduced by active Zener-Zap trimming to optimize overall accuracy. RST RST 0 0 1 1 DET 0 1 1 0 OPERATIONAL MODE PEAK DETECT PEAK HOLD RESET INDETERMINATE CH SWITCHES SHOWN FOR: RST = "0," DET = "0" The output buffer amplifier features an FET input stage to reduce droop rate error during lengthy peak hold periods. A bias current cancellation circuit minimizes droop error at high ambient temperatures. Through the DET control pin, new peaks may either be detected or ignored. Detected peaks are presented as positive output levels. Positive or negative peaks may be detected without additional active circuits, since Amplifier A can operate as an inverting or noninverting gain stage. An uncommitted comparator provides many application options. Status indication and logic shaping/shifting are typical examples. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001 PKD01-SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = 15 V, C S Parameter gm AMPLIFIERS A, B Zero-Scale Error Input Offset Voltage Input Bias Current Input Offset Current Voltage Gain Open-Loop Bandwidth Common-Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range1 Slew Rate Feedthrough Error1 Acquisition Time to 0.1% Accuracy1 Acquisition Time to 0.01% Accuracy1 = 1000 pF, TA = 25C, unless otherwise noted.) PKD01A/E Min Typ Max Symbol Conditions VZS VOS IB IOS AV BW CMRR PSRR VCM SR RL = 10 k, VO = 10 V AV = 1 -10 V VCM +10 V 9 V VS 18 V VIN = 20 V, DET = 1, RST = 0 tAQ tAQ COMPARATOR Input Offset Voltage Input Bias Current Input Offset Current Voltage Gain Common-Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range1 Low Output Voltage "OFF" Output Leakage Current Output Short-Circuit Current Response Time2 VOS IB IOS AV CMRR PSRR VCM VOL IL ISC tS DIGITAL INPUTS - RST, DET2 Logic "1" Input Voltage Logic "0" Input Voltage Logic "1" Input Current Logic "0" Input Current VH VL IINH IINL MISCELLANEOUS Droop Rate3 VDR Output Voltage Swing: Amplifier C Short-Circuit Current: Amplifier C Switch Aperture Time Switch Switching Time Slew Rate: Amplifier C Power Supply Current H VOP ISC tAP ts SR ISY 18 80 86 10 66 20 V Step, AVCL = +1 20 V Step, AVCL = +1 2 k Pull-Up Resistor to 5 V -10 V VCM +10 V 9 V VS 18 V ISINK 5 mA, Logic GND = 0 V VOUT = 5 V VOUT = 5 V 5 mV Overdrive, 2 k Pull-Up Resistor to 5 V 2 2 80 20 25 0.4 90 96 11 0.5 80 4 3 150 40 41 45 70 0.5 700 75 5 7.5 82 106 76 90 11.5 12.5 -0.2 +0.15 25 7 12 150 10 74 76 10 66 1.5 1000 300 +0.4 80 45 2 VH = 3.5 V VL = 0.4 V 0.02 1.6 TJ = 25C TA = 25C DET = 1 RL = 2.5 k 0.01 0.02 0.07 0.15 11.5 12.5 RL = 2.5 k No Load 3 3 80 20 25 0.4 90 96 11 0.5 80 7 6 250 75 mV mV nA nA V/mV MHz dB dB V V/s dB 41 45 70 s s 1 700 75 3.5 7.5 82 106 76 90 11.5 12.5 -0.2 +0.15 25 7 12 150 3 mV 1000 nA 300 nA V/mV dB dB V +0.4 V 80 A 45 mA ns 2 0.8 1 10 7 PKD01F Min Typ Max Unit 15 75 50 2.5 5 40 7 0.02 1.6 0.8 1 10 V V A A 0.01 0.03 0.1 0.20 mV/ms mV/ms 11 12 7 15 75 50 2.5 6 V 40 9 mA ns ns V/s mA NOTES 1 Guaranteed by design. 2 DET = 1, RST = 0. 3 Due to limited production test times, the droop current corresponds to junction temperature (T J). The droop current vs. time (after power-on) curve clarified this point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T A) also. The warmed-up (T A) droop current specification is correlated to the junction temperature (TJ) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature. Ambient (T A) temperature specifications are not subject to production testing. Specifications subject to change without notice. -2- REV. A PKD01 ELECTRICAL CHARACTERISTICS (@ VS = 15 V, CH = 1000 pF, -55C TA +125C for PKD01AY, -25C TA +85C for PKD01EY, PKD01FY and 0C TA +70C for PKD01EP, PKD01FP, unless otherwise noted.) Parameter Symbol Conditions PKD01A/E PKD01F Min Typ Max Min Typ Max Unit "gm" AMPLIFIERS A, B Zero-Scale Error Input Offset Voltage Average Input Offset Drift1 Input Bias Current Input Offset Current Voltage Gain Common-Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range1 Slew Rate Acquisition Time to 0.1% Accuracy1 VZS VOS TCVOS IB IOS AV CMRR PSRR VCM SR tAQ 4 3 -9 160 30 7.5 9 74 82 80 90 10 11 0.4 60 COMPARATOR Input Offset Voltage Average Input Offset Drift1 Input Bias Current Input Offset Current Voltage Gain Common-Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range1 Low Output Voltage OFF Output Leakage Current Output Short-Circuit Current Response Time VOS TCVOS IB IOS AV CMRR PSRR VCM VOL IL ISC tS DIGITAL INPUTS - RST, DET Logic "1" Input Voltage Logic "0" Input Voltage Logic "1" Input Current Logic "0" Input Current VH VL IINH IINL MISCELLANEOUS Droop Rate3 VDR RL = 10 k, VO = 10 V -10 V VCM +10 V 9 V VS 18 V 20 V Step, AVCL = +1 2 -4 1000 100 6.5 100 82 2 k Pull-Up Resistor to 5 V -10 V VCM +10 V 9 V VS 18 V 7 6 -24 250 100 5 72 70 10 2.5 -6 2000 600 4 2.5 80 80 72 72 11 11 ISINK 5 mA, Logic GND = 0 V -0.2 +0.15 +0.4 -0.2 VOUT = 5 V 25 100 VOUT = 5 V 6 10 45 6 5 mV Overdrive, 2 k Pull-Up Resistor to 5 V 200 6 5 -9 160 30 9 80 90 11 0.4 60 12 10 -24 500 150 mV mV V/C nA nA V/mV dB dB V V/s s 2 -4 1100 100 6.5 92 86 5 -6 2000 600 +0.15 +0.4 100 180 10 45 mV V/C nA nA V/mV dB dB V V A mA 200 ns 2 Output Voltage Swing Amplifier C Short-Circuit Current Amplifier C Switch Aperture Time Slew Rate: Amplifier C Power Supply Current VOP ISC tAP SR ISY 2 2 0.02 2.5 0.8 1 15 V V A A VH = 3.5 V VL = 0.4 V 0.02 2.5 0.8 1 15 TJ = Max Operating Temp. TA = Max Operating Temp. DET = 1 1.2 10 3 15 mV/ms 2.4 20 6 20 mV/ms 11 12 RL = 2.5 k 6 RL = 2.5 k No Load 12 75 2 5.5 10.5 12 40 8 6 12 75 2 6.5 V 40 10 mA ns V/s mA NOTES 1 Guaranteed by design. 2 DET = 1, RST = 0. 3 Due to limited production test times, the droop current corresponds to junction temperature (T J ). The droop current vs. time (after power-on) curve clarifies this point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T A ) also. The warmed-up (T A ) droop current specification is correlated to the junction temperature (T J) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature. Ambient (T A ) temperature specifications are not subject to production testing. Specifications subject to change without notice. REV. A -3- PKD01 ABSOLUTE MAXIMUM RATINGS 1, 2 ORDERING GUIDE1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input Voltage . . . . . . . . . . . . . . . . . . . Equal to Supply Voltage Logic and Logic Ground Voltage . . . . . . . . . . . . . . . . . . . . . . Equal to Supply Voltage Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Amplifier A or B Differential Input Voltage . . . . . . . . . . 24 V Comparator Differential Input Voltage . . . . . . . . . . . . . 24 V Comparator Output Voltage . . . . . . . . . . . . . . . . . . . . . . Equal to Positive Supply Voltage Hold Capacitor Short-Circuit Duration . . . . . . . . . . Indefinite Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300C Storage Temperature Range PKD01AY, PKD01EY, PKD01FY . . . . . -65C to +150C PKD01EP, PKD01FP . . . . . . . . . . . . . . . -65C to +125C Operating Temperature Range PKD01AY . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C PKD01EY, PKD01FY . . . . . . . . . . . . . . . . -25C to +85C PKD01EP, PKD01FP . . . . . . . . . . . . . . . . . . . 0C to 70C Junction Temperature . . . . . . . . . . . . . . . . . -65C to +150C Model2 Temperature Range Package Description Package Option PKD01AY PKD01EY PKD01FY PKD01EP PKD01FP -55C to +85C -25C to +85C -25C to +85C 0C to 70C 0C to 70C Cerdip Cerdip Cerdip Plastic DIP Plastic DIP Q-14 Q-14 Q-14 N-14 N-14 NOTES 1 Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages. 2 For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet. PIN CONFIGURATION DET RST V+ NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. LOGIC GND OUTPUT CH COMP OUT PKD01 -IN C -IN A +IN C +IN A -IN B V- +IN B THERMAL CHARACTERISTICS Package Type JA* JC Unit 14-Lead Hermetic DIP (Y) 14-Lead Plastic DIP (P) 99 76 12 33 C/W C/W *JA is specified for worst-case mounting conditions, i.e., JA is specified for device in socket for cerdip and PDIP packages. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the PKD01 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE DICE CHARACTERISTICS -4- REV. A PKD01 WAFER TEST LIMITS (@ V = 15 V, C S H = 1000 pF, TA = 25C, unless otherwise noted.) Parameter Symbol "gm" AMPLIFIERS A, B Zero-Scale Error Input Offset Voltage Input Bias Current Input Offset Current Voltage Gain Common-Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range1 Feedthrough Error VZS VOS IB IOS AV CMRR PSRR VCM COMPARATOR Input Offset Voltage Input Bias Current Input Offset Current Voltage Gain1 Common-Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range1 Low Output Voltage "OFF" Output Leakage Current Output Short-Circuit Current VOS IB IOS AV CMRR PSRR VCM VOL IL ISC DIGITAL INPUTS-RST, DET2 Logic "1" Input Voltage Logic "0" Input Voltage Logic "1" Input Current Logic "0" Input Current VH VL IINH IINL MISCELLANEOUS Droop Rate3 VDR Conditions RL = 10 k, VO = 10 V -10 V VCM +10 V 9 V VS 18 V VIN = 20 V, DET = 1, RST = 0 2 k Pull-Up Resistor to 5 V -10 V VCM +10 V 9 V VS 18 V ISINK 5 mA, Logic GND = 5 V VOUT = 5 V VOUT = 5 V VH = 3.5 V VL = 0.4 V Unit 7 6 250 75 10 74 76 11.5 66 mV max mV max nA max nA max V/mV min dB min dB min V min dB min 3 1000 300 3.5 82 76 11.5 0.4 -0.2 80 45 7 mV max nA max nA max V/mV min dB min dB min V min V max V min A max mA min mA min 2 0.8 1 10 V min V max A max A max mV/ms max mV/ms max V min mA max mA min mA max Output Voltage Swing Amplifier C Short-Circuit Current Amplifier C VOP ISC Power Supply Current ISY No Load 0.1 0.20 11 40 7 9 SR tA tA 0.1% Accuracy, 20 V Step, AVCL = 1 0.01% Accuracy, 20 V Step, AVCL = 1 0.5 41 45 V/s s s 5 mV Overdrive, 2 k Pull-Up Resistor to 5 V 150 ns RL = 2.5 k 75 50 2.5 ns ns V/s gm AMPLIFIERS A, B Slew Rate Acquisition Time1 COMPARATOR Response Time MISCELLANEOUS Switch Aperture Time Switching Time Buffer Slew Rate tAP tS SR TJ = 25C, TA = 25C RL = 2.5 k PKD01N Limit NOTES 1 Guaranteed by design. 2 DET = 1, RST = 0. 3 Due to limited production test times, the droop current corresponds to junction temperature (T J). The droop current vs. time (after power-on) curve clarifies this point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T A) also. The warmed-up (T A) droop current specification is correlated to the junction temperature (T J) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature. Ambient (TA) temperature specifications are not subject to production testing. REV. A -5- PKD01-Typical Performance Characteristics 18 INPUT RANGE OF AMPLIFIER - V 35 6 2 -55C +25C -2 +125C -6 -10 V- SUPPLY 30 2 A,B IOS - nA INPUT + RANGE = V+ -55C TA +125C OFFSET VOLTAGE - mV 4 10 0 9 12 15 6 SUPPLY VOLTAGE +V AND -V -V TPC 1. A and B Input Range vs. Supply Voltage 0 25 50 75 100 125 150 TEMPERATURE - C TPC 3. A, B IOS vs. Temperature 1.0 100 VS = 15V TA = 25C AV = +1 +125C +25C 0.5 100 RS = 10k RS = 0 10 10 ERROR - mV RMS NOISE - V -55C 0 1 -0.5 0 0 1 10 100 FREQUENCY - Hz 1k 0.1 1 TPC 4. Input Spot Noise vs. Frequency TPC 5. Wideband Noise vs. Bandwidth 1.0 18 POLARITY OF ERROR MAY BE POSITIVE OR NEGATIVE CH = 1000pF TA = 25C 10 OUTPUT SWING - V 0 +125C +25C 15 12.5 +125C 6 +25C -55C 2 -55C -2 +25C -6 -10 -55C -1.0 -10 RL = 10k V+ SUPPLY +125C V- SUPPLY -14 10.0 7.5 5.0 2.5 0 -2.5 -5.0 -7.5 -10.0 -12.5 -15 -18 -5 0 VIN - V 5 TPC 7. Amplifier A Charge Injection Error vs. Input Voltage and Temperature 10 4 9 12 15 6 SUPPLY VOLTAGE +V AND -V - V 18 TPC 8. Output Voltage Swing vs. Supply Voltage (Dual Supply Operation) -6- -5 0 VIN - V 5 10 TPC 6. Amplifier B Charge Injection Error vs. Input Voltage and Temperature 14 0.5 -0.5 -1.0 -10 1000 10 100 BANDWIDTH - kHz OUTPUT SWING - Volts INPUT NOISE VOLTAGE - nV/ Hz 0 -75 -50 -25 100 125 TPC 2. A and B Amplifiers Offset Voltage vs. Temperature 1000 15 5 -6 -75 -50 -25 0 25 50 75 TEMPERATURE - C 18 20 10 -14 4 25 -2 -4 -18 ERROR - mV 40 6 14 1.0 +25C -55C +125C -55C +25C +125C 0.1 10.0 LOAD RESISTOR TO GROUND - k TPC 9. Output Voltage vs. Load Resistance REV. A PKD01 12 CH = 1000pF PEAK OUTPUT 90 8 200mV ERROR 90 DETECTED PEAK 4 10 0% 2s 10mV 10k 100k 1k FREQUENCY - Hz 10mV 1M TPC 10. Output Error vs. Frequency and Input Voltage TPC 11. Settling Response TPC 12. Settling Response 90 0V 10 0% OUTPUT VOLTAGE - 5V/DIV 100 100 90 0V 10 0% TIME - 20s/DIV 100 GAIN TA = 25C 10 0% CH = 1000pF GAIN - dB TA = 25C TA = 25C 0 CH = 1000pF 45 90 30 135 PHASE 180 10 0 0% 0V -30 1 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M TPC 17. Small-Signal Open-Loop Gain/Phase vs. Frequency -7- TPC 15. Settling Time for -10 V to 0 V Step Input 120 TA = 25C RL = 10k CL = 30pF CH = 1000pF 60 90 REV. A 90 TIME - 20s/DIV TPC 14. Large-Signal Noninverting Response 90 TPC 16. Settling Time for +10 V to 0 V Step Input 0V 100 TIME - 20s/DIV TPC 13. Large-Signal Inverting Response TIME - 20s/DIV OUTPUT VOLTAGE - 5mV/DIV TA = 25C TA = 25C CHANNEL-TO-CHANNEL ISOLATION - dB 0 100 10V 3kHz SINEWAVE INPUT 10 0% 2 OUTPUT VOLTAGE - 5V/DIV CH = 1000pF 100 2mV ERROR 6 20mV ERROR OUTPUT VOLTAGE - 5mV/DIV 2s 10mV 100 PHASE LAG - Degrees PK OF SINEWAVE - V 10 TA = 25C 100 80 60 TEST CONDITION: CH = 1000pF AMPLIFIER A AND B CONNECTED IN +1 GAIN 40 20 AMPLIFIER A(B) OFF, INPUT = 20V p-p AMPLIFIER B(B) ON, INPUT = 0V 0 1 10 100 1k 10k 100k FREQUENCY - Hz 1M TPC 18. Channel-to-Channel Isolation vs. Frequency 10M PKD01 100 ACQUISITION TIME TO 0.1% ACCURACY - s 3 A, AV = +1 B, AV = 1 TA = 125C CH = 1000pF DROOP RATE - mV/ms A, AV = -1 60 40 2 1 20 1 10 100 1k 10k 100k FREQUENCY - Hz 1M 0 10M TPC 19. Off Isolation vs. Frequency ) % .1 (0 ) 1% (0. mV 0 1 V TO 20 ) EP .1% ST V (0 V 0 O 5m 1 T P TE ) 5V S V (0.1% P TO 1m 1V STE EP ST 200 100 80 60 40 20 0 TO V m 20 0 2000 4000 6000 8000 HOLD CAPACITANCE - pF 10000 TO 20mV 30 TO 2mV 20 TO 200mV 10 0 5 10 INPUT STEP - V 15 5V 1000 RESET 0V 10 5V 3kHz SINEWAVE INPUT -10V -10V JUNCTION TEMPERATURE 100 0 50 TEMPERATURE - C 500 100 5 5mV 5mV 1V 1V 90 4 +5 3 0 2 -5 1 TPC 24. Acquisition of Step Input 50ns 50ns COMPARATOR OUTPUT COMPARATOR OUTPUT 10 0% 0 100 5 5mV 5mV 50ns 50ns COMPARATOR OUTPUT COMPARATOR OUTPUT 90 +5 4 3 0 2 -5 1 10 0% 0 50s TIME - 50ns/DIV TPC 25. Acquisition of Sine Wave Peak 0V -10V 10V -50 +10V 0% TPC 23. Droop Rate vs. Temperature OUTPUT VOLTAGE - V +10V 0V INPUT 10 10 1V 1V 90 50s RESET PEAK OUTPUT 1 -100 DETECTED PEAK PEAK DETECT +10V AMBIENT TEMPERATURE 100 5V CH = 1000pF 10V RESET 90 20 TPC 22. Acquisition Time vs. Input Voltage Step Size 0% 100 TPC 26. Comparator Output Response Time (2 k Pull-Up Resistor, TA = 25 C) -8- TIME - 50ns/DIV TPC 27. Comparator Output Response Time (2 k Pull-Up Resistor, TA = 25 C) REV. A INPUT VOLTAGE - mV 40 SETTLING TIME - s 300 TPC 21. Acquisition Time vs. External Hold Capacitor and Acquisition Step TPC 20. Droop Rate vs. Time after Power On DROOP RATE (mV/sec), CH = 1000pF TA = 25C CH = 1000pF 100 2 3 4 5 6 7 8 9 10 1 TIME AFTER POWER APPLIED - Minutes 400 10000 50 0 0 INPUT VOLTAGE - mV 0 OUTPUT VOLTAGE - V OFF ISOLATION - dB 80 500 PKD01 18 +VIN V+ FOR -55C TA +125C 6 2 -55C +25C -2 +125C -6 -10 V- -14 -18 +125C 6 +25C 2 0 -2 -55C ACCEPTABLE GROUND PIN POTENTIAL IS BETWEEN SLIDE LINES. +25C -6 -10 +125C 4 9 12 15 6 SUPPLY VOLTAGE +V AND -V - V 18 4 6 9 12 15 SUPPLY VOLTAGE +V AND -V - V REJECTION RATIO - dB 80 +125C POSITIVE SUPPLY (+15V +1V SIN T) 60 40 NEGATIVE SUPPLY (-15V +1V SIN ) CHANNEL A = 1 CHANNEL B = 0 3 6 9 12 SUPPLY +V AND -V - V 15 TPC 31. Supply Current vs. Supply Voltage 3 110 2 100 1 0 -1 100 125 TPC 34. Comparator Offset Voltage vs. Temperature REV. A 1k 10k FREQUENCY - Hz 100k 1M 0 1 2 3 LOGIC INPUT VOLTAGE - V 4 5 3 VS = 15V TA = 25C INPUT CURRENT MUST BE LIMITED TO LESS THAN 1mA 2 1 OTHER INPUT AT -10V OTHER INPUT AT 0V 0 -1 -15 OTHER INPUT AT +10V -10 -5 0 5 INPUT VOLTAGE - V 10 15 TPC 33. Comparator Input Bias Current vs. Differential Input Voltage 1000 90 80 70 50 -75 -50 -25 -1 1200 800 600 400 60 -2 -3 -75 -50 -25 0 25 50 75 TEMPERATURE - C 100 TPC 32. Hold Mode Power Supply Rejection vs. Frequency COMPARATOR IOS - nA OFFSET VOLTAGE - mV 0 10 18 COMPARATOR IB - nA 0 +25C -2 TPC 30. Logic Input Current vs. Logic Input Voltage 20 4 +125C -3 -2 18 TA = 25C VIN = 0V CH = 1000pF +25C 5 -1 LOGIC GROUND = 0V 100 -55C -55C LOGIC 0 TPC 29. Input Range of Logic Ground vs. Supply Voltage 6 0 V- -14 -18 TPC 28. Input Logic Range vs. Supply Voltage SUPPLY CURRENT - mA LOGIC 1 10 INPUT BIAS CURRENT (EITHER INPUT) - A INPUT LOGIC RANGE - V 10 1 V+ 14 LOGIC CURRENT - A INPUT RANGE OF LOGIC GROUND - V 18 14 0 25 50 75 100 125 150 TEMPERATURE - C TPC 35. Comparator IOS vs. Temperature -9- 200 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - C TPC 36. Comparator IB vs. Temperature 14 V+ 10 +125C 6 +25C 2 -55C -2 +25C -6 +125C -10 V- -14 -18 4 9 12 15 6 SUPPLY VOLTAGE +V AND -V - V 18 VO - VOLTAGE OUTPUT - V DC 1.0 0.8 +125C 0.6 +25C 0.4 0.2 -55C 0 -0.2 0 2 4 6 8 10 12 IO - OUTPUT SINK CURRENT - mA TPC 40. Comparator Output Voltage vs. Output Current and Temperature 14 4 5 3 2 INVERTING INPUT = V IN NONINVERTING INPUT = 0V PULL-UP RESISTOR = 2k TA = +25C TA = -55C TA = +125C 1 0 +5 -5 -50 VS = 15V TA = 25C 4 3 2 RL = 2k TO 5V RL = 1k TO 5V 1 0 0 50 100 150 TIME - ns 200 250 300 TPC 38. Comparator Response Time vs. Temperature INPUT VOLTAGE - mV OUTPUT VOLTAGE - V TPC 37. Output Swing of Comparator vs. Supply Voltage 6 5 OUTPUT VOLTAGE - V OUTPUT RANGE OF COMPARATOR - V 18 INPUT VOLTAGE - mV OUTPUT VOLTAGE - V PKD01 0 -1.5 -1.0 -0.5 0 0.5 1.0 INPUT VOLTAGE - mV 1.5 2.0 TPC 39. Comparator Transfer Characteristic 5 PULL-UP RESISTOR = 2k 4 3 TA = -55C TA = +125C 2 TA = +25C 1 0 +5 0 -5 -50 0 50 100 150 TIME - ns 200 250 300 TPC 41. Comparator Response Time vs. Temperature -10- REV. A PKD01 THEORY OF OPERATION The typical peak detector uses voltage amplifiers and a diode or an emitter follower to charge the hold capacitor, CH, indirectionally (see Figure 1). The output impedance of A plus D1's dynamic impedance, rd, make up the resistance which determines the feedback loop pole. The dynamic impedance is rd = kT , where Id is the capacitor charging current. qI d The pole moves toward the origin of the S plane as Id goes to zero. The pole movement in itself will not significantly lengthen the acquisition time since the pole is enclosed in the system feedback loop. only be: 2K - gm VIN. The net current into the hold capacitor node then, is gmVIN [IH = 2I - (2I - gmVIN)]. In the hold mode, Q2 and Q3 are ON while Q1 and Q4 are OFF. The net current into the top of D1 is -I until D3 turns ON. With Q1 OFF, the bottom of D2 is pulled up with a current I until D4 turns ON, thus, D1 and D2 are reverse biased by <0.6 V, and charge injection is independent of input level. The monolithic layout results in points A and B having equal nodal capacitance. In addition, matched diodes D1 and D2 have equal diffusion capacitance. When the transconductance amplifier outputs are switched open, points A and B are ramped equally, but in opposite phase. Diode clamps D3 and D4 cause the swings to have equal amplitudes. The net charge injection (voltage change) at node C is therefore zero. V+ VOUT (A) = V IN (A) AV (A) I A VIN VOUT R + OUT 2I D3 A D1 OUTPUT C VH D1 rd C C CH INPUT D4 D2 CH B Q1 Figure 1. Conventional Voltage Amplifier Peak Detector When the moving pole is considered with the typical frequency compensation of voltage amplifiers however, there is a loop stability problem. The necessary compensation can increase the required acquisition time. ADI's approach replaces the input voltage amplifier with a transconductance amplifier (see Figure 2). The PKD01 transfer function can be reduced to: VOUT = VIN VIN Q2 6 Q3 A Q4 B gm V IN 3I 3I LOGIC CONTROL A > B = PEAK DETECT A < B = PEAK HOLD V- Figure 3. Transconductance Amplifier with Low Glitch Current Switch The peak transconductance amplifier, A is shown in Figure 4. Unidirectional hold capacitor charging requires diode D1 to be connected in series with the output. Upon entering the peak hold mode D1 is reverse-biased. The voltage clamp limits charge injection to approximately 1 pC and the hold step to 0.6 mV. 1 1 1 sCH sC 1+ + 1+ H gm gm ROUT gm where: gm 1 A/mV, ROUT 20 M. The diode in series with A's output (see Figure 2) has no effect because it is a resistance in series with a current source. In addition to simplifying the system compensation, the input transconductance amplifier output current is switched by current steering. The steered output is clamped to reduce and match any charge injection. Minimizing acquisition time dictates a small CH capacitance. A 1000 pF value was selected. Droop rate was also minimized by providing the output buffer with an FET input stage. A current cancellation circuit further reduces droop current and minimizes the gate current's tendency to double for every 10 temperature change. V+ I 2I D3 IOUT (A) = V IN (A) gm (A) D1 A IOUT VIN INPUT ROUT D1 C VH OUTPUT D4 CH VOUT CH Q1 VIN Figure 2. Transconductance Amplifier Peak Detector Q2 6 Q3 A Q4 B gm V IN 3I Figure 3 shows a simplified schematic of the reset gm amplifier, B. In the track mode, Q1 and Q4 are ON and Q2 and Q3 are OFF. A current of 2I passes through D1, I is summed at B and passes through Q1, and is summed with gmVIN. The current sink can absorb only 3I, thus the current passing through D2 can REV. A C rd D2 3I V- LOGIC CONTROL A > B = PEAK DETECT A < B = PEAK HOLD Figure 4. Peak Detecting Transconductance Amplifier with Switched Output -11- PKD01 A. Nulling Gated Output gm Amplifier A. Diode D1 must be conducting to close the feedback circuit during amplifier A VOS adjustment. Resistor network RA - RC cause D1 to conduct slightly. With DET = 0 and VIN = 0 V, monitor the PKD01 output. Adjust the null potentiometer until VOUT = 0 V. After adjustment, disconnect RC from CH. APPLICATIONS INFORMATION Optional Offset Voltage Adjustment Offset voltage is the primary zero scale error component since a variable voltage clamp limits voltage excursions at D1's anode and reduces charge injection. The PKD01 circuit gain and operational mode (positive or negative peak detection) determine the applicable null circuit. Figures 5 through 8 are suggested circuits. Each circuit also corrects amplifier C offset voltage error. VS+ B. Nulling Gated gm Amplifier B. Set Amplifier B signal input to VIN = 0 V and monitor the PKD01 output. Set DET = 1, RST = 1 and adjust the null potentiometer for VOUT = 0 V. The circuit gain--inverting or noninverting--will determine which null circuit illustrated in Figures 5 through 8 is applicable. 100k VS- R2 2M R1 1k DET 0.1F DET D1 R1 1k VIN+ R2 R1 VIN VS- A D1 R3 20k VOUT C A VOUT C 25k R4 20 0.1F VS+ -15V PKD01 B RC 2M RST RA 200k RC 2M RB 1k CH 1000pF -15V PKD01 B RA 200k RST RB CH NOTES: 1k 1000pF R4 1. NULL RANGE = VS R3 2. DISCONNECT RC FROM CH AFTER AMPLIFIER A ADJUSTMENT. 3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED. NOTES: 1. NULL RANGE = VS R1 R2 2. DISCONNECT RC FROM CH AFTER AMPLIFIER A ADJUSTMENT. 3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED. RA, RB AND RC NOT NECESSARY FOR AMPLIFIER B ADJUSTMENT. ( ) ( ) Figure 7. VOS Null Circuit for Negative Peak Detector Figure 5. VOS Null Circuit for Unity Gain Positive Peak Detector VS- R2 = R3 + R4 VIN+ R1 VS+ DET D1 A R4 VOUT VIN VOUT C R4 = R2 R1 R1 + R2 R3 25k 0.1F R3 20 R2 R1 + R3 VS+ D1 C R5 20k 0.1F GAIN = 1 + R2 A R1 VS- R1 25k DET VIN- R5 20k -15V PKD01 B R4 20 B RC 2M RA 200k RST -15V PKD01 RC 2M RA 200k RB CH 1k 1000pF NOTES: R1 1. NULL RANGE = VS R5 R4 R1 + R3 2. DISCONNECT RC FROM CH AFTER AMPLIFIER A ADJUSTMENT. 3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED. RST RB CH NOTES: 1k 1000pF R3 1. NULL RANGE = VS R5 2. DISCONNECT RC FROM CH AFTER AMPLIFIER A ADJUSTMENT. 3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED. Figure 6. VOS Null Circuit for Differential Peak Detector Figure 8. VOS Null Circuit for Positive Peak Detector with Gain ( )( ) ( ) -12- REV. A PKD01 PEAK HOLD CAPACITOR RECOMMENDATIONS COMPARATOR INPUT The hold capacitor (CH) serves as the peak memory element and compensating capacitor. Stable operation requires a minimum value of 1000 pF. Larger capacitors may be used to lower droop rate errors, but acquisition time will increase. VC R1 PKD01 VOH CMP R2 Zero scale error is internally trimmed for CH = 1000 pF. Other CH values will cause a zero scale shift which can be approximated with the following equation. ( ) VZS mV = ( ) - 0.6 mV (nF ) 1 x 103 pC CH The peak hold capacitor should have very high insulation resistance and low dielectric absorption. For temperatures below 85C, a polystyrene capacitor is recommended, while a Teflon capacitor is recommended for high temperature environments. CAPACITOR GUARDING AND GROUND LAYOUT Ground planes are recommended to minimize ground path resistance. Separate analog and digital grounds should be used. The two ground systems are tied together only at the common system ground. This avoids digital currents returning to the system ground through the analog ground path. INVERTING COMPARATOR INPUT DIGITAL GND V- R1 = R2 ( VV C ) -1 OH Figure 10. Comparator Output with External Level-Setting Resistors Table I. VC VOH R1 R2 5 5 15 15 15 15 3.5 5.0 3.5 5.0 7.5 10.0 2.7 k 2.7 k 4.7 k 4.7 k 7.5 k 7.5 k 6.2 k 1.5 k 2.4 k 7.5 k 15 k R1 VC I SINK 1 R2 VC - 1 VOH 1 14 13 PEAK DETECTOR LOGIC CONTROL (RST, DET) 2 PKD01 3 12 4 CH 11 10 5 9 6 8 7 REPEAT ON "COMPONENT SIDE" OF PC BOARD IF POSSIBLE BOTTOM VIEW The transconductance amplifier outputs are controlled by the digital logic signals RST and DET. The PKD01 operational mode is selected by steering the current (I1) through Q1 and Q2, thus providing high-speed switching and a predictable logic threshold. The logic threshold voltage is 1.4 V when digital ground is at zero volts. Other threshold voltages (VTH) may be selected by applying the formula: Figure 9. CH Terminal (Pin 4) Guarding. See Text. VTH 1.4 V + Digital Ground Potential. The CH terminal (Pin 4) is a high impedance point. To minimize gain errors and maintain the PKD01's inherently low droop rate, guarding Pin 4 as shown in Figure 9 is recommended. For proper operation, digital ground must always be at least 3.5 V below the positive supply and 2.5 V above the negative supply. The RST or DET signal must always be at least 2.8 V above the negative supply. COMPARATOR Operating the digital ground at other than zero volts does influence the comparator output low voltage. The VOL level is referenced to digital ground and will follow any changes in digital ground potential: The comparator output high level (VOH) is set by external resistors. It is possible to optimize noise immunity while interfacing to all standard logic families--TTL, DTL, and CMOS. Figure 10 shows the comparator output with external level-setting resistors. Table I gives typical R1 and R2 values for common circuit conditions. VOL 0.2 V + Digital Ground Potential. The maximum comparator high output voltage (VOH) should be limited to: VOH (maximum) < V+ -2.0 V With the comparator in the low state (VOL), the output stage will be required to sink a current approximately equal to VC/R1. REV. A -13- PKD01 V+ I1 DET OR RST Q1 56k 5% I2 Q2 D +18V 1 14 2 13 18k DIGITAL GROUND Q3 3 12 PKD01 5% 36k 5% V- CURRENT TO CONTROL MODES Figure 11. Logic Control 4 11 5 10 6 9 7 8 -18V Figure 12. Burn-In Circuit Typical Circuit Configurations V+ DET/RST V- D1 +10V A INPUT INPUT OUTPUT C 0V PKD01 +10V OUTPUT 0V RESET VOLTAGE A GAIN = +1 B GAIN = +1 B TIME - 50s/DIV CH 1000pF Figure 13. Unity Gain Positive Peak Detector V+ DET 10k 1% +5V 0V -2V +10V INPUT 0V OUTPUT -4V INPUT (GAIN = +2) 5.1k 5% V- D1 A C 40.2k 1% 10k 5% 10k 1% RESET VOLTAGE = +1V (RESETS TO -4V) OUTPUT PKD01 B A GAIN = +2 B GAIN = -4 8.2k 5% -10V TIME - 50s/DIV RST CH 1000pF Figure 14. Positive Peak Detector with Gain -14- REV. A PKD01 V+ DET/RST +2V 0V INPUT INPUT (GAIN = -2) 10k 20k 1% 1% 30.1k 1% C 8.2k 5% A GAIN = -2 B GAIN = +4 B -4V RESET VOLTAGE = -1V (RESETS TO -4V) -10V TIME - 50s/DIV OUTPUT PKD01 10k 1% 0V OUTPUT D1 A -5V +10V V- 7.5k 5% CH 1000pF RST Figure 15. Negative Peak Detector with Gain V+ DET INPUT 10k 1% VIN 0V 10k 1% V- D1 A OUTPUT PKD01 +10V OUTPUT C 10k 5% -10V RESET VOLTAGE 0V B TIME - 50s/DIV A GAIN = -1 B GAIN = +1 CH 1000pF Figure 16. Unity Gain Negative Peak Detector R2 R3 INPUT RESET VOLTAGE IF BOTH INPUT SIGNAL (AMPLIFIER A INPUT) AND THE RESET VOLTAGE (AMPLIFIER B INPUT) HAVE THE SAME POSITIVE VOLTAGE GAIN, THE GAIN CAN BE SET BY A SINGLE VOLTAGE DIVIDER FOR BOTH INPUT AMPLIFIERS. OUTPUT A C R4 R1 B PKD01 CH 1000pF INPUT AMPLIFIER GAIN RESET AMPLIFIER GAIN R3 = R4 = = 1 + R2 R1 NOTE: R1, R2, R3 AND R4 > 5k 1 1 + 1 R1 R2 Figure 17. Alternate Gain Configuration REV. A -15- PKD01 PKD01 POSITIVE PEAK DETECTOR VPK+ VPK+ 10k VPK- + V PK+ VIN VIN PKD01 NEGATIVE PEAK DETECTOR VPK- VOUT OP27 10k VPK- 10k 10k Figure 18. Peak-to-Peak Detector POS/NEG PEAK DETECTOR +15V 10.5k +15V -15V OUTPUT S2 R S3 PKD01 SW-02 S1 S4 PEAK DETECTOR RESET R CH INPUT 1000pF POLYSTYRENE NOTES: 1. DEVICE IS RESET TO 0 VOLTS. 2. DETECTED PEAKS ARE PRESENTED AS POSITIVE OUTPUT LEVELS. 3. R = 10k. -15V Figure 19. Logic Selectable Positive or Negative Peak Detector DAC10 PORT 0 0 1 2 3 4 5 6 7 BIT 1 PROCESSOR PORT 1 0 BIT 10 1 2 3 4 5 6 7 5V R 2.7k CMP R D1 INPUT SIGNAL A C DET RST PKD01 B RESET VOLTAGE CH Figure 20. Peak Reading A/D Converter -16- REV. A PKD01 5V INPUT A VIN VOUT C -15V +15V RESET PEAK DETECT VRS1 PKD01 B VRS2 OUTPUT VRS3 VRS4 2V SW-201 A1 A2 A3 A4 +15V -15V ANALOG GND 1ms NOTES: RESET VOLTAGE = -1.0V TRACE 1 = 2V/DIV TRACE 2 = 5V/DIV TRACE 3 = 2V/DIV LOGIC GND PK DET/RST Figure 21. Positive Peak Detector with Selectable Reset Voltage AMPLITUDE SELECTION LOGIC DET D1 A0 A1 A2 CH1 A BUFFERED RAMP OUTPUT C CH2 CH3 RAMP AMPLITUDE CH4 CH5 MUX-08 B RAMP SLOPE SELECTION PKD01 CH6 15V CH7 RST CH8 I RAMP AMPLITUDE 0 B8 CH SLOPE = ~0.5V/s B1 DAC08 RAMP START PULSE I0 SLOPE = C I1 C ~0.5V/s RAMP START PULSE NOTES: 1. NEGATIVE SLOPE OF RAMP IS SET BY DAC08 OUTPUT CURRENT. 2. DAC08 IS A DIGITALLY CONTROLLED CURRENT GENERATOR. THE MAXIMUM FULL-SCALE CURRENT MUST BE LESS THAN 0.5mA. Figure 22. Programmable Low Frequency Ramp Generator REV. A -17- R > 20k REF-01 PKD01 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C00481-0-2/01 (rev. A) 14-Lead Plastic DIP (PDIP) (N-14) 0.795 (20.19) 0.725 (18.42) 14 8 1 0.280 (7.11) 0.240 (6.10) 7 PIN 1 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.210 (5.33) MAX 0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) 0.022 (0.558) 0.070 (1.77) SEATING PLANE 0.014 (0.356) 0.045 (1.15) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 14-Lead Cerdip (Q-14) 0.005 (0.13) MIN 0.098 (2.49) MAX 14 8 PIN 1 1 7 0.100 (2.54) BSC 0.785 (19.94) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING 0.070 (1.78) 15 PLANE 0 0.030 (0.76) 0.015 (0.38) 0.008 (0.20) PRINTED IN U.S.A. 0.200 (5.08) MAX 0.310 (7.87) 0.220 (5.59) -18- REV. A