REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
PKD01
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
Monolithic Peak Detector
with Reset-and-Hold Mode
FUNCTIONAL BLOCK DIAGRAM
–
+
PKD01
OUTPUT
BUFFER
OUTPUT
LOGIC
GND
C
H
DET
–IN
+IN
–IN
+IN
RST
–IN+IN OUTPUT V+ V–
–
+
–
+
–
+
CMP
A
B
C
V–
D
1
GATED
"g
m
"
AMP
GATED
"g
m
"
AMP
RST
0
0
1
1
DET
0
1
1
0
OPERATIONAL MODE
PEAK DETECT
PEAK HOLD
RESET
INDETERMINATE
SWITCHES SHOWN FOR:
RST = “0,” DET = “0”
FEATURES
Monolithic Design for Reliability and Low Cost
High Slew Rate: 0.5 V/␮s
Low Droop Rate
TA = 25ⴗC: 0.1 mV/ms
TA = 125ⴗC: 10 mV/ms
Low Zero-Scale Error: 4 mV
Digitally Selected Hold and Reset Modes
Reset to Positive or Negative Voltage Levels
Logic Signals TTL and CMOS Compatible
Uncommitted Comparator On-Chip
Available in Die Form
GENERAL DESCRIPTION
The PKD01 tracks an analog input signal until a maximum
amplitude is reached. The maximum value is then retained as a
peak voltage on a hold capacitor. Being a monolithic circuit, the
PKD01 offers significant performance and package density
advantages over hybrid modules and discrete designs without
sacrificing system versatility. The matching characteristics
attained in a monolithic circuit provide inherent advantages
when charge injection and droop rate error reduction are
primary goals.
Innovative design techniques maximize the advantages of mono-
lithic technology. Transconductance (g
m
) amplifiers were chosen
over conventional voltage amplifier circuit building blocks. The
g
m
amplifiers simplify internal frequency compensation, minimize
acquisition time and maximize circuit accuracy. Their outputs
are easily switched by low glitch current steering circuits. The
steered outputs are clamped to reduce charge injection errors
upon entering the hold mode or exiting the reset mode. The inher-
ently low zero-scale error is further reduced by active Zener-Zap
trimming to optimize overall accuracy.
The output buffer amplifier features an FET input stage to
reduce droop rate error during lengthy peak hold periods. A bias
current cancellation circuit minimizes droop error at high ambi-
ent temperatures.
Through the DET control pin, new peaks may either be detected
or ignored. Detected peaks are presented as positive output
levels. Positive or negative peaks may be detected without
additional active circuits, since Amplifier A can operate as an
inverting or noninverting gain stage.
An uncommitted comparator provides many application options.
Status indication and logic shaping/shifting are typical examples.
REV. A
–2–
PKD01–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
PKD01A/E PKD01F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
g
m
AMPLIFIERS A, B
Zero-Scale Error V
ZS
24 37mV
Input Offset Voltage V
OS
23 36mV
Input Bias Current I
B
80 150 80 250 nA
Input Offset Current I
OS
20 40 20 75 nA
Voltage Gain A
V
R
L
= 10 kΩ, V
O
= ±10 V 18 25 10 25 V/mV
Open-Loop Bandwidth BW A
V
= 1 0.4 0.4 MHz
Common-Mode Rejection Ratio CMRR –10 V ≤ V
CM
≤ +10 V 8090 7490 dB
Power Supply Rejection Ratio PSRR ±9 V ≤ V
S
≤ ±18 V 8696 7696 dB
Input Voltage Range
1
V
CM
±10 ±11 ±10 ±11 V
Slew Rate SR 0.5 0.5 V/µs
Feedthrough Error
1
∆V
IN
= 20 V, DET = 1, RST = 0 66 80 66 80 dB
Acquisition Time to
0.1% Accuracy
1
t
AQ
20 V Step, A
VCL
= +1 41 70 41 70 µs
Acquisition Time to t
AQ
20 V Step, A
VCL
= +1 45 45 µs
0.01% Accuracy
1
COMPARATOR
Input Offset Voltage V
OS
0.5 1.5 1 3 mV
Input Bias Current I
B
700 1000 700 1000 nA
Input Offset Current I
OS
75 300 75 300 nA
Voltage Gain A
V
2kΩ Pull-Up Resistor to 5 V 5 7.5 3.5 7.5 V/mV
Common-Mode Rejection Ratio CMRR –10 V ≤ V
CM
≤ +10 V 82 106 82 106 dB
Power Supply Rejection Ratio PSRR ±9 V ≤ V
S
≤ ±18 V 7690 7690 dB
Input Voltage Range
1
V
CM
±11.5 ±12.5 ±11.5 ±12.5 V
Low Output Voltage V
OL
I
SINK
≤5 mA, Logic GND = 0 V –0.2 +0.15 +0.4 –0.2 +0.15 +0.4 V
“OFF” Output Leakage Current I
L
V
OUT
= 5 V 2580 2580µA
Output Short-Circuit Current I
SC
V
OUT
= 5 V 7 12 45 7 12 45 mA
Response Time
2
t
S
5 mV Overdrive, 2 kΩ Pull-Up 150 150 ns
Resistor to 5 V
DIGITAL INPUTS – RST, DET
2
Logic “1” Input Voltage V
H
22V
Logic “0” Input Voltage V
L
0.8 0.8 V
Logic “1” Input Current I
INH
V
H
= 3.5 V 0.02 1 0.02 1 µA
Logic “0” Input Current I
INL
V
L
= 0.4 V 1.6 10 1.6 10 µA
MISCELLANEOUS
Droop Rate
3
V
DR
T
J
= 25°C 0.01 0.07 0.01 0.1 mV/ms
T
A
= 25°C 0.02 0.15 0.03 0.20 mV/ms
Output Voltage Swing: V
OP
DET = 1
Amplifier C R
L
= 2.5 kΩ±11.5 ±12.5 ±11 ±12 V
Short-Circuit Current:
Amplifier C I
SC
7 15 40 7 15 40 mA
Switch Aperture Time t
AP
75 75 ns
Switch Switching Time ts 50 50 ns
Slew Rate: Amplifier C SR R
L
= 2.5 kΩ2.5 2.5 V/µs
Power Supply Current I
SY
No Load 57 69mA
NOTES
1
Guaranteed by design.
2
DET = 1, RST = 0.
3
Due to limited production test times, the droop current corresponds to junction temperature (T
J
). The droop current vs. time (after power-on) curve clarified this point. Since
most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T
A
) also. The warmed-up (T
A
) droop current specification is correlated
to the junction temperature (T
J
) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature. Ambient (T
A
) temperature specifications
are not subject to production testing.
Specifications subject to change without notice.
(@ VS = ⴞ15 V, CH = 1000 pF, TA = 25ⴗC, unless otherwise noted.)
REV. A –3–
PKD01
ELECTRICAL CHARACTERISTICS
PKD01A/E PKD01F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
“g
m
” AMPLIFIERS A, B
Zero-Scale Error V
ZS
47 612 mV
Input Offset Voltage V
OS
36 510 mV
Average Input Offset Drift
1
TCV
OS
–9 –24 –9 –24 µV/°C
Input Bias Current I
B
160 250 160 500 nA
Input Offset Current I
OS
30 100 30 150 nA
Voltage Gain A
V
R
L
= 10 kΩ, V
O
= ±10 V 7.5 9 5 9 V/mV
Common-Mode Rejection Ratio CMRR –10 V ≤ V
CM
≤ +10 V 74 82 72 80 dB
Power Supply Rejection Ratio PSRR ±9 V ≤ V
S
≤ ±18 V 80 90 70 90 dB
Input Voltage Range
1
V
CM
±10 ±11 ±10 ±11 V
Slew Rate SR 0.4 0.4 V/µs
Acquisition Time to 0.1% Accuracy
1
t
AQ
20 V Step, A
VCL
= +1 60 60 µs
COMPARATOR
Input Offset Voltage V
OS
2 2.5 2 5 mV
Average Input Offset Drift
1
TCV
OS
–4 –6 –4 –6 µV/°C
Input Bias Current I
B
1000 2000 1100 2000 nA
Input Offset Current I
OS
100 600 100 600 nA
Voltage Gain A
V
2 kΩ Pull-Up Resistor to 5 V 4 6.5 2.5 6.5 V/mV
Common-Mode Rejection Ratio CMRR –10 V ≤ V
CM
≤ +10 V 80 100 80 92 dB
Power Supply Rejection Ratio PSRR ±9 V ≤ V
S
≤ ±18 V 72 82 72 86 dB
Input Voltage Range
1
V
CM
±11 ±11 V
Low Output Voltage V
OL
I
SINK
≤ 5 mA, Logic GND = 0 V –0.2 +0.15 +0.4 –0.2 +0.15 +0.4 V
OFF Output Leakage Current I
L
V
OUT
= 5 V 25 100 100 180 µA
Output Short-Circuit Current I
SC
V
OUT
= 5 V 6 10 45 6 10 45 mA
Response Time t
S
5 mV Overdrive, 2 kΩ Pull-Up
Resistor to 5 V 200 200 ns
DIGITAL INPUTS – RST, DET
2
Logic “1” Input Voltage V
H
22 V
Logic “0” Input Voltage V
L
0.8 0.8 V
Logic “1” Input Current I
INH
V
H
= 3.5 V 0.02 1 0.02 1 µA
Logic “0” Input Current I
INL
V
L
= 0.4 V 2.5 15 2.5 15 µA
MISCELLANEOUS
Droop Rate
3
V
DR
T
J
= Max Operating Temp. 1.2 10 3 15 mV/ms
T
A
= Max Operating Temp.
DET = 1 2.4 20 6 20 mV/ms
Output Voltage Swing
Amplifier C V
OP
R
L
= 2.5 kΩ±11 ±12 ±10.5 ±12 V
Short-Circuit Current
Amplifier C I
SC
6 12406 1240 mA
Switch Aperture Time t
AP
75 75 ns
Slew Rate: Amplifier C SR R
L
= 2.5 kΩ22V/µs
Power Supply Current I
SY
No Load 5.5 8 6.5 10 mA
NOTES
1
Guaranteed by design.
2
DET = 1, RST = 0.
3
Due to limited production test times, the droop current corresponds to junction temperature (T
J
). The droop current vs. time (after power-on) curve clarifies this
point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T
A
) also. The warmed-up (T
A
) droop current
specification is correlated to the junction temperature (T
J
) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature.
Ambient (T
A
) temperature specifications are not subject to production testing.
Specifications subject to change without notice.
(@ VS = ⴞ15 V, CH = 1000 pF, –55ⴗC ≤ TA ≤ +125ⴗC for PKD01AY, –25ⴗC ≤ TA ≤ +85ⴗC for
PKD01EY, PKD01FY and 0ⴗC ≤ TA ≤ +70ⴗC for PKD01EP, PKD01FP, unless otherwise noted.)
REV. A
PKD01
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the PKD01 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1, 2
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage . . . . . . . . . . . . . . . . . . . Equal to Supply Voltage
Logic and Logic Ground
Voltage . . . . . . . . . . . . . . . . . . . . . . Equal to Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Amplifier A or B Differential Input Voltage . . . . . . . . . . ±24 V
Comparator Differential Input Voltage . . . . . . . . . . . . . ±24 V
Comparator Output Voltage
. . . . . . . . . . . . . . . . . . . . . . Equal to Positive Supply Voltage
Hold Capacitor Short-Circuit Duration . . . . . . . . . . Indefinite
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C
Storage Temperature Range
PKD01AY, PKD01EY, PKD01FY . . . . . –65°C to +150°C
PKD01EP, PKD01FP . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range
PKD01AY . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
PKD01EY, PKD01FY . . . . . . . . . . . . . . . . –25°C to +85°C
PKD01EP, PKD01FP . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
Package Type ␪
JA
*␪
JC
Unit
14-Lead Hermetic DIP (Y) 99 12 °C/W
14-Lead Plastic DIP (P) 76 33 °C/W
*θ
JA
is specified for worst-case mounting conditions, i.e., θ
JA
is specified for device
in socket for cerdip and PDIP packages.
ORDERING GUIDE
1
Temperature Package Package
Model
2
Range Description Option
PKD01AY –55°C to +85°C Cerdip Q-14
PKD01EY –25°C to +85°C Cerdip Q-14
PKD01FY –25°C to +85°C Cerdip Q-14
PKD01EP 0°C to 70°C Plastic DIP N-14
PKD01FP 0°C to 70°C Plastic DIP N-14
NOTES
1
Burn-in is available on commercial and industrial temperature range parts in
cerdip, plastic DIP, and TO-can packages.
2
For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet.
PIN CONFIGURATION
DET
LOGIC GND
COMP OUT
–IN C
+IN C
–IN B
+IN B
RST
V+
OUTPUT
C
H
–IN A
+IN A
V–
PKD01
DICE CHARACTERISTICS
REV. A
PKD01
–5–
WAFER TEST LIMITS
PKD01N
Parameter Symbol Conditions Limit Unit
“g
m
” AMPLIFIERS A, B
Zero-Scale Error V
ZS
7mV max
Input Offset Voltage V
OS
6mV max
Input Bias Current I
B
250 nA max
Input Offset Current I
OS
75 nA max
Voltage Gain A
V
R
L
= 10 kΩ, V
O
= ±10 V 10 V/mV min
Common-Mode Rejection Ratio CMRR –10 V ≤ V
CM
≤ +10 V 74 dB min
Power Supply Rejection Ratio PSRR ±9 V ≤ V
S
≤ ±18 V 76 dB min
Input Voltage Range
1
V
CM
±11.5 V min
Feedthrough Error ∆V
IN
= 20 V, DET = 1, RST = 0 66 dB min
COMPARATOR
Input Offset Voltage V
OS
3mV max
Input Bias Current I
B
1000 nA max
Input Offset Current I
OS
300 nA max
Voltage Gain
1
A
V
2 kΩ Pull-Up Resistor to 5 V 3.5 V/mV min
Common-Mode Rejection Ratio CMRR –10 V ≤ V
CM
≤ +10 V 82 dB min
Power Supply Rejection Ratio PSRR ±9 V ≤ V
S
≤ ±18 V 76 dB min
Input Voltage Range
1
V
CM
±11.5 V min
Low Output Voltage V
OL
I
SINK
≤5 mA, Logic GND = 5 V 0.4 V max
–0.2 V min
“OFF” Output Leakage Current I
L
V
OUT
= 5 V 80 µA max
Output Short-Circuit Current I
SC
V
OUT
= 5 V 45 mA min
7 mA min
DIGITAL INPUTS–RST, DET
2
Logic “1” Input Voltage V
H
2V min
Logic “0” Input Voltage V
L
0.8 V max
Logic “1” Input Current I
INH
V
H
= 3.5 V 1 µA max
Logic “0” Input Current I
INL
V
L
= 0.4 V 10 µA max
MISCELLANEOUS
Droop Rate
3
V
DR
T
J
= 25°C, 0.1 mV/ms max
T
A
= 25°C 0.20 mV/ms max
Output Voltage Swing Amplifier C V
OP
R
L
= 2.5 kΩ±11 V min
Short-Circuit Current Amplifier C I
SC
40 mA max
7 mA min
Power Supply Current I
SY
No Load 9 mA max
g
m
AMPLIFIERS A, B
Slew Rate SR 0.5 V/µs
Acquisition Time
1
t
A
0.1% Accuracy, 20 V Step, A
VCL
= 1 41 µs
t
A
0.01% Accuracy, 20 V Step, A
VCL
= 1 45 µs
COMPARATOR
Response Time 5 mV Overdrive, 2 kΩ Pull-Up Resistor to 5 V 150 ns
MISCELLANEOUS
Switch Aperture Time t
AP
75 ns
Switching Time t
S
50 ns
Buffer Slew Rate SR R
L
= 2.5 kΩ2.5 V/µs
NOTES
1
Guaranteed by design.
2
DET = 1, RST = 0.
3
Due to limited production test times, the droop current corresponds to junction temperature (T
J
). The droop current vs. time (after power-on) curve clarifies this
point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T
A
) also. The warmed-up (T
A
) droop current
specification is correlated to the junction temperature (T
J
) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature.
Ambient (T
A
) temperature specifications are not subject to production testing.
(@ VS = ⴞ15 V, CH = 1000 pF, TA = 25ⴗC, unless otherwise noted.)
REV. A
PKD01
–6–
–Typical Performance Characteristics
18
14
–18
46 18
91215
–2
–6
–10
–14
10
2
6
INPUT + RANGE = V+
–55ⴗC T
A
+125ⴗC
V– SUPPLY
–55ⴗC
+25ⴗC
+125ⴗC
INPUT RANGE OF AMPLIFIER – V
SUPPLY VOLTAGE +V AND –V –V
TPC 1. A and B Input Range vs.
Supply Voltage
FREQUENCY – Hz
INPUT NOISE VOLTAGE – nV/ Hz
1000
100
0110 1k100
10
R
S
= 10k⍀
R
S
= 0
TPC 4. Input Spot Noise vs.
Frequency
–1.0
1.0
+125ⴗC
+25ⴗC
–55ⴗC
0.5
–0.5
V
IN
– V
ERROR – mV
0
–10 –50 510
POLARITY OF
ERROR MAY BE
POSITIVE OR
NEGATIVE
C
H
= 1000pF
T
A
= 25ⴗC
TPC 7. Amplifier A Charge Injec-
tion Error vs. Input Voltage and
Temperature
TEMPERATURE – ⴗC
6
–6
–75 –50 125–25 0 25 50 75 100
4
2
0
–2
–4
OFFSET VOLTAGE – mV
TPC 2. A and B Amplifiers Offset
Voltage vs. Temperature
BANDWIDTH – kHz
RMS NOISE – ␮V
100
10
0
0.1 1 10010
1
1000
V
S
= 15V
T
A
= 25ⴗC
A
V
= +1
TPC 5. Wideband Noise vs.
Bandwidth
SUPPLY VOLTAGE +V AND –V – V
OUTPUT SWING – V
18
14
–18
46 18
91215
–2
–6
–10
–14
10
2
6
V– SUPPLY
–55ⴗC
+25ⴗC
+125ⴗC
V+ SUPPLY
–55ⴗC
+25ⴗC
+125ⴗC
R
L
= 10k⍀
TPC 8. Output Voltage Swing vs.
Supply Voltage (Dual Supply
Operation)
TEMPERATURE – ⴗC
A,B I
OS
– nA
40
0
–75 –50 150
–25 0 25 75 100 12550
35
20
15
10
5
30
25
TPC 3. A, B I
OS
vs. Temperature
–1.0
1.0
+125ⴗC
+25ⴗC
–55ⴗC
0.5
–0.5
V
IN
– V
ERROR – mV
0
–10 –50 510
TPC 6. Amplifier B Charge Injec-
tion Error vs. Input Voltage and
Temperature
LOAD RESISTOR TO GROUND – k⍀
OUTPUT SWING – Volts
15
12.5
–15
1.0 10.0
0.1
2.5
0
–2.5
–5.0
10.0
5.0
7.5
–12.5
–10.0
–7.5
+25ⴗC
–55ⴗC
+125ⴗC
–55ⴗC
+25ⴗC
+125ⴗC
TPC 9. Output Voltage vs. Load
Resistance
REV. A
PKD01
–7–
FREQUENCY – Hz
PK OF SINEWAVE – V
12
10
0
100 1k 1M
10k 100k
8
6
4
2
2mV ERROR
200mV ERROR
20mV ERROR
TPC 10. Output Error vs.
Frequency and Input Voltage
10
0%
100
90
T
A
= 25ⴗC
0V
TIME – 20␮s/DIV
OUTPUT VOLTAGE – 5V/DIV
TPC 13. Large-Signal Inverting
Response
TA = 25ⴗC
0V
TIME – 20␮s/DIV
OUTPUT VOLTAGE – 5mV/DIV
10
0%
100
90
TA = 25ⴗC
TPC 16. Settling Time for +10 V to
0 V Step Input
10
0%
100
90
2
␮
s10mV
C
H
= 1000pF
PEAK
OUTPUT
TPC 11. Settling Response
10
0%
100
90
T
A
= 25ⴗC
0V
TIME – 20␮s/DIV
OUTPUT VOLTAGE – 5V/DIV
TPC 14. Large-Signal Noninverting
Response
FREQUENCY – Hz
GAIN – dB
90
60
–30 1 10 10M
100 1k 10k 100k 1M
30
0
PHASE LAG – Degrees
90
0
45
180
135
TA = 25ⴗC
RL = 10k⍀
CL = 30pF
CH = 1000pF
GAIN
PHASE
CH = 1000pF CH = 1000pF
TPC 17. Small-Signal Open-Loop
Gain/Phase vs. Frequency
10
0%
100
90
2
␮
s
C
H
= 1000pF
10mV
DETECTED
PEAK
3kHz
SINEWAVE
INPUT
10mV
10V
TPC 12. Settling Response
10
0%
100
90
TIME – 20␮s/DIV
OUTPUT VOLTAGE – 5mV/DIV
T
A
= 25ⴗC
0V
TPC 15. Settling Time for –10 V to
0 V Step Input
FREQUENCY – Hz
CHANNEL-TO-CHANNEL ISOLATION – dB
120
01 10 10M
100 1k 10k 100k 1M
100
80
60
40
20
TA = 25ⴗC
AMPLIFIER A(B) OFF, INPUT = 20V p-p
AMPLIFIER B(B) ON, INPUT = 0V
TEST CONDITION:
CH = 1000pF
AMPLIFIER A AND B CONNECTED IN +1 GAIN
TPC 18. Channel-to-Channel
Isolation vs. Frequency
REV. A
PKD01
–8–
TPC 26. Comparator Output
Response Time (2 k
Ω
Pull-Up
Resistor, T
A
= 25
°
C)
TPC 27. Comparator Output
Response Time (2 k
Ω
Pull-Up
Resistor, T
A
= 25
°
C)
TPC 24. Acquisition of Step Input
10
0%
100
90
50
␮
s
5V
10V
10V PEAK
DETECT
PEAK
OUTPUT
RESET
INPUT
RESET
+10V
0V
–10V
+10V
0V
–10V
TPC 21. Acquisition Time vs.
External Hold Capacitor and
Acquisition Step
TPC 23. Droop Rate vs. Temperature
TPC 20. Droop Rate vs. Time after
Power On
TPC 25. Acquisition of Sine
Wave Peak
10
0%
100
90
50
␮
s
5V
DETECTED
PEAK
RESET
+10V
0V
–10V
5V
CH = 1000pF
3kHz
SINEWAVE
INPUT
TPC 22. Acquisition Time vs. Input
Voltage Step Size
TPC 19. Off Isolation vs. Frequency
FREQUENCY – Hz
OFF ISOLATION – dB
100
80
01 10 10M
100 1k 10k 100k 1M
60
40
20
A, A
V
= +1
B, A
V
= ⴞ1
A, A
V
= –1
1V 5mV 50ns
COMPARATOR OUTPUT
5
+5
0
–5
TIME – 50ns/DIV
4
3
2
1
0
OUTPUT VOLTAGE – V
INPUT VOLTAGE – mV
10
0%
100
90
50ns
1V 5mV
COMPARATOR OUTPUT
1V 5mV 50ns
COMPARATOR OUTPUT
5
+5
0
–5
TIME – 50ns/DIV
4
3
2
1
0
OUTPUT VOLTAGE – V
INPUT VOLTAGE – mV
10
0%
100
90
50ns
1V 5mV
COMPARATOR OUTPUT
TEMPERATURE – ⴗC
DROOP RATE (mV/sec), CH = 1000pF
10000
1000
1
–100 –50 500
100
100 500
AMBIENT
TEMPERATURE
JUNCTION
TEMPERATURE
10
INPUT STEP – V
SETTLING TIME – ␮s
50
20
40
30
51015200
10
0
T
A
= 25ⴗC
C
H
= 1000pF
TO 2mV
TO 20mV
TO 200mV
HOLD CAPACITANCE – pF
ACQUISITION TIME TO 0.1% ACCURACY – ␮s
500
200
400
300
2000 4000 6000 8000 100000
100
80
60
40
20
0
20V STEP TO 20mV (0.1%)
10V STEP TO 10mV (0.1%)
5V STEP TO 5mV (0.1%)
1V STEP TO 1mV (0.1%)
TIME AFTER POWER APPLIED – Minutes
DROOP RATE – mV/ms
3
01
2
1
TA = 125ⴗC
CH = 1000pF
23456789100
REV. A
PKD01
–9–
SUPPLY VOLTAGE +V AND –V – V
INPUT LOGIC RANGE – V
18
10
–18 46 9121518
2
–10
14
6
–2
–6
–14
+VIN V+ FOR
–55ⴗC TA +125ⴗC
–55ⴗC
+125ⴗC
+25ⴗC
V–
TPC 28. Input Logic Range vs.
Supply Voltage
SUPPLY +V AND –V – V
SUPPLY CURRENT – mA
6
5
31215180
496
–55ⴗC+25ⴗC
+125ⴗC
TPC 31. Supply Current vs. Supply
Voltage
TEMPERATURE – ⴗC
OFFSET VOLTAGE – mV
3
–3
–75 –50 125–25 0 25 50 75 100
2
1
0
–1
–2
TPC 34. Comparator Offset Voltage
vs. Temperature
SUPPLY VOLTAGE +V AND –V – V
INPUT RANGE OF LOGIC GROUND – V
18
–14
46 9 12 1815
14
2
0
–2
–6
10
6
–10
–18
V–
–55ⴗC
+125ⴗC
ACCEPTABLE GROUND PIN
POTENTIAL IS BETWEEN
SLIDE LINES.
+25ⴗC
+25ⴗC
+125ⴗC
V+
TPC 29. Input Range of Logic
Ground vs. Supply Voltage
FREQUENCY – Hz
REJECTION RATIO – dB
100
80
010 100 1M
1k 10k 100k
60
40
20
T
A
= 25ⴗC
V
IN
= 0V
C
H
= 1000pF
CHANNEL A = 1
CHANNEL B = 0
POSITIVE SUPPLY
(+15V +1V SIN ␻T)
NEGATIVE SUPPLY
(–15V +1V SIN ␻)
TPC 32. Hold Mode Power Supply
Rejection vs. Frequency
TEMPERATURE – ⴗC
110
50
–75 –50 150
–25 0 25 75 100 12550
100
80
70
60
90
COMPARATOR I
OS
– nA
TPC 35. Comparator I
OS
vs.
Temperature
LOGIC INPUT VOLTAGE – V
LOGIC CURRENT – ␮A
1
0
–3–2–15
01234
–1
–2
LOGIC GROUND = 0V
LOGIC 0
LOGIC 1
–55ⴗC
+125ⴗC
+25ⴗC
TPC 30. Logic Input Current vs.
Logic Input Voltage
INPUT VOLTAGE – V
INPUT BIAS CURRENT (EITHER INPUT) – ␮A
3
2
–1
–15 –10 15
–50 510
1
0
V
S
= ⴞ15V
T
A
= 25ⴗC
OTHER
INPUT
AT +10V
OTHER
INPUT
AT –10V
OTHER
INPUT
AT 0V
INPUT CURRENT
MUST BE LIMITED
TO LESS THAN 1mA
TPC 33. Comparator Input Bias
Current vs. Differential Input Voltage
TEMPERATURE – ⴗC
COMPARATOR I
B
– nA
1200
200
–75 –50 150
–25 0 25 75 100 12550
1000
800
600
400
TPC 36. Comparator I
B
vs.
Temperature
REV. A
PKD01
–10–
SUPPLY VOLTAGE +V AND –V – V
OUTPUT RANGE OF COMPARATOR – V
18
10
–18 46 9121518
2
–10
14
6
–2
–6
–14
V–
–55ⴗC
+25ⴗC
+125ⴗC
V+
+25ⴗC
+125ⴗC
TPC 37. Output Swing of Com-
parator vs. Supply Voltage
I
O
– OUTPUT SINK CURRENT – mA
0.8
014
42 6 10 128
0.6
0.2
0
–0.2
0.4
1.0
V
O
– VOLTAGE OUTPUT – V
DC
–55ⴗC
+125ⴗC
+25ⴗC
TPC 40. Comparator Output
Voltage vs. Output Current and
Temperature
TIME – ns
INPUT VOLTAGE – mV
5
–50 300
500 100 200 250150
4
2
1
0
3
+5
0
–5
OUTPUT VOLTAGE – V
PULL-UP
RESISTOR = 2k⍀
TA = +25ⴗC
TA = –55ⴗC
TA = +125ⴗC
TPC 38. Comparator Response
Time vs. Temperature
TIME – ns
INPUT VOLTAGE – mV
5
–50 300
500 100 200 250150
4
2
1
0
3
+5
0
–5
OUTPUT VOLTAGE – V
PULL-UP
RESISTOR = 2k⍀
T
A
= –55ⴗCT
A
= +125ⴗC
T
A
= +25ⴗC
TPC 41. Comparator Response
Time vs. Temperature
INPUT VOLTAGE – mV
5
–1.5 2.0
–0.5–1.0 0 1.0 1.50.5
4
2
1
0
3
6
OUTPUT VOLTAGE – V
V
S
= ⴞ15V
T
A
= 25ⴗC
INVERTING INPUT = V
IN
NONINVERTING INPUT = 0V
R
L
= 2k⍀
TO 5V
R
L
= 1k⍀
TO 5V
TPC 39. Comparator Transfer
Characteristic
REV. A
PKD01
–11–
THEORY OF OPERATION
The typical peak detector uses voltage amplifiers and a diode or
an emitter follower to charge the hold capacitor, C
H
, indirect-
ionally (see Figure 1). The output impedance of A plus D
1
’s
dynamic impedance, r
d
, make up the resistance which deter-
mines the feedback loop pole. The dynamic impedance is
rkT
qI
d
d
=
, where I
d
is the capacitor charging current.
The pole moves toward the origin of the S plane as I
d
goes to
zero. The pole movement in itself will not significantly lengthen
the acquisition time since the pole is enclosed in the system
feedback loop.
C
H
V
OUT
INPUT
V
IN
V
H
V
OUT
(A) = V
IN
(A) ⴛ A
V
(A)
A
+C
D
1
R
OUT
r
d
OUTPUT
Figure 1. Conventional Voltage Amplifier Peak Detector
When the moving pole is considered with the typical frequency
compensation of voltage amplifiers however, there is a loop stability
problem. The necessary compensation can increase the required
acquisition time. ADI’s approach replaces the input voltage ampli-
fier with a transconductance amplifier (see Figure 2).
The PKD01 transfer function can be reduced to:
V
VsC
ggR
sC
g
OUT
IN H
mm
OUT
H
m
=
++
≈
+
1
11
1
1
where: g
m
⬇ 1 µA/mV, R
OUT
⬇ 20 MΩ.
The diode in series with A’s output (see Figure 2) has no effect
because it is a resistance in series with a current source. In
addition to simplifying the system compensation, the input
transconductance amplifier output current is switched by cur-
rent steering. The steered output is clamped to reduce and match
any charge injection.
CH
C
ROUT
IOUT D1
INPUT
VIN
VH
IOUT (A) = VIN (A) ⴛ gm (A)
A
VOUT
OUTPUT
Figure 2. Transconductance Amplifier Peak Detector
Figure 3 shows a simplified schematic of the reset g
m
amplifier,
B. In the track mode, Q
1
and Q
4
are ON and Q
2
and Q
3
are
OFF. A current of 2I passes through D
1
, I is summed at B and
passes through Q
1
, and is summed with g
m
V
IN
. The current sink
can absorb only 3I, thus the current passing through D
2
can
only be: 2K – g
m
V
IN
. The net current into the hold capacitor
node then, is g
m
V
IN
[I
H
= 2I – (2I – g
m
V
IN
)]. In the hold mode,
Q
2
and Q
3
are ON while Q
1
and Q
4
are OFF. The net current
into the top of D
1
is –I until D
3
turns ON. With Q
1
OFF, the
bottom of D
2
is pulled up with a current I until D
4
turns ON,
thus, D
1
and D
2
are reverse biased by <0.6 V, and charge injec-
tion is independent of input level.
The monolithic layout results in points A and B having equal
nodal capacitance. In addition, matched diodes D
1
and D
2
have
equal diffusion capacitance. When the transconductance ampli-
fier outputs are switched open, points A and B are ramped
equally, but in opposite phase. Diode clamps D
3
and D
4
cause
the swings to have equal amplitudes. The net charge injection
(voltage change) at node C is therefore zero.
V+
gm V IN
VIN
3I 3I V–
I2I D3
D1
D4
CH
C
Q1Q2Q3Q4A
B
LOGIC
CONTROL
A > B = PEAK DETECT
A < B = PEAK HOLD
A
D2
C
B
6
Figure 3. Transconductance Amplifier with Low Glitch
Current Switch
The peak transconductance amplifier, A is shown in Figure 4.
Unidirectional hold capacitor charging requires diode D
1
to be
connected in series with the output. Upon entering the peak
hold mode D
1
is reverse-biased. The voltage clamp limits charge
injection to approximately 1 pC and the hold step to 0.6 mV.
Minimizing acquisition time dictates a small C
H
capacitance. A
1000 pF value was selected. Droop rate was also minimized by
providing the output buffer with an FET input stage. A cur-
rent cancellation circuit further reduces droop current and
minimizes the gate current’s tendency to double for every 10°
temperature change.
gm V IN
VIN
3I 3I V–
V+
I2I D3
D1
D2D4
CH
C
Q1Q2Q3Q4A
B
LOGIC
CONTROL
A > B = PEAK DETECT
A < B = PEAK HOLD
rd
6
Figure 4. Peak Detecting Transconductance Amplifier
with Switched Output
REV. A
PKD01
–12–
APPLICATIONS INFORMATION
Optional Offset Voltage Adjustment
Offset voltage is the primary zero scale error component since a
variable voltage clamp limits voltage excursions at D
1
’s anode
and reduces charge injection. The PKD01 circuit gain and opera-
tional mode (positive or negative peak detection) determine the
applicable null circuit. Figures 5 through 8 are suggested circuits.
Each circuit also corrects amplifier C offset voltage error.
A. Nulling Gated Output g
m
Amplifier A.Diode D
1
must
be conducting to close the feedback circuit during amplifier A
V
OS
adjustment. Resistor network R
A
– R
C
cause D
1
to conduct
slightly. With DET = 0 and V
IN
= 0 V, monitor the PKD01
output. Adjust the null potentiometer until V
OUT
= 0 V. After
adjustment, disconnect R
C
from C
H
.
B. Nulling Gated g
m
Amplifier B. Set Amplifier B signal
input to V
IN
= 0 V and monitor the PKD01 output. Set DET =
1, RST = 1 and adjust the null potentiometer for V
OUT
= 0 V.
The circuit gain—inverting or noninverting—will determine which
null circuit illustrated in Figures 5 through 8 is applicable.
PKD01
D
1
C
H
1000pF
C
A
B
V
OUT
V
S
–
V
S
+
0.1␮FDET
R1
1k⍀
RST
–15V
R
C
2M⍀
R
A
200k⍀
R
B
1k⍀
NOTES:
1. NULL RANGE = ⴞV
S
(
)
2. DISCONNECT R
C
FROM C
H
AFTER AMPLIFIER A ADJUSTMENT.
3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED.
R
A
, R
B
AND R
C
NOT NECESSARY FOR AMPLIFIER B ADJUSTMENT.
V
IN
+
R1
1k⍀
R2
2M⍀
100k⍀
R1
R2
Figure 5. V
OS
Null Circuit for Unity Gain Positive Peak
Detector
PKD01
D
1
CH
1000pF
C
A
B
VOUT
R2 = R3 + R4
VS–
VS+
25k⍀
R4
20⍀
0.1␮F
DET
R1
RST
–15V
RC
2M⍀
RA
200k⍀
RB
1k⍀
NOTES:
1. NULL RANGE = ⴞVS ( )( )
2. DISCONNECT RC FROM CH AFTER AMPLIFIER A ADJUSTMENT.
3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED.
R1
VIN–
VIN+
R5
20k⍀
R3
R5
R4
R1
R1 + R3
Figure 6. V
OS
Null Circuit for Differential Peak Detector
PKD01
D
1
C
H
1000pF
C
A
B
V
OUT
R2
V
IN
R1
0.1␮F
V
S
–
V
S
+
25k⍀
DET
R3
20k⍀
RST
–15V
R
C
2M⍀
R
A
200k⍀
R
B
1k⍀
NOTES:
1. NULL RANGE = ⴞV
S
(
)
2. DISCONNECT R
C
FROM C
H
AFTER AMPLIFIER A ADJUSTMENT.
3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED.
R4
R3
R4
20⍀
Figure 7. V
OS
Null Circuit for Negative Peak Detector
PKD01
D
1
C
H
1000pF
C
A
B
V
OUT
R2
V
IN
R1
R5
20k⍀
R3
20⍀
0.1␮F
V
S
–
V
S
+
25k⍀DET
R4 = R2 R1
R1 + R2
R4
RST
–15V
R
C
2M⍀
R
A
200k⍀
R
B
1k⍀
GAIN = 1 + R2
R1 + R3
NOTES:
1. NULL RANGE = ⴞV
S
(
)
2. DISCONNECT R
C
FROM C
H
AFTER AMPLIFIER A ADJUSTMENT.
3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED.
R3
R5
Figure 8. V
OS
Null Circuit for Positive Peak Detector with
Gain
REV. A
PKD01
–13–
PEAK HOLD CAPACITOR RECOMMENDATIONS
The hold capacitor (C
H
) serves as the peak memory element
and compensating capacitor. Stable operation requires a mini-
mum value of 1000 pF. Larger capacitors may be used to lower
droop rate errors, but acquisition time will increase.
Zero scale error is internally trimmed for C
H
= 1000 pF. Other
C
H
values will cause a zero scale shift which can be approxi-
mated with the following equation.
∆VmV pC
CnF
mV
ZS
H
()
=×
()
()
−
110 06
3
.
The peak hold capacitor should have very high insulation resis-
tance and low dielectric absorption. For temperatures below
85°C, a polystyrene capacitor is recommended, while a Teflon
capacitor is recommended for high temperature environments.
CAPACITOR GUARDING AND GROUND LAYOUT
Ground planes are recommended to minimize ground path
resistance. Separate analog and digital grounds should be used.
The two ground systems are tied together only at the common
system ground. This avoids digital currents returning to the
system ground through the analog ground path.
PKD01
C
H
REPEAT ON
“COMPONENT SIDE”
OF PC BOARD IF POSSIBLE
BOTTOM VIEW
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Figure 9. C
H
Terminal (Pin 4) Guarding. See Text.
The C
H
terminal (Pin 4) is a high impedance point. To minimize
gain errors and maintain the PKD01’s inherently low droop rate,
guarding Pin 4 as shown in Figure 9 is recommended.
COMPARATOR
The comparator output high level (V
OH
) is set by external resis-
tors. It is possible to optimize noise immunity while interfacing
to all standard logic families—TTL, DTL, and CMOS. Figure
10 shows the comparator output with external level-setting
resistors. Table I gives typical R1 and R2 values for common
circuit conditions.
The maximum comparator high output voltage (V
OH
) should be
limited to:
V
OH
(maximum) < V+ –2.0 V
With the comparator in the low state (V
OL
), the output stage
will be required to sink a current approximately equal to V
C
/R1.
CMP
PKD01
COMPARATOR
INPUT
INVERTING
COMPARATOR
INPUT
DIGITAL
GND
V–R1 = R2
( )
V
C
V
OH
–1
R1
R2
V
OH
V
C
Figure 10. Comparator Output with External Level-Setting
Resistors
Table I.
V
C
V
OH
R1 R2
5 3.5 2.7 kΩ6.2 kΩ
5 5.0 2.7 kΩ⬁
15 3.5 4.7 kΩ1.5 kΩ
15 5.0 4.7 kΩ2.4 kΩ
15 7.5 7.5 kΩ7.5 kΩ
15 10.0 7.5 kΩ15 kΩ
PEAK DETECTOR LOGIC CONTROL (RST, DET)
The transconductance amplifier outputs are controlled by the
digital logic signals RST and DET. The PKD01 operational
mode is selected by steering the current (I
1
) through Q
1
and Q
2
,
thus providing high-speed switching and a predictable logic
threshold. The logic threshold voltage is 1.4 V when digital
ground is at zero volts.
Other threshold voltages (V
TH
) may be selected by applying
the formula:
V
TH
≈ 1.4 V + Digital Ground Potential.
For proper operation, digital ground must always be at least
3.5 V below the positive supply and 2.5 V above the negative
supply. The RST or DET signal must always be at least 2.8 V
above the negative supply.
Operating the digital ground at other than zero volts does influence
the comparator output low voltage. The V
OL
level is referenced
to digital ground and will follow any changes in digital ground
potential:
V
OL
≈ 0.2 V + Digital Ground Potential.
RV
I
C
SINK
1≈
RV
V
C
OH
21
1
≈
−
REV. A
PKD01
–14–
Typical Circuit Configurations
V+
DET OR RST
CURRENT TO
CONTROL MODES
Q
2
Q
1
I
1
I
2
D
Q
3
V–
DIGITAL
GROUND
Figure 11. Logic Control
INPUT
DET/RST
PKD01
D
1
C
H
1000pF
C
A
B
RESET
VO LTAG E
V+ V–
OUTPUT
A GAIN = +1
B GAIN = +1
0V
+10V
0V
+10V
INPUT
OUTPUT
TIME – 50␮s/DIV
Figure 13. Unity Gain Positive Peak Detector
10k⍀
1%
INPUT
(GAIN = +2)
DET
PKD01
D1
CH
1000pF
C
A
B
10k⍀
5%
40.2k⍀
1%
5.1k⍀
5%
10k⍀
1%
RESET
VOLTAGE = +1V
(RESETS TO –4V)
8.2k⍀
5%
RST
V+ V–
OUTPUT
A GAIN = +2
B GAIN = –4
+5V
0V
–2V
+10V
0V
–4V
–10V
INPUT
OUTPUT
TIME – 50␮s/DIV
Figure 14. Positive Peak Detector with Gain
2
3
4
5
6
7
14
13
12
11
10
9
8
1
PKD01
56k⍀
5%
36k⍀
5%
18k⍀
5%
+18V
–18V
Figure 12. Burn-In Circuit
REV. A
PKD01
–15–
20k⍀
1%
INPUT
(GAIN = –2)
DET/RST
PKD01
D1
CH
1000pF
C
A
B
8.2k⍀
5%
30.1k⍀
1%
10k⍀
1%
10k⍀
1%
RESET
VOLTAGE = –1V
(RESETS TO –4V)
7.5k⍀
5%
RST
V+ V–
OUTPUT
A GAIN = –2
B GAIN = +4
+2V
0V
–5V
+10V
0V
–4V
–10V
INPUT
OUTPUT
TIME – 50␮s/DIV
Figure 15. Negative Peak Detector with Gain
10k⍀
1%
V
IN
DET
PKD01
D
1
C
H
1000pF
C
A
B
10k⍀
5%
10k⍀
1%
RESET
VO LTAG E
V+ V–
OUTPUT
A GAIN = –1
B GAIN = +1
0V
+10V
0V
–10V
INPUT
OUTPUT
TIME – 50␮s/DIV
Figure 16. Unity Gain Negative Peak Detector
PKD01
C
H
1000pF
C
A
B
RESET
VO LTAG E
OUTPUT
INPUT AMPLIFIER GAIN
RESET AMPLIFIER GAIN = 1 +
R3 = R4 = 1
+
R2
R4
INPUT
R1
1
R1
1
R2
R2
R1
R3
IF BOTH INPUT SIGNAL (AMPLIFIER A INPUT) AND THE RESET
VOLTAGE (AMPLIFIER B INPUT) HAVE THE SAME POSITIVE
VOLTAGE GAIN, THE GAIN CAN BE SET BY A SINGLE VOLTAGE
DIVIDER FOR BOTH INPUT AMPLIFIERS.
NOTE:
R1, R2, R3 AND R4 > 5k⍀
Figure 17. Alternate Gain Configuration
REV. A
PKD01
–16–
OP27
PKD01
POSITIVE
PEAK
DETECTOR
PKD01
NEGATIVE
PEAK
DETECTOR
V
IN
V
PK
+
V
PK
–
10k⍀
10k⍀
10k⍀
10k⍀
V
OUT
V
PK
– + V
PK
+
V
IN
V
PK
+
V
PK
–
Figure 18. Peak-to-Peak Detector
NOTES:
1. DEVICE IS RESET TO 0 VOLTS.
2. DETECTED PEAKS ARE PRESENTED AS POSITIVE OUTPUT LEVELS.
3. R = 10k⍀.
1000pF
POLYSTYRENE
CH
OUTPUT
PEAK DETECTOR
RESET
+15V –15V
10.5k⍀
+15V
POS/NEG
PEAK DETECTOR
SW-02
S2
S1
S3
S4
R
R
INPUT
–15V
PKD01
Figure 19. Logic Selectable Positive or Negative Peak Detector
5V
2.7k⍀
INPUT
SIGNAL
RESET
VO LTAG E
RST
DET
BIT 1
BIT 10
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
PORT 1
PORT 0
␮PROCESSOR
PKD01
D
1
C
H
R
R
DAC10
C
CMP
A
B
Figure 20. Peak Reading A/D Converter
REV. A
PKD01
–17–
PKD01
A
B
C
LOGIC
GND
ANALOG
GND
–15V+15V
V
OUT
5V
1ms2V
INPUT
RESET
OUTPUT
PEAK
DETECT
NOTES:
RESET VOLTAGE = –1.0V
TRACE 1 = 2V/DIV
TRACE 2 = 5V/DIV
TRACE 3 = 2V/DIV
SW-201
–15V +15V
VRS1
VRS2
VRS3
VRS4
VIN
A1
A2
A3
A4
PK DET/RST
Figure 21. Positive Peak Detector with Selectable Reset Voltage
PKD01
D
1
C
H
DAC08
C
A
B
DET
RAMP START
PULSE
BUFFERED
RAMP
OUTPUT
RAMP SLOPE
SELECTION
IB1 B8 R > 20k⍀
REF-01
15V
A0 A1 A2
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
MUX-08
AMPLITUDE
SELECTION
LOGIC
RAMP
AMPLITUDE
SLOPE = I
0
C
~0.5V/␮s~0.5V/␮s
SLOPE = I
1
C
RAMP
AMPLITUDE
RAMP
START
PULSE
0
NOTES:
1. NEGATIVE SLOPE OF RAMP IS SET BY DAC08 OUTPUT CURRENT.
2. DAC08 IS A DIGITALLY CONTROLLED CURRENT GENERATOR.
THE MAXIMUM FULL-SCALE CURRENT MUST BE LESS THAN 0.5mA.
RST
Figure 22. Programmable Low Frequency Ramp Generator
REV. A
PKD01
–18–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic DIP (PDIP)
(N-14)
14
17
8
PIN 1
0.795 (20.19)
0.725 (18.42)
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.160 (4.06)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
14-Lead Cerdip
(Q-14)
14
17
80.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN 0.098 (2.49) MAX
0.100 (2.54) BSC
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.785 (19.94) MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
C00481-0-2/01 (rev. A)
PRINTED IN U.S.A.