TwinDie™ DDR3 SDRAM
MT41J2G4 – 128 Meg x 4 x 8 Banks x 2 Ranks
MT41J1G8 – 64 Meg x 8 x 8 Banks x 2 Ranks
Features
• Uses 4Gb Micron die
• Two ranks (includes dual CS#, ODT, CKE, and ZQ
balls)
• Each rank has eight internal banks for concurrent
operation
• VDD = VDDQ = 1.5V (1.425–1.575V)
• 1.5V center-terminated push/pull I/O
• JEDEC-standard ball-out
• Low-profile package
• TC of 0°C to 95°C
– 0°C to 85°C: 8192 refresh cycles in 64ms
– 85°C to 95°C: 8192 refresh cycles in 32ms
Description
The 8Gb (TwinDie™) DDR3 SDRAM (1.5V) uses
Micron’s 4Gb DDR3 SDRAM die (essentially two ranks
of the 4Gb DDR3 SDRAM). Refer to Micron’s 4Gb
DDR3 SDRAM data sheet for the specifications not in-
cluded in this document. Specifications for base part
number MT41J1G4 correlate to TwinDie manufactur-
ing part number MT41J2G4; specifications for base
part number MT41J512M8 correlate to TwinDie man-
ufacturing part number MT41J1G8.
Options Marking
• Configuration
– 128 Meg x 4 x 8 banks x 2 ranks 2G4
– 64 Meg x 8 x 8 banks x 2 ranks 1G8
• FBGA package (Pb-free)
– 78-ball FBGA
(10.5mm x 12mm x 1.2mm) Rev :D
THE
– 78-ball FBGA
(9.5mm x 11.5mm x 1.2mm) Rev :E
TRF
• Timing – cycle time1
– 1.071ns @ CL = 13 (DDR3L-1866) -107
– 1.25ns @ CL = 11 (DDR3L-1600) -125
– 1.5ns @ CL = 9 (DDR3L-1333) -15E
– 1.87ns @ CL = 7 (DDR3L-1066) -187E
• Self refresh
– Standard None
• Operating temperature
– Commercial (0°C ≤ TC ≤ 95°C) None
• Revision :D / :E
Note: 1. CL = CAS (READ) latency.
Table 1: Key Timing Parameters
Speed
Grade
Data Rate
(MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) tCL (ns)
-1071, 2, 31866 13-13-13 13.91 13.91 13.91
-1251, 21600 11-11-11 13.75 13.75 13.75
-15E11333 9-9-9 13.5 13.5 13.5
-187E 1066 7-7-7 13.1 13.1 13.1
Notes: 1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-125).
Preliminary‡
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Features
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‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Table 2: Addressing
Parameter 2048 Meg x 4 1024 Meg x 8
Configuration 128 Meg x 4 x 8 banks x 2 ranks 64 Meg x 8 x 8 banks x 2 ranks
Refresh count 8K 8K
Row address 64K A[15:0] 64K A[15:0]
Bank address 8 BA[2:0] 8 BA[2:0]
Column address 2K A[11, 9:0] 1K A[9:0]
Preliminary
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Features
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Ball Assignments and Descriptions
Figure 1: 78-Ball FBGA Ball Assignments (Top View)
4 65
A
B
C
D
E
F
G
H
J
K
L
M
N
1
VSS
VSS
VDDQ
VSSQ
VREFDQ
ODT1
ODT0
CS1#
VSS
VDD
VSS
VDD
VSS
2
VDD
VSSQ
DQ2
NF, DQ6
VDDQ
VSS
VDD
CS0#
BA0
A3
A5
A7
RESET#
3
NC
DQ0
DQS
DQS#
NF, DQ4
RAS#
CAS#
WE#
BA2
A0
A2
A9
A13
7
NF, NF/TDQS#
DM, DM/TDQS
DQ1
VDD
NF, DQ7
CK
CK#
A10/AP
A15
A12/BC#
A1
A11
A14
8
VSS
VSSQ
DQ3
VSS
NF, DQ5
VSS
VDD
ZQ0
VREFCA
BA1
A4
A6
A8
9
VDD
VDDQ
VSSQ
VSSQ
VDDQ
CKE1
CKE0
ZQ1
VSS
VDD
VSS
VDD
VSS
Note: 1. Dark balls (with ring) designate balls that differ from the monolithic versions.
Preliminary
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Ball Assignments and Descriptions
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Table 3: FBGA 78-Ball Descriptions
Symbol Type Description
A15, A14, A13,
A12/BC#, A11,
A10/AP, A[9:0]
Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled
in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-
mine whether burst chop (on-the-fly) will be performed (HIGH = burst length (BL) of 8 or
no burst chop, LOW = burst chop (BC) of 4, burst chop).
BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All command, address, and control input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE[1:0] Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-
cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-
ent upon the DDR3L SDRAM configuration and operating mode. Taking CKE LOW pro-
vides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active
power-down (row active in any bank). CKE is synchronous for power-down entry and exit
and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-
ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-
cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA.
CS#[1:0] Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-
nal rank selection on systems with multiple ranks. CS# is considered part of the command
code.
DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. Although the DM
ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM
is referenced to VREFDQ. DM has an optional use as TDQS on the x8.
ODT[1:0] Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-
mination resistance internal to the DDR3L SDRAM. When enabled in normal operation,
ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the
x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the
LOAD MODE command. ODT is referenced to VREFCA.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered and are referenced to VREFCA.
RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver
is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤
0.2 × VDDQ. RESET# assertion and desertion are asynchronous.
DQ[3:0] I/O Data input/output: Bidirectional data bus for x4 configuration. DQ[3:0] are referenced
to VREFDQ.
Preliminary
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Ball Assignments and Descriptions
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© 2011 Micron Technology, Inc. All rights reserved.
Table 3: FBGA 78-Ball Descriptions (Continued)
Symbol Type Description
DQ[7:0] I/O Data input/output: Bidirectional data bus for x8 configuration. DQ[7:0] are referenced
to VREFDQ.
DQS, DQS# I/O Data strobe: DQS and DQS# are differential data strobes: Output with read data; edge
aligned with read data; input with write data; center-aligned with write data.
TDQS, TDQS# I/O Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled,
DM is disabled, and the TDQS and TDQS# balls provide termination resistance.
VDD Supply Power supply: 1.5V (1.425V to 1.575V operational)
VDDQ Supply DQ power supply: 1.5V (1.425V to 1.575V operational)
VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained
at all times (including self refresh) for proper device operation.
VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (including self re-
fresh) for proper device operation.
VSS Supply Ground.
VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.
ZQ[1:0] Reference External reference ball for output drive calibration: This ball is tied to an external
240Ω resistor (RZQ), which is tied to VSSQ.
NC – No connect: These balls should be left unconnected (the ball has no connection to the
DRAM or to other balls).
NF – No function: When configured as a x4 device, these balls are NF. When configured as a
x8 device, these balls are defined as TDQS#, DQ[7:4].
Preliminary
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Ball Assignments and Descriptions
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Functional Description
The TwinDie DDR3 SDRAM is a high-speed, CMOS dynamic random access memory
device internally configured as two 8-bank DDR3 SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like-die tested within a monolithic die package.
The DDR3 SDRAM uses a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-
nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O balls.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
Read and write accesses to the DDR3 SDRAM are burst oriented. Accesses start at a se-
lected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The ad-
dress bits (including CSn#, BAn, and An) registered coincident with the READ or WRITE
command are used to select the rank, bank, and starting column location for the burst
access.
This data sheet provides a general description, package dimensions, and the package
ballout. Refer to the Micron monolithic DDR3 data sheet for complete information re-
garding individual die initialization, register definition, command descriptions, and die
operation.
Preliminary
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Functional Description
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Functional Block Diagrams
Figure 2: Functional Block Diagram (128 Meg x 4 x 8 Banks x 2 Ranks)
RAS#
CAS#
WE#
CK
CK#
DQ[3:0]
DQS, DQS#
DM
A[15:0],
BA[2:0]
CS0#
CKE0
ODT0
Rank 0
(128 Meg x 4 x 8 banks)
Rank 1
(128 Meg x 4 x 8 banks)
CS1#
CKE1
ODT1
ZQ1 ZQ0
Figure 3: Functional Block Diagram (64 Meg x 8 x 8 Banks x 2 Ranks)
TDQS#
CAS#
RAS#
WE#
CK
CK#
DQ[7:0]
DQS, DQS#
DM/TDQS
A[15:0],
BA[2:0]
Rank 0
(64 Meg x 8 x 8 banks)
Rank 1
(64 Meg x 8 x 8 banks)
CS0#
CKE0
ODT0
ZQ0
CS1#
CKE1
ODT1
ZQ1
Preliminary
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Functional Block Diagrams
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Electrical Specifications – Absolute Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions outside those indicated in the device data sheet is not implied. Exposure to abso-
lute maximum rating conditions for extended periods may adversely affect reliability.
Table 4: Absolute Maximum DC Ratings
Parameter Symbol Min Max Units Notes
VDD supply voltage relative to VSS VDD –0.4 1.975 V 1
VDD supply voltage relative to VSSQ VDDQ –0.4 1.975 V
Voltage on any ball relative to VSS VIN, VOUT –0.4 1.975 V
Input leakage current
Any input 0V ≤ VIN ≤ VDD,
VREF pin 0V ≤ VIN ≤ 1.1V
(All other pins not under test = 0V)
II–4 4 µA
VREF supply leakage current
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
IVREF –2 2 µA 2
Operating case temperature TC0 95 °C 3, 4
Storage temperature TSTG –55 150 °C
Notes: 1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are less than 500mV, VREF may be ≤300mV.
2. The minimum limit requirement is for testing purposes. The leakage current on the VREF
pin should be minimal.
3. MAX operating case temperature. TC is measured in the center of the package (see Fig-
ure 4 (page 9)).
4. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC dur-
ing operation.
Temperature and Thermal Impedance
It is imperative that the DDR3 SDRAM device’s temperature specifications, shown in
the following table, be maintained in order to ensure the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in main-
taining the proper junction temperature is using the device’s thermal impedances cor-
rectly. The thermal impedances listed in Table 6 (page 9) apply to the current die re-
vision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications,” prior to using the values listed in the
thermal impedance table. For designs that are expected to last several years and require
the flexibility to use several DRAM die shrinks, consider using final target theta values
(rather than existing values) to account for increased thermal impedances from the die
size reduction.
The DDR3 SDRAM device’s safe junction temperature range can be maintained when
the TC specification is not exceeded. In applications where the device’s ambient tem-
perature is too high, use of forced air and/or heat sinks may be required to satisfy the
case temperature specifications.
Preliminary
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Electrical Specifications – Absolute Ratings
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Table 5: Thermal Characteristics
Notes 1–3 apply to entire table
Parameter Symbol Value Units Notes
Operating temperature TC0 to 85 °C
0 to 95 °C 4
Notes: 1. MAX operating case temperature TC is measured in the center of the package, as shown
below.
2. A thermal solution must be designed to ensure that the device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs
interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh
(ASR), if available, must be enabled.
Figure 4: Temperature Test Point Location
Test point
Length (L)
Width (W)
0.5 (W)
0.5 (L)
Table 6: Thermal Impedance
Die Rev Package Substrate
Θ JA (°C/W)
Airflow =
0m/s
Θ JA (°C/W)
Airflow =
1m/s
Θ JA (°C/W)
Airflow =
2m/s Θ JB (°C/W) Θ JC (°C/W) Notes
D 78-ball Low Con-
ductivity
55.7 42.3 36.8 32 1.5 1
High Con-
ductivity
35.6 29.3 26.7 23.9
E 78-ball Low Con-
ductivity
57.7 44.1 38.8 20.5 2.1 1
High Con-
ductivity
36.7 30.6 28.1 18.6
Note: 1. Thermal resistance data is based on a number of samples from multiple lots and should
be viewed as a typical number.
Preliminary
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Electrical Specifications – Absolute Ratings
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© 2011 Micron Technology, Inc. All rights reserved.
Electrical Specifications – ICDD Parameters
Table 7: DDR3 ICDD Specifications and Conditions (Rev. D)
Note 1 applies to the entire table
Combined
Symbol
Individual
Die Status
Bus
Width -187E -15E -125 Units
ICDD0 ICDD0 =
IDD0 + IDD2P0
x4, x8 80 85 95 mA
ICDD1 ICDD1 =
IDD1 + IDD2P0
x4 90 95 100 mA
x8 97 102 107
ICDD2P0 (slow exit) ICDD2P0 =
IDD2P0 + IDD2P0
x4, x8 40 40 40 mA
ICDD2P1 (fast exit) ICDD2P1 =
IDD2P1 + IDD2P0
x4, x8 50 52 57 mA
ICDD2Q ICDD2Q =
IDD2Q + IDD2P0
x4, x8 57 62 67 mA
ICDD2N ICDD2N =
IDD2N + IDD2P0
x4, x8 62 65 70 mA
ICDD2N T ICDD2NT =
IDD2NT + IDD2P0
x4, x8 60 65 70 mA
ICDD3P ICDD3P = IDD3P + IDD2P0 x4, x8 70 75 80 mA
ICDD3N ICDD3N =
IDD3N + IDD2P0
x4, x8 67 72 77 mA
ICDD4R ICDD4RCDD4R =
IDD4R + IDD2P0
x4 155 175 195 mA
x8 167 187 207
ICDD4W ICDD4W =
IDD4W + IDD2P0
x4 135 155 175 mA
x8 145 165 185
ICDD5B ICDD5B =
IDD5B + IDD2P0
x4, x8 225 230 240 mA
ICDD6 ICDD6 =
IDD6 + IDD6
x4, x8 44 44 44 mA
ICDD6ET ICDD6ET =
IDD6ET + IDD6ET
x4, x8 56 56 56 mA
ICDD7 ICDD7 =
IDD7 + IDD2P0
x4, x8 230 270 310 mA
ICDD8 ICDD8 = 2 × IDD2P0 + 4 x4, x8 44 44 44 mA
Note: 1. ICDD values reflect the combined current of both individual die. IDDx represents individu-
al die values.
Preliminary
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Electrical Specifications – ICDD Parameters
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© 2011 Micron Technology, Inc. All rights reserved.
Table 8: DDR3 ICDD Specifications and Conditions (Rev. E)
Note 1 applies to the entire table
Combined
Symbol
Individual
Die Status
Bus
Width -187E -15E -125 -107 Units
ICDD0 ICDD0 =
IDD0 + IDD2P0 + 5
x4, x8 67 70 78 85 mA
ICDD1 ICDD1 =
IDD1 + IDD2P0 + 5
x4 76 80 84 88 mA
x8 82 85 89 93
ICDD2P0 (slow exit) ICDD2P0 =
IDD2P0 + IDD2P0
x4, x8 36 36 36 36 mA
ICDD2P1 (fast exit) ICDD2P1 =
IDD2P1 + IDD2P0
x4, x8 44 46 50 55 mA
ICDD2Q ICDD2Q =
IDD2Q + IDD2P0
x4, x8 45 46 50 53 mA
ICDD2N ICDD2N =
IDD2N + IDD2P0
x4, x8 46 47 50 53 mA
ICDD2NT ICDD2NT =
IDD2NT + IDD2P0
x4, x8 50 53 57 60 mA
ICDD3P ICDD3P = IDD3P + IDD2P0 x4, x8 50 53 56 59 mA
ICDD3N ICDD3N =
IDD3N + IDD2P0
x4, x8 50 53 56 59 mA
ICDD4R ICDD4RCDD4R =
IDD4R + IDD2P0 + 5
x4 136 153 1170 187 mA
x8 146 163 180 197
ICDD4W ICDD4W =
IDD4W + IDD2P0 + 5
x4 110 126 141 156 mA
x8 118 133 148 164
ICDD5B ICDD5B =
IDD5B + IDD2P0
x4, x8 242 246 253 260 mA
ICDD6 ICDD6 =
IDD6 + IDD6
x4, x8 40 40 40 40 mA
ICDD6ET ICDD6ET =
IDD6ET + IDD6ET
x4, x8 50 50 50 50 mA
ICDD7 ICDD7 =
IDD7 + IDD2P0 + 5
x4, x8 183 213 243 274 mA
ICDD8 ICDD8 = 2 × IDD2P0 + 4 x4, x8 40 40 40 40 mA
Note: 1. ICDD values reflect the combined current of both individual die. IDDx represents individu-
al die values.
Preliminary
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Electrical Specifications – ICDD Parameters
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Package Dimensions
Figure 5: 78-Ball FBGA (package code THE)
Seating plane
0.12 A
123789
Ball A1 ID Ball A1 ID
A
0.25 MIN
1.1 ±0.1
6.4 CTR
10.5 ±0.1
0.8 TYP
9.6 CTR
12 ±0.1
78X Ø0.45
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
0.8 TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
Notes: 1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
Preliminary
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Package Dimensions
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Figure 6: 78-Ball FBGA (package code TRF)
Seating plane
0.12 A
123789
Ball A1 Index
(covered by SR)
Ball A1 Index
A
0.25 MIN
1.1 ±0.1
6.4 CTR
9.5 ±0.1
0.8 TYP
9.6 CTR
11.5 ±0.1
78X Ø0.45
Dimensions apply
to solder balls
post-reflow
on Ø0.33 NSMD
ball pads.
0.8 TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
Notes: 1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
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www.micron.com/productsupport Customer Comment Line: 800-932-4992
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All other trademarks are the property of their respective owners.
This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
Preliminary
8Gb: x4, x8 1.5V TwinDie DDR3 SDRAM
Package Dimensions
PDF: 09005aef847fe0df
ddr3_8gb_1_5v_twindie_x4x8.pdf - Rev. C 4/13 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.
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