FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontroller
CMOS
MB90335 Series
MB90337/F337/V330A
■DESCRIPTION
The MB90335 series are 16-bit microcontrollers designed for applications , such as personal computer peripheral
devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but
also MiniHost operation. It is equipped with functions that are suitable for personal computer peripheral devices
such as displays and audio devices, and control of mobile devices that support USB communications. While
inheriting the AT architecture of the F2MC* family, the instruction set supports the C language and extended
addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial
collection of improved bit manipulation instructions. In addition, long word processing is now available by intro-
ducing a 32-bit accumulator.
* : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
■FEATURES
•
••
• Clock
• Built-in oscillation circuit and PLL clock frequency multiplication circuit
• Oscillation clock
The machine clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz)
Clock for USB is 48 MHz
Machine clock frequency of 6 MHz, 12 MHz or 24 MHz selectable
• Minimum execution time of instruction : 41.6 ns (6 MHz oscillation clock, 4-time multiplied : machine clock
24 MHz and at operating VCC = 3.3 V)
•
••
• The maximum memory space:16 MB
•
••
• 24-bit addressing
•
••
• Bank addressing
(Continued)
■PACKAGE
R
64-pin plastic LQFP
(FPT-64P-M09)
Preliminary
2004.01.09
MB90335 Series
2
(Continued)
•
••
• Instruction system
Data types: Bit, Byte, Word, Long word
Addressing mode (23 types)
Enhanced high-precision computing with 32-bit accumulator
Enhance Multiply/Divide instructions with sign and the RETI instruction
•
••
• Instruction system compatible with high-level languag e (C language) and multitask
• Employing system stack pointer
• Instruction set symmetry and barrel shift instructions
•
••
• Program Patch Function (2 address pointer)
•
••
• 4-b yte instruction queue
•
••
• Interrupt function
• Priority levels are programmable
• 20 interrupts
•
••
• Data transfer function
• Expanded intelligent I/O service function (EI2OS) : Maximum of 16 channels
•µDMAC : Maximum 16 channels
•
••
• Low Power Consumption Mode
• Sleep mode (with the CPU operating clock stopped)
• Time - base timer mode (with the oscillator clock and time - base timer operating)
• Stop mode (with the oscillator clock stopped)
• CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles)
•
••
• Package
• LQFP-64P (FPT-64P-M09 : 0.65 mm pin pitch)
•
••
• Process : CMOS technology
•
••
• Operation guaranteed temperature: −
−−
−40 °
°°
°C to +
++
+85 °
°°
°C (0 °
°°
°C to +
++
+70 °
°°
°C when USB is in use)
Preliminary
2004.01.09
MB90335 Series
3
■
■■
■INTERNAL PERIPHERAL FUNCTION (RESOURCE)
•
••
• I/O port: Max 45 ports
•
••
• Time-base timer : 1channel
•
••
• Watchdog timer : 1 channel
•
••
• 16-bit reload timer : 1 channel
•
••
• Multi-functional timer
• 8/16-bit PPG timer (8-bit × 4 channels or 16-bit × 2 channels) the period and duty of the output pulse can be
set by the program.
• 16-bit PWC timer : 1 channel
Timer function and pulse width measurement function
•
••
• UART : 2 channels
• Equipped with Full duplex double buffer with 8-bit lenghth
• Asynchronous transfer or clock-synchronous serial (I/O extended serial) transfer can be set.
•
••
• Extended I/O serial interface: 1 channel
•
••
• DTP/External interrupt circuit (8 channels)
• Activate the extended intelligent I/O service by external interrupt input
• Interrupt output by external interr upt input
•
••
• Delayed interrupt output module
• Output an interrupt request for task switching
•
••
• USB : 1 channel
• USB function (conform to USB 2.0 Full Speed)
• Supports for Full Speed/Endpoint are specifiable up to six.
• Dual port RAM (The FIFO mode is supported).
• Transfer type: Control, Interrupt, Bulk or Isochronous transfer possible
• USB Mini Host function
•
••
• I2C Interface : 1 channel
• Supports Intel SM bus standards and Phillips I2C bus standards
• Two-wire data transfer protocol specification
• Master and slave transmission/reception
Note : I2C licenae :
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use,
these components in an I2C system provided that the system conf orms to the I2C Standard Specification as
defined by Phillips.
Preliminary
2004.01.09
MB90335 Series
4
■
■■
■PRODUCT LINEUP
1. MB90335 Series
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-
01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.
■PACKAGES AND PRODUCT MODELS
: Yes × : No
Note : For detailed information on each package, see “■ PACKAGE DIMENSIONS”.
Part number MB90V330A MB90F337 MB90337
Type For evaluation Built-in FLASH MEMORY Built-in Mask ROM
ROM capacity No 64 Kbyte
RAM capacity 28 Kbyte 4 Kbyte
Emulator-specific
power supply * Used bit
CPU functions
Number of basic instructions
Minimum instruction execu-
tion time
Addressing type
Program Patch Function
maximum memory space
: 351 instructions
: 41.6 ns / at oscillation of 6 MHz
(When 4 times is used : Machine clock of 24 MHz)
: 23 types
: For two address pointers
: 16 Mbyte
Ports I/O Ports(CMOS) 45 ports
UART
Equipped with full-duplex double buffer
Clock synchronous or asynchronous operation selectable.
It can also be used for I/O serial.
Built-in special baud-rate generator
Built-in 2 channels
16-bit reload timer 16-bit reload timer operation
Built-in 1 channel
Multi-functional timer 8/16-bit PPG timer (8-bit mode × 4 channels, 16-bit mode × 2 channels)
16-bit PWC timer × 1 channel
DTP/External interrupt 8 channels
Interrupt factor : “L”→“H” edge /“H”→“L” edge /“L” level /“H” level selectable
I2C 1 channel
Extended I/O serial interface 1 channel
USB 1 channel
USB function (conform to USB 2.0 Full Speed)
USB Mini-HOST function
Withstand voltage of 5 V 6 ports (Excluding VBUS and I/O for I2C)
Low Power Consumption
Mode Sleep mode/Timebase timer mode/Stop mode/CPU intermittent mode
Process CMOS
Operating voltage VCC 3.3 V ± 0.3 V (at maximum machine clock 24 MHz)
Package MB90337 MB90F337 MB90V330A
FPT-64P-M09 (LQFP-0.65 mm) ×
PGA-299C-A01 (PGA) × ×
Preliminary
2004.01.09
MB90335 Series
5
■
■■
■PIN ASSIGNMENT
(TOP VIEW)
(FPT-64P-M09)
VBUS
Vss
DVM
DVP
Vcc
Vss
HVM
HVP
Vcc
HCONX
P42/SIN0
P43/SOT0
P44/SCK0
P45/SIN1
P46/SOT1
P47/SCK1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Vss
X1
X0
P24/PPG0
P23
P22
P21
P20
P17
P16
P15
P14
P13
P12
P11
P10
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P51
P41/TOT0
P40/TIN0
P67/INT7/SDA0
P66/INT6/SCL0
P65/INT5/PWC
P64/INT4/SCK
P63/INT3/SOT
P62/INT2/SIN
P61/INT1
P60/INT0
P27/PPG3
P26/PPG2
P25/PPG1
P50
Vcc
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P52
P53
Vss
MD2
MD1
MD0
RST
P54
P00
P01
P02
P03
P04
P05
P06
P07
Preliminary
2004.01.09
MB90335 Series
6
■
■■
■PIN DESCRIPTION
* : For circuit information, see “■ I/O CIRCUIT TYPE”.
(Continued)
Pin no. Pin name Circuit
type*
Status at
reset/
function Function
QFPM09
46 , 47 X0, X1 A Oscillation
status
It is a terminal which connects the oscillator.
When connecting an external clock, leave the X1 pin side uncon-
nected.
23 RST F Reset input External reset input pin.
25 to 32 P00 to P07 I
Port input
(High-Z)
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD00 to
RD07 = 1) by the pull-up resistor setting register (RDR0). (When
the power output is set, it is invalid.)
33 to 40 P10 to P17 I
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD10 to
RD17 = 1) by the pull-up resistor setting register (RDR1). (When
the power output is set, it is invalid.)
41 to 44 P20 to P23 D General purpose input/output port.
45 P24 DGeneral purpose input/output port.
PPG0 Functions as output pins of PPG timers ch0.
51 to 53 P25 to P27 DGeneral purpose input/output port.
PPG1 to
PPG3 Functions as output pins of PPG timers ch1 to ch3.
62 P40 HGeneral purpose input/output port.
TIN0 Function as event input pin of 16-bit reload timer.
63 P41 HGeneral purpose input/output port.
TOT0 Function as output pin of 16-bit reload timer.
11 P42 HGeneral purpose input/output port.
SIN0 Functions as a data input pin for UART ch0.
12 P43 HGeneral purpose input/output port.
SOT0 Functions as a data output pin for UART ch0.
13 P44 HGeneral purpose input/output port.
SCK0 Functions as a clock I/O pin for UART ch0.
14 P45 HGeneral purpose input/output port.
SIN1 Functions as a data input pin for UART ch1.
15 P46 HGeneral purpose input/output port.
SOT1 Functions as a data output pin for UART ch1.
16 P47 HGeneral purpose input/output port.
SCK1 Functions as a clock I/O pin for UART ch1.
50 P50 K General purpose input/output port.
64 P51 K General purpose input/output port.
17, 18 P52, P53 K General purpose input/output port.
24 P54 K General purpose input/output port.
Preliminary
2004.01.09
MB90335 Series
7
(Continued)
* : For circuit information, see “■ I/O CIRCUIT TYPE”.
Pin no. Pin name Circuit
type*
Status at
reset/
function Function
QFPM09
54, 55 P60, P61 C
Port input
(High-Z)
General purpose input/output port. (withstand voltage of 5 V)
INT0, INT1 Functions as the input pin for external interrupt ch0 and ch1.
56 P62 CGeneral purpose input/output port. (withstand voltage of 5 V)
INT2 Functions as the input pin for external interrupt ch2.
SIN Data input pin for simple serial IO.
57 P63 CGeneral purpose input/output port. (withstand voltage of 5 V)
INT3 Functions as the input pin for external interrupt ch3.
SOT Data output pin for simple serial IO
58 P64 CGeneral purpose input/output port. (withstand voltage of 5 V)
INT4 Functions as the input pin for external interrupt ch4.
SCK Clock I/O pin for simple serial IO.
59 P65 CGeneral purpose input/output port. (withstand voltage of 5 V)
INT5 Functions as the input pin for external interrupt ch5.
PWC Functions as the PWC input pin.
60
P66
C
General purpose input/output port.
INT6 Functions as the input pin for external interrupt ch6.
SCL0 Functions as the input/output pin for I2C interface clock. The port
output must be placed in High-Z state during I2C interface
operation.
61
P67
C
General purpose input/output port.
INT7 Functions as the input pin for external interrupt ch7.
SDA0 Functions as the I2C interface data input/output pin. The port out-
put must be placed in High-Z state during I2C interface operation.
1 VBUS C VBUS input Status detection pin of USB cable.
3DVMJ
USB input
(SUSPEND)
USB function D − pin.
4 DVP J USB function D + pin.
7 HVM J USB Mini Host D − pin.
8 HVP J USB Mini Host D + pin.
10 HCONX E High output External pull-up resistor connection pin.
21, 22 MD1, MD0 B Mode input
Pin Input pin for selecting operation mode.
20 MD2 G
5Vcc
Power
supply
Power supply pin.
9VccPower supply pin.
49 Vcc Power supply pin.
2VssPower supply pin (GND).
6VssPower supply pin (GND).
19 Vss Power supply pin (GND).
48 Vss Power supply pin (GND).
Preliminary
2004.01.09
MB90335 Series
8
■
■■
■I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A
• Oscillation feedback resistance :
approx. 1 MΩ
• With standby control
B• CMOS hysteresis input
C
• Hysteresis input
• Nch open drain output
D
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
Note : • The I/O ports and internal
resources share one output
buffer for their outputs.
• The I/O por t and internal
resources share one input b uffer
for their input.
E
• CMOS output
F
• CMOS hysteresis input with pull-up
• Resistor approx. 50 kΩ
G
• CMOS hysteresis input with pull-down
• Resistor approx. 50 kΩ
• FLASH product is not provided with
pull-down resistor.
X1
X0
Standby control signal
Clock input
Hysteresis input
NoutNch
Hysteresis input
Standby control signal
Pout
Nout
Pch
Nch
Hysteresis input
Standby control signal
Pout
Nout
Pch
Nch
Hysteresis input
Hysteresis input
Preliminary
2004.01.09
MB90335 Series
9
(Continued)
Type Circuit Remarks
H
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
With open drain control signal
I
• CMOS output
•CMOS input
(With input interception function at
standby)
Programmable pull-up
Resistor approx. 50 kΩ
J
• USB I/O pin
K
• CMOS output
•CMOS input
(With input interception function at
standby)
Pout
Nout
Pch
Nch
Open drain control
signal
Standby control signal
Hysteresis input
Pout
Nout
Pch
Nch
CTL
CMOS input
Standby control signal
D+
D−
D + input
D-input
Differential input
Full D + output
Full D-output
Low D + output
Low D-output
Direction
Speed
Pout
Nout
Pch
Nch
CMOS input
Standby control signal
Preliminary
2004.01.09
MB90335 Series
10
■
■■
■HANDLING DEVICES
1. Preventing latchup and turning on power supply
Latchup may occur on CMOS IC under the following conditions:
1. If a voltage higher than VCC or lower than VSS is applied to input and output pins.
2. A voltage higher than the rated voltage is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using CMOSICs, take great care to prevent the occurrence of latchup.
2. Treatment of unused pins
Leaving un used input pins open ma y cause a malfunction. These pins must theref ore be set to a pull-up or pull-
down state.
3. About the attention when the external clock is used
• Using external clock
4. Treatment of power supply pins (VCC/VSS)
When the de vice is provided with multiple VCC and VSS pins , be sure to connect all of the power pins to the po wer
supply and ground outside the de vice to reduce latch-up and unwanted r adiation, pre vent the strobe signal from
malfunctioning due to a rise of grand level, and to follow the standards of total output current for device design
reasons. The po w er supply source should be connected to the VCC and VSS of this de vice at the lo we st possible
impedance. It is also advisable to connect a bypass capacitor of approximately 0.1 µF between VCC and VSS near
this device.
5. About crystal oscillator circuit
Noise near the X0/X1 pin may cause the device to malfunction. When designing the artwork for a PC board
using the microcontroller, it is strongly advisable to place the X0/X1 and crystal (ceramic) oscillator, and the
bypass capacitor leading to the ground as close to one another as possible and prevent their writing patter ns
from crossing other patterns as possible be cause stable operation can be expected with such a layout.
6. Caution on Operations during PLL Clock Mode
Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the
microcontroller may continue to operate at the free-running frequency of the PLL inter nal automatic oscillator
circuit.Performance of this operation, however, cannot be guaranteed.
X0
X1OPEN
Preliminary
2004.01.09
MB90335 Series
11
7. Stabilization of supply voltage
A sudden change in the supply v oltage ma y cause the device to malfunction ev en within the VCC supply v oltage
operating range . F or stabilization refe rence, the supply v oltage should be controlled so that VCC ripple variations
(peak-to-peak v alues) at commercial frequencies (50 MHz to 60 MHz) fall below 10% of the standard VCC supply
voltage and the transient regulation does not exceed
0.1 V/ms at temporary changes such as power supply switching.
8. Writing to flash memory
F or serial writing to flash memory, alwa ys make sure that the operating v oltage VCC is between 3.13 V and 3.6 V.
F or normal writing to flash memory, alwa ys make sure that the operating v oltage VCC is between 3.0 V and 3.6 V.
Preliminary
2004.01.09
MB90335 Series
12
■
■■
■BLOCK DIAGRAM
F2MC-16LX
CPU
RAM
ROM
UART/SIO
ch0, ch1
I2C SIO
µDMAC
USB
(Function)
(Mini-HOST)
P00
P07
P10
P17
P20
P27
P40
P47
P50
P54
P60
P67
X0, X1
RST
MD0 to MD2
SIN0, SIN1
SOT0, SOT1
SCK0, SCK1
SCL0
SDA0
INT0 to INT7
DVP
DVM
HVP
HVM
HCONX
VBUS
TOT0
TIN0
PPG0 to PPG3
PWC
SIN
SOT
SCK
* : Channel for use in 8-bit mode. Two channels (ch1, ch3) are used in 16-bit mode.
Note : I/O ports share pins with peripheral resources.
For details, see “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”.
Note also that pins used for peripheral resources cannot serve as I/O ports.
16-bit reload
timer
External interrupt
16-bit PWC
8/16-bit PPG
timer
ch0 to ch3*
Clock control
circuit
Interrupt
controller
Internal data bus
I/O port (port 0, 1, 2, 4, 5, 6)
Preliminary
2004.01.09
MB90335 Series
13
■
■■
■MEMORY MAP
Memory Map of MB90335 Series
Notes : •When the ROM mirror function register has been set, the mirror image data at higher addresses (“FF8000H
to FFFFFFH” ) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of bank 00.
•For setting the ROM mirror function, see “16. ROM mirror function select module” in “■ PERIPHERAL
RESOURCES”.
Reference : •The ROM mirror function is for using the C compiler small model.
•The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in
bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be
reproduced in bank 00.
•When the C compiler small model is used, the data table mirror image can be sho wn at “008000H to
00FFFFH” by storing the data table at “FF8000H to FFFFFFH”.
Theref ore, data tab les in the ROM area can be ref erenced without declaring the f ar addressing with
the pointer.
FFFFFFH
00FFFFH
007FFFH
007900H
007100H
008000H
FF0000H
000100H
0000FBH
000000H
FFFFFFH
00FFFFH
007FFFH
007900H
001100H
008000H
FF0000H
000100H
0000FBH
000000H
FFFFFFH
00FFFFH
007FFFH
007900H
001100H
008000H
FF0000H
000100H
0000FBH
000000H
MB90V330A MB90F337 MB90337
Single chip mode (ROM mirror function)
Peripheral area
ROM (FF bank)
ROM area
(image of FF bank)
Register
RAM area
(28 Kbytes)
Peripheral area
Peripheral area
ROM (FF bank)
ROM area
(image of FF bank)
Register
RAM area
(4 Kbytes)
Peripheral area
Peripheral area
ROM (FF bank)
ROM area
(image of FF bank)
Register
RAM area
(4 Kbytes)
Peripheral area
Preliminary
2004.01.09
MB90335 Series
14
■
■■
■F2MC-16L CPU PROGRAMMING MODEL
• Dedicated register
• General purpose registers
• Processor status
AH AL
DPR
PCB
DTB
USB
SSB
ADB
8 bit
16 bit
32 bit
USP
SSP
PS
PC
Accumulator
User stack pointer
System stack pointer
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
R1 R0
R3 R2
R5 R4
R7 R6
RW0
RW1
RW2
RW3
16 bit
000180H + RP × 10H
RW4
RW5
RW6
RW7
RL0
RL1
RL2
RL3
MSB LSB
ILM
15 13
PS RP CCR
12 8 70
Preliminary
2004.01.09
MB90335 Series
15
■
■■
■I/O MAP
(Continued)
Address Register
abbreviation Register Read/
Write Resource name Initial Value
000000HPDR0 Port 0 Data Register R/W Port 0 XXXXXXXXB
000001HPDR1 Port 1 Data Register R/W Port 1 XXXXXXXXB
000002HPDR2 Port 2 Data Register R/W Port 2 XXXXXXXXB
000003HProhibited
000004HPDR4 Port 4 Data Register R/W Port 4 XXXXXXXXB
000005HPDR5 Port 5 Data Register R/W Port 5 - - - XXXXXB
000006HPDR6 Port 6 Data Register R/W Port 6 XXXXXXXXB
000007H
to
00000FHProhibited
000010HDDR0 Port 0 Direction Register R/W Port 0 0 0 0 0 0 0 0 0B
000011HDDR1 Port 1 Direction Register R/W Port 1 0 0 0 0 0 0 0 0B
000012HDDR2 Port 2 Direction Register R/W Port 2 0 0 0 0 0 0 0 0B
000013HProhibited
000014HDDR4 Port 4 Direction Register R/W Port 4 0 0 0 0 0 0 0 0B
000015HDDR5 Port 5 Direction Register R/W Port 5 - - - 0 0 0 0 0B
000016HDDR6 Port 6 Direction Register R/W Port 6 0 0 0 0 0 0 0 0B
000017H
to
00001AHProhibited
00001BHODR4 Port 4 Output Pin Register R/W Port 4
(OD control) 0 0 0 0 0 0 0 0B
00001CHRDR0 Port 0 Pull-up Resistance Register R/W Port 0 (PULL-UP) 0 0 0 0 0 0 0 0B
00001DHRDR1 Port 0 Pull-up Resistance Register R/W Port 1 (PULL-UP) 0 0 0 0 0 0 0 0B
00001EHProhibited
00001FH
000020HSMR0 Serial Mode Register ch0 R/W
UART0
0 0 1 0 0 0 0 0B
000021HSCR0 Serial Control Register ch0 R/W 0 0 0 0 0 1 0 0B
000022HSIDR0 Serial Input Data Register ch0 R XXXXXXXXB
SODR0 Serial Output Data Register ch0 W
000023HSSR0 Serial Status Register ch0 R/W 0 0 0 0 1 0 0 0B
000024HUTRLR0 UART Prescaler Reload Register ch0 R/W Communication
Prescaler (UART0) 0 0 0 0 0 0 0 0B
000025HUTCR0 UART Prescaler Control Register ch0 R/W 0 0 0 0 - 0 0 0B
000026HSMR1 Serial Mode Register ch1 R/W
UART1
0 0 1 0 0 0 0 0B
000027HSCR1 Serial Control Register ch1 R/W 0 0 0 0 0 1 0 0B
000028HSIDR1 Serial Input Data Register ch1 R XXXXXXXXB
SODR1 Serial Output Data Register ch1 W
000029HSSR1 Serial Status Register ch1 R/W 0 0 0 0 1 0 0 0B
Preliminary
2004.01.09
MB90335 Series
16
(Continued)
Address Register
abbreviation Register Read/
Write Resource name Initial Value
00002AHUTRLR1 UART Prescaler Reload Register ch1 R/W Communication
Prescaler (UART1) 0 0 0 0 0 0 0 0B
00002BHUTCR1 UART Prescaler Control Register ch1 R/W 0 0 0 0 - 0 0 0B
00002CH
to
00003BHProhibited
00003CHENIR Interrupt/DTP Enable Register R/W DTP/External
interrupt
0 0 0 0 0 0 0 0B
00003DHEIRR Interrupt/DTP source Register R/W 0 0 0 0 0 0 0 0B
00003EHELVR Request Level Setting Register Lower R/W 0 0 0 0 0 0 0 0B
00003FHRequest Level Setting Register Higher R/W 0 0 0 0 0 0 0 0B
000040H
to
000045HProhibited
000046HPPGC0 PPG0 Operation Mode Control Register R/W PPG ch0 0X0 0 0XX1B
000047HPPGC1 PPG1 Operation Mode Control Register R/W PPG ch1 0X0 0 0 0 0 1B
000048HPPGC2 PPG2 Operation Mode Control Register R/W PPG ch2 0X0 0 0XX1B
000049HPPGC3 PPG3 Operation Mode Control Register R/W PPG ch3 0X0 0 0 0 0 1B
00004AHProhibited
00004BH
00004CHPPG01 PPG0 and PPG1 Output Control Register R/W PPG ch0/1 0 0 0 0 0 0XXB
00004DHProhibited
00004EHPPG23 PPG2 and PPG3 Output Control Register R/W PPG ch2/3 0 0 0 0 0 0 XXB
00004FH
to
000057HProhibited
000058HSMCS Serial Mode Control Status Register R/W Extended Serial
I/O
XXXX0 0 0 0B
000059H0 0 0 0 0 0 1 0B
00005AHSDR Serial Data Register R/W XXXXXXXXB
00005BHSDCR Communication Prescaler Control
Register R/W Communication
Prescaler 0XXX0 0 0 0B
00005CHPWCSR PWC Control Status Register R/W 16-bit
PWC Timer
0 0 0 0 0 0 0 0B
00005DH0 0 0 0 0 0 0 XB
00005EHPWCR PWC Data Buffer Register R/W 0 0 0 0 0 0 0 0B
00005FH0 0 0 0 0 0 0 0B
000060HDIVR PWC Dividing Ratio Register R/W - - - - - - 0 0B
000061HProhibited
000062HTMCSR0 Timer control status Register R/W
16-bit Reload
Timer
0 0 0 0 0 0 0 0B
000063HXXXX 0 0 0 0B
000064HTMR0 16-bit Timer Register Lower R XXXXXXXXB
TMRLR0 16-bit Reload Register Lower W XXXXXXXXB
000065HTMR0 16-bit Timer Register Higher R XXXXXXXXB
TMRLR0 16-bit Reload Register Higher W XXXXXXXXB
Preliminary
2004.01.09
MB90335 Series
17
(Continued)
Address Register
abbreviation Register Read/
Write Resource name Initial Value
000066H
to
00006EHProhibited
00006FHROMM ROM Mirroring Function Selection
Register WROM Mirror
Function
Selection Module - - - - - - 1 1B
000070HIBSR0 I2C Bus Status Register R
I2C Bus Interface
0 0 0 0 0 0 0 0B
000071HIBCR0 I2C Bus Control Register R/W 0 0 0 0 0 0 0 0B
000072HICCR0 I2C Bus Clock Selection Register R/W XX 0 XXXXXB
000073HIADR0 I2C Bus Address Register R/W XXXXXXXXB
000074HIDAR0 I2C Bus Data Register R/W XXXXXXXXB
000075H
to
00009AHProhibited
00009BHDCSR DMA Descriptor Channel Specification
Register R/W µDMAC 0 0 0 0 0 0 0 0B
00009CHDSRL DMA Status Register Lower R/W 0 0 0 0 0 0 0 0B
00009DHDSRH DMA Status Register Higher R/W 0 0 0 0 0 0 0 0B
00009EHPACSR Program Address Detection Control
Status Register R/W Address Match
Detection 0 0 0 0 0 0 0 0B
00009FHDIRR Delayed Interrupt Source generate/
release Register R/W Delayed Interrupt - - - - - - - 0B
0000A0HLPMCR Low Power Consumption Mode Register R/W Low Power
Consumption
control circuit 0 0 0 1 1 0 0 0B
0000A1HCKSCR Clock Selection Register R/W Clock 1 1 1 1 1 1 0 0B
0000A2HProhibited
0000A3H
0000A4HDSSR DMA Stop Status Register R/W µDMAC 0 0 0 0 0 0 0 0B
0000A5H
to
0000A7HProhibited
0000A8HWDTC Watchdog Control Register R/W Watchdog Timer X - XXX 1 1 1B
0000A9HTBTC Time-base Timer Control Register R/W Time-base Timer 1 - - 0 0 1 0 0B
0000AAHProhibited
0000ABH
0000ACHDERL DMA Enable Register Lower R/W µDMAC 0 0 0 0 0 0 0 0B
0000ADHDERH DMA Enable Register Higher R/W 0 0 0 0 0 0 0 0B
0000AEHFMCR Flash Memory Control Status Register R/W FLASH
MEMORY I/F 0 0 0 X 0 0 0 0B
0000AFHProhibited
Preliminary
2004.01.09
MB90335 Series
18
(Continued)
Address Register
abbreviation Register Read/
Write Resource name Initial Value
0000B0HICR00 Interrupt Control Register 00 R/W
Interrupt
Controller
0 0 0 0 0 1 1 1B
0000B1HICR01 Interrupt Control Register 01 R/W 0 0 0 0 0 1 1 1B
0000B2HICR02 Interrupt Control Register 02 R/W 0 0 0 0 0 1 1 1B
0000B3HICR03 Interrupt Control Register 03 R/W 0 0 0 0 0 1 1 1B
0000B4HICR04 Interrupt Control Register 04 R/W 0 0 0 0 0 1 1 1B
0000B5HICR05 Interrupt Control Register 05 R/W 0 0 0 0 0 1 1 1B
0000B6HICR06 Interrupt Control Register 06 R/W 0 0 0 0 0 1 1 1B
0000B7HICR07 Interrupt Control Register 07 R/W 0 0 0 0 0 1 1 1B
0000B8HICR08 Interrupt Control Register 08 R/W 0 0 0 0 0 1 1 1B
0000B9HICR09 Interrupt Control Register 09 R/W 0 0 0 0 0 1 1 1B
0000BAHICR10 Interrupt Control Register 10 R/W 0 0 0 0 0 1 1 1B
0000BBHICR11 Interrupt Control Register 11 R/W 0 0 0 0 0 1 1 1B
0000BCHICR12 Interrupt Control Register 12 R/W 0 0 0 0 0 1 1 1B
0000BDHICR13 Interrupt Control Register 13 R/W 0 0 0 0 0 1 1 1B
0000BEHICR14 Interrupt Control Register 14 R/W 0 0 0 0 0 1 1 1B
0000BFHICR15 Interrupt Control Register 15 R/W 0 0 0 0 0 1 1 1B
0000C0HHCNT0 USB Host Control Register 0 R/W
USB Mini HOST
0 0 0 0 0 0 0 0B
0000C1HHCNT1 USB Host Control Register 1 R/W 0 0 0 0 0 0 0 1B
0000C2HHIRQ USB Host Interruption Register R/W 0 0 0 0 0 0 0 0B
0000C3HHERR USB Host Error Status Register R/W 0 0 0 0 0 0 1 1B
0000C4HHSTATE USB Host State Status Register R/W XX 0 1 0 0 1 0B
0000C5HHFCOMP USB SOF Interrupt FRAME compare
Register R/W 0 0 0 0 0 0 0 0B
0000C6H
HRTIMER USB Retry Timer Setting Register 0 R/W 0 0 0 0 0 0 0 0B
0000C7HUSB Retry Timer Setting Register 1 R/W 0 0 0 0 0 0 0 0B
0000C8HUSB Retry Timer Setting Register 2 R/W XXXXXX 0 0B
0000C9HHADR USB Host Address Register R/W X 0 0 0 0 0 0 0B
0000CAHHEOF USB EOF Setting Register 0 R/W 0 0 0 0 0 0 0 0B
0000CBHUSB EOF Setting Register 1 R/W XX 0 0 0 0 0 0B
0000CCHHFRAME USB FRAME Setting Register 0 R/W 0 0 0 0 0 0 0 0B
0000CDHUSB FRAME Setting Register 1 R/W XXXXX 0 0 0B
0000CEHHTOKEN USB Host Token End Point Register R/W 0 0 0 0 0 0 0 0B
0000CFHProhibited
0000D0HUDCC UDC Control Register R/W USB function 1 0 1 0 0 0 0 0B
0000D1HProhibited
Preliminary
2004.01.09
MB90335 Series
19
(Continued)
Address Register
abbreviation Register Read/
Write Resource name Initial Value
0000D2HEP0C EP0 Control Register R/W
USB Function
X 1 0 0 0 0 0 0B
0000D3HR/W XXXX 0 0 0 XB
0000D4HEP1C EP1 Control Register R/W 0 0 0 0 0 0 0 0B
0000D5HR/W 0 1 1 0 0 0 0 1B
0000D6HEP2C EP2 Control Register R/W 0 1 0 0 0 0 0 0B
0000D7HR/W 0 1 1 0 0 0 0 0B
0000D8HEP3C EP3 Control Register R/W 0 1 0 0 0 0 0 0B
0000D9HR/W 0 1 1 0 0 0 0 0B
0000DAHEP4C EP4 Control Register R/W 0 1 0 0 0 0 0 0B
0000DBHR/W 0 1 1 0 0 0 0 0B
0000DCHEP5C EP5 Control Register R/W 0 1 0 0 0 0 0 0B
0000DDHR/W 0 1 1 0 0 0 0 0B
0000DEHTMSP Time Stamp Register R 0 0 0 0 0 0 0 0B
0000DFHR/W 0 0 0 0 0 0 0 0B
0000E0HUDCS UDC Status Register R/W 0 0 0 0 0 0 0 0B
0000E1HUDCIE Interrupt Enable Register R/W 0 0 0 0 0 0 0 0B
0000E2HEP0IS EP0I Status Register R/W XXXXXXXXB
0000E3HR/W 1 0 XXX 1 XXB
0000E4HEP0OS EP0O Status Register R/W XXXXXXXXB
0000E5HR/W 1 0 0 XX 0 0 XB
0000E6HEP1S EP1 Status Register R XXXXXXXXB
0000E7HR/W 1 0 0 0 0 0 0 XB
0000E8HEP2S EP2 Status Register R XXXXXXXXB
0000E9HR/W 1 0 0 0 0 0 0 XB
0000EAHEP3S EP3 Status Register R XXXXXXXXB
0000EBHR/W 1 0 0 0 0 0 0 XB
0000ECHEP4S EP4 Status Register R XXXXXXXXB
0000EDHR/W 1 0 0 0 0 0 0 XB
0000EEHEP5S EP5 Status Register R XXXXXXXXB
0000EFHR/W 1 0 0 0 0 0 0 XB
0000F0HEP0DT EP0 Data Register R/W XXXXXXXXB
0000F1HR/W XXXXXXXXB
0000F2HEP1DT EP1 Data Register R/W XXXXXXXXB
0000F3HR/W XXXXXXXXB
0000F4HEP2DT EP2 Data Register R/W XXXXXXXXB
0000F5HR/W XXXXXXXXB
0000F6HEP3DT EP3 Data Register R/W XXXXXXXXB
0000F7HR/W XXXXXXXXB
0000F8HEP4DT EP4 Data Register R/W XXXXXXXXB
0000F9HR/W XXXXXXXXB
Preliminary
2004.01.09
MB90335 Series
20
(Continued)
Address Register
abbreviation Register Read/
Write Resource name Initial Value
0000FAHEP5DT EP5 Data Register R/W USB Function XXXXXXXXB
0000FBHR/W XXXXXXXXB
0000FCH
to
0000FFHProhibited
000100H
to
001100HRAM Area
001FF0H
PADR0
Program Address Detection Register
ch0 Lower R/W
Address Match
Detection
XXXXXXXXB
001FF1HProgram Address Detection Register
ch0 Middle R/W XXXXXXXXB
001FF2HProgram Address Detection Register
ch0 Higher R/W XXXXXXXXB
001FF3H
PADR1
Program Address Detection Register
ch1 Lower R/W XXXXXXXXB
001FF4HProgram Address Detection Register
ch1 Middle R/W XXXXXXXXB
001FF5HProgram Address Detection Register
ch1 Higher R/W XXXXXXXXB
007900HPRLL0 PPG Reload Register Lower ch0 R/W PPG ch0 XXXXXXXXB
007901HPRLH0 PPG Reload Register Higher ch0 R/W XXXXXXXXB
007902HPRLL1 PPG Reload Register Lower ch1 R/W PPG ch1 XXXXXXXXB
007903HPRLH1 PPG Reload Register Higher ch1 R/W XXXXXXXXB
007904HPRLL2 PPG Reload Register Lower ch2 R/W PPG ch2 XXXXXXXXB
007905HPRLH2 PPG Reload Register Higher ch2 R/W XXXXXXXXB
007906HPRLL3 PPG Reload Register Lower ch3 R/W PPG ch3 XXXXXXXXB
007907HPRLH3 PPG Reload Register Higher ch3 R/W XXXXXXXXB
007908H
to
00790BHProhibited
00790CHFWR0 Flash Program Control Register 0 R/W Flash 0 0 0 0 0 0 0 0B
00790DHFWR1 Flash Program Control Register 1 R/W Flash 0 0 0 0 0 0 0 0B
00790EHSSR0 Sector Conversion Setting Register R/W Flash 0 0 XXXXX0B
00790FH
to
00791FHProhibited
Preliminary
2004.01.09
MB90335 Series
21
(Continued)
• Explanation on read/write
• Explanation of initial values
Note : No IO instruction can be used for registers located between 007900H to 007FFFH.
Address Register
abbreviation Register Read/
Write Resource name Initial Value
007920HDBAPL DMA Buffer Address Pointer Lower 8-bit R/W
µDMAC
XXXXXXXXB
007921HDBAPM DMA Buffer Address Pointer Middle 8-bit R/W XXXXXXXXB
007922HDBAPH DMA Buffer Address Pointer Higher 8-bit R/W XXXXXXXXB
007923HDMACS DMA Control Register R/W XXXXXXXXB
007924HDIOAL DMA I/O Register Address Pointer Lower
8-bit R/W XXXXXXXXB
007925HDIOAH DMA I/O Register Address Pointer
Higher 8-bit R/W XXXXXXXXB
007926HDDCTL DMA Data Counter Lower 8-bit R/W XXXXXXXXB
007927HDDCTH DMA Data Counter Higher 8-bit R/W XXXXXXXXB
007928H
to
007FFFHProhibited
R/W Read and write enabled
R Read only
W Write only
0 : Initial Value is “0”.
1 : Initial Value is “1”.
X : Initial Value is undefined.
- : Initial Value is undefined (None).
Preliminary
2004.01.09
MB90335 Series
22
■INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source EI2OS
support µ
µµ
µDMAC Interrupt vector Interrupt control
register Priori-
ty
Number* Address ICR Address
Reset × × #08 08HFFFFDCHHigh
INT 9 instruction × × #09 09HFFFFD8H
Exceptional treatment × × #10 0AHFFFFD4H
USB Function1 × 0, 1 #11 0BHFFFFD0HICR00 0000B0H
USB Function2 × 2 to 6 #12 0CHFFFFCCH
USB Function3 × × #13 0DHFFFFC8HICR01 0000B1H
USB Function4 × × #14 0EHFFFFC4H
USB Mini-HOST1 × × #15 0FHFFFFC0HICR02 0000B2H
USB Mini-HOST2 × × #16 10HFFFFBCH
I2C ch0 × × #17 11HFFFFB8HICR03 0000B3H
DTP/External interrupt ch0/1 × #18 12HFFFFB4H
No #19 13HFFFFB0HICR04 0000B4H
DTP/External interrupt ch2/3 × #20 14HFFFFACH
No #21 15HFFFFA8HICR05 0000B5H
DTP/External interrupt ch4/5 × #22 16HFFFFA4H
PWC/Reload timer ch0 14 #23 17HFFFFA0HICR06 0000B6H
DTP/External interrupt ch6/7 × #24 18HFFFF9CH
No #25 19HFFFF98HICR07 0000B7H
No #26 1AHFFFF94H
No #27 1BHFFFF90HICR08 0000B8H
No #28 1CHFFFF8CH
No #29 1DHFFFF88HICR09 0000B9H
PPG ch0/1 × × #30 1EHFFFF84H
No #31 1FHFFFF80HICR10 0000BAH
PPG ch2/3 × × #32 20HFFFF7CH
No #33 21HFFFF78HICR11 0000BBH
No #34 22HFFFF74H
No #35 23HFFFF70HICR12 0000BCH
No #36 24HFFFF6CH
UART (Send completed) ch0/ch1 13 #37 25HFFFF68HICR13 0000BDH
Extended serial I/O × 9 #38 26HFFFF64H
UART(Reception completed) ch0/ch1 12 #39 27HFFFF60HICR14 0000BEH
Time-base timer × × #40 28HFFFF5CH
Flash memory status × × #41 29HFFFF58HICR15 0000BFH
Delayed interrupt output module × × #42 2AHFFFF54HLow
Preliminary
2004.01.09
MB90335 Series
23
: Available. EI2OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal.
There is a stop demand.)
: Available (The interrupt request flag is cleared by the interrupt clear signal).
: Available when any interrupt source sharing ICR is not used.
× : Unavailable
• If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted, the
EI2OS is activated when either of the factors is detected. As any interrupt other than the activation factor is
masked while the EI2OS is running, it is recommended that you should mask either of the interrupt requests
when using the EI2OS.
• The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt factors
in the same interrupt control register (ICR).
Note : If a resource has two interrupt sources for the same interrupt number , both of the interrupt request flags are
cleared by the µDMA C interrupt clear signal. Theref ore, when y ou use either of two interrupt f actors f or the
DMA C function, another interrupt function is disabled. Set the interrupt request permission bit to " 0 " in the
appropriate resource, and take measures by software polling.
■
■■
■USB INTERRUPT FACTOR CONTENTS
USB interrupt factor Details
USB function 1 End Point0-IN, EndPoint 0-OUT
USB function 2 End Point 1-5
USB function 3 VOFF, VON, SUSP, SOF, BRST, WKOP, COHF
USB function 4 SPIT
USB Mini-HOST1 DIRQ, CHHIRQ, URIRQ, RWKIRQ
USB Mini-HOST2 SOFIRQ, CMPIRQ
Preliminary
2004.01.09
MB90335 Series
24
■
■■
■PERIPHERAL RESOURCES
1. I/O port
• The I/O por ts are used as general-pur pose input/output por ts (parallel I/O por ts). MB90335 ser ies model is
provided with 6 ports (45 inputs) . The ports function as input/output pins for peripheral functions also.
• An I/O port, using port data register (PDR) , outputs the output data to I/O pin and input a signal input to I/O
port. The port direction register (DDR) specifies direction of input/output of I/O pins on a bit-by-bit basis.
• The following table lists the I/O ports and the peripheral functions with which they share pins.
Port pin name Pin Name (Peripheral) Peripheral Function that Shares Pin
Port 0 P00 to P07
Port 1 P10 to P17
Port 2 P20 to P23
P24 to P27 PPG0 to PPG3 8/16 bit PPG timer 0, 1
Port 4 P40, P41 TIN0, TOT0 16-bit reload timer
P42 to P47 SIN0, SOT0, SCK0,
SIN1, SOT1, SCK1 UART0, 1
Port 5 P50 to P54
Port 6
P60, P61 INT0, INT1 External interrupt
P62 to P64 INT2 to INT4,
SIN, SOT, SCK External interrupt, serial IO
P65 INT5, PWC External interrupt, PWC
P66, P67 INT6, INT7, SCL0, SDA0 External interrupt, I2C
Preliminary
2004.01.09
MB90335 Series
25
• Register list (port data register)
* : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows:
• Input mode
Read : The level at the relevant pin is read.
Write : Data is written to the output latch.
• Output mode
Read : The data register latch value is read.
Write : Data is output to the relevant pin.
PDR0 Initial Value Access
Address : 000000HXXXXXXXXBR/W*
PDR1
Address : 000001HXXXXXXXXBR/W*
PDR2
Address : 000002HXXXXXXXXBR/W*
PDR4
Address : 000004HXXXXXXXXBR/W*
PDR5
Address : 000005H- - - XXXXXBR/W*
PDR6
Address : 000006HXXXXXXXXBR/W*
76543210
P06P07 P05 P04 P03 P02 P01 P00
15 14 13 12 11 10 9 8
P16P17 P15 P14 P13 P12 P11 P10
76543210
P26P27 P25 P24 P23 P22 P21 P20
76543210
P46P47 P45 P44 P43 P42 P41 P40
15 14 13 12 11 10 9 8
P54 P53 P52 P51 P50
76543210
P66 P65 P64 P63 P62 P61 P60
P67
Preliminary
2004.01.09
MB90335 Series
26
• Register list (port direction register)
• When each pin is serving as a port, the corresponding pin is controlled as follows:
0 : Input mode
1 : Output mode
This bit becomes 0 after a reset.
Note : If these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits
manipulated by the instruction are set to prescribed values but those other bits in output registers which
hav e been set f or input are re written to the current input values of the pins . When s witching a pin from input
port to output port, therefore, write a desired value in the PDR first, then set the DDR to switch the pin for
output.
• Register list (Port pull-up register)
Controls the pull-up resistor in input mode.
0 : Without pull-up resistor in input mode.
1 : With Pull-up resistor in input mode.
Meaningless in output mode (without pull-up resistor) ./ The input/output register is decided by the setting of the
direction register (DDR) .
No pull-up resistor is used in stop mode (SPL = 1).
DDR0 Initial Value Access
Address : 000010H00000000BR/W
DDR1
Address : 000011H00000000BR/W
DDR2
Address : 000012H00000000BR/W
DDR4
Address : 000014H00000000BR/W
DDR5
Address : 000015H- - - 00000BR/W
DDR6
Address : 000016H00000000BR/W
76543210
D06D07 D05 D04 D03 D02 D01 D 00
15 14 13 12 11 10 9 8
D16D17 D15 D14 D13 D12 D11 D10
76543210
D26D27 D25 D24 D23 D22 D21 D20
76543210
D46D47 D45 D44 D43 D42 D41 D40
15 14 13 12 11 10 9 8
D54 D53 D52 D51 D50
76543210
D66D67 D65 D64 D63 D62 D61 D60
RDR0 Initial Value Access
Address : 00001CH00000000BR/W
RDR1
Address : 00001DH00000000BR/W
76543210
RD06RD07 RD05 RD04 RD03 RD02 RD01 RD00
15 14 13 12 11 10 9 8
RD16RD17 RD15 RD14 RD13 RD12 RD11 RD10
Preliminary
2004.01.09
MB90335 Series
27
• Register list (output pin register)
Controls open-drain output in output mode.
0 : Serves as a standard output por t in output mode.
1 : Serves as an open-drain output port in output mode.
Meaningless in input mode. (output High-Z) / The input/output register is decided by the setting of the direction
register (DDR) .
• Block diagram of port 0 pin and port1 pin
• Block diagram of port 2 pin, port 4 pin, port 5 pin and port 6 pin
ODR4 Initial Value Access
Address : 00001BH00000000BR/W
76543210
OD46OD47 OD45 OD44 OD43 OD42 OD41 OD40
Pull-up resistor
setting register
(RDRx)
Port data
register
(PDRx)
Port direction
register
(DDRx)
I/O
decision circuit
Input
buffer
Output
buffer
Internal data bus
PDRx read
PDRx
Write
Port
pin
Built-in pull-up
resistor
Standby control (LPMCR : SPL = “1”)
Port data
register
(PDRx)
Port direction
register
(DDRx)
I/O
decision circuit
input
buffer
Output
buffer
Internal data bus
PDRx read
PDRx
write
Port
pin
Standby control (LPMCR : SPL = “1”)
Resource output control signal
Release output
Resource input
Preliminary
2004.01.09
MB90335 Series
28
2. Time-base timer
• The time-base timer is an 18-bit free-running counter (time-base timer counter) that counts in synchronization
with the main clock (2 cycles of the oscillation clock HCLK).
• Four different time intervals can be selected, for each of which an interrupt request can be generated.
• Operating clock signals are supplied to peripheral resources such as the oscillation stabilization wait timer and
watchdog timer.
•
••
• Interval time of time-base timer
Notes : •HCLK : Oscillation clock frequency
•The parenthesized values assume an oscillator clock frequency of 6 MHz.
•
••
• Clock cycles supplied from time-base timer
Notes : •HCLK : Oscillation clock frequency
•The parenthesized values assume an oscillator clock frequency of 6 MHz.
• Register list
Note : For the conditions for clearing the time-base timer, refer to the chapter for the time-base timer in the hardware
manual.
Internal count clock cycle Interval time
2/HCLK (0.33 µs)
212/HCLK (Approx. 0.68 ms)
214/HCLK (Approx. 2.7 ms)
216/HCLK (Approx. 10.9 ms)
219/HCLK (Approx. 87.4 ms)
Where to supply clock Clock cycle
Oscillation stabilization wait of
main clock
213/HCLK (Approx. 1.36 ms)
215/HCLK (Approx. 5.46 ms)
217/HCLK (Approx. 21.84 ms)
Watch dog timer
212/HCLK (Approx. 0.68 ms)
214/HCLK (Approx. 2.7 ms)
216/HCLK (Approx. 10.9 ms)
219/HCLK (Approx. 87.4 ms)
Time-base timer control register (TBTC) Initial Value
Address : 0000A9H1--00100B
( )( ) ( R/W ) ( R/W ) ( W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
( R/W )
RESV TBIE TBOF TBR TBC1 TBC0
Preliminary
2004.01.09
MB90335 Series
29
• Block Diagram
Actual interrupt request number of time-base timer is as follows:
Interrupt request number:#40 (28H)
TBIE TBOF TBRRESV TBC1 TBC0
OF OF OF OF
× 21× 22× 28× 29× 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
To PPG timer
Time-base timer counter
Dividing HCLK by 2
To
watchdog
timer
CKSCR : MCS = 1→0*1
Counter
clear control
circuit
Interval timer selector
TBOF clear
Time-base timer control register (TBTC)
Time-base timer interrupt signal
To clock controller
oscillation stabilizing
wait time selector
TBOF
set
:Unused
OF :Overflow
HCLK :Oscillation clock
*1 :Switching the machine clock from main clock to PLL clock
Power-on reset
Stop mode start
Preliminary
2004.01.09
MB90335 Series
30
3. Watchdog timer
• The watchdog timer is a timer counter prepared in case programs run out of control.
• The watchdog timer is a 2-bit counter using the time-base timer as the count clock.
• When started, the watchdog timer resets the CPU if it is not cleared before the two-bit counter overflows.
•
••
• Interval time of watchdog timer
Notes : •The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing.
•The watchdog timer contains a 2-bit counter that counts the carry signals of the time-base timer . When
the de vice is operating with HCLK, theref ore, clearing the time-base timer lengthens the watchdog reset
generation time interval.
• Event that stop the watchdog timer
1 : Stop due to a Power-on reset
2 : watchdog reset
• Clear factor of watch dog timer
1 : External reset input by RST pin
2 : Writing “0” to the software reset bit
3 : Writing “0” to the watchdog control bit (second and subsequent times)
4 : Transition to sleep mode (Clearing the watchdog timer, and suspend counting)
5 : Transition to time-base timer mode (Clearing the watchdog timer, and suspend counting)
6 : Transition to stop mode (Clearing the watchdog timer, and suspend counting)
• Register list
HCLK: Oscillation clock (6 MHz)
Min Max Clock cycle
Approx. 2.39 ms Approx. 3.07 ms 214 ± 211 / HCLK
Approx. 9.56 ms Approx. 12.29 ms 216 ± 213 / HCLK
Approx. 38.23 ms Approx. 49.15 ms 218 ± 215 / HCLK
Approx. 305.83 ms Approx. 393.22 ms 221 ± 218 / HCLK
Watchdog timer control register (WDTC) Initial Value
Address : 0000A8HX-XXX111B
( ) ( R ) ( R ) ( R ) ( W ) ( W ) ( W )
76543210
( R )
PONR WRST ERST SRST WTE WT1 WT0
Preliminary
2004.01.09
MB90335 Series
31
• Block Diagram
PONR WRST ERST SRST WTE WT1 WT0
× 21× 22× 28× 29× 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
CLR
CLR
2
4
Watchdog timer control register (WDTC)
Watchdog timer
Timer-base timer mode start
Sleep mode start
Counter
clear control
circuit
Count clock
selector 2-bit
counter
watchdog timer
reset
generation
circuit
To
internal
reset
generation
circuit
CLR and
start
Time-base timer counter
Dividing HCLK by 2
HCLK: Oscillation clock
Clear
Stop mode start
Preliminary
2004.01.09
MB90335 Series
32
4. 16 - bit Reload Timer
The 16-bit reload timer has the internal clock mode to be decrement in synchronization with three different
inter nal clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input
to the external pin. Either can be selected. This timer defines when the count value changes from 0000H to
FFFFH as an underflow. The timer therefore causes an underflow when the count reaches [reload register
setting +1]. Either mode can be selected f or the count oper ation from the reload mode which repeats the count
by reloading the count setting va lue at the underflow occurrence or the one-shot mode which stops the count
at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to
correspond to the DTC.
• Register list
• Timer control status register
Timer control status register (Higher) (TMCSR0)
Timer control status register (Lower) (TMCSR0)
• 16-bit timer register/16-bit reload register
TMR0/TMRLR0 (Higher)
TMR0/TMRLR0 (Lower)
Initial Value
Address : 000063HXXXX0000B
Initial Value
Address : 000062H00000000B
Initial Value
Address : 000065HXXXXXXXXB
Initial Value
Address : 000064HXXXXXXXXB
( )( )( ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
( )
CSL1 CSL0 MOD2 MOD1
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
OUTE
( R/W )
MOD0 OUTL RELD INTE UF CNTE TRG
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
D14
( R/W )
D15 D13 D12 D11 D10 D09 D08
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
D06
( R/W )
D07 D05 D04 D03 D02 D01 D00
Preliminary
2004.01.09
MB90335 Series
33
• Block Diagram
TMRLR0
TMR0
CLK
TIN0
UF
EN TOT0
CLK
3
32
CSL1 CSL0 MOD2MOD1MOD0OUTE OUTL RELD UFINTE CNTE TRG
∗2
Internal data bus
16-bit reload register
16-bit timer register
Reload signal Reload
control circuit
Wait signal
Output control circuit
Output signal
generation
circuit Pin
Valid
clock
decision
circuit
Clock
selector
Operating
Control
circuit
Select
signal
External clock
Internal
clock
Input
control
circuit
Pin
Prescaler
Count clock generation circuit
Gate
input
Timer control status register (TMCSR0) Interrupt
request output
#23 (17H)*1
Select
function
Clear
Trriger
Machine
clock φ
*1 : Interrupt number
*2 : Underflow
Preliminary
2004.01.09
MB90335 Series
34
5. Multifunction timer
• The multifunction timer can be used for waveform output, input pulse width measurement, and e xternal clock
cycle measurement.
•
••
• Configuration of a multi-functional timer
• 8/16 bit PPG timer (8 bit : 4 channels, 16 bit : 2 channels)
8/16 bit PPG timer consists of a 8 bit down counter (PCNT) , PPG control register (PPGC0 to PPGC3) , PPG
clock control register (PCS01, PCS23) and PPG reload register (PRLL0 to PRLL3, PRLH0 to PRLH3) .
When used as an 8/16 bit reload timer, the PPG timer serves as an event timer. It can also output pulses of an
arbitrary duty ratio at an arbitrary frequency.
• 8 bit PPG mode
Each channel operates as an independent 8 bit PPG.
• 8 bit prescaler + 8 bit PPG mode
Operates as an arbitrary-cycle 8 bit PPG with ch0 (ch2) operating as an 8 bit prescaler and ch2 (ch3) counted
by the borrow output of ch0 (ch2).
• 16 bit PPG mode
Operates as a 16 bit PPG with ch0 (ch2) and ch1 (ch3) connected.
• PPG Operation
The PPG timer outputs pulses of an arbitrary duty ratio (the ratio between the High and Low level per iods of
pulse waveform) at an arbitrary frequency. Can also be used as a D/A converter b y an external circuit.
8/16 bit PPG timer 16 bit PWC timer
8 bit × 4 ch
(16 bit × 2 ch) 1 ch
Preliminary
2004.01.09
MB90335 Series
35
• Register list
PPG operation mode control register
(PPGC1/PPGC3)
(PPGC0/PPGC2)
PPG output control register (PPG01/PPG23)
PPG reload register
(PRLH0 to PRLH3)
(PRLL0 to PRLL3)
Address : 000047H
000049H
Initial Value
0X000001B
Address : 000046H
000048H
Initial Value
0X000XX1B
Address : 00004CH
00004EH
Initial Value
000000XXB
Address :
007901H
007903H
007905H
007907H
Initial Value
XXXXXXXXB
Address :
007900H
007902H
007904H
007906H
Initial Value
XXXXXXXXB
15 14 13 12 11 10 9 8
( R/W ) ( ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
PEN1 PE10 PIE1 PUF1 MD1 MD0 Reserved
76543210
( R/W ) ( ) ( R/W ) ( R/W ) ( R/W ) ( )( ) ( R/W )
PEN0 PE0O PIE0 PUF0
Reserved
76543210
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
PCS1PCS2 PCS0 PCM2 PCM1 PCM0 Reserved
Reserved
15 14 13 12 11 10 9 8
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
D14D15 D13 D12 D11 D10 D09 D08
76543210
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
D06D07 D05 D04 D03 D02 D01 D00
Preliminary
2004.01.09
MB90335 Series
36
• 8 bit PPG ch0/2 block diagram
PPG0/2
PEN0
IRQ
PIE0PUF0
PRLL PRLHB
PRLL
S
RQ
PCNT
(down counter)
Peripheral clock × 16
PPG 0/2 output latch
Count clock
selector
Timebase counter
output main clock × 512
ch1/3/5 borrow
L/H selector
PPGC0
(operation mode control)
* : Interrupt number
To interrupt
#30 (1EH)*
#32 (20H)*
L/H selector
PPG 0/2 output enable
Peripheral clock × 8
Peripheral clock × 4
Peripheral clock × 2
Peripheral clock A/D converter
L data bus
H data bus
Preliminary
2004.01.09
MB90335 Series
37
• 8 bit PPG ch1/3 block diagram
PPG1/3
PEN1
IRQ
PIE1PUF1
PRLL PRLHB
PRLL
S
RQ
PCNT0
(down counter)
Peripheral clock × 16
PPG 1/3 output latch
Count clock
selector
Timebase counter
output main clock × 512
L/H selector
PPGC0
(operation mode control)
* : Interrupt number
To interrupt
#30 (1EH)*
#32 (20H)*
L/H selector
PPG 1/3 output enable
Peripheral clock × 8
Peripheral clock × 4
Peripheral clock × 2
Peripheral clock
L data bus
H data bus
Preliminary
2004.01.09
MB90335 Series
38
• PWC timer
The PWC timer is a 16 bit multifunction up-count timer capable of measuring the input signal pulse width.
• Register list
PWC control status register (PWCSR)
PWC data buffer register (PWCR)
Ratio of dividing frequency control register (DIVR)
Initial Value
Address : 00005DH0000000XB
Initial Value
Address : 00005CH00000000B
Initial Value
Address : 00005FH00000000B
Initial Value
Address : 00005EH00000000B
Initial Value
Address : 000060H------00B
( R/W ) ( R ) ( R/W ) ( R/W ) ( R/W ) ( R ) ( R/W )
15 14 13 12 11 10 9 8
STOP
( R/W )
STRT EDIR EDIE OVIR OVIE ERR Reserved
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
CKS0
( R/W )
CKS1 PIS1 PIS0 S/C MOD2 MOD1 MOD0
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
D14
( R/W )
D15 D13 D12 D11 D10 D9 D8
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
D6
( R/W )
D7 D5 D4 D3 D2 D1 D0
( )( )( )( )( ) ( R/W ) ( R/W )
76543210
( )
DIV1 DIV0
Preliminary
2004.01.09
MB90335 Series
39
• Block Diagram
ERR
PWCR
16
16
CKS1/CKS0
15
ERR CKS0/CKS1
PIS0/PIS1
PWCSR
DIVR
2
22
23
PWC
PWCR read Error
detection
Reload
Data transfer
Over-
flow 16 bit up-count timer Clock
Internal clock
(Machine clock/4)
Clock
devider
Control circuit
Timer
clear Count enable
Divider
clear
Flag set etc...
Control bit output
Start edge
selection
Measurement
termination edge
end edge
selection
Edge
detection
Divider ON/OFF
Measurement
starting edge
Overflow interrupt
request Divide ratio
select
8-bit
divider
F2MC-16 bus
Measurement
termination interrupt
request
Input
waveform
comparator
Preliminary
2004.01.09
MB90335 Series
40
6. UART
Overview of UART
• UAR T is a gener al purpose serial communication interface f or synchronous or asynchronous (start-stop syn-
chronization) communications with external devices.
• It supports bi-directional communication (normal mode) and master/slave communication (multi-processor
mode: supported on master side only).
• An interrupt can be generated upon completion of reception, detection of a reception errror, or upon completion
of transmission. EI2OS is supported also.
• UART functions
UART, or a generic serial data communication interface that sends and receives serial data to and from other
CPU and peripherals, has the functions listed in following.
Note : In clock synchronous transfer mode, the UART transfers only data with no start or stop bit added.
UART operation modes
: Setting disabled
*1 : + 1 is an address/data setting bit (A/D) which is used for communication control.
*2 : Only one bit can be detected as a stop bit at reception.
Operation mode Data length Synchronization Stop bit length
Without parity With parity
0 Normal mode 7 bits or 8 bits Asynchronous 1 bit or 2 bits *2
1 Multi processor mode 8 + 1 *1Asynchronous
2 Normal mode 8 Synchronous No
Function
Data buffer Full-duplex double-buffered
Transmission mode • Clock synchronous (without start/stop bit)
• Clock asynchronous (start-stop synchronous)
Baud rate • Special-purpose baud-rate generator
It is optional from eight kinds.
• Baud rate by external clock (clock of SCK0/SCK1 terminal input)
Data length • 8 bits or 7 bits (in the asynchronous normal mode only)
• 1 to 8 bits (in the synchronous mode only)
Signaling system Non Return to Zero (NRZ) system
Reception error detection • Framing error
• Overrun error
• Parity error (Not supported in operation mode 1)
Interrupt request • Receive interrupt (reception completed, reception error detected)
• Transmission interrupt (transmission completed)
• Both the transmission and reception support EI2OS.
Master/slave type
communication function
(multi processor mode) Capable of 1 (master) to n (slaves) communication (available just as master)
Preliminary
2004.01.09
MB90335 Series
41
• Register list
Serial mode register (SMR0, SMR1)
Serial control register (SCR0, SCR1)
Serial input/output register (SIDR0, SIDR1 / SODR0, SODR1)
Serial data register (SSR0, SSR1)
UART prescaler reload register (UTRLR0, UTRLR1)
UART prescaler control register (UTCR0, UTCR1)
000020H
000026H
Initial Value
Address : 00100000B
000021H
000027H
Initial Value
Address : 00000100B
000022H
000028H
Initial Value
Address : XXXXXXXXB
000023H
000029H
Initial Value
Address : 00001000B
000024H
00002AH
Initial Value
Address : 00000000B
000025H
00002BH
Initial Value
Address : 0000-000B
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
MD0
( R/W )
MD1 SCKL M2L2 M2L1 SCKE SOE
M2L0
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
P
( R/W )
PEN SBL CL A/D REC RXE TXE
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
D6
( R/W )
D7 D5 D4 D3 D2 D1 D0
( R ) ( R ) ( R ) ( R ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
ORE
( R )
PE FRE RDRF TDRE BDS RIE TIE
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
D6
( R/W )
D7 D5 D4 D3 D2 D1 D0
( R/W ) ( R/W ) ( R/W ) ( ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
SRST
( R/W )
MD CKS D10 D9 D8
Reserved
Preliminary
2004.01.09
MB90335 Series
42
・Block Diagram
MD1
MD0
SCKL
M2L2
M2L1
M2L0
SCKE
SOE
PEN
P
SBL
CL
A/D
REC
RXE
TXE
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
SIDR0, SIDR1
SCK0, SCK1
SOT0, SOT1
#39 (27H)∗
#37 (25H)∗
SIN0, SIN1
SODR0, SODR1
SMR0,
SMR1 SCR0,
SCR1 SSR0,
SSR1
Reception
complete
Control bus
Special-purpose
baud-rate generator
(UART prescaler
control register
UTCR0, 1) Clock
selector
Receive status
decision circuit Reception error
occurrence signal for
EI2OS (to CPU)
Reception
clock Reception
control
circuit
Start bit
detection circuit
Reception bit
counter
Reception parity
counter
Shift register for
reception
Internal data bus
Transmission
clock
Reception interrupt
signal
Transmission
control circuit
Transmission
start circuit
Transmission bit
counter
Transmission
parity counter
Shift register for
transmission
Start
transmission
* : Interrupt number
Send interrupt signal
Pin
Pin
Pin
Preliminary
2004.01.09
MB90335 Series
43
7. Extended I/O serial interface
The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8-bit ×
1 channel configured clock synchronization scheme. LSB-first or MSB-first transfer mode can be selected for
data transfer.
There are two serial I/O operation modes available:
• Internal shift clock mode: Transfer data in synchronization with the internal clock.
• External shift clock mode: Transf er data in synchronization with the cloc k supplied via the external pin (SCK).
By manipulating the general-purpose port sharing the external pin (SCK) in this
mode, data can also be transferred by a CPU instruction.
• Register list
Serial mode control status register (SMCS)
Serial data register (SDR)
Communication prescaler control register (SDCR)
Initial Value
Address : 000059H00000010 B
Initial Value
Address : 000058HXXXX0000 B
Initial Value
Address : 00005AHXXXXXXXXB
Initial Value
Address : 00005BH0XXX0000B
15 14 13 12 11 10 9 8
SMD1SMD2 SMD0 SIE SIR BUSY STOP STRT
( R/W ) ( R/W ) ( R/W ) ( R/W )
( R/W )
( R/W )( R/W )( R/W )
76543210
MODE BDS SOE SCOE
( ) ( )
( )
( ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
D6D7 D5 D4 D3 D2 D1 D0
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )( R/W )
( R/W )
( )( )( ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
( R/W )
MD DIV3 DIV2 DIV1 DIV0
Preliminary
2004.01.09
MB90335 Series
44
• Block Diagram
SIN
SOT
SCK
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS
21 0
SOE SCOE
(MSB first) D0 to D7 D7 to D0 (LSB first)
SDR (serial data register)
Internal clock
Internal data bus
Transfer direction selection
Read
Write
Control circuit Shift clock counter
Interrupt
request
Internal data bus
Initial Value
Preliminary
2004.01.09
MB90335 Series
45
8. I2C Interface
The I2C interface is a serial I/O port supporting the Inter IC BUS. It serves as a master/slave device on the I2C
bus and has the following features.
• Master/slave sending and receiving
• Arbitration function
• Clock synchronization function
• Slave address and general call address detection function
• Detecting transmitting direction function
• Start condition repeated generation and detection function
• Bus error detection function
• Register list
I2C bus status register (IBSR0)
I2C bus control register (IBCR0)
I2C bus clock selection register (ICCR0)
I2C bus address register (IADR0)
I2C bus data register (IDAR0)
Initial Value
Address : 000070H00000000B
Initial Value
Address : 000071H00000000B
Initial Value
Address : 000072HXXX0XXXXB
Initial Value
Address : 000073HXXXXXXXXB
Initial Value
Address : 000074HXXXXXXXXB
( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R )
76543210
RSC
( R )
BB AL LRB TRX AAS GCA FBT
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
BEIE
( R/W )
BER SCC MSS ACK GCAA INTE INT
( ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
( )
EN CS4 CS3 CS2 CS1 CS0
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
A6
( )
A5 A4 A3 A2 A1 A0
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
D6
( R/W )
D7 D5 D4 D3 D2 D1 D0
Preliminary
2004.01.09
MB90335 Series
46
• Block Diagram
ICCR
EN
ICCR
IBSR
BB
RSC
LRB Last Bit
TRX
FBT
AL
IBCR
BER
BEIE
INTE
INT
IBCR
SCC
MSS
ACK
GCAA
IBSR
IDAR
IADR
AAS
GCA
CS4
CS3
CS2
CS1
CS0
2 4 8 16 128 25632 64
56 78
Sync
First Byte
IRQ
SCL0
SDA0
I2C enable
Clock devide 2
Clock selector 2
Bus busy
Repeat start
Send/receive
Start stop condition
generation
Arbitration lost detection
Interrupt request
Start
Master
ACK enable
GC-ACK enable
Slave Slave address
compare
End
Error
Shift clock edge
change timing
Start stop condition
detection
Generating shift clock
F2MC-16 bus
Clock devide 1
Clock selector 1
Peripheral clock
Global call
Preliminary
2004.01.09
MB90335 Series
47
9. USB Function
The USB is an interface supporting the USB (Universal Serial Bus) communications protocol.
Feature of USB function
• Conform to USB 2.0 Full Speed
• FULL speed (12 Mbps) is supported.
• The device status is auto-answer.
• Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16.
• Toggle check by data synchronization bit.
• A utomatic response to all standard commands e xcept Get/SetDescriptor and SynchF rame commands (these
three commands can be processed the same way as the class v endor commands).
• The class vendor commands can be received as data and responded via firmware.
• Supports up to maximum six EndPoints (EndPoint0 is fixed to control transfer).
• Two transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for end point 0).
• Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint0).
• Capable of detection of connection and disconnection by monitoring the USB bus power line.
• Register list
(Continued)
UDC control register (UDCC)
EP0 control register (EP0C)
EP1 control register (EP1C)
Initial Value
Address : 0000D0H10100000B
Initial Value
Address : 0000D2HX1000000B
Initial Value
Address : 0000D3HXXXX0000B
Initial Value
Address : 0000D4H00000000B
Initial Value
Address : 0000D5H01100001B
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
RESUM
( R/W )
RST HCONX USTP RFBK PWC
Reserved Reserved
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
PKS0
( R/W )
PKS0 PKS0 PKS0 PKS0 PKS0
PKS0
Reserved
( )( )( ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
( )
STAL
Reserved Reserved Reserved
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
PKS1
( R/W )
PKS1 PKS1 PKS1 PKS1 PKS1 PKS1 PKS1
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
TYPE
( R/W )
EPEN TYPE DIR DMAE NULE STAL PKS1
Preliminary
2004.01.09
MB90335 Series
48
(Continued)
EP2/3/4/5 control register (EP2C 〜EP5C)
Time stamp register (TMSP)
UDC status register (UDCS)
Interrupt enable register (UDCIE)
EP0I status register (EP0IS)
Initial Value
Address : 0000D6H
0000D8H01000000B
0000DAH
0000DCH
Initial Value
Address : 0000D7H
0000D9H01100000B
0000DBH
0000DDH
Initial Value
Address : 0000DEH00000000B
Initial Value
Address : 0000DFH00000000B
Initial Value
Address : 0000E0H00000000B
Initial Value
Address : 0000E1H00000000B
Initial Value
Address : 0000E2HXXXXXXXXB
Initial Value
Address : 0000E3H10XXX1XXB
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
PKS2∼5
( R/W )
PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5
Reserved
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
TYPE
( R/W )
EPEN TYPE DIR DMAE NULE STAL Reserved
( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R )
76543210
TMSP
( R )
TMSP TMSP TMSP TMSP TMSP TMSP
TMSP
( )( )( )( ) ( R ) ( R ) ( R )
15 14 13 12 11 10 9 8
( )
TMSP TMSP TMSP
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
VON
( R/W )
VOFF SUSP SOF BRST WKUP SETP CONF
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R ) ( R/W )
15 14 13 12 11 10 9 8
VONIE
( R/W )
VOFFIE SUSPIE SOFIE BRSTIE WKUPIE CONFN CONFIE
( )( )( )( )( )( )( )
76543210
( )
( R/W ) ( )( )( ) ( R/W ) ( )( )
15 14 13 12 11 10 9 8
DRQIIE
( R/W )
BFINI DRQI
Preliminary
2004.01.09
MB90335 Series
49
(Continued)
EP0O status register (EP0OS)
EP1 status register (EP1S)
EP2/3/4/5 status register (EP2S to EP5S)
EP0/1/2/3/4/5 data register (EP0DT to EP5DT)
Initial Value
Address : 0000E4HXXXXXXXXB
Initial Value
Address : 0000E5H100XX00XB
Initial Value
Address : 0000E6HXXXXXXXXB
Initial Value
Address : 0000E7H1000000XB
Initial Value
Address : 0000E8H
0000EAHXXXXXXXXB
0000ECH
0000EEH
Initial Value
Address : 0000E9H
0000EBH1000000XB
0000EDH
0000EFH
0000F0H
0000F2HInitial Value
Address : 0000F4H
0000F6HXXXXXXXXB
0000F8H
0000FAH
0000F1H
0000F3HInitial Value
Address : 0000F5H
0000F7HXXXXXXXXB
0000F9H
0000FBH
( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R )
76543210
SIZE
( )
SIZE SIZE SIZE SIZE SIZE SIZE
( R/W ) ( R/W ) ( )( ) ( R/W ) ( R/W ) ( )
15 14 13 12 11 10 9 8
DRQOIE
( R/W )
BFINI SPKIE DRQO SPK
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
SIZE
( R/W )
SIZE SIZE SIZE SIZE SIZE SIZE
SIZE
( R/W ) ( R/W ) ( ) ( R ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
DRQIE
( R/W )
BFINI SPKIE BUSY DRQ SPK SIZE
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
SIZE
( )
SIZE SIZE SIZE SIZE SIZE SIZE
( R/W ) ( R/W ) ( ) ( R ) ( R/W ) ( R/W ) ( )
15 14 13 12 11 10 9 8
DRQIE
( R/W )
BFINI SPKIE BUSY DRQ SPK
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
BFDT
( R/W )
BFDT BFDT BFDT BFDT BFDT BFDT
BFDT
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
BFDT
( R/W )
BFDT BFDT BFDT BFDT BFDT BFDT BFDT
Preliminary
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MB90335 Series
50
10. USB Mini-HOST
USB Mini-HOST provides minimal host oper ations required and is a function that enables data to be transf erred
to and from Device without PC intervention.
Feature of USB Mini-HOST
• Automatic detection of Low Speed/Full Speed transfer
• Low Speed/Full Speed transfer support
• Automatic detection of connection and cutting device
• Reset sending function support to USB-bus
• Support of IN/OUT/SETUP/SOF token
• In-token handshake packet automatic transmission (excluding STALL)
• Handshake pac ket automatic detection at out-token
• Supports a maximum packet length of 256 bytes
• Error (CRC error/toggle error/time-out) various supports
• Wake-Up function support
Differences between the USB HOST and USB Mini-HOST
: Supported
× : Not supported
HOST Mini-HOST
Hub support ×
Transfer
Bulk transfer
Control transfer
Interrupt transfer
ISO transfer ×
Transfer speed Low Speed
Full Speed
PRE packet support ×
SOF packet support
Error
CRC error
Toggle error
Time-out
Maximum packet < receive
data
Detection of connection and cutting of device
Transfer speed detection
Preliminary
2004.01.09
MB90335 Series
51
• Register list
(Continued)
USB HOST control register 0 (HCONT0)
USB HOST control register 1 (HCONT1)
USB HOST interruption register (HIRQ)
USB HOST error status register (HERR)
USB HOST state status register (HSTATE)
USB SOF interruption FRAME comparison register (HFCOMP)
USB retry timer setting register 0/1/2 (HRTIMER)
Initial Value
Address : 0000C0H00000000B
Initial Value
Address : 0000C1H00000001B
Initial Value
Address : 0000C2H00000000B
Initial Value
Address : 0000C3H00000011B
Initial Value
Address : 0000C4HXX010010B
Initial Value
Address : 0000C5H00000000B
Initial Value
Address : 0000C6H00000000B
Initial Value
Address : 0000C7H00000000B
Initial Value
Address : 0000C8HXXXXXX00B
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
URIRE
( R/W )
RWKIRE CMPIRE CNNIRE DIRE SOFIRE URST HOST
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
( R/W )
SOFSTEPCANCEL RETRY
Reserved Reserved Reserved Reserved Reserved
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
( R/W )
TCAN RWKIRQ URIRQ CMPIRQ CNNIRQ DIRQ SOFIRQ
Reserved
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
RERR
( R/W )
LSTSOF TOUT CRC TGERR STUFF HS HS
( ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R ) ( R )
76543210
( )
ALIVE CLKSELSOFBUSY SUSP TMODE CSTAT
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
( R/W )
FRAME
COMP FRAME
COMP FRAME
COMP FRAME
COMP
FRAME
COMP FRAME
COMP
FRAME
COMP FRAME
COMP
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
RTIMER0
( R/W )
RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
RTIMER1
( R/W )
RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1
( )( )( )( )( ) ( R/W ) ( R/W )
76543210
( )
RTIMER2 RTIMER2
Preliminary
2004.01.09
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52
(Continued)
USB HOST address register (HADR)
USB EOF setting register 0/1 (HEOF)
USB FRAME setting register (HFRAME)
USB token end point register (HTOKEN)
Initial Value
Address : 0000C9HX0000000B
Initial Value
Address : 0000CAH00000000B
Initial Value
Address : 0000CBHXX000000B
Initial Value
Address : 0000CCH00000000B
Initial Value
Address : 0000CDHXXXXX000B
Initial Value
Address : 0000CEH00000000B
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
ADDRESS
( )
ADDRESSADDRESSADDRESSADDRESSADDRESSADDRESS
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
EOF0
( R/W )
EOF0 EOF0 EOF0 EOF0 EOF0 EOF0 EOF0
( ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
( )
EOF1 EOF1 EOF1 EOF1 EOF1 EOF1
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
FRAME0
( R/W )
FRAME0 FRAME0FRAME0 FRAME0FRAME0FRAME0 FRAME0
( )( )( )( ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
( )
FRAME1 FRAME1 FRAME1
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
TKNEN
( R/W )
TGGL TKNEN TKNEN ENDPT ENDPT ENDPT ENDPT
Preliminary
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53
11. DTP/external interrupt circuit
Feature of DTP/external interrupt circuit
DTP (Data Transfer Peripheral)/external interrupt circuit detects the interrupt request input from the external
interrupt input terminal INT7 to INT0, and outputs the interrupt request.
• DTP/external interrupt circuit function
The DTP/e xternal interrupt function outputs an interrupt request upon detection of the edge or le v el signal input
to the external interrupt input pins (INT7 to INT0).
If CPU accept the interrupt request, and if the extended intelligent I/O service (EI2OS) is enabled, branches to
the interrupt handling routine after completing the automatic data transfer (DTP function) performed by EI2OS.
And if EI2OS is disabled, it branches to the interrupt handling routine without activating the automatic data transfer
(DTP function) performed by EI2OS.
•
••
• Feature of DTP/external interrupt circuit
• Register list
External interrupt DTP function
Input pin 8 channels (P60/INT0, P61/INT1, P62/INT2/SIN, P63/INT3/SOT, P64/INT4/SCK,
P65/INT5/PWC, P66/INT6/SCL0, P67/INT7/SDA0)
Interrupt source The detection level or the type of the edge for each terminals can be set in the
request level setting register (ELVR)
Input of “H” level/ “L” level/rising edge/falling edge.
Interrupt number #18 (12H) , #20 (14H) , #22 (16H) , #24 (18H)
Interrupt control Enabling/Prohibit the interrupt request output using the DTP/interrupt enable
register (ENIR)
Interrupt flag Holding the interrupt source using the DTP/interrupt cause register (EIRR)
Process setting Prohibit EI2OS (ICR: ISE=“0”) Enable EI2OS (ICR: ISE=“1”)
Process Branched to the interrupt handling
routine After an automatic data transfer by EI2OS,
Branched to the interrupt handling routine
Interrupt/DTP enable register (ENIR)
Interrupt/DTP source register (EIRR)
Request level setting register (ELVR)
Initial Value
Address : 00003CH00000000B
Initial Value
Address : 00003DH00000000B
Initial Value
Address : 00003EH00000000B
Initial Value
Address : 00003FH00000000B
76543210
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
EN6EN7 EN5 EN4 EN3 EN2 EN1 EN0
15 14 13 12 11 10 9 8
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
ER6ER7 ER5 ER4 ER3 ER2 ER1 ER0
76543210
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
LA3LB3 LB2 LA2 LB1 LA1 LB0 LA0
15 14 13 12 11 10 9 8
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
LA7LB7 LB6 LA6 LB5 LA5 LB4 LA4
Preliminary
2004.01.09
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54
• Block Diagram
LB7
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
P60/INT0
LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
P61/INT1
P62/INT2
SIN
P63/INT3
SOT
#18(12H)∗
#20(14H)∗
#22(16H)∗
#24(18H)∗
22222222
P64/INT4
SCK
P65/INT5
PWC
P66/INT6
SCL0
P67/INT7
SDA0
Request level setting register (ELVR)
Pin
Pin
Pin
Pin
Selector
Selector
Selector
Selector Selector
Selector
Selector
Selector Pin
Pin
Pin
Pin
Interrupt request signal
Internal data bus
DTP/interrupt
source register
(EIRR)
DTP/interrupt
enable register
(ENIR)
* : Interrupt number
DTP/external interrupt input detection circuit
Preliminary
2004.01.09
MB90335 Series
55
12. Interrupt controller
The interrupt control register is located inside the interr upt controller, it exists for every I/O having an interrupt
function. This register has the following functions.
• Setting of the interrupt levels of relevant peripheral
•
••
• Register list
Note : Do not access interrupt control registers using any read modify write instruction because it causes a
malfunction.
• Block Diagram
Interrupt control register
Address：ICR01 : 0000B1H
ICR03 : 0000B3H
ICR05 : 0000B5H
ICR07 : 0000B7H
ICR09 : 0000B9H
ICR11 : 0000BBH
ICR13 : 0000BDH
ICR15 : 0000BFH
ICR01, 03,
05, 07, 09,
11, 13, 15
Read/Write →
Initial Value →
Address：ICR00 : 0000B0H
ICR02 : 0000B2H
ICR04 : 0000B4H
ICR06 : 0000B6H
ICR08 : 0000B8H
ICR10 : 0000BAH
ICR12 : 0000BCH
ICR14 : 0000BEH
ICR00, 02,
04, 06, 08,
10, 12, 14
Read/Write →
Initial Value →
( W )
( 0 ) ( W )
( 0 ) ( W )
( 0 ) ( R/W )
( 0 ) ( R/W )
( 1 ) ( R/W )
( 1 ) ( R/W )
( 1 )
15 14 13 12 11 10 9 8
ICS2
( W )
( 0 )
ICS3 ICS1 ICS0 ISE IL2 IL1 IL0
( W )
( 0 ) ( W )
( 0 ) ( W )
( 0 ) ( R/W )
( 0 ) ( R/W )
( 1 ) ( R/W )
( 1 ) ( R/W )
( 1 )
76543210
ICS2
( W )
( 0 )
ICS3 ICS1 ICS0 ISE IL2 IL1 IL0
IL2 IL1 IL0 32
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Determine
priority
of
interrupt
Interrupt request
(peripheral resource)
(CPU)
Interrupt level
F2MC-16LX bus
Preliminary
2004.01.09
MB90335 Series
56
13. µ
µµ
µDMAC
µDMAC is simple DMA with the function equal with EI2OS. It has 16 channels DMA transfer channels with the
following features.
• Performs automatic data transfer between the peripheral resource (I/O) and memory
• The program execution of CPU stops in the DMA startup
• Capable of selecting whether to increment the transfer source and destination addresses
• DMA transfer is controlled by the DMA enable register, DMA stop status register, DMA status register and
descriptor
• A STOP request is available for stopping DMA transfer from the resource
• Upon completion of DMA transfer, the flag bit corresponding to the transfer completed channel in the DMA
status register is set and a termination interrupt is output to the transfer controller.
• Register list
(Continued)
DMA enable register higher (DERH)
DMA enable register lower (DERL)
DMA stop status register (DSSR)
DMA status register higher (DSRH)
DMA status register lower (DSRL)
DMA descriptor channel specification register (DCSR)
* : The DSSR is lower when the STP bit of DCSR in the DSSR is 0.
The DSSR is upper when the STP bit of DCSR in the DSSR is 1.
Initial Value
Address : 0000ADH00000000B
Initial Value
Address : 0000ACH00000000B
Initial Value
Address : 0000A4H00000000B
*
Initial Value
Address : 00009DH00000000B
Initial Value
Address : 00009CH00000000B
Initial Value
Address : 00009BH00000000B
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
EN14
( R/W )
EN15 EN13 EN12 EN11 EN10 EN9 EN8
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
EN6
( R/W )
EN7 EN5 EN4 EN3 EN2 EN1 EN0
76543210
STP6
STP14
STP7
STP15 STP5
STP13 STP4
STP12 STP3
STP11 STP2
STP10 STP1
STP9 STP0
STP8
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )
15 14 13 12 11 10 9 8
DTE14DTE15 DTE13 DTE12 DTE11 DTE10 DTE9 DTE8
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
DTE6
( R/W )
DTE7 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
( R/W )
STP DCSR3 DCSR2 DCSR1 DCSR0
Reserved Reserved Reserved
Preliminary
2004.01.09
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57
(Continued)
DMA buffer address pointer lower 8 bit (DBAPL)
DMA buffer address pointer middle 8 bit (DBAPM)
DMA Buffer address pointer higher 8 bit (DBAPH)
DMA control register (DMACS)
DMA I/O register address pointer lower 8 bit (DIOAL)
DMA I/O register address pointer higher 8 bit (DIOAH)
DMA data counter lower 8 bit (DDCTL)
DMA data counter higher 8 bit (DDCTH)
Note : The above register is switched for each channel depending on the DCSR.
Initial Value
Address : 007920HXXXXXXXXB
Initial Value
Address : 007921HXXXXXXXXB
Initial Value
Address : 007922HXXXXXXXXB
Initial Value
Address : 007923HXXXXXXXXB
Initial Value
Address : 007924HXXXXXXXXB
Initial Value
Address : 007925HXXXXXXXXB
Initial Value
Address : 007926HXXXXXXXXB
Initial Value
Address : 007927HXXXXXXXXB
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
DBAPL
( R/W )
DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL
15 14 13 12 11 10 9 8
DBAPMDBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )
76543210
DBAPHDBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )
15 14 13 12 11 10 9 8
RDY1RDY2 BYTEL IF BW BF DIR SE
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
A06
( R/W )
A07 A05 A04 A03 A02 A01 A00
15 14 13 12 11 10 9 8
A14A15 A13 A12 A11 A10 A09 A08
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )
76543210
B06B07 B05 B04 B03 B02 B01 B00
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )
15 14 13 12 11 10 9 8
B14B15 B13 B12 B11 B10 B09 B08
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )
Preliminary
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14. Address matching detection function
When the address is equal to the v alue set in the address detection register , the instruction code to be read into
the CPU is forcibly replaced with the INT9 instruction code (01H). As a result, the CPU executes the INT9
instruction when executing the set instruction. By performing processing by the INT#9 interrupt routine, the
program patch function is enabled.
Two address detection registers are provided, for each of which there is an interrupt enable bit. When the address
matches the v alue set in the address detection register with the interrupt enable bit set to 1, the instruction code
to be read into the CPU is forcibly replaced with the INT9 instruction code.
• Register list
• Program address detect register 0 to 2 (PADR0)
• Program address detect register 3 to 5 (PADR1)
• Program address detect control status register (PACSR)
R/W : Readable and Writable
X : Undefined
PADR0 (lower) Initial Value
Address : 001FF0HXXXXXXXXB
PADR0 (middle) Initial Value
Address : 001FF1HXXXXXXXXB
PADR0 (higher) Initial Value
Address : 001FF2HXXXXXXXXB
PADR1 (lower) Initial Value
Address : 001FF3HXXXXXXXXB
PADR1 (middle) Initial Value
Address : 001FF4HXXXXXXXXB
PADR1 (higher) Initial Value
Address : 001FF5HXXXXXXXXB
PACSR Initial Value
Address : 00009EH00000000B
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
76543210
(R/W)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
15 14 13 12 11 10 9 8
(R/W)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
76543210
(R/W)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
15 14 13 12 11 10 9 8
(R/W)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
76543210
(R/W)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
15 14 13 12 11 10 9 8
(R/W)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
76543 210
(R/W)
AD1E AD0E
Reserved Reserved Reserved Reserved Reserved Reserved
Preliminary
2004.01.09
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15. Delay interrupt generator module
• The delay interr upt generation module is a module that generates interrupts for switching tasks. A hardware
interrupt can be generated by software.
• Function of delay interrupt generator module
• Block Diagram
Function and contr ol
Interrupt source
•Setting the R0 bit in the delayed interrupt request generate/cancel register to
1 (DIRR: R0 = 1) generates a interrupt request.
•Setting the R0 bit in the delayed interrupt request generate/cancel register to
0 (DIRR: R0 = 0) cancels the interrupt request.
Interrupt control • No setting of permission register is provided.
Interrupt flag • Set in bit R0 of the delayed interrupt request generation/clear register (DIRR : R0)
EI2OS support • Not ready for expanded intelligent I/O service (EI2OS).
R0
Internal data bus
Delayed Interrupt source/release register (DIRR) S Interrupt request
R Latch
: Undefined bit
Interrupt
request
signal
Preliminary
2004.01.09
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60
16. ROM mirroring function selection module
• The R OM mirror function select module can make a setting so that R OM data located in bank FF can be read
by accessing bank 00.
• RO M mirroring function selection module
• Block Diagram
Description
Mirror setting address FFFFFFH to FF8000H in the FF bank can be read through 00FFFFH to 008000H in
the 00 bank.
Interrupt source • None
EI2OS support • Not ready for extended intelligent I/O service (EI2OS).
MI
ROM
Internal data bus
ROM mirror function selection register (ROMM)
00 bank
FF bank
Address
Data
Address area
Re-
served
Preliminary
2004.01.09
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61
17. Lo w power consumption (standby) mode
•The F
2MC-16LX can be set to save power consumption by selecting and setting the low power consumption
mode.
• CPU operation mode and functional description
• Register list
CPU
operating clock Operation
mode Description
PLL clock
Normally
run The CPU and peripheral resources operate at the clock frequency obtained by
PLL multiplication of the oscillator clock (HCLK) frequency.
Sleep Only peripheral resources operate at the clock frequency obtained by PLL
multiplication of the oscillator clock (HCLK) frequency.
Time-base
timer Only the time-base timer operates at the clock frequency obtained by PLL
multiplication of the oscillator clock (HCLK) frequency.
Stop The CPU and peripheral resources are suspended with the oscillator clock
stopped.
Main clock
normally
run The CPU and peripheral resources operate at the clock frequency obtained by
dividing the oscillator clock (HCLK) frequency by two.
Sleep Only peripheral resources operate at the clock frequency obtained by dividing the
oscillator clock (HCLK) frequency by two.
Time-base
timer Only the time-base timer operates at the clock frequency obtained by dividing the
oscillator clock (HCLK) frequency by two.
Stop The CPU and peripheral resources are suspended with the oscillator clock
stopped.
CPU intermittent
operation mode Normally
run The halved or PLL-multiplied oscillator clock (HCLK) frequency is used for
operation while being decimated in a certain period.
Lowe power consumption mode control register (LPMCR) Initial Value
Address : 0000A0H00011000B
( W ) ( R/W ) ( W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
SLP
( W )
STP SPL RST TMD CG1 CG0 Reserved
Preliminary
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18. Clock
The clock gener ator controls the internal clock as the operating cloc k for the CPU and peripheral resources. The
internal clock is referred to as machine clock whose one cycle is defined as machine cycle. The cloc k based on
source oscillation is ref erred to as oscillator clock while the cloc k based on internal PLL oscillation as PLL clock.
• Register list
Clock selection register (CKSCR) Initial Value
Address : 0000A1H11111100B
( R ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 8
MCM
( R )
SCM WS1 WS0 SCS MCS CS1 CS0
Preliminary
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19. 512 Kbits flash memory
The description that follo ws applies to the flash memory b uilt in the MB90F334; it is not applicable to evaluation
ROM or masked ROM.
The method of data write/erase to flash memory is following three types.
• Parallel writer
• Serial dedicated writer
• Write/erase by executing program
• Description of 512 Kbits flash memory
512 Kbits flash memor y is located in FFH bank in the CPU memory map. Function of flash memory interface
circuit enables read and program access from CPU.
Write/erase to flash interface is executed by instruction from CPU via flash memory interface, so rewrite of
program and data is carried on in the mounting state effectively.
Data can be reprogrammed not only by program execution in existing RAM but by program execution in flash
memory by dual operation. The different banks (the upper and lower banks) can be used to execute an erase/
program and a read concurrently.
Also, erase/write and read in the defferent bank (Upper Bank/Lower Bank) is executed simultaneously.
• Features of 512 Kbits flash memory
• Sector configuration : 64 Kwords × 8 bits/32 words × 16 bits (4K × 4 + 16K × 2 + 4K × 4)
• Simultaneous execution of erase/write and read by 2-bank configuration
• Automatic program algorithm (Embeded AlgorithmTM*)
• Built-in deletion pause/deletion resume function
• Detection of progr amming/erasure completion using data polling and the toggle bit
• At least 10,000 times guaranteed
• Minimum flash read cycle time : 2 machine cycles
* : Embedded AlgorithmTM is a trade mark of Advanced Micro Devices Inc.
Note : The read function of manufacture code and device coad is not including.
Also, these code is not accessed by the command.
• Flash write/erase
• Flash memory can not execute write/erase and read by the same bank simultaneously.
• Data can be progra mmed/deleted into and erased from flash memory by executing either the program
residing in the flash memory or the one copied to RAM from the flash memory.
Preliminary
2004.01.09
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64
• Sector configuration of flash memoly
SA0 (4 Kbyte)
SA1 (4 Kbyte)
SA2 (4 Kbyte)
SA3 (4 Kbyte)
FF0000H
FF0FFFH
FF1000H
FF1FFFH
FF2000H
FF2FFFH
70000H
70FFFH
71000H
71FFFH
72000H
72FFFH
SA4 (16 Kbyte)
SA5 (16 Kbyte)
SA6 (4 Kbyte)
FF3000H
FF3FFFH
FF4000H
FF7FFFH
FF8000H
FFBFFFH
FFC000H
FFCFFFH
73000H
73FFFH
74000H
77FFFH
78000H
78FFFH
7C000H
7CFFFH
SA7 (4 Kbyte)
SA8 (4 Kbyte)
SA9 (4Kbyte)
FFD000H
FFDFFFH
FFE000H
FFEFFFH
FFF000H
FFFFFFH
7D000H
7DFFFH
7E000H
7EFFFH
7F000H
7FFFFH
Lower BankUpper Bank
Flash Memory CPU address Writer address *
* : Flash memory writer address indicates the address equivalent to the CPU address when data is written
to the flash memory using a parallel writer. Programming and erasing by the general-purpose parallel
programmer are executed based on writer addresses.
Preliminary
2004.01.09
MB90335 Series
65
• Register list
Flash memory control register (FMCS)
Flash memory program control register (FWR0)
Flash memory program control register (FWR1)
Sector conversion setting register (SSR0)
∗ When writing to SSR0 register, write “0” except for SEN0.
Initial Value
Address : 0000AEH000X0000B
Initial Value
Address : 00790CH00000000B
Initial Value
Address : 00790DH00000000B
Initial Value
Address : 00790EH00XXXXX0B
( R/W ) ( R/W ) ( R ) ( W ) ( R/W ) ( W ) ( R/W )
76543210
RDYINT
( R/W )
INTE WE RDY LPM1 LPM0
Reserved Reserved
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
76543210
SA6E
( R/W )
SA7E SA5E SA4E SA3E SA2E SA1E SA0E
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
15 14 13 12 11 10 9 0
( R/W )
SA9E SA8E
( R/W ) ( )( )( )( )( ) ( R/W )
76543210
( R/W )
SEN0
Preliminary
2004.01.09
MB90335 Series
66
• Standard configuration for Fujitsu standard serial on-board writing
The flash microcontroller programmer (AF220/AF210/AF120/AF110) made by Yokogawa Digital Computer Corp.
is used for Fujitsu standard serial onboard writing.
Note : Inquire of Yokogawa Digital Computer Corporation for details about the functions and operations of the
flash microcontroller programmer (AF220, AF210, AF120 and AF110) , gener al-purpose common cable f or
connection (AZ210) and connectors.
• Pins Used for Fujitsu Standard Serial On-board Programming
Pin Function Description
MD2,
MD1, MD0 Mode input pin The device enters the serial program mode by setting MD2 = 1,
MD1 = 1 and MD0 = 0.
X0, X1 Oscillation pin Because the internal CPU operation clock is set to be the 1 multiplication
PLL clock in the serial write mode, the internal operation clock frequency
is the same as the oscillation clock frequency.
P60, P61 Write program start pins Input a Low level to P60 and a High level to P61.
RST Reset input pin
SIN0 Serial data input pin UART0 is used as CLK synchronous mode.
In write mode, the pins used for the UART0 CLK synchronous mode are
SIN0, SOT0, and SCK0.
SOT0 Serial data output pin
SCK0 Serial clock input pin
VCC Power source input pin
When supplying the write voltage (MB90F337 : 3.3 V±0.3 V) from the
user system, connection with the flash microcontroller programmer is
not necessary.
When connecting, do not short-circuit with the user power supply.
VSS GND Pin Share GND with the flash microcontroller programmer.
RS232C
Host interface cable (AZ201) General-purpose common cable (AZ210)
CLK synchronous
serial MB90F337
user system
Can operate standalone
Flash
microcontroller
programmer
+
Memory card
Preliminary
2004.01.09
MB90335 Series
67
The control circuit shown in the diag ram is required for using the P60, P61, SIN0, SOT0 and SCK0 pins on the
user system. Isolate the user circuit during serial on-board writing, with the /TICS signal of the flash microcon-
troller programmer.
Control circuit
The MB90F337 serial clock frequency that can be input is determined by the following expression • Use the
flash microcontroller programmer to change the serial cloc k input frequency setting depending on the oscillator
clock frequency to be used.
Imputable serial clock frequency = 0.125 × oscillation clock frequency.
• Maximum serial clock frequency
• System configuration of the flash microcontroller programmer (AF220/AF210/AF120/AF110) (made by Yokogawa
Digital Computer Corp.)
Contact to : Yokogawa Digital Computer Corp. TEL : (81)-42-333-6224
Note : The AF200 flash micon programmer is a retired product, but it can be supported using control module FF201.
Oscillation
clock
frequency
Maximum serial clock
frequency acceptab le to the
microcontroller
Maximum serial cl ock
frequency that can be set
with the AF220/AF210/
AF120/AF110
Maximum serial clock
frequency that can be set
with the AF200
At 6 MHz 750 kHz 500 kHz 500 kHz
Part number Function
Unit
AF220/AC4P Model with internal Ethernet interface /100 V to 220 V power adapter
AF210/AC4P Standard model /100 V to 220 V power adapter
AF120/AC4P Single key internal Ethernet interface mode /100 V to 220 V power adapter
AF110/AC4P Single key model /100 V to 220 V power adapter
AZ221 PC/AT RS232C cable for writer
AZ210 Standard target probe (a) length : 1 m
FF201 Control module for Fujitsu F2MC-16LX flash microcontroller control module
AZ290 Remote controller
/P2 2 MB PC Card (option) FLASH memory capacity to respond to 128 KB
/P4 4 MB PC Card (option) FLASH memory capacity to respond to 512 KB
10 kΩ
AF220/AF210/AF120/AF110
Write control pin
AF220/AF210/AF120/AF110
/TICS pin
MB90F337 write control pin
User
Preliminary
2004.01.09
MB90335 Series
68
■
■■
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings (VCC = 3.3 V, VSS = 0.0 V)
*1 : VI and VO must not exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some
means with external components, the ICLAMP rating supersedes the VI ra ting.
*2 : A peak value of an applicable one pin is specified as a maximum output current.
*3 : The av er age output current specifies the mean value of the current flowing in the relevant single pin during a
period of 100 ms.
*4 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins
during a period of 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage VCC VSS − 0.3 VSS + 4.0 V
Input voltage VI
VSS − 0.3 VSS + 4.0 V *1
VSS − 0.3 VSS + 6.0 V Nch0.D
(Withstand voltage I/O of 5 V)
− 0.5 VSS + 4.5 V USB I/O
Output voltage VOVSS − 0.3 VSS + 4.0 V *1
− 0.5 VSS + 4.5 V USB I/O
L level maximum output
current IOL1 10 mA Other than USB I/O*2
IOL2 43 mA USB I/O*2
L level average output cur-
rent IOLAV 3mA*3
L level maximum total out-
put current ΣIOL 60 mA
L level average total
output current ΣIOLAV 30 mA *4
H level maximum output
current IOH1 − 10 mA Other than USB I/O*2
IOH2 − 43 mA USB I/O*2
H level average output cur-
rent IOHAV − 3mA*3
H level maximum total out-
put current ΣIOH − 60 mA
H level average total
output current ΣIOHAV − 30 mA *4
Power consumption Pd 351 mW Target value
Operating temperature TA − 40 + 85 °C
Storage temperature Tstg − 55 + 150 °C
− 55 + 125 °C USB I/O
Preliminary
2004.01.09
MB90335 Series
69
2. Recommended Operating Conditions (VSS = 0.0 V)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Max
Power supply voltage VCC
3.0 3.6 V At normal operation (At USB is used)
2.7 3.6 V At normal operation (At USB is unused)
1.8 3.6 V Hold state of stop operation
Input H level voltage
VIH 0.7 VCC VCC + 0.3 V CMOS input pin
VIHS 0.8 VCC VCC + 0.3 V CMOS hysteresis input pin
VIHM VCC − 0.3 VCC + 0.3 V MD input pin
VIHUSB 2.0 VCC + 0.3 V USB input pin
Input L level voltage
VIL VSS − 0.3 0.3 VCC V CMOS input pin
VILS VSS − 0.3 0.2 VCC V CMOS hysteresis input pin
VILM VSS − 0.3 VSS + 0.3 V MD input pin
VILUSB VSS 0.8 V USB input pin
Differential input
sensitivity VDI 0.2 V USB input pin
Differential common
mode input voltage
range VCM 0.8 2.5 V USB input pin
Series resistance RS25 30 ΩRecommended value = 27 Ω at using USB
Operating
temperature TA − 40 + 85 °C At USB is unused
0 + 70 °CAt USB is used
Preliminary
2004.01.09
MB90335 Series
70
3. DC Characteristics (TA = − 40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)
Note : P60 to P67 are N-ch open-drain pins usually used as CMOS.
Parameter Sym-
bol Pin name Conditions Value Unit Remarks
Min Typ Max
Output
H level
voltage VOH
Output pin of other
than P60 to P67, HVP,
HVM, DVP, DVM IOH = −4.0 mA VCC − 0.5 Vcc V
HVP, HVM, DVP, DVM RL = 15 kΩ ± 5%2.8 3.6 V
Output
L level
voltage VOL
Output pin of other
than HVP, HVM, DVP,
DVM IOL = 4.0 mA Vss Vss + 0.4 V
HVP, HVM, DVP, DVM RL = 1.5 kΩ ± 5%00.3 V
Input leak
current IIL
Output pin of other
than P60 to P67, HVP,
HVM, DVP, DVM
VCC = 3.3 V,
Vss < VI < VCC − 10 10 µA
HVP, HVM, DVP, DVM − 5 5µA
Pull-up
resistor RPULL P00 to P07,
P10 to P17 VCC = 3.3 V,
Ta = + 25 °C25 50 100 kΩ
Open drain
output
current ILIOD P60 to P67 0.1 10 µA
Power
supply
current
ICC
VCC
VCC = 3.3 V,
Internal frequency 24 MHz,
At normal operating TBD mA
At USB
operating
Max 90 mA
(Target)
VCC = 3.3 V,
Internal frequency 24 MHz,
At normal operating 70 mA
At non-
operating
USB
(USTP = 0)
VCC = 3.3 V,
Internal frequency 24 MHz,
At normal operating TBD mA
At non-
operating
USB
(USTP = 1)
ICCS VCC = 3.3 V,
Internal frequency 24 MHz,
At sleep mode 27 mA
ICTS
VCC = 3.3 V,
Internal frequency 24 MHz,
At timer mode 3.5 mA
VCC = 3.3 V,
Internal frequency 3 MHz,
At timer mode 1mA
ICCH Ta = +25 °C,
At Stop mode 1µA
Input
capacitance CIN Other than Vcc and
Vss 515pF
Pull-up
resistor Rup RST 25 50 100 kΩ
Preliminary
2004.01.09
MB90335 Series
71
4. AC Characteristics
(1) Cloc k input timing (TA = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)
Parameter Sym-
bol Pin
name Value Unit Remarks
Min Typ Max
Clock frequency fCH X0, X1 6MHz External crystal oscillation
624 MHz External clock input
Clock cycle time tHCYL X0, X1 166.7 ns External crystal oscillation
166.7 41.7 ns External clock input
Input clock pulse width PWH
PWL X0 10 ns A reference duty ratio is
30% to 70%.
Input clock rise time and fall
time tcr
tcf X0 5 ns At external clock
Internal operating clock
frequency fCP 324 MHz At main clock is used
Internal operating clock
cycle time tCP 42 333 ns At main clock is used
0.8 VCC
0.2 VCC
tcf tcr
tHCYL
PWH PWL
X0
• Clock timing
Preliminary
2004.01.09
MB90335 Series
72
The AC standards provide that the following measurement reference voltages.
• PLL operation guarantee range
Relation between internal operation clock frequency and power supply voltage
* : When the USB is used, operation is guaranteed at voltages between 3.0 V to 3.6 V.
Relation between oscillation frequency and internal operation clock frequency
3.6
3.0
2.7
3 6 12 24
Internal clock fCP (MHz)
Power supply voltage VCC (V)
PLL operation guarantee range
Normal operation
assurance range
3
12
6
6
24
24
Internal clock fCP (MHz)
Oscillation clock FC (MHz)
Multiply by 4
Multiply by 2
Multiply by 1
External clock
0.8 VCC
0.2 VCC
2.4 V
0.8 V
0.7 VCC
0.3 VCC
• Input signal waveform
Hysteresis input pin
Hysteresis input/other than MD input pin
• Output signal waveform
Output pin
Preliminary
2004.01.09
MB90335 Series
73
(2) Reset (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
* : Oscillation time of oscillator is the time that the amplitude reaches 90 %. It takes se v er al milliseconds to se v eral
dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a
FAR/ceramic oscillator, and 0 milliseconds on an external clock.
Parameter Sym-
bol Pin
name Condi-
tions Value Unit Remarks
Min Max
Reset input
time tRSTL RST 500 ns
At normal operating,
At time base timer mode,
At main sleep mode,
At PLL sleep mode
Oscillation time of
oscillator* + 500 ns µs At stop mode
RST
X0
500 ns
tRSTL
0.2 VCC 0.2 VCC
RST
tRSTL
0.2 VCC 0.2 VCC
• In stop mode
Internal
operation
clock
Internal reset
Oscillation time
of oscillator
Oscillation stabilization wait time
Execute instruction
90% of
amplitude
• During normal operation, in time-base timer mode, in main sleep mode and in PLL sleep mode
Preliminary
2004.01.09
MB90335 Series
74
(3) Power-on reset (TA = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)
Notes : •VCC must be lower than 0.2 V before the power supply is turned on.
•The above standard is a value for performing a power - on reset.
•In the device, there are internal registers which is initialized only by a power-on reset. When the initial
ization of these items is expected, turn on the power supply according to the standards.
Parameter Symbol Pin name Condi-
tions Value Unit Remarks
Min Max
Power supply rising time tRVCC 30 ms
Power supply shutdown time tOFF VCC 1ms For repeated
operation
VCC
VCC
3.0 V
VSS
tR
0.2 V0.2 V
2.7 V
tOFF
0.2 V
Sudden change of power supply voltage may activate the power-on reset function.
When changing the power supply voltage during operation as illustrated below, voltage fluctuation
should be minimized so that the voltage rises as smoothly as possible. When raising the power,
do not use PLL clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during
operation.
RAM data hold
The rising edge should be 50 mV/ms
or less.
Preliminary
2004.01.09
MB90335 Series
75
(4) UART0, UART1 I/O extended serial timing (TA = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)
Notes : •AC rating in CLK synchronous mode.
•CL is a load capacitance value on pins for testing.
•tCP is the machine cycle period (unit : ns) .
Parameter Sym-
bol Pin name Conditions Value Unit Remarks
Min Max
Serial clock cycle time tSCYC SCKx
Internal shiftc lock
Mode output pin is
CL = 80 pF + 1 TTL
8 tCP ns
SCK ↓ → SOT delay time tSLOV SCKx
SOTx − 80 80 ns
Valid SIN → SCK ↑tIVSH SCKx
SINx 100 ns
SCK ↑ → valid
SIN hold time tSHIX SCKx
SINx 60 ns
Serial clock H pulse width tSHSL SCKx, SINx
External shift clock
Mode output pin is
CL = 80 pF + 1 TTL
4 tCP ns
Serial clock L pulse width tSLSH SCKx, SINx 4 tCP ns
SCK ↓ → SOT delay time tSLOV SCKx
SOTx 150 ns
Valid SIN → SCK ↑tIVSH SCKx
SINx 60 ns
SCK ↑ → valid
SIN hold time tSHIX SCKx
SINx 60 ns
• Internal shift clock mode
• External shift clock mode
SCK
SOT
SIN
tSCYC
tSLOV
tIVSH tSHIX
0.8 V 0.8 V
2.4 V
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SCK
SOT
SIN
tSLSH tSHSL
tSLOV
tIVSH tSHIX
0.2 VCC 0.2 VCC
0.8 VCC 0.8 VCC
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
Preliminary
2004.01.09
MB90335 Series
76
(5) I2C timing (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Sym-
bol Pin
name Condi-
tions Value Unit Remarks
Min Max
SCL clock frequency fSCL
0 100 kHz
Bus-free time between stop
and start conditions tBUS 4.7 µs
Hold time (resend) start tHDSTA 4.0 µsThe first clock pulse is generated
immediately after the period.
SCL clock “L” status hold time tLOW 4.7 µs
SCL clock “H” status hold time tHIGH 4.0 µs
Resend start condition setup
time tSUSTA 4.7 µs
Data hold time tHDDAT 0µs
Data set-up time tSUDAT 40 ns
SDA and SCL signal rise time tR1000 ns
SDA and SCL signal fall time tF300 ns
Stop condition setup time tSUSTO 4.0 µs
SDA
SCL
tBUS
tHDSTA tHDDAT tSUDAT tSUSTA tSUSTO
tLOW tHIGH tHDSTA
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tRtF
fSCL
Preliminary
2004.01.09
MB90335 Series
77
(6) Timer Input Timing (TA = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)
(7) Timer output timing (TA = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)
(8) Trigger Input Timing (TA = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)
Parameter Symbol Pin name Condi-
tions Value Unit Remarks
Min Max
Input pulse width tTIWH
tTIWL PWC 4 tCP ns
Parameter Sym-
bol Pin name Condi-
tions Value Unit Remarks
Min Max
CLK ↑ → TOUT change time
PPG0 to PPG3 change time tTO PPGx 30 ns
Parameter Symbol Pin name Condi-
tions Value Unit Remarks
Min Max
Input pulse width tTRGH
tTRGL INTx 5 tCP ns At normal operating
1µs At Stop mode
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tTIWH tTIWL
PWC
CLK
PPGx
2.4 V
tTO
2.4 V
0.8 V
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tTRGH tTRGL
INTx
Preliminary
2004.01.09
MB90335 Series
78
5. USB characteristics (TA = 0 °C to +70 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)
• Data signal timing (Full Speed)
• Data signal timing (Low Speed)
Parameter Symbol Sym
bol Value Unit Remarks
Min Max
Input
characteristics
Input High level voltage VIH 2.0 V
Input Low level voltage VIL 0.8 V
Differential input sensitivity VDI 0.2 V
Differential common mode range VCM 0.8 2.5 V
Output
characteristics
Output High level voltage VOH 2.8 3.6 V IOH = −200 µA
Output Low level voltage VOL 0.0 0.3 V IOL = 2 mA
Cross over voltage VCRS 1.3 2.0 V
Rise time tFR 4 20 ns Full Speed
tLR 75 300 ns Low Speed
Fall time tFF 4 20 ns Full Speed
tLF 75 300 ns Low Speed
Rising/falling time matching tRFM 90 111.11 % (TFR/TFF)
tRLM 80 125 % (TLR/TLF)
Output registance ZDRV 28 44 ΩIncluding Rs = 27 Ω
DVM/HVM
90%
tFR
10% 90% 10%
tFF
Vcrs
DVP/HVP Rise time Fall time
HVP 90%
tLR
10% 90% 10%
tLF
Vcrs
HVM
Rise time Fall time
Preliminary
2004.01.09
MB90335 Series
79
• Load condition (Full Speed)
• Load condition (Low Speed)
DVP/HVP RS = 27 Ω
CL = 50 pF
DVM/HVM RS = 27 Ω
CL = 50 pF
Testing point
Testing point
HVP RS = 27 Ω
CL = 50 pF ∼ 150 pF
HVM RS = 27 Ω
CL = 50 pF ∼ 150 pF
Testing point
Testing point
Preliminary
2004.01.09
MB90335 Series
80
■
■■
■ORDERING INFORMATION
• MB90335 Series
Part number Package Remarks
MB90F337PFM
MB90337PFM 64-pin plastic LQFP
(FPT-64P-M09)
Preliminary
2004.01.09
MB90335 Series
81
■
■■
■PACKAGE DIMENSION
64-pin plastic LQFP
(FPT-64P-M09)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
C
2003 FUJITSU LIMITED F64018S-c-3-5
0.65(.026)
0.10(.004)
116
17
32
49
64
3348
12.00±0.10(.472±.004)SQ
14.00±0.20(.551±.008)SQ
INDEX
0.32±0.05
(.013±.002) M
0.13(.005)
0.145±0.055
(.0057±.0022)
"A"
.059 –.004
+.008
–0.10
+0.20
1.50
0~8˚
0.25(.010)
(Mounting height)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
0.10(.004)
*
Preliminary
2004.01.09
MB90335 Series
82
MEMO
Preliminary
2004.01.09
MB90335 Series
83
MEMO
Preliminary
2004.01.09
MB90335 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Marketing Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3353
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94088-3470, U.S.A.
Tel: +1-408-737-5600
Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTR ONICS EUR OPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fme.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTR ONICS ASIA PTE LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-6281-0770
Fax: +65-6281-0220
http://www.fmal.fujitsu.com/
Korea
FUJITSU MICROELECTR ONICS K OREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
F0312
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
Preliminary
2004.01.09
