SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com FEATURES * * * * * * * * * * * * Member of the Texas Instruments WidebusTM Family TI-OPCTM Circuitry Limits Ringing on Unevenly Loaded Backplanes OECTM Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant High-Drive GTLP Outputs (100 mA) LVTTL Outputs (-24 mA/24 mA) Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II SCES290D - OCTOBER 1999 - REVISED JUNE 2005 DGG OR DGV PACKAGE (TOP VIEW) 1DIR 1A1 1A2 GND 1A3 1A4 VCC GND 1A5 1A6 GND 1A7 1A8 GND ERC 2A1 2A2 GND 2A3 2A4 GND VCC 2A5 2A6 GND 2A7 2A8 2DIR 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OE 1B1 1B2 GND 1B3 1B4 VCC GND 1B5 1B6 GND 1B7 1B8 BIAS VCC VREF 2B1 2B2 GND 2B3 2B4 GND VCC 2B5 2B6 GND 2B7 2B8 2OE DESCRIPTION/ORDERING INFORMATION The SN74GTLPH1645 is a high-drive, 16-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It is partitioned as two 8-bit transceivers. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OECTM circuitry, and TI-OPCTM circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11 . GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH1645 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, TI-OPC, OEC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2005, Texas Instruments Incorporated SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com SCES290D - OCTOBER 1999 - REVISED JUNE 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load. Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA -40C to 85C (1) 2 PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP - DGG Tape and reel SN74GTLPH1645DGGR GTLPH1645 TVSOP - DGV Tape and reel SN74GTLPH1645DGVR GL45 VFBGA - GQL Tape and reel SN74GTLPH1645GQLR GL45 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com SCES290D - OCTOBER 1999 - REVISED JUNE 2005 GQL PACKAGE (TOP VIEW) 1 2 3 4 5 6 A B C D E F G H J K TERMINAL ASSIGNMENTS 1 2 3 4 5 6 A 1A2 1A1 B 1A4 1A3 1DIR 1OE 1B1 1B2 GND GND 1B3 C 1A5 1B4 GND VCC VCC GND 1B5 D E 1A7 1A6 GND GND 1B6 1B7 GND 1A8 1B8 BIAS VCC F ERC 2A1 2B1 VREF G 2A2 2A3 GND H 2A4 GND VCC GND 2B3 2B2 VCC GND J 2A5 2A6 2B4 GND GND 2B6 K 2A7 2A8 2B5 2DIR 2OE 2B8 2B7 3 SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com SCES290D - OCTOBER 1999 - REVISED JUNE 2005 FUNCTIONAL DESCRIPTION The SN74GTLPH1645 is a high-drive (100-mA), 16-bit bus transceiver partitioned as two 8-bit segments and is designed for asynchronous communication between data buses. The device transmits data from the A port to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input. OE can be used to disable the device so the buses are effectively isolated. Data polarity is noninverting. For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When OE is high, the outputs are in the high-impedance state. The data flow for B to A is similar to A to B, except OE and DIR are low. FUNCTION TABLES <br/> OUTPUT CONTROL INPUTS OUTPUT MODE X Z Isolation L B data to A port H A data to B port OE DIR H L L True transparent B-PORT EDGE-RATE CONTROL (ERC) INPUT ERC 4 LOGIC LEVEL NOMINAL VOLTAGE OUTPUT B-PORT EDGE RATE L GND Slow H VCC Fast SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com SCES290D - OCTOBER 1999 - REVISED JUNE 2005 LOGIC DIAGRAM (POSITIVE LOGIC)(1) 1 1DIR 56 ERC 1A1 15 1OE 55 2 1B1 42 VREF To Seven Other Channels 28 2DIR 29 2OE 2A1 41 16 2B1 To Seven Other Channels (1) Pin numbers shown are for the DGG and DGV packages. 5 SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com SCES290D - OCTOBER 1999 - REVISED JUNE 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC BIAS VCC Supply voltage range VI Input voltage range (2) VO Voltage range applied to any output in the high-impedance or power-off state (2) IO Current into any output in the low state IO Current into any A-port output in the high state (3) MIN MAX -0.5 4.6 A-port, ERC, and control inputs -0.5 7 B port and VREF -0.5 4.6 A port -0.5 7 B port -0.5 4.6 A port 48 B port 200 Continuous current through each VCC or GND UNIT V V V mA 48 mA 100 mA IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA JA Package thermal impedance (4) Tstg (1) (2) (3) (4) 6 Storage temperature range DGG package 64 DGV package 48 GQL package 42 -65 150 C/W C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. www.ti.com SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D - OCTOBER 1999 - REVISED JUNE 2005 Recommended Operating Conditions VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage (1) (2) (3) (4) MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 B port VTT Except B port B port ERC Except B port and ERC VCC 5.5 VCC 5.5 Low-level input voltage IIK Input clamp current IOH High-level output current IOL Low-level output current t/v Input transition rise or fall rate t/VCC Power-up ramp rate TA Operating free-air temperature VCC - 0.6 (2) (3) (4) V V 2 VREF - 0.05 ERC GND Except B port and ERC (1) V VREF + 0.05 B port VIL V 0.6 V 0.8 A port -18 mA -24 mA A port 24 B port 100 Outputs enabled 10 ns/V s/V 20 -40 mA 85 C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable but, generally, GND is connected first. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current drain. 7 SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com SCES290D - OCTOBER 1999 - REVISED JUNE 2005 Electrical Characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port VCC = 3.15 V, II = -18 mA VCC = 3.15 V to 3.45 V, IOH = -100 A VCC - 0.2 IOH = -12 mA 2.4 IOH = -24 mA 2 VCC = 3.15 V VCC = 3.15 V to 3.45 V, A port VCC = 3.15 V VOL B port II Control inputs IOZH (2) A port B port MIN TYP (1) MAX TEST CONDITIONS VCC = 3.15 V VCC = 3.45 V, VCC = 3.45 V -1.2 0.2 IOL = 12 mA 0.4 IOL = 24 mA 0.5 IOL = 10 mA 0.2 IOL = 64 mA 0.4 IOL = 100 mA 0.55 VI = 0 or 5.5 V 10 VO = VCC 10 VO = 1.5 V 10 A and B ports VCC = 3.45 V, VO = GND IBHL (3) A port VCC = 3.15 V, VI = 0.8 V (4) V V IOL = 100 A IOZL (2) UNIT -10 V A A A 75 A A port VCC = 3.15 V, VI = 2 V -75 A IBHLO (5) A port VCC = 3.45 V, VI = 0 to VCC 500 A IBHHO (6) A port VCC = 3.45 V, VI = 0 to VCC -500 A ICC A or B port VCC = 3.45 V, IO = 0, VI (A-port or control inputs) = VCC or GND, VI (B port) = VTT or GND IBHH Cio (1) (2) (3) (4) (5) (6) (7) 40 Outputs low 40 Outputs disabled 40 VCC = 3.45 V, One A-port or control input at VCC - 0.6 V, Other A-port or control inputs at VCC or GND ICC (7) Ci Outputs high mA 1.5 mA pF Control inputs VI = 3.15 V or 0 4 5 A port VO = 3.15 V or 0 6.5 7.5 B port VO = 1.5 V or 0 9.5 11 pF All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameters IOZH and IOZL include the input leakage current. The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and then raising it to VILmax. The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and then lowering it to VIHmin. An external driver must source at least IBHLO to switch this node from low to high. An external driver must sink at least IBHHO to switch this node from high to low. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Hot-Insertion Specifications for A Port over recommended operating free-air temperature range PARAMETER Ioff 8 TEST CONDITIONS MIN MAX UNIT 10 A OE = 0 30 A OE = 0 30 A VCC = 0, BIAS VCC = 0, VI or VO = 0 to 5.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com SCES290D - OCTOBER 1999 - REVISED JUNE 2005 Live-Insertion Specifications for B Port over recommended operating free-air temperature range PARAMETER Ioff TEST CONDITIONS MIN A 30 A VO = 0.5 V to 1.5 V, OE = 0 30 A 5 mA 10 A VI or VO = 0 to 1.5 V IOZPU VCC = 0 to 1.5 V, BIAS VCC = 0, IOZPD VCC = 1.5 V to 0, BIAS VCC = 0, ICC (BIAS VCC) VCC = 3.15 V to 3.45 V UNIT VO = 0.5 V to 1.5 V, OE = 0 BIAS VCC = 0, VCC = 0 to 3.15 V MAX 10 VCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0 to 1.5 V VO VCC = 0, BIAS VCC = 3.3 V, IO = 0 IO VCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V 0.95 1.05 V A -1 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL ten tdis ten tdis TO (OUTPUT) EDGE RATE (1) A B Slow A B Fast OE B Slow OE B Fast tr Rise time, B outputs (20% to 80%) tf Fall time, B outputs (80% to 20%) tPLH tPHL ten tdis (1) (2) FROM (INPUT) B A OE A MIN TYP (2) MAX 3.9 7.2 3.1 8.4 2.6 5.7 2.1 5.8 4.1 7.3 4 9.4 2.9 5.9 4 6.9 Slow 3 Fast 1.5 Slow 4 Fast 2.5 UNIT ns ns ns ns ns ns 0.5 6.7 1.2 4.5 1.1 6.3 1.7 5.1 ns ns Slow (ERC = GND) and Fast (ERC = VCC) All typical values are at VCC = 3.3 V, TA = 25C. 9 SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com SCES290D - OCTOBER 1999 - REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION 500 From Output Under Test S1 1.5 V 6V Open GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 12.5 From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND Test Point LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1V Output 1V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) 1V 0V tPLH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH VOH Output 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V 1.5 V tPZL 1.5 V 1V Input 3V Output Control Output Waveform 2 S1 at GND (see Note B) tPHZ VOH 1.5 V VOH - 0.3 V 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 10 SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com SCES290D - OCTOBER 1999 - REVISED JUNE 2005 Distributed-Load Backplane Switching Characteristics The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more information. 22 0.25" ZO = 50 1" Conn. 1" Conn. 1" Conn. Conn. 1" 1" 0.25" 22 1.5 V 1.5 V 1" Rcvr Rcvr Rcvr Slot 2 Slot 19 Slot 20 Drvr Slot 1 Figure 2. High-Drive Test Backplane 1.5 V 11 From Output Under Test LL = 14 nH Test Point CL = 18 pF Figure 3. High-Drive RLC Network 11 SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com SCES290D - OCTOBER 1999 - REVISED JUNE 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL ten tdis ten tdis (1) (2) 12 FROM (INPUT) TO (OUTPUT) EDGE RATE (1) A B Slow A B Fast OE B Slow OE B Fast tr Rise time, B outputs (20% to 80%) tf Fall time, B outputs (80% to 20%) Slow (ERC = GND) and Fast (ERC = VCC) All typical values are at VCC = 3.3 V, TA = 25C. All values are derived from TI-SPICE models. TYP (2) 4.9 4.9 3.7 3.7 5.1 5.4 4.1 4.1 Slow 2 Fast 1.2 Slow 2.5 Fast 1.8 UNIT ns ns ns ns ns ns PACKAGE OPTION ADDENDUM www.ti.com 3-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) 74GTLPH1645DGGRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74GTLPH1645DGGRG4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74GTLPH1645DGVRE4 ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74GTLPH1645DGVRG4 ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH1645DGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH1645DGVR ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH1645GQLR LIFEBUY BGA MICROSTAR JUNIOR GQL 56 1000 TBD SNPB Level-1-240C-UNLIM SN74GTLPH1645ZQLR ACTIVE BGA MICROSTAR JUNIOR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com (3) 3-May-2012 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1.8 12.0 24.0 Q1 SN74GTLPH1645DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 SN74GTLPH1645DGVR TVSOP DGV 56 2000 330.0 24.4 6.8 11.7 1.6 12.0 24.0 Q1 SN74GTLPH1645GQLR BGA MI CROSTA R JUNI OR GQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1 SN74GTLPH1645ZQLR ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 BGA MI CROSTA R JUNI OR Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74GTLPH1645DGGR TSSOP DGG 56 2000 367.0 367.0 45.0 SN74GTLPH1645DGVR TVSOP DGV 56 2000 367.0 367.0 45.0 SN74GTLPH1645GQLR BGA MICROSTAR JUNIOR GQL 56 1000 333.2 345.9 28.6 SN74GTLPH1645ZQLR ZQL 56 1000 333.2 345.9 28.6 BGA MICROSTAR JUNIOR Pack Materials-Page 2 MECHANICAL DATA MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0-8 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins - MO-153 14/16/20/56 Pins - MO-194 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D - JANUARY 1995 - REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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