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FEATURES
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1DIR
1A1
1A2
GND
1A3
1A4
VCC
GND
1A5
1A6
GND
1A7
1A8
GND
ERC
2A1
2A2
GND
2A3
2A4
GND
VCC
2A5
2A6
GND
2A7
2A8
2DIR
1OE
1B1
1B2
GND
1B3
1B4
VCC
GND
1B5
1B6
GND
1B7
1B8
BIAS VCC
VREF
2B1
2B2
GND
2B3
2B4
GND
VCC
2B5
2B6
GND
2B7
2B8
2OE
DESCRIPTION/ORDERING INFORMATION
SN74GTLPH164516-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED JUNE 2005
•Member of the Texas Instruments Widebus™Family
•TI-OPC™ Circuitry Limits Ringing onUnevenly Loaded Backplanes•OEC™ Circuitry Improves Signal Integrity andReduces Electromagnetic Interference•Bidirectional Interface Between GTLP SignalLevels and LVTTL Logic Levels•LVTTL Interfaces Are 5-V Tolerant•High-Drive GTLP Outputs (100 mA)•LVTTL Outputs (–24 mA/24 mA)•Variable Edge-Rate Control ( ERC) InputSelects GTLP Rise and Fall Times for OptimalData-Transfer Rate and Signal Integrity inDistributed Loads•I
off
, Power-Up 3-State, and BIAS V
CC
SupportLive Insertion•Bus Hold on A-Port Data Inputs•Distributed V
CC
and GND Pins MinimizeHigh-Speed Switching Noise•Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II
The SN74GTLPH1645 is a high-drive, 16-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTLsignal-level translation. It is partitioned as two 8-bit transceivers. The device provides a high-speed interfacebetween cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed(about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reducedoutput swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed andtested using several backplane models. The high drive allows incident-wave switching in heavily loadedbackplanes with equivalent load impedance down to 11 Ω.
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.The ac specification of the SN74GTLPH1645 is given only at the preferred higher noise-margin GTLP, but theuser has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V andV
REF
= 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
REF
is the B-port differential inputreference voltage.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus, TI-OPC, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED JUNE 2005
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
offcircuitry disables the outputs, preventing damaging current backflow through the device when it is powereddown. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and powerdown, which prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port input/outputconnections, preventing disturbance of active data on the backplane during card insertion or removal, andpermits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminatedbackplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signalintegrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control ( ERC). Changing the ERCinput voltage between GND and V
CC
adjusts the B-port output rise and fall times. This allows the designer tooptimize system data-transfer rate and signal integrity to the backplane load.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup orpulldown resistors with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.However, to ensure the high-impedance state above 1.5 V, the output-enable ( OE) input should be tied to V
CCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of thedriver.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
TSSOP – DGG Tape and reel SN74GTLPH1645DGGR GTLPH1645–40 °C to 85 °C TVSOP – DGV Tape and reel SN74GTLPH1645DGVR GL45VFBGA – GQL Tape and reel SN74GTLPH1645GQLR GL45
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
2
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GQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
123456
SN74GTLPH164516-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED JUNE 2005
TERMINAL ASSIGNMENTS
123456
A1A2 1A1 1DIR 1 OE 1B1 1B2
B1A4 1A3 GND GND 1B3 1B4
C1A5 GND V
CC
V
CC
GND 1B5
D1A7 1A6 GND GND 1B6 1B7
EGND 1A8 1B8 BIAS V
CC
FERC 2A1 2B1 V
REF
G2A2 2A3 GND GND 2B3 2B2
H2A4 GND V
CC
V
CC
GND 2B4
J2A5 2A6 GND GND 2B6 2B5
K2A7 2A8 2DIR 2 OE 2B8 2B7
3
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FUNCTIONAL DESCRIPTION
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED JUNE 2005
The SN74GTLPH1645 is a high-drive (100-mA), 16-bit bus transceiver partitioned as two 8-bit segments and isdesigned for asynchronous communication between data buses. The device transmits data from the A port to theB port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input. OE canbe used to disable the device so the buses are effectively isolated. Data polarity is noninverting.
For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs.When OE is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to A to B, except OE and DIR are low.
FUNCTION TABLES
<br/>
OUTPUT CONTROL
INPUTS
OUTPUT MODEOE DIR
H X Z IsolationL L B data to A port
True transparentL H A data to B port
B-PORT EDGE-RATE CONTROL ( ERC)
INPUT ERC
OUTPUT
B-PORTLOGIC NOMINAL
EDGE RATELEVEL VOLTAGE
L GND SlowH V
CC
Fast
4
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1DIR
1OE
1A1 1B1
1
2
56
55
VREF
42
2DIR
2OE
2A1 2B1
To Seven Other Channels
28
16
29
41
ERC 15
To Seven Other Channels
SN74GTLPH164516-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED JUNE 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
(1)
(1) Pin numbers shown are for the DGG and DGV packages.
5
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Absolute Maximum Ratings
(1)
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED JUNE 2005
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 4.6 VBIAS V
CC
A-port, ERC, and control inputs –0.5 7V
I
Input voltage range
(2)
VB port and V
REF
–0.5 4.6A port –0.5 7Voltage range applied to any output in theV
O
Vhigh-impedance or power-off state
(2)
B port –0.5 4.6A port 48I
O
Current into any output in the low state mAB port 200I
O
Current into any A-port output in the high state
(3)
48 mAContinuous current through each V
CC
or GND ±100 mAI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mADGG package 64θ
JA
Package thermal impedance
(4)
DGV package 48 °C/WGQL package 42T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3) This current flows only when the output is in the high state and V
O
> V
CC
.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
6
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Recommended Operating Conditions
(1) (2) (3) (4)
SN74GTLPH164516-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED JUNE 2005
MIN NOM MAX UNIT
V
CC
,
Supply voltage 3.15 3.3 3.45 VBIAS V
CC
GTL 1.14 1.2 1.26V
TT
Termination voltage VGTLP 1.35 1.5 1.65GTL 0.74 0.8 0.87V
REF
Reference voltage VGTLP 0.87 1 1.1B port V
TTV
I
Input voltage VExcept B port V
CC
5.5B port V
REF
+ 0.05V
IH
High-level input voltage ERC V
CC
– 0.6 V
CC
5.5 VExcept B port and ERC 2B port V
REF
– 0.05V
IL
Low-level input voltage ERC GND 0.6 VExcept B port and ERC 0.8I
IK
Input clamp current –18 mAI
OH
High-level output current A port –24 mAA port 24I
OL
Low-level output current mAB port 100∆t/ ∆v Input transition rise or fall rate Outputs enabled 10 ns/V∆t/ ∆V
CC
Power-up ramp rate 20 µs/VT
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.(2) Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V
CC
= 3.3 V first, I/O second, and V
CC
= 3.3 Vlast, because the BIAS V
CC
precharge circuitry is disabled when any V
CC
pin is connected. The control and V
REF
inputs can beconnected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence isacceptable but, generally, GND is connected first.(3) V
TT
and R
TT
can be adjusted to accommodate backplane impedances if the dc recommended I
OL
ratings are not exceeded.(4) V
REF
can be adjusted to optimize noise margins, but normally is two-thirds V
TT
. TI-OPC circuitry is enabled in the A-to-B direction and isactivated when V
TT
> 0.7 V above V
REF
. If operated in the A-to-B direction, V
REF
should be set to within 0.6 V of V
TT
to minimize currentdrain.
7
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Electrical Characteristics
Hot-Insertion Specifications for A Port
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED JUNE 2005
over recommended operating free-air temperature range for GTLP (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IK
V
CC
= 3.15 V, I
I
= –18 mA –1.2 VV
CC
= 3.15 V to 3.45 V, I
OH
= –100 µA V
CC
– 0.2V
OH
A port I
OH
= –12 mA 2.4 VV
CC
= 3.15 V
I
OH
= –24 mA 2V
CC
= 3.15 V to 3.45 V, I
OL
= 100 µA 0.2A port I
OL
= 12 mA 0.4V
CC
= 3.15 V
I
OL
= 24 mA 0.5V
OL
VI
OL
= 10 mA 0.2B port V
CC
= 3.15 V I
OL
= 64 mA 0.4I
OL
= 100 mA 0.55I
I
Control inputs V
CC
= 3.45 V, V
I
= 0 or 5.5 V ±10 µAA port V
O
= V
CC
10I
OZH
(2)
V
CC
= 3.45 V µAB port V
O
= 1.5 V 10I
OZL
(2)
A and B ports V
CC
= 3.45 V, V
O
= GND –10 µAI
BHL
(3)
A port V
CC
= 3.15 V, V
I
= 0.8 V 75 µAI
BHH
(4)
A port V
CC
= 3.15 V, V
I
= 2 V –75 µAI
BHLO
(5)
A port V
CC
= 3.45 V, V
I
= 0 to V
CC
500 µAI
BHHO
(6)
A port V
CC
= 3.45 V, V
I
= 0 to V
CC
–500 µAOutputs high 40V
CC
= 3.45 V, I
O
= 0,I
CC
A or B port V
I
(A-port or control inputs) = V
CC
or GND, Outputs low 40 mAV
I
(B port) = V
TT
or GND
Outputs disabled 40V
CC
= 3.45 V, One A-port or control input at V
CC
– 0.6 V,∆I
CC
(7)
1.5 mAOther A-port or control inputs at V
CC
or GNDC
i
Control inputs V
I
= 3.15 V or 0 4 5 pFA port V
O
= 3.15 V or 0 6.5 7.5C
io
pFB port V
O
= 1.5 V or 0 9.5 11
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.(2) For I/O ports, the parameters I
OZH
and I
OZL
include the input leakage current.(3) The bus-hold circuit can sink at least the minimum low sustaining current at V
IL
max. I
BHL
should be measured after lowering V
IN
to GNDand then raising it to V
IL
max.(4) The bus-hold circuit can source at least the minimum high sustaining current at V
IH
min. I
BHH
should be measured after raising V
IN
to V
CCand then lowering it to V
IH
min.(5) An external driver must source at least I
BHLO
to switch this node from low to high.(6) An external driver must sink at least I
BHHO
to switch this node from high to low.(7) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC
or GND.
over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
I
off
V
CC
= 0, BIAS V
CC
= 0, V
I
or V
O
= 0 to 5.5 V 10 µAI
OZPU
V
CC
= 0 to 1.5 V, V
O
= 0.5 V to 3 V, OE = 0 ±30 µAI
OZPD
V
CC
= 1.5 V to 0, V
O
= 0.5 V to 3 V, OE = 0 ±30 µA
8
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Live-Insertion Specifications for B Port
Switching Characteristics
SN74GTLPH164516-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED JUNE 2005
over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
I
off
V
CC
= 0, BIAS V
CC
= 0, V
I
or V
O
= 0 to 1.5 V 10 µAI
OZPU
V
CC
= 0 to 1.5 V, BIAS V
CC
= 0, V
O
= 0.5 V to 1.5 V, OE = 0 ±30 µAI
OZPD
V
CC
= 1.5 V to 0, BIAS V
CC
= 0, V
O
= 0.5 V to 1.5 V, OE = 0 ±30 µAV
CC
= 0 to 3.15 V 5 mAI
CC
(BIAS V
CC
) BIAS V
CC
= 3.15 V to 3.45 V, V
O
(B port) = 0 to 1.5 VV
CC
= 3.15 V to 3.45 V 10 µAV
O
V
CC
= 0, BIAS V
CC
= 3.3 V, I
O
= 0 0.95 1.05 VI
O
V
CC
= 0, BIAS V
CC
= 3.15 V to 3.45 V, V
O
(B port) = 0.6 V –1 µA
over recommended ranges of supply voltage and operating free-air temperature,V
TT
= 1.5 V and V
REF
= 1 V for GTLP (see Figure 1)
FROM TOPARAMETER EDGE RATE
(1)
MIN TYP
(2)
MAX UNIT(INPUT) (OUTPUT)
t
PLH
3.9 7.2A B Slow nst
PHL
3.1 8.4t
PLH
2.6 5.7A B Fast nst
PHL
2.1 5.8t
en
4.1 7.3OE B Slow nst
dis
4 9.4t
en
2.9 5.9OE B Fast nst
dis
4 6.9Slow 3t
r
Rise time, B outputs (20% to 80%) nsFast 1.5Slow 4t
f
Fall time, B outputs (80% to 20%) nsFast 2.5t
PLH
0.5 6.7B A nst
PHL
1.2 4.5t
en
1.1 6.3OE A nst
dis
1.7 5.1
(1) Slow ( ERC = GND) and Fast ( ERC = V
CC
)(2) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.
9
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PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
S1 Open
GND
500 Ω
500 Ω
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6 V
GND
tPLH tPHL
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH − 0.3 V
≈0 V
Input
3 V
3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
Output
1.5 V
Test
Point
CL = 30 pF
(see Note A)
From Output
Under Test
12.5 Ω
LOAD CIRCUIT FOR B OUTPUTS
0 V
VOH
VOL
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
Output
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈2 ns, tf ≈2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
6 V
tPLH tPHL
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1 V 1 V
1 V 1 V
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED JUNE 2005
Figure 1. Load Circuits and Voltage Waveforms
10
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Distributed-Load Backplane Switching Characteristics
0.25”
Drvr
1.5 V
0.25” 1”
1” 1”
1.5 V
1”1”
1”
Rcvr Rcvr Rcvr
Slot 1 Slot 2 Slot 19 Slot 20
Conn. Conn. Conn. Conn.
ZO = 50 Ω
22 Ω
22 Ω
From Output
Under Test Test
Point
1.5 V
CL = 18 pF
11 Ω
LL = 14 nH
SN74GTLPH164516-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED JUNE 2005
The preceding switching characteristics table shows the switching characteristics of the device into a lumpedload (Figure 1). However, the designer's backplane application probably is a distributed load. The physicalrepresentation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to aresistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimumperformance in this RLC circuit. The following switching characteristics table shows the switching characteristicsof the device into the RLC load, to help the designer better understand the performance of the GTLP device inthis typical backplane. See www.ti.com/sc/gtlp for more information.
Figure 2. High-Drive Test Backplane
Figure 3. High-Drive RLC Network
11
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Switching Characteristics
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED JUNE 2005
over recommended ranges of supply voltage and operating free-air temperature,V
TT
= 1.5 V and V
REF
= 1 V for GTLP (see Figure 3)
FROM TOPARAMETER EDGE RATE
(1)
TYP
(2)
UNIT(INPUT) (OUTPUT)
t
PLH
4.9A B Slow nst
PHL
4.9t
PLH
3.7A B Fast nst
PHL
3.7t
en
5.1OE B Slow nst
dis
5.4t
en
4.1OE B Fast nst
dis
4.1Slow 2t
r
Rise time, B outputs (20% to 80%) nsFast 1.2Slow 2.5t
f
Fall time, B outputs (80% to 20%) nsFast 1.8
(1) Slow ( ERC = GND) and Fast ( ERC = V
CC
)(2) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C. All values are derived from TI-SPICE models.
12
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74GTLPH1645DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
SN74GTLPH1645DGVR TVSOP DGV 56 2000 330.0 24.4 6.8 11.7 1.6 12.0 24.0 Q1
SN74GTLPH1645GQLR BGA MI
CROSTA
R JUNI
OR
GQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1
SN74GTLPH1645ZQLR BGA MI
CROSTA
R JUNI
OR
ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74GTLPH1645DGGR TSSOP DGG 56 2000 367.0 367.0 45.0
SN74GTLPH1645DGVR TVSOP DGV 56 2000 367.0 367.0 45.0
SN74GTLPH1645GQLR BGA MICROSTAR
JUNIOR GQL 56 1000 333.2 345.9 28.6
SN74GTLPH1645ZQLR BGA MICROSTAR
JUNIOR ZQL 56 1000 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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