NAL Am27C256 256 Kilobit (32,768 x 8-Bit) CMOS EPROM at Advanced Micro Devices DISTINCTIVE CHARACTERISTICS @ Fast access time 55ns m Low power consumption 20 A typical CMOS standby current JEDEC-approved pinout Single +5 V power supply +10% power supply tolerance available 100% Flashrite programming Typical programming time of 4 seconds GENERAL DESCRIPTION The Am27C256 is a 256K-bit ultraviolet erasable pro- grammable read-only memory. It is organized as 32K words by 8 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast sin- gle address location programming. Products are avail- able in windowed ceramic DIP and LCC packages as well as plastic one time programmable (OTP) PDIP, TSOP, and PLCC packages. Typically, any byte can be accessed in less than 55 ns, allowing operation with high-performance microproces- sors without any WAIT states. The Am27C256 offers separate Output Enable (OE) and Chip Enable (CE) @ Latch-up protected to 100 mA from -1 V to Veco+1V @ High noise immunity @ Versatile features for simple interfacing Both CMOS and TTL input/output compatibility Two line control functions @ Standard 28-pin DIP, PDIP, 32-pin TSOP, LCC and LCC packages m@ DESC SMD No. 5962-86063 controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD's CMOS process technology provides high speed, low power, and high noise immunity. Typical power con- sumption is only 80 mW in active mode, and 100 pW in standby mode. All signals are TTL levels, including programming sig- nals. Bit locations may be programmed singly, in blocks, or at random. The Am27C256 supports AMD's Flashrite programming algorithm (100 ys pulses) re- sulting in typical programming time of 4 seconds. BLOCK DIAGRAM Data Outputs DQ0-DQ7 thhttttt Output Buffers Gating v O Vcc O> Vss O-> Vpp Output Enable OE 1 Chip Enable cE and Prog Logic Y > Decoder AOQ-A14 Address > Inputs _ X Decoder , Pi > 262,144 Bit Cell Matrix 08007G-1 2-34 Publication# 08007 Rev.G Amendment/o Issue Date: July 1993AMD al PRODUCT SELECTOR GUIDE Family Part No. Am27C256 Ordering Part No: Vcc + 5% -255 Vcc + 10% -55 -70 -90 -120 -150 -200 -250 Max Access Time (ns) 55 70 90 120 150 200 250 CE (E) Access Time (ns) 55 70 90 120 150 200 250 OE (G) Access Time (ns) 35 40 40 50 65 75 100 CONNECTION DIAGRAMS Top View DIP PLCC/LCC vee [ 10" 28 1 Vcc ai2[f2 271] ata A7[]3 261] A13 Ao [] 4 25] as ass 24[] ag AB A4[} 6 231] att AS a3 [7 22 1] OE G) A4 a2 8 211) ato A3 aif}s 20] cE) A2 Ao [] 10 191] DQ7 Al Dao [] 11 181] pas AO pat [f 12 1700 pas NC Dao paz13 = 16) daa vss Y 14 151] pas 08007G-2 1 JEDEC nomenclature is in parentheses. ~ 0800763 2. Dont use (DU) for PLCC. Am27C256 2-35al AMD TSOP* OF (G) TC] 1@ 32 [4 NC A11 CY 0 31 ( Ato AS C4 3 30 [-) CECE) A8 C4 4 29 FI DaQ7 Ai3 Cy 5 28 F-) D6 NC CJ 6 27 ( Das Ai4 Cy 7 26 LF Da4 Vec C4 8 Am27C256 25 [1 Das Vep CJ 9 Standard Pinout 24 [] Vss NC CJ 10 23 FE) Da2 Al2 (4 11 22 fF bat A7 co 12 21 ) DQo A6 CC] 43 20 (I NC A5 CJ] 14 19 EL Ao A4 C4 45 19 EI Al A3 C4 16 17 fF A2 08007G-4 *Contact local AMD sales office for package availability PIN DESIGNATIONS LOGIC SYMBOL A0-A14 = Address Inputs CE (E) = Chip Enable 15 Da0-Da7 = Data Inputs/Outputs cr AO-AI4 OE (G) = Output Enable Input Voc = Vcc Supply Voltage 3 Vpp = Program Supply Voltage DQ0-DQ7 c/> Vss = Ground +] CE () _-} OE (G) 08007G-5 2-36 Am27C256ORDERING INFORMATION EPROM Products AMD al AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C256 35 oD C ___.._ DEVICE NUMBER Am27C256 LL OPTIONAL PROCESSING Blank B Standard Processing Burn-in Hou TEMPERATURE RANGE C = Commercial (0C to +70C) Industrial (~40C to +85C) Extended Commercial (-55C to +125C) m- PACKAGE TYPE D = 28-Pin Ceramic DIP (CDV028) L = 32-Pin Rectangular Ceramic Leadless Chip Carrier (CLV032) SPEED OPTION See Product Selector Guide and Valid Combinations 256 Kilobit (32,768 x 8-Bit) CMOS EPROM Valid Combinations AM27C256-55 __| DC, DCB, DI, DIB AM27C256-70 LC, LCB, LI, LIB AMESGSSETZO) C008, DI AM27C256-41 5] DIB, DE, DEB, Move oc LC, LCB, LI, 256-200 | 1B, LE, LEB AM27C256-255 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the lo- cal AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am27C256 2-37cl AMD ORDERING INFORMATION OTP Products AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C256 -55 L_ OPTIONAL PROCESSING DEVICE NUMBER Am27C256 Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0C to +70C) | = Industrial (40C to + 85C) PACKAGE TYPE P = 28-Pin Plastic DIP (PD 028) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin TSOP (TS 032) SPEED OPTION See Product Selector Guide and Valid Combinations 256 Kilobit (32,768 x 8-Bit) CMOS OTP EPROM Valid Combinations AM27C256-55 AM27C256-70 AM27C256-90 AM27C256-120 AM27C256-150 AM27C256-200 AM27C256-255 JC, PC, EC, Ji, Pl, El Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the lo- cal AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 2-38 Am27C256AMD cl ORDERING INFORMATION Military APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of: AM27C256 -70 /B X A L_ LEAD FINISH A = Hot Solder Dip PACKAGE TYPE X = 28-Pin Ceramic DIP (CDV028) U = 32-Pin Rectangular Ceramic Leadless Chip Carrier (CLV032) DEVICE CLASS /B = Class B SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27C256 256 Kilobit (32,768 x 8-Bit) CMOS EPROM Valid Combinations Valid Combinations AM27C256-70 Valid Combinations list configurations planned to 7 be supported in volume for this device. Consult AM27C256-90 the local AMD sales office to confirm availability of AM27C256-120 /BXA. (BUA specific valid combinations and to check on newly AM27C256-150 , released combinations. AM27C256-200 AM27C256-250 Group A Tests Group A tests consist of Subgroups 1,2, 3, 7, 8,9, 10, 11. Am27C256 2-39zi AMD FUNCTIONAL DESCRIPTION Erasing the Am27C256 In order to clear all locations of their programmed con- tents, it is necessary to expose the Am27C256 to an ultraviolet light source. A dosage of 15 W sec/cmis re- quired to completely erase an Am27C256. This dosage can be obtained by exposure to an ultraviolet lamp wavelength of 2537 Awith intensity of 12,000 uW/cr? for 15 to 20 minutes. The Am27C256 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to era- sure. it is important to note that the Am27C256 and similar devices will erase with light sources having wavelengths shorter than 4000 A. Although erasure times will be much longer than with UV sources at 25374, exposure to fluorescent light and sunlight will eventually erase the Am27C256 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque label or substance. Programming the Am27C256 Upon delivery or after each erasure the Am27C256 has all 262,144 bits in the ONE or HIGH state. ZEROs are loaded into the Am27C256 through the procedure of programming. The programming mode is entered when 12.75 V + 0.25 Vis applied to the Vep pin, OE is at Vin, and CE is at Vit. For programming, the data to be programmed is applied 8 bits in parallel to the data output pins. The Flashrite algorithm reduces programming time by using 100 1s programming pulses and by giving each address only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum is reached. This process is re- peated while sequencing through each address of the Am27C256. This part of the algorithm is done at Vcc = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final ad- dress is completed, the entire EPROM memory is veri- fied at Vcc = Vep = 5.25 V. Please refer to Section 6 for programming flow chart and characteristics. Program Inhibit Programming of multiple Am27C256 in parallel with dif- ferent data is also easily accomplished. Except for CE, all like inputs of the parallel Am27C256 may be com- mon. A TTL low-level program pulse applied to an Am27C256 CE input with Vep = 12.75 V + 0.25 V, and OE High will program that Am27C256. A high-level CE input inhibits the other Am27C256 devices from being programmed. Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE at Vu, CE at Vin, and Vpp between 12.5 V to 13.0 V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that wiil identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C + 5C ambient temperature range that is required when programming the Am27C256. To activate this mode, the programming equipment must force 12.0 V + 0.5 V on address like AQ of the Am27C256. Two identifier bytes may then be se- quenced from the device outputs by toggling address line AO from Vit to Vin. All other address lines must be held at Vic during auto select mode. Byte 0 (AO = ViL) represents the manufacturer code, and byte 1 (AO = Vin), the device code. For the Am27C256, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The Am27C256 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power contro! and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. As- suming that addresses are stable, address access time (tacc ) is equal to the delay from CE to output (tce). Data is available at the outputs toe after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tacc -toe. Standby Mode The Am27C256 has a CMOS standby mode which re- duces the maximum Vcc current to 100 LA. It is placed in CMOS-standby when CE is at Vcc + 0.3 V. The Am27C256 also has a TTL-standby mode which re- duces the maximum Vcc current to 1.0 mA. It is placed in TTL-standby when CE is at Vin. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. 2-40 Am27C256Output OR-Tieing To accommodate multiple memory connections, a two- line control function is provided to allow for: m Low memory power dissipation m Assurance that output bus contention will not occur It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and con- nected to the READ line from the system control bus. This assures that all deselected memory devices are in low-power standby mode and that the output pins are only active when data is desired from a particular mem- ory device. AMD cl System Applications During the switch between active and standby condi- tions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. At a minimum, a 0.1-yF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and Vss to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM ar- rays, a 4.7-uF bulk electrolytic capacitor should be used between Vcc and Vss for each eight devices. The loca- tion of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE Pins Mode CE OE AO AS Vpp Outputs Read VIL ViL Xx X Vec DouT Output Disable X ViH X X Voc Hi-Z Standby (TTL) VIH xX x xX Voc Hi-Z Standby (CMOS) Vec + 0.3 V X X X Voc Hi-Z Program VIL VIH X X Vpp Din Program Verify VIH Vit X X Vep Dout Program Inhibit VIH VIH X Xx Vpp Hi-Z Manufacturer Auto Select Code VIL Vit VIL VH Voc O1H (Note 3) Device Code ViL VIL VIH VH Vcc 10H Notes: 1. Va =120V205V 2. X = Either Win or Vit 3. A1-A8=A10-Al4=Viu 4 . See DC Programming Characteristics for Vpp voltage during programming. Am27C256 2-41cl AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature OTP Products ............... 65C to +125C All Other Products ............ ~65C to +150C Ambient Temperature with Power Applied ............. 55C to +125C Voltage with Respect To Vss All pins except A9,Vpp ,Vcc (Note 1) ............... 0.6 V to Veco +0.5V AQ and Vpp (Note 2) ......... O.6Vt0o+13.5V VOC oc cee ee eee 0.6 Vto +7.0V Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During transitions, the inputs may overshoot Vss to 2.0 V for pe- riods of up to 20 ns. Maximum DC voltage on input and/O pins is Vcc + 0.5 V which may overshoot to Vcc + 2.0 Vfor periods up to 20 ns. 2. For A9 and Vpp the minimum DC input is -0.5 V. During transitions, A9 and Vpp may overshoot Vss to -2.0 V for periods of up to 20 ns. A9 and Vpp must not exceed 13.5 V for any period of time. Stresses above those listed under Absolute Maximum Rat- ings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for ex- tended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Case Temperature (Tc) ......... 0C to +70C Industrial (1) Devices Case Temperature (Tc) ....... 40C to +85C Extended Commercial (E) Devices Case Temperature (Tc) ...... 55C to +125C Military (M) Devices Case Temperature (Tc) ...... 55C to +125C Supply Read Voltages Vec for Am27C256-XX5 ..... +4.75 V to +5.25 V Vcc for AmM27C256-XX0 ..... +4.50 V to +5.50 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. 2-42 Am27C256AMD ol DC CHARACTERISTICS over operating range unless otherwise specified. (Notes 1, 2 and 4) (for APL Products, Group A, Subgroups 1, 2, 3, 7 and 8 are tested unless otherwise noted) Parameter Symbol | Parameter Description Test Conditions Min Max Unit VoH Output HIGH Voltage loH = 400 LA 2.4 Vv VoL Output LOW Voltage lo. = 2.1 mA 0.45 V VIH Input HIGH Voltage 2.0 Veco+O05]} V Vit Input LOW Voltage 0.5 +0.8 V Ii Input Load Current VIN = 0 V to +Voc 1.0 BA ILo Output Leakage Current Vout = 0 V to +Vcc C/l Devices 1.0 yA E/M Devices 5.0 lect Vec Active Current CE = VIL, f = 10 MHz, 25 mA (Note 3) lout = OmA Icc2 Vec TTL Standby Current CE = VIH 1.0 mA Icc3 Vcc CMOS Standby Current | CE = Vcc +0.3 V 100 LA IPPs Vep Current During Read CE = OE = VIL, Vp = Vcc 100 LA Notes: 1. Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. . Caution: The Am27C256 must not be removed from (or inserted into) a socket when Vcc or Vpp is applied. 2 3. Icc1 is tested with OE = Vix to simulate open outputs. 4 . Minimum DC Input Voltage is -0.5 V. During transitions, the inputs may overshoot to -2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is Vcc + 0.5 V, which may overshoot to Vcc + 2.0 V for periods less than 20 ns. 30 30 = 25 + 25 2 g I< 5 < C 20 SE 20 Ze Zs S 5 a o 15 oO 15 _ = 10 10 1 2 3 4 5 6 7 8 9 10 -75 -50 -25 0 25 50 75 100 125 150 Frequency in MHz Temperature in C Figure 1. Typical Supply Current Figure 2. Typical Supply Current vs. Frequency vs. Temperature Vee = 5.5 V, T = 25C Vec = 5.5 V, f = 10 MHz 08007G-6 08007G-7 Am27C256 2-43al AMD CAPACITANCE Parameter Parameter Test CLV032 CDV028 PL 032 PD 028 TS 032 Symbol Description Conditions| Typ | Max | Typ | Max | Typ | Max | Typ | Max | Typ | Max | Unit CIN Input Capacitance VIN = 0 11 14 8 12 8 12 6 10 10 12 pF CouT |Output Capacitance| Vout =0 10 14 8 12 8 12 8 10 12 14 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25C, f= 1 MHz. SWITCHING CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 3 and 4) (for APL Products, Group A, Subgroups 9,10 and 11 are tested unless otherwise noted) Parameter Am27C256 Symbols Parameter Test -255 JEDEC | Standard | Description Conditions -55 | -70 -90 | -120 | -150 | -200 | -250 | Unit tavav tacc Address to CE=OE=([Min| = - - - - - Output Delay Vit Max] 55 70 90 120 | 150 |} 200 | 250 ns tELav tCE Chip Enable to OE=Vi [Min] - - - - - - Output Delay Max] 55 70 90 120 | 150 | 200 | 250 ns teLav toe Output Enable to CE=Vi [Min] - - ~ - - - - Output Delay Max} 35 40 40 50 50 50 50 ns teHaz, toF Chip Enable HIGH or Min | | = | = =| = tGHaz (Note 2) Output Enable HIGH, Max| 25 25 25 30 30 30 30 ns whichever comes first, to Output Float tAxax toH Output Hold from Min 0 0 0 0 0 0 0 Addresses, CE, Max! - _ _ - _ _ ns or OE, whichever occurred first Notes: 1. Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Vep. This parameter is only sampled and not 100% tested. 2 3. Caution: The Am27C256 must not be removed from (or inserted into) a socket or board when Vpp or Vcc is applied. 4. For the -55 and -70: Output Load: 1 TTL gate and Ci = 30 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0 Vto3 V Timing Measurement Reference Level: 1.5 V for inputs and outputs For all other versions: Output Load: 1 TTL gate and Ci = 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs 2-44 Am27C256AMD ai SWITCHING TEST CIRCUIT 2.7 kQ Device Under Test +5.0 V Diodes = IN3064 or Equivalent CL = 100 pF including jig capacitance (30 pF for -55, -70) 08007G-8 SWITCHING TEST WAVEFORM 2.4V 3V 2.0 VX > Tes Poins Vy 1.5 V % Test Points =X 1s V 0.45 V OV Input Output Input Output 08007G-9 AC Testing: Inputs are driven at 2.4 V for a logic 1 AC Testing: Inputs are driven at 3.0 V for a logic 1 and 0.45 V for a logic 0. Input pulse and 0 V for alogic 0. Input pulse rise and rise and fall times are < 20 ns. fall times are < 20 ns for -55 and -70. Am27C256 2-45cl AMD KEY TO SWITCHING TEST WAVEFORMS WAVEFORM INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from H to L from H toL May Will Be Change Changing from L to H from L to H Don't Care, Changing Any Change State Permitted Unknown Does Not Center Apply Line is High Impedence Off State KS000010 SWITCHING WAVEFORMS Addresses Mt 2.0 Addresses Valid 2.0 _0.8 ____ 9.8 _ te - \ 7 _ tDF taco Ed (Note 2) ______! tOH . Note 1) -- . High Z ( - High Z Output (CCC Valid Output )) _ Notes: 08007G-10 1. OE may be delayed up to tacc - toe after the falling edge of the addresses without impact on tacc. 2. tor is specified from OE or CE, whichever occurs first. 2-46 Am27C256