Semiconductor Components Industries, LLC, 2001
October, 2001 – Rev. 7 1Publication Order Number:
SN74LS194A/D
SN74LS194A
4-Bit Bidirectional
Universal Shift Register
The SN74LS194A is a High Speed 4-Bit Bidirectional Universal
Shift Register. As a high speed multifunctional sequential building
block, it is useful in a wide variety of applications. It may be used in
serial-serial, shift left, shift right, serial-parallel, parallel-serial, and
parallel-parallel data register transfers. The LS194A is similar in
operation to the LS195A Universal Shift Register, with added features
of shift left without external connections and hold (do nothing) modes
of operation. It utilizes the Schottky diode clamped process to achieve
high speeds and is fully compatible with all ON Semiconductor TTL
families.
•Typical Shift Frequency of 36 MHz
•Asynchronous Master Reset
•Hold (Do Nothing) Mode
•Fully Synchronous Serial or Parallel Data Transfers
•Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range 0 25 70 °C
IOH Output Current – High –0.4 mA
IOL Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
SOIC
D SUFFIX
CASE 751B
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
Device Package Shipping
ORDERING INFORMATION
SN74LS194AN 16 Pin DIP 2000 Units/Box
SN74LS194AD SOIC–16 38 Units/Rail
SN74LS194ADR2 SOIC–16 2500/Tape & Reel
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SN74LS194A
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Mode Control Inputs
Parallel Data Inputs
Serial (Shift Right) Data Input
Serial (Shift Left) Data Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs
S0, S1
P0 - P3
DSR
DSL
CP
MR
Q0 - Q3
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
14 13 12 11 10 9
123456 7
16 15
8
VCC
MR
Q0Q1Q2Q3S1
CP S0
DSR P0P1P2P3DSL GND
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3
LOGIC DIAGRAM
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
S1
S0
DSR DSL
CP
MR
Q0Q1Q2Q3
P0P1P2P3
14
1
2
6
7
345
9
11
12
10
1315
SQ
0
CP
R
CLEAR
SQ
1
CP
R
CLEAR
SQ
2
CP
R
CLEAR
SQ
3
CP
R
CLEAR
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the
functional characteristics of the LS194A 4-Bit Bidirectional
Shift Register. The LS194A is similar in operation to the
ON Semiconductor LS195A Universal Shift Register when
used in serial or parallel data register transfers. Some of the
common features of the two devices are described below:
All data and mode control inputs are edge-triggered,
responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control and selected data inputs must be stable one set-up
time prior to the positive transition of the clock pulse.
The register is fully synchronous, with all operations
taking place in less than 15 ns (typical) making the device
especially useful for implementing very high speed CPUs,
or the memory buffer registers.
The four parallel data inputs (P0, P1, P2, P3) are D-type
inputs. When both S0 and S1 are HIGH, the data appearing
on P 0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2,
and Q3 outputs respectively following the next LOW to
HIGH transition of the clock.
The asynchronous Master Reset (MR), when LOW,
overrides all other input conditions and forces the Q outputs
LOW.
Special logic features of the LS194A design which
increase the range of application are described below:
Two mode control inputs (S0, S1) determine the
synchronous operation of the device. As shown in the Mode
Selection Table, data can be entered and shifted from left to
right (shift right, Q0 Q1, etc.) or right to left (shift left, Q 3
Q2, etc.), or parallel data can be entered loading all four
bits of the register simultaneously. When both S0 and S1,are
LOW, the existing data is retained in a “do nothing” mode
without restricting the HIGH to LOW clock transition.
D-type serial data inputs (DSR, DSL) are provided on both
the first and last stages to allow multistage shift right or shift
left data transfers without interfering with parallel load
operation.
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MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS OUTPUTS
OPERATING MODE MR S1S0DSR DSL PnQ0Q1Q2Q3
Reset L X X X X X L L L L
Hold H I I X X X q0q1q2q3
Shift Left H h I X I X q1q2q3L
H h I X h X q1q2q3H
Shift Right H I h I X X L q0q1q2
H I h h X X H q0q1q2
Parallel Load H h h X X PnP0P1P2P3
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition
pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.8 VGuaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Out
p
ut LOW Voltage
0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN VIL or VIH
VOL Output LOW Voltage 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH
per Truth Table
IIH
In
p
ut HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH Current 0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 23 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Clock Frequency 25 36 MHz
tPLH
tPHL Propagation Delay,
Clock to Output 14
17 22
26 ns VCC = 5.0 V
CL
=
15
p
F
tPHL Propagation Delay,
MR to Output 19 30 ns
C
L =
15
pF
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AC SETUP REQUIREMENTS (TA = 25°C)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tWClock or MR Pulse Width 20 ns
tsMode Control Setup Time 30 ns
tsData Setup Time 20 ns VCC = 5.0 V
thHold time, Any Input 0 ns
CC
trec Recovery Time 25 ns
DEFINITIONS OF TERMS
SETUP TIME(ts) —is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — i s defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays Clock Pulse
Width and fmax
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
1.3 V
1.3 V
OTHER CONDITIONS: S1 = L, MR = H, S0 = H
OTHER CONDITIONS: S0, S1 = H
OTHER CONDITIONS: PO = P1 = P2 = P3 = H
OTHER CONDITIONS: MR = H
OTHER CONDITIONS: *DSR SETUP TIME AFFECTS Q0 ONLY
OTHER CONDITIONS: DSL SETUP TIME AFFECTS Q3 ONLY
OTHER CONDITIONS: MR = H
S0
S1
DSR DSL
P0 P1 P2 P3
CLOCK
OUTPUT*
(--- IS SHIFT LEFT)
CLOCK
CLOCK
CLOCK
OUTPUT
OUTPUT
S0 S1
ts(H)
th(L) = 0 th(H) = 0
th(H) = 0
ts(H)
th(L) = 0
ts(L)
th = 0 th = 0
(STABLE TIME)
tPHL tPLH
1/fmax
tW
ts(L)
MR
tWtrec
tPHL
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
tsts
Figure 3. Setup (ts) and Hold (th) Time for Serial Data
(DSR, DSL) and Parallel Data (P0, P1, P2, P3)
Figure 4. Setup (ts) and Hold (th) Time for S Input
SN74LS194A
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6
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
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7
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45
G
8 PLP
–B–
–A–
M
0.25 (0.010) B S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019

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8
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SN74LS194A/D
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