WMS7121100P - Winbond Electronics

PRELIMINARY DATASHEET

Publication Release Date: July 2003

- 1 - Revision 1.0

WMS7120 / 7121

NON-VOLATILE DIGITAL POTENTIOMETERS

WITH UP/DOWN (3-WIRE) INTERFACE,

10KOHM, 50KOHM, 100KOHM RESISTANCE

64 TAPS

WITHOUT / WITH OUTPUT BUFFER

WMS7120 / 7121

- 2 -

1. GENERAL DESCRIPTION

The WMS7120/7121 is a single channel 64-tap non-volatile linear digital potentiometer available in

10KΩ, 50KΩ and 100KΩ resistance. The device consists of Up/Down serial interface, tap register,

decoder, resistor array, wiper switches, NV memory and control logics.

The WMS7120 device can be configured as a two-terminal variable resistor or a three-terminal voltage

divider without an output buffer, but the WMS7121 device, which has a built-in output buffer, can only

be configured as a three-terminal voltage divider. Both devices can be used in a wide variety of

applications.

The output of the potentiometer is determined by its wiper position, which varies linearly between its

end terminals, RA/VA and RB/VB. The wiper position, Rw/Vw, is controlled by Up/Down serial interface

(CS , INC and U/D) through the Tap Register (TR). In addition, the wiper position can also be

stored into a non-volatile memory location (NVMEM0), which is then automatically recalled upon

power up.

2. FEATURES

• Drop-in replacement for many popular parts

• Single linear-taper channel

• 64 taps

• 10K, 50K and 100K end-to-end resistance

• VSS to VDD terminal voltages

• Automatic recall of wiper position when power-on

• Potentiometer control through Up/Down (3-wire) serial interface

• Endurance 100,000 cycles

• Data retention 100 years

• Package options:

- 8-pin PDIP, SOIC or MSOP

• Industrial temperature range: -40° to 85°C

• Single supply operation : 2.7V to 5.5V

WMS7120 / 7121

Publication Release Date: July 2003

- 3 - Revision 1.0

Up/Down

Serial

Interface

Tap Register

Decode

r

NVMEM0

NV Memory

Control

CS

VSS VDD

VA

VB

VW

INC

U/D

3. BLOCK DIAGRAM

FIGURE 1 – WMS7120 BLOCK DIAGRAM (Rheostat/Divider Mode)

FIGURE 2 – WMS7121 BLOCK DIAGRAM (Divider Mode)

Up/Down

Serial

Interface

Tap Register

Decoder

NVMEM0

NV Memory

Control

CS

V

SS

VDD

RA/VA

INC

U /D

RW/VW

RB/VB

WMS7120 / 7121

- 4 -

4. TABLE OF CONTENTS

1. GENERAL DESCRIPTION.................................................................................................................. 2

2. FEATURES ......................................................................................................................................... 2

3. BLOCK DIAGRAM............................................................................................................................... 3

4. TABLE OF CONTENTS ...................................................................................................................... 4

5. PIN CONFIGURATION ....................................................................................................................... 5

6. PIN DESCRIPTION ............................................................................................................................. 6

7. FUNCTIONAL DESCRIPTION............................................................................................................ 7

7.1. Rheostat And Divider Operations ........................................................................................... 7

7.1.1. Rheostat Configuration .......................................................................................................... 7

7.1.2. Divider Configuration.............................................................................................................. 7

7.2. Non-Volatile Memory (NVMEM0) ........................................................................................... 7

7.3. Serial Data Interface ................................................................................................................. 8

7.4. Operation Overview .................................................................................................................. 8

8. TIMING DIAGRAMS............................................................................................................................ 9

9. ABSOLUTE MAXIMUM RATINGS & OPERATING CONDITIONS .................................................. 11

10. ELECTRICAL CHARACTERISTICS ............................................................................................... 12

10.1 Test Circuits ............................................................................................................................ 14

11. TYPICAL APPLICATION CIRCUITS............................................................................................... 15

11.1. Layout Considerations.......................................................................................................... 17

12. PACKAGE DRAWINGS AND DIMENSIONS.................................................................................. 18

13. ORDERING INFORMATION........................................................................................................... 21

14. VERSION HISTORY ....................................................................................................................... 22

WMS7120 / 7121

Publication Release Date: July 2003

- 5 - Revision 1.0

5. PIN CONFIGURATION

1

VSS

1

2

3

45

6

7

8

2

3

45

6

7

8

1

2

3

45

6

7

8

INC VDD

U/D

RA/VA

CS

RB/VB

Rw/VW

VSS Rw/VW

Rw/VW

8-MSOP

8-SOIC

8-PDIP

INC

U/D

RA/VA

VDD

CS

RB/VB

VSS

INC

U/D

RA/VA

VDD

CS

RB/VB

WMS7120 / 7121

- 6 -

6. PIN DESCRIPTION

TABLE 1 – PIN DESCRIPTION

Pin Name Description

CS

Chip Select: When CS is LOW, the device is enabled.

When CS is HIGH, the part is deselected and is in

standby mode

U/D

Up/Down Control: HIGH state enables the wiper to

move towards the RA / VA terminal, while LOW state

implies the wiper moves towards the RB / VB terminal

INC

Increment Control: When CS is LOW, a HIGH-LOW

transition on INC will move the wiper one increment

either up or down based on the U/ D input

RA/VA High terminal of the device

RB/VB Low terminal of the device

RW/VW Wiper Terminal: Output of the resistor array is determined

by the INC , U/ D and CS inputs

VSS Ground pin, logic ground reference

VDD Power Supply

Notes: The terminology of high and low terminals above references to the relative

position of the terminal with respect to the wiper moving direction and not the

voltage potential of the terminal.

WMS7120 / 7121

Publication Release Date: July 2003

- 7 - Revision 1.0

7. FUNCTIONAL DESCRIPTION

7.1. RHEOSTAT AND DIVIDER OPERATIONS

The WMS7120 device can operate as either a two-terminal variable resistor or a three-terminal

voltage divider without an output buffer. However, the WMS7121 can only operate in a three-terminal

voltage divider with an output buffer.

7.1.1. Rheostat Configuration

In the rheostat mode, the WMS7120 can be configured as a two-terminal resistive element, where one

terminal is connected to one end of the resistor (RA or RB) and the other terminal is the wiper (RW).

The moving direction of the wiper depends upon the setting of U/Dcontrol signal. When the U/D is

set to Up, then the wiper moves towards RA. Conversely, when the U/ D is set to Down, then the

wiper moves towards RB. The wiper movement to either direction is controlled by toggling the INC

signal from HIGH to LOW.

This configuration controls the resistance between the wiper and either end. The wiper resistance can

be adjusted by either changing the wiper position or loading a stored wiper position value from

NVMEM0 upon power up.

7.1.2. Divider Configuration

Additionally, the WMS7120 can also be configured as a voltage divider. With an input voltage applied

to one end (usually VA ), the ground is connected to the other end (usually VB). These input voltages

cannot exceed the VDD level or go below the VSS level. The voltage on the wiper, VW, is proportional

to the wiper position with respect to the voltage difference between VA and VB. The moving direction of

the wiper depends upon the setting of the U/ D control signal. When the U/D is set to Up, then the

wiper moves towards VA. Conversely, when the U/D is set to Down, then the wiper moves towards

VB. The wiper movement to either direction is controlled by toggling the INC signal from HIGH to

LOW.

Nevertheless, the WMS7121 can only be configured as a voltage divider and operate similarly as the

WMS7120 device. The only difference is WMS7121 has an output buffer, but WMS7120 doesn’t have.

Besides, the resistance cannot be directly measured in this configuration.

7.2. NON-VOLATILE MEMORY (NVMEM0)

The WMS7120/7121 has one NVMEM0 location available for storing the current wiper position via the

Up/Down serial interface. This stored value is automatically recalled and loaded into the tap register

upon power up.

WMS7120 / 7121

- 8 -

7.3. SERIAL DATA INTERFACE

The WMS7120/7121 device has a 3-wire Up/Down Serial Interface consisting of CS , INC and U/D

control signals. The key features of this interface include:

• Enabling the device

• Determining the moving direction of the wiper

• Increment/Decrement operation on the wiper

• Non-volatile storage of the present wiper position into the NVMEM0 for automatic recall at

power up

• Entering into the standby mode

7.4. OPERATION OVERVIEW

The wiper position can be changed either up or down by operating the CS , U/D and INC control

signals.

When CS is LOW, the device is selected and the wiper can be moved by toggling the INC . As a

result, the wiper moves up when U/D is HIGH and moves down when U/D is LOW. The status of the

U/D can be changed even though the CS remains LOW. This allows the system to enable the

device and then move the wiper position either up or down until the desired position is reached.

When the wiper is already at the lowest position, further Down operation won’t change the wiper

position. Similarly, when the wiper is at the highest position, further Up operation won’t change the

wiper position too.

The current wiper position can be automatically stored into the NVMEM0 each time the CS goes

from LOW to HIGH while the INC remains HIGH. Adversely, if the INC is LOW when the CS goes

HIGH, the wiper position cannot be stored. Meanwhile, the NVMEM0 content is automatically loaded

into the wiper during power on.

When the CS is held HIGH, the device enters into Standby mode and the wiper position cannot be

changed. Changing the CS to LOW exits the Standby mode and enables the device again.

The operating modes of Up/Down interface are summarized in the table below:

CS U/D INC Operation

LOW HIGH HIGH to LOW Move Wiper toward RA /VA

LOW LOW HIGH to LOW Move Wiper toward RB /VB

LOW to HIGH x HIGH Store Current Wiper Position

LOW to HIGH x LOW No Store, Return to Standby

HIGH x x Standby

Note: x means don’t care

WMS7120 / 7121

Publication Release Date: July 2003

- 9 - Revision 1.0

8. TIMING DIAGRAMS

Conditions: VDD = +2.7V to 5.5V, VA = VDD, VB = 0V, T = 25°C

FIGURE 3 –WMS7120/1 TIMING DIAGRAM

Note:

[1] This only applies to the Power-Up sequence.

[2] MI in the AC Timing diagram (Figure 3) refers to the minimum incremental change in the wiper output due to a change in the

wiper position.

U

/D

CS

INC

t

I

L

t

I

H

t

C

YC

V

W

MI

[

2

]

90%

10%

(store)

tCPH

t

I

W

t

PUD

[

1

]

tCI

tDI tID tF tR

WMS7120 / 7121

- 10 -

TABLE 10 – TIMING PARAMETERS

PARAMETERS SYMBOL MIN. MAX. UNITS

CS to INC Setup tCI 100 ns

U/D to INC Setup tDI 50 ns

U/D to INC Hold tID 100 ns

INC LOW Period tIL 250 ns

INC HIGH Period tIH 250 ns

INC Inactive to CS Inactive tIC 1

µs

CS Deselect Time (NO STORE) tCPH 100 ns

CS Deselect Time (STORE) tCPH

15 (2.7V)

30 (5.5V)

ms

INC to Wiper Change tIW 5

µs

INC Cycle Time tCYC 1

µs

INC Input Rise and Fall Time tR, tF

500

µs

Power-Up Delay tPUD 1 ms

VCC Power-Up rate tR VCC

0.2

(13ms

0-2.7V)

50

(54µs

0-2.7V)

V/ms

WMS7120 / 7121

Publication Release Date: July 2003

- 11 - Revision 1.0

9. ABSOLUTE MAXIMUM RATINGS & OPERATING CONDITIONS

TABLE 11 – ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS) [1]

Conditions Values

Junction temperature 150ºC

Storage temperature -65º to +150ºC

Voltage applied to any pad (Vss – 0.3V) to (VDD + 0.3V)

Lead temperature (soldering – 10 seconds) 300ºC

VSS – VDD -0.3 to 7.0V

TABLE 12 – OPERATING CONDITIONS (PACKAGED PARTS)

Conditions Values

Industrial operating temperature -40ºC to +85ºC

Supply voltage (VDD) +2.7V to +5.5V

Ground voltage (VSS) 0V

[1] Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum

ratings may affect device performance and reliability. Functional operation is not implied at these conditions.

WMS7120 / 7121

- 12 -

10. ELECTRICAL CHARACTERISTICS

TABLE 12 – ELECTRICAL CHARACTERISTICS (Packaged parts)

PARAMETERS SYMBOL MIN. TYP. MAX. UNITS CONDITIONDS [5]

Rheostat Mode

Nominal Resistance R -20 +20 % T=25ºC, Wiper open

Different Non Linearity [2] R-DNL -1

±0.2 +1 LSB

[6]

Integral Non Linearity [2] R-INL -1

±0.4 +1 LSB

[6]

Tempo [1] ∆RAB/∆T 300

ppm/°C

Wiper Resistance [2] RW 50 Ω V

DD=5V, I=VDD/RTotal

[7]

80 Ω V

DD=2.7V, I=VDD/RTotal

[7]

Wiper Current IW -1 1 mA

Divider Mode

Resolution N 8 Bits

Different Non Linearity [2] DNL -1

±0.5 +1 LSB

Integral Non Linearity [2] INL -1

±0.5 +1 LSB

Temperature Coefficient [1] ∆W /∆T +20 ppm/°C Wiper at center

Full Scale Error VFSE -1 0 LSB Wiper at highest position

Zero Scale Error VZSE 0 1 LSB Wiper at lowest position

Resistor Terminal

Voltage Range VA, VB, VW V

SS V

DD V

Terminal Capacitance [1] CA, CB 30 pF

Wiper Capacitance [1] 30 pF

Dynamic Characteristics [1]

BW10K 1.5 MHz VDD=5V, B =VSS

Bandwidth –3dB BW50K 300 KHz Wiper at center

BW100K 200 KHz

Analog Output (Buffer enables)

Amp Output Current IOUT 3 mA VO=1/2 scale

Amp Output Resistance Rout 1 10 Ω I

L = 100uA

Total Harmonic Distortion [1] THD 0.08 %

A =2.5V, VDD=5V, f=1kHz,

VIN=1VRMS

Digital Inputs/Outputs

Input High Voltage VIH 0.7xVDD V

Input Low Voltage VIL 0.3xVDD V

Output Low Voltage VOL 0.4 V IOL=2mA

WMS7120 / 7121

Publication Release Date: July 2003

- 13 - Revision 1.0

TABLE 12 – ELECTRICAL CHARACTERISTICS (Packaged parts) – Cont’d

PARAMETERS SYMBOL MIN. TYP. MAX. UNITS CONDITIONDS [5]

Input Leakage Current ILI -1 +1 uA

CS =VDD,Vin=Vss ~ VDD

Output Leakage Current ILo -1 +1 uA

CS =VDD,Vin=VSS ~ VDD

Input Capacitance [1] CIN 25 pF VDD=5V, fc = 1Mhz

Output Capacitance [1] COUT 25 pF VDD=5V, fc = 1Mhz

Power Requirements

Operating Voltage VDD 2.7 5.5 V

Operating Current IDDR, IDDW 1 2 mA All operations

ISA

[3] 0.5 1 mA

Buffer = ON

CS = HIGH, no load

Standby Current

ISB

[4] 0.1 1 uA

Buffer = OFF

CS = HIGH, no load

Power Supply Rejection

Ratio PSRR 1 LSB/V

VDD=5V±10%, Wiper at center

Notes:

[1] Not subject to production test.

[2] LSB = (RA/VA – RB/VB) / (T - 1); DNL = (Vi - Vi+1) / LSB + 1 (if increment) or = (Vi -

Vi+1) / LSB - 1 (if decrement); INL = (Vi - i*LSB) / LSB; where i = [0, (T -1)] and T =

# of taps of the device.

[3] WMS7121 only.

[4] WMS7120 only.

[5] Conditions: VCC = 2.7 to 5.5V, T = 25ºC and timing measured at 50% level, unless stated.

[6] Only guarantee by design.

[7] Rtotal = end-to-end resistance.

WMS7120 / 7121

- 14 -

10.1 TEST CIRCUITS

FIGURE 4 – TEST CIRCUITS

Potentiometer divider nonlinearit

y

error

test circuit

(

INL, DNL

)

*Assume infinite in

p

ut im

p

edance

V+

VMS*

V+ = VDD

1LSB

=

V

+

/

63

WMS71xx

VA

VB

VW

Resistor

p

osition nonlinearit

y

error test

circuit (Rheostat Operation: R-INL, R-DNL)

*Assume infinite in

p

ut im

p

edance

No Connection

V

MS

*

WMS71xx

W

RA

RB

RW

IW

WMS71xx

Wi

p

er resistance test circuit

*Assume infinite in

p

ut im

p

edance

V

MS

*

WMS71xx

VA

VB

VW

IW

I

W

= V

DD

/R

Total

R

W

= V

MS

/I

W

Power supply sensitivity test circuit (PSS, PSRR)

*Assume infinite in

p

ut im

p

edance

+

V

VA

VB

VW

VMS*

PSRR

(

dB

)

= 20LOG

(

)

∆

VMS

∆

VDD

PSS

(

%/%

)

=

∆

V

MS

∆

V

DD

WMS71xx

VAVB

VW

VIN

~

+5V

2.5V DC

Offset

V

OUT

Ca

p

acitance test circuit

VA

VB

WMS71xx

VW

VIN ~

+5V

2.5V DC

VOUT

OFFSET

GND

Gain vs. fre

q

uenc

y

test circuit

VA

V

A

= VDD

V+= VDD ± 10%

WMS7120 / 7121

Publication Release Date: July 2003

- 15 - Revision 1.0

11. TYPICAL APPLICATION CIRCUITS

Vin

V

OUT = - VIN

A

B

R

RA = , R

B =

R

AB = Total resistance of potentiometer

W = Wiper setting for WMS71XX

FIGURE 5 – PROGRAMMABLE INVERTING GAIN AMPLIFIER USING THE WMS7120/7121

V

OUT = VIN (1+

A

B

R

R)

RA = , R

B =

R

AB = Total resistance of potentiometer

W = Wiper setting for WMS71XX

FIGURE 6 – PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING THE WMS7120/7121

OP

A

MP

_

VOUT

WMS71XX

+

OP

A

MP

VIN VOUT

WMS71XX

_

R

A R

B

R

A R

B

+

RAB (64-W)

64 64

RAB*W

RAB (64-W)

64 64

RAB*W

WMS7120 / 7121

- 16 -

FIGURE 7 – WMS7121 TRIMMING VOLTAGE REFERENCE

FIGURE 8 – WMS7121 RF AMP CONTROL

FILTER

L1

CHOKE

WMS71xx WINPOT

CS\

U/D\

INC\

VSS

R

A/VA

R

W/VW

R

B/VB

V

DD

RF Input

RF OUT

Q1

RF POWER AMP

C1

0.1uF

C2

CS\

INC\ U/D\

VREFH

WMS71xx

V+

GND

VREF = 5.0v

0V

5V

Vout

WMS7120 / 7121

Publication Release Date: July 2003

- 17 - Revision 1.0

11.1. LAYOUT CONSIDERATIONS

Use a 0.1µF bypass capacitor as close as possible to the VDD pin. This is recommended for best

performance. Often this can be done by placing the surface mount capacitor on the bottom side of the

PC board, directly between the VDD and VSS pins. Care should be taken to separate the analog and

digital traces. Sensitive traces should not run under the device or close to the bypass capacitors.

A dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals.

CAP

VDD

CS

RB/VB

RW/VW

INC

U/D

RA/VA

VSS

ANALOG

SIGNAL LINES

DIGITAL

CONTROL LINES

ANALOG

SIGNAL LINE

DIGITAL

CONTROL LINE

FIGURE 9 – WMS7120/7121 LAYOUT

WMS7120 / 7121

- 18 -

12. PACKAGE DRAWINGS AND DIMENSIONS

E

1

85

4

Control demensions are in milmeters .

θ

E

FIGURE 10: 8L 150MIL SOIC

WMS7120 / 7121

Publication Release Date: July 2003

- 19 - Revision 1.0

1.631.47

0.0640.058

Symbol Min Nom Max Max

Nom

Min

Dim ension in in ch Dim ension in m m

A

B

c

D

e

A

L

S

A

1

2

E

0.060 1.52

0.175 4.45

0.010

0.125

0.016 0.130

0.018

0.135

0.022

3.18

0.41

0.25

3.30

0.46

3.43

0.56

0.008

0.120

0.375

0.010

0.130

0.014

0.140

0.20

3.05

0.25

3.30

0.36

3.56

0.255

0.250

0.245 6.486.35

6.22

9.53

7.62

7.37 7.87

0.3000.290 0.310

2.29 2.54 2.790.090 0.100 0.110

B

1

e

E

1

0.360 0.380 9.14 9.65

0 15

0.045 1.14

0.355

0.335 8.51 9.02

150

Seating Plane

eA

2

A

c

E

Base Plane

1

A

1

e

L

A

S

1

E

D

1

B

8 5

1 4

α

FIGURE 11: 8L 300MIL PDIP

WMS7120 / 7121

- 20 -

FIGURE 12: 8L 3MM MSOP

WMS7120 / 7121

Publication Release Date: July 2003

- 21 - Revision 1.0

13. ORDERING INFORMATION

Winbond’s WinPot Part Number Description:

Output

Buffer

End-to-End

Resistance

SOIC PDIP MSOP

10K WMS7120010S WMS7120010P WMS7120010M

50K WMS7120050S WMS7120050P WMS7120050M

NO

100K WMS7120100S WMS7120100P WMS7120100M

10K WMS7121010S WMS7121010P WMS7121010M

50K WMS7121050S WMS7121050P WMS7121050M

YES

100K WMS7121100S WMS7121100P WMS7121100M

Notes:

Part number with white background: Available for sampling and mass production.

Part numbers with shaded background: Call factory for availability.

For the latest product information, access Winbond’s worldwide website at

http://www.winbond-usa.com

T B RRR P Winbond WinPot Products w/ Up-Down Interface

Number Of Taps:

2 = 64

WMS71

For Up/Down interface:

0 : No buffer

1 : With buffer

End-to-end Resistance:

010: 10Kohm

050: 50Kohm

100: 100Kohm

Package:

S: SOIC

P: PDIP

M: MSOP

WMS7120 / 7121

- 22 -

14. VERSION HISTORY

VERSION DATE DESCRIPTION

1.0 July 2003 Initial issue

Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

No. 4, Creation Rd. III 2727 North First Street, San Jose, 27F, 299 Yan An W. Rd. Shanghai,

Science-Based Industrial Park, CA 95134, U.S.A. 200336 China

Hsinchu, Taiwan TEL: 1-408-9436666 TEL: 86-21-62365999

TEL: 886-3-5770066 FAX: 1-408-5441797 FAX: 86-21-62356998

FAX: 886-3-5665577 http://www.winbond-usa.com/

http://www.winbond.com.tw/

Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd.

9F, No. 480, Pueiguang Rd. 7F Daini-ueno BLDG. 3-7-18 Unit 9-15, 22F, Millennium City,

Neihu District Shinyokohama Kohokuku, No. 378 Kwun Tong Rd.,

Taipei, 114 Taiwan Yokohama, 222-0033 Kowloon, Hong Kong

TEL: 886-2-81777168 TEL: 81-45-4781881 TEL: 852-27513100

FAX: 886-2-87153579 FAX: 81-45-4781800 FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.

This product incorporates SuperFlash® technology licensed from SST.

The contents of this document are provided only as a guide for the applications of Winbond

products. Winbond makes no representation or warranties with respect to the accuracy o

r

completeness of the contents of this publication and reserves the right to discontinue or make

changes to specifications and product descriptions at any time without notice. No license, whethe

r

express or implied, to any intellectual property or other right of Winbond or others is granted by this

publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond

assumes no liability whatsoever and disclaims any express or implied warranty of merchantability,

fitness for a particular purpose or infringement of any Intellectual property.

Winbond products are not designed, intended, authorized or warranted for use as components in

systems or equipments intended for surgical implantation, atomic energy control instruments,

airplane or spaceship instruments, transportation instruments, traffic signal instruments,

combustion control instruments, or for other applications intended to support or sustain life.

Further, Winbond products are not intended for applications wherein failure of Winbond products

could result or lead to a situation wherein personal injury, death or severe property o

r

environmental in

j

ur

y

could occur.