Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LM5105 SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 LM5105 100-V Half-Bridge Gate Driver With Programmable Dead Time 1 Features 3 Description * The LM5105 is a high-voltage gate driver designed to drive both the high-side and low-side N-Channel MOSFETs in a synchronous buck or half-bridge configuration. The floating high-side driver is capable of working with rail voltages up to 100 V. The single control input is compatible with TTL signal levels and a single external resistor programs the switching transition dead time through tightly matched turnon delay circuits. A high-voltage diode is provided to charge the high-side gate-drive bootstrap capacitor. The robust level shift technology operates at high speed while consuming low power and provides clean output transitions. Undervoltage lockout disables the gate driver when either the low-side or the bootstrapped high-side supply voltage is below the operating threshold. The LM5105 is offered in the thermally enhanced WSON plastic package. 1 * * * * * * * * * * * Drives Both a High-Side and Low-Side N-Channel MOSFET 1.8-A Peak Gate Drive Current Bootstrap Supply Voltage Range up to 118-V DC Integrated Bootstrap Diode Single TTL Compatible Input Programmable Turnon Delays (Dead Time) Enable Input Pin Fast Turnoff Propagation Delays (26 ns Typical) Drives 1000 pF With 15-ns Rise and Fall Time Supply Rail Undervoltage Lockout Low Power Consumption Package: Thermally Enhanced 10-Pin WSON (4 mm x 4 mm) Device Information(1) 2 Applications * * PART NUMBER Solid-State Motor Drives Half- and Full-Bridge Power Converters LM5105 PACKAGE WSON (10) BODY SIZE (NOM) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Application Diagram HB VDD HB UVLO HO LEVEL SHIFT DRIVER HS VDD UVLO VSS IN LEADING EDGE DELAY RDT LEADING EDGE DELAY EN VDD DRIVER LO Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5105 SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 5 5 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes ....................................... 11 11 11 12 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application .................................................. 13 9 Power Supply Recommendations...................... 16 9.1 Power Dissipation Considerations .......................... 16 9.2 HS Transient Voltages Below Ground .................... 16 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Example ................................................... 17 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 18 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (March 2016) to Revision E * Updated values in the Thermal Information table to align with JEDEC standards................................................................. 5 Changes from Revision C (March 2013) to Revision D * 2 Page Added Device Information table, ESD Ratings, Detailed Description section, Application and Implementation section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................. 1 Changes from Revision B (March 2013) to Revision C * Page Page Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 13 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 LM5105 www.ti.com SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 5 Pin Configuration and Functions DPR Package 10-Pin WSON Top View VDD 1 10 LO HB 2 9 VSS HO 3 8 IN HS 4 7 EN NC 5 6 RDT Not to scale Pin Functions PIN NO. NAME TYPE (1) DESCRIPTION 1 VDD P Positive gate drive supply. Decouple VDD to VSS using a low ESR/ESL capacitor, placed as close to the IC as possible. 2 HB P High-side gate driver bootstrap rail. Connect the positive terminal of bootstrap capacitor to the HB pin and connect negative terminal to HS. The Bootstrap capacitor must be placed as close to IC as possible. 3 HO O High-side gate driver output. Connect to the gate of high side N-MOS device through a short, low inductance path. 4 HS P High-side MOSFET source connection. Connect to the negative terminal of the bootstrap capacitor and to the source of the high side N-MOS device. 5 NC -- Not connected. 6 RDT I Dead-time programming pin. A resistor from RDT to VSS programs the turnon delay of both the high and low side MOSFETs. The resistor must be placed close to the IC to minimize noise coupling from adjacent PCB traces. 7 EN I Logic input for driver disable or enable. TTL compatible threshold with hysteresis. LO and HO are held in the low state when EN is low. 8 IN I Logic input for gate driver. TTL compatible threshold with hysteresis. The high side MOSFET is turned on and the low side MOSFET turned off when IN is high. 9 VSS G Ground return. All signals are referenced to this ground. 10 LO O Low-side gate driver output. Connect to the gate of the low side N-MOS device with a short, low inductance path. -- Exposed Pad -- It is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PCB to aid thermal dissipation. (1) G = Ground, I = Input, O = Output, P = Power Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 3 LM5105 SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT VDD to VSS -0.3 18 V HB to HS -0.3 18 V IN and EN to VSS -0.3 VDD + 0.3 V LO to VSS -0.3 VDD + 0.3 V HO to VSS HS - 0.3 HB + 0.3 V -5 100 V 118 V HS to VSS (3) HB to VSS RDT to VSS -0.3 Junction temperature, TJ Storage temperature, Tstg (1) (2) (3) -55 5 V 150 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage generally does not exceed -1 V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15 V. For example, if VDD = 10 V, the negative transients at HS must not exceed -5 V. 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM) (1) (2) VALUE UNIT 2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. The human-body model is a 100-pF capacitor discharged through a 1.5-k resistor into each pin. Pin 2, Pin 3 and Pin 4 are rated at 500 V. 6.3 Recommended Operating Conditions MIN VDD HS (1) HB HS Slew rate TJ Junction temperature (1) 4 NOM MAX UNIT 8 14 V -1 100 V HS + 8 HS + 14 V -40 <50 V/ns 125 C In the application the HS node is clamped by the body diode of the external lower N-MOSFET; therefore, the HS voltage generally does not exceed -1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15 V. For example, if VDD = 10 V, the negative transients at HS must not exceed -5 V. Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 LM5105 www.ti.com SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 6.4 Thermal Information LM5105 THERMAL METRIC (1) DPR (WSON) UNIT 10 PINS RJA Junction-to-ambient thermal resistance 37.8 C/W RJC(top) Junction-to-case (top) thermal resistance 36.2 C/W RJB Junction-to-board thermal resistance 14.9 C/W JT Junction-to-top characterization parameter 0.3 C/W JB Junction-to-board characterization parameter 15.2 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 4.4 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics Unless otherwise noted, VDD = HB = 12 V, VSS = HS = 0 V, EN = 5 V, no load on LO or HO, RDT= 100 k (1). Typical limits are for TJ = 25C, and minimum and maximum limits apply over the operating junction temperature range (-40C to 125C). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS IDD VDD quiescent current IN = EN = 0 V 0.34 0.6 mA IDDO VDD operating current f = 500 kHz IHB Total HB quiescent current IN = EN = 0 V 1.65 3 mA 0.06 0.2 IHBO Total HB operating current f = 500 kHz mA 1.3 3 mA IHBS HB to VSS current, quiescent HS = HB = 100 V IHBSO HB to VSS current, operating f = 500 kHz 0.05 10 A 0.1 mA 0.8 1.8 V 1.8 2.2 V 100 200 500 k INPUT IN AND EN VIL Low-level input voltage threshold VIH High-level input voltage threshold Rpd Input pulldown resistance pin IN and EN DEAD-TIME CONTROLS VRDT Nominal voltage at RDT IRDT RDT pin current limit RDT = 0 V 2.7 3 3.3 V 0.75 1.5 2.25 mA 6 6.9 7.4 V UNDER VOLTAGE PROTECTION VDDR VDD rising threshold VDDH VDD threshold hysteresis VHBR HB rising threshold VHBH HB threshold hysteresis 0.5 5.7 6.6 V 7.1 0.4 V V BOOT STRAP DIODE VDL Low-current forward voltage IVDD-HB = 100 A 0.6 0.9 V VDH High-current forward voltage IVDD-HB = 100 mA 0.85 1.1 V RD Dynamic resistance IVDD-HB = 100 mA 0.8 1.5 LO GATE DRIVER VOLL Low-level output voltage ILO = 100 mA 0.25 0.4 V VOHL High-level output voltage ILO = -100 mA, VOHL = VDD - VLO 0.35 0.55 V IOHL Peak pullup current LO = 0 V 1.8 A IOLL Peak pulldown current LO = 12 V 1.6 A (1) Minimum and maximum limits are 100% production tested at 25C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 5 LM5105 SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 www.ti.com Electrical Characteristics (continued) Unless otherwise noted, VDD = HB = 12 V, VSS = HS = 0 V, EN = 5 V, no load on LO or HO, RDT= 100 k(1). Typical limits are for TJ = 25C, and minimum and maximum limits apply over the operating junction temperature range (-40C to 125C). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HO GATE DRIVER VOLH Low-level output voltage IHO = 100 mA 0.25 0.4 V VOHH High-level output voltage IHO = -100 mA, VOHH = HB - HO 0.35 0.55 V IOHH Peak pullup current HO = 0 V 1.8 A IOLH Peak pulldown current HO = 12 V 1.6 A 6.6 Switching Characteristics Unless otherwise noted, VDD = HB = 12 , VSS = HS = 0 V, no Load on LO or HO (1). Typical limits are for TJ = 25C, and minimum and maximum limits apply over the operating junction temperature range (-40C to 125C). PARAMETER TEST CONDITIONS MIN TYP tLPHL Lower turnoff propagation delay 26 tHPHL Upper turnoff propagation delay tLPLH Lower turnon propagation delay RDT = 100 k 485 tHPLH Upper turnon propagation delay RDT = 100 k 485 tLPLH Lower turnon propagation delay RDT = 10 k tHPLH Upper turnon propagation delay RDT = 10 k ten, tsd Enable and shutdown propagation delay DT1, DT2 Dead-time LO OFF to HO ON and HO OFF to LO ON MDT MAX UNIT 56 ns 26 56 ns 595 705 ns 595 705 ns 75 105 150 ns 75 105 150 ns 28 ns RDT = 100 k 570 ns RDT = 10 k 80 ns Dead-time matching RDT = 100 k 50 ns tR, tF Either output rise or fall time CL = 1000 pF 15 ns tBS Bootstrap diode turnon or turnoff time IF = 20 mA, IR = 200 mA 50 ns (1) Minimum and maximum limits are 100% production tested at 25C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). IN EN LO ten tLPHL tHPHL tHPLH tLPLH DT1 DT2 DT1 DT2 tsd ten HO tsd Figure 1. LM5105 Input - Output Waveforms 6 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 LM5105 www.ti.com IN SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 VIH VIL tLPHL tLPLH 90% LO 10% tHPLH 90% tHPHL HO 10% Figure 2. LM5105 Switching Time Definitions: TLPLH, TLPHL, THPLH, THPHL VIH EN tsd LO or HO 90% Figure 3. LM5105 Enable: Tsd 90% HO 10% DT1 DT2 90% MDT = |DT1-DT2| LO 10% Figure 4. LM5105 Dead-Time: DT Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 7 LM5105 SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 www.ti.com 6.7 Typical Characteristics 100 2.2 VDD = HB = 12V CL = 2200 pF VSS = HS = 0V RDT = 10K f = 500 kHz 2.0 VSS = HS = 0 CURRENT (mA) CL = 1000 pF CURRENT (mA) VDD = HB = 12V CL = 470 pF 10 1.8 CL = 0 pF IDDO 1.6 1.4 IHBO 1.2 CL = 0 pF 1 10 1 100 1.0 -50 -30 -10 10 30 50 70 90 110 130 150 1000 TEMPERATURE (oC) FREQUENCY (kHz) Figure 6. Operating Current vs Temperature Figure 5. VDD Operating Current vs Frequency 1.20 1.20 1.00 1.00 IDD @ RDT = 10k CURRENT (mA) CURRENT (mA) IDD @ RDT = 10k 0.80 VDD = HB VSS = HS = 0V 0.60 IDD @ RDT = 100k 0.40 0.20 0.00 9 VDD = HB = 12V VSS = HS = 0V 0.60 IDD @ RDT = 100k 0.40 0.20 IHB @ RDT = 10k, 100k 8 0.80 IHB @ RDT = 10k, 100k 0.00 -50 10 11 12 13 14 15 16 17 18 -25 0 VDD, VHB (V) 2.00 VDD = HB = 12V, HS = 0V 1.80 1.60 CL = 2200 pF 1.40 CURRENT (A) CURRENT (PA) CL = 4400 pF CL = 1000 pF 1000 SOURCING 1.00 0.80 SINKING 0.40 CL = 0 pF 10 0.1 1.20 0.60 100 0.20 CL = 470 pF 0.00 1 10 100 1000 0 2 4 6 8 10 12 HO, LO (V) FREQUENCY (kHz) Figure 9. HB Operating Current vs Frequency 8 75 100 125 150 Figure 8. Quiescent Current vs Temperature 100000 10000 50 TEMPERATURE (C) Figure 7. Quiescent Current vs Supply Voltage HB = 12V, HS = 0V 25 Figure 10. HO & LO Peak Output Current vs Output Voltage Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 LM5105 www.ti.com SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 Typical Characteristics (continued) 0.60 1.00E-01 T = 150C 0.55 1.00E-02 VDDH 0.50 HYSTERESIS (V) T = 25C ID (A) 1.00E-03 1.00E-04 0.45 VHBH 0.40 T = -40C 1.00E-05 1.00E-06 0.2 0.35 0.3 0.4 0.5 0.6 0.7 0.8 0.30 -50 0.9 -25 FORWARD VOLTAGE (V) 75 100 125 150 TEMPERATURE ( C) 0.700 VDDR = VDD - VSS Output Current = 100 mA VHBR = HB - HS 0.600 VDD = HB = 8V 7.00 0.500 VDDR 6.90 VDD = HB = 12V VOH (V) THRESHOLD (V) 50 Figure 12. Undervoltage Hysteresis vs Temperature 7.30 7.10 25 o Figure 11. Diode Forward Voltage 7.20 0 6.80 6.70 0.400 VHBR 6.60 0.300 VDD = HB = 16V 6.50 0.200 6.40 6.30 -50 -25 0 25 50 0.100 -50 -25 75 100 125 150 0 25 50 75 100 125 150 TEMPERATURE (C) TEMPERATURE (C) Figure 13. Undervoltage Rising Threshold vs Temperature Figure 14. LO & HO High-Level Output Voltage vs Temperature 1.96 0.400 Output Current - 100 mA 1.94 0.350 1.92 VDD = HB = 8V 1.90 VDD = HB = 12V VIL, VIH (V) VOL (V) 0.300 0.250 0.200 1.88 1.86 1.84 1.82 VDD = HB = 16V 1.80 0.150 1.78 0.100 -50 -25 0 25 50 75 100 125 150 1.76 -50 -30 -10 10 30 50 70 90 110 130 150 TEMPERATURE (oC) TEMPERATURE (C) Figure 15. LO & HO Low-Level Output Voltage vs Temperature Figure 16. Input Threshold vs Temperature Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 9 LM5105 SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 www.ti.com Typical Characteristics (continued) 88 900 800 86 DEAD-TIME (ns) DEAD-TIME (ns) 700 600 500 400 300 200 84 VDD = HB = 12V VSS = HS = 0 82 80 78 100 76 -50 -30 -10 10 30 50 70 90 110 130 150 0 10 30 50 70 90 110 130 150 TEMPERATURE (oC) RDT (k:) Figure 18. Dead-Time vs Temperature (RT = 10 k) Figure 17. Dead-Time vs RT Resistor Value 600 590 VDD = HB = 12V DEAD-TIME (ns) VSS = HS = 0V 580 570 560 550 540 -50 -30 -10 10 30 50 70 90 110 130 150 TEMPERATURE (oC) Figure 19. Dead-Time vs Temperature (RT = 100 k) 10 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 LM5105 www.ti.com SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 7 Detailed Description 7.1 Overview The LM5105 is a single PWM input Gate Driver with Enable that offers a programmable dead time. The dead time is set with a resistor at the RDT pin and can be adjusted from 100 ns to 600 ns. The wide dead-time programming range provides the flexibility to optimize drive signal timing for a wide range of MOSFETS and applications. The RDT pin is biased at 3 V and current-limited to 1-mA maximum programming current. The time delay generator accommodates resistor values from 5 k to 100 k with a dead time that is proportional to the RDT resistance. Grounding the RDT pin programs the LM5105 to drive both outputs with minimum dead time. 7.2 Functional Block Diagram HB VDD HB UVLO HO LEVEL SHIFT DRIVER HS VDD UVLO VSS IN LEADING EDGE DELAY RDT LEADING EDGE DELAY VDD DRIVER EN LO Copyright (c) 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Start-Up and UVLO Both top and bottom drivers include undervoltage lockout (UVLO) protection circuitry, which monitors the supply voltage (VDD) and bootstrap capacitor voltage (HB - HS) independently. The UVLO circuit inhibits each driver until sufficient supply voltage is available to turn on the external MOSFETs, and the UVLO hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to the VDD pin of LM5105, the top and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.9 V. Any UVLO condition on the bootstrap capacitor disables only the high-side output (HO). Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 11 LM5105 SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 www.ti.com 7.4 Device Functional Modes Table 1 lists the functional modes for LM5105. Table 1. Function Table 12 EN IN PIN LO PIN L Any L L H H L H H L H L Submit Documentation Feedback HO PIN Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 LM5105 www.ti.com SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM5105 is one of the latest generation of high-voltage gate drivers which are designed to drive both the high-side and low-side N-channel MOSFETs in a half-bridge or full-bridge configuration or in a synchronous buck circuit. The floating high-side driver can operate with supply voltages up to 110 V. This allows for N-channel MOSFET control in half-bridge, full-bridge, push-pull, two-switch forward, and active clamp topologies. The outputs of the LM5105 are controlled from a single input. The rising edge of each output can be delayed with a programming resistor. 8.2 Typical Application (Optional external fast recovery diode) VIN VCC RGATE HB VDD HO VDD CBOOT 0.1 PF IN OUT1 CONTROLLER HS T1 LM5105 EN ENABLE LO 0.47 PF RGATE RDT GND VSS Copyright (c) 2016, Texas Instruments Incorporated Figure 20. LM5105 Driving MOSFETS Connected in Half-Bridge Configuration 8.2.1 Design Requirements Table 2 lists the design parameters for this application example. Table 2. Design Parameters PARAMETER VALUE Gate Drive IC LM5105 Mosfet CSD18531Q5A VDD 10 V Qgmax 43 nC Fsw 100 kHz DMax 95% IHBS 10 A VDH 1.1 V Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 13 LM5105 SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 www.ti.com Table 2. Design Parameters (continued) PARAMETER VALUE VHBR 7.1 V VHBH 0.4 V 8.2.2 Detailed Design Procedure VHB = VDD - VDH - VHBL where * * * CBOOT VDD = Supply voltage of the gate drive IC VDH = Bootstrap diode forward voltage drop Vgsmin = Minimum gate source threshold voltage (1) QTOTAL = DVHB QTOTAL Qgmax (2) D IHBS u Max FSW (3) The quiescent current of the bootstrap circuit is 10 A, which is negligible compared to the Qgs of the MOSFET. 0.95 QTOTAL = 43nC + 10mA 100kHz (4) QTOTAL = 43.01 nC (5) In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where the power stage may skip pulse due to load transients. In this circumstance the boot capacitor must maintain the HB pin voltage above the UVLO voltage for the HB circuit. As a general rule the local VDD bypass capacitor should be 10 times greater than the calculated value of CBOOT. VHBL = VHBR - VHBH VHBL = 6.7 V VHB = 10 V - 1.1 V - 6.7 V VHB = 2.2 V CBOOT = 43.01nc / 2.2 V CBOOT = 19.6 nF (6) (7) (8) (9) (10) (11) In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients. Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the VDD and VSS pins as possible. A 50-V, 0.1-F capacitor is chosen in this example. The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be twice that of the maximum VDD to allow for loss of capacitance once the devices have a DC bias voltage across them and to ensure long-term reliability of the devices. The resistor values, RT, for setting turnon delay can be found in Figure 17. 14 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 LM5105 www.ti.com SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 8.2.3 Application Curves 1.000 1.000 CL = 4400 pF 0.100 POWER (W) POWER (W) CL = 4400 pF CL = 0 pF 0.010 0.001 1.0 kHz 0.100 CL = 0 pF 0.010 10.0 kHz 100.0 kHz 0.001 1.0 kHz 1000.0 kHz SWITCHING FREQUENCY (kHz) 10.0 kHz 100.0 kHz 1000.0 kHz SWITCHING FREQUENCY (kHz) Figure 21. Diode Power Dissipation, VIN = 80 V Figure 22. Diode Power Dissipation, VIN = 40 V 1.000 CL = 4400 pF CL = 2200 pF POWER (W) 0.100 CL = 1000 pF 0.010 CL = 470 pF CL = 0 pF 0.001 0.1 1.0 10.0 100.0 1000.0 SWITCHING FREQUENCY (kHz) Figure 23. Gate Driver Power Dissipation (LO + HO) VCC = 12 V, Neglecting Diode Losses Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 15 LM5105 SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 www.ti.com 9 Power Supply Recommendations 9.1 Power Dissipation Considerations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can be roughly calculated with Equation 12. PDGATES = 2 x f x CL x VDD2 (12) There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. Figure 23 shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the previous equation. Figure 23 can be used to approximate the power losses due to the gate drivers. 9.2 HS Transient Voltages Below Ground The HS node is always clamped by the body diode of the lower external FET. In some situations, board resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS node can swing below ground provided: 1. HS must always be at a lower potential than HO. Pulling HO more than -0.3 V below HS can activate parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must be placed as close to the IC pins as possible in order to be effective. 2. HB to HS operating voltage should be 14 V or less. Hence, if the HS pin transient voltage is -5 V, VDD should be ideally limited to 9 V to keep HB to HS below 14 V. 3. Low ESR bypass capacitors from HB to HS and from VCC to VSS are essential for proper operation. The capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO and HO can be quite large. Any inductances in series with the bypass capacitor will cause voltage ringing at the leads of the IC which must be avoided for reliable operation. 16 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 LM5105 www.ti.com SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 10 Layout 10.1 Layout Guidelines The optimum performance of high- and low-side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. A low ESR or ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between HB and HS pins to support high peak currents being drawn from VDD during turnon of the external MOSFET. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between MOSFET drain and ground (VSS). 3. To avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounding considerations: - The first priority in designing grounding connections is to confine the high peak currents from charging and discharging the MOSFET gate in a minimal physical area. This decreases the loop inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs must be placed as close as possible to the gate driver. - The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. 5. The resistor on the RDT pin must be placed very close to the IC and separated from high current paths to avoid noise coupling to the time delay generator which could disrupt timer operation. 10.2 Layout Example Figure 24. Component Placement Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 17 LM5105 SNVS349E - FEBRUARY 2005 - REVISED AUGUST 2016 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: AN-1187 Leadless Leadframe Package (LLP) (SNOA401) 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5105 PACKAGE OPTION ADDENDUM www.ti.com 13-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM5105SD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L5105SD LM5105SDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L5105SD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 13-Jul-2016 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 31-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM5105SD/NOPB Package Package Pins Type Drawing WSON DPR 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 180.0 12.4 Pack Materials-Page 1 4.3 B0 (mm) K0 (mm) P1 (mm) 4.3 1.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5105SD/NOPB WSON DPR 10 1000 203.0 203.0 35.0 Pack Materials-Page 2 MECHANICAL DATA DPR0010A SDC10A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, "Designers") understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers' applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI's provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, "TI Resources") are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer's company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI's provision of TI Resources does not expand or otherwise alter TI's applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2017, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: LM5105SD LM5105SD/NOPB LM5105SDX LM5105SDX/NOPB