© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 9 1Publication Order Number:
MC10E175/D
MC10E175, MC100E175
5VECL 9-Bit Latch With
Parity
Description
The MC10E/100E175 is a 9-bit latch. It also features a tenth latched
output, ODDPAR, which is formed as the odd parity of the nine data
inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH).
The E175 can also be used to generate byte parity by using D8 as the
parity-type select (L = even parity, H = odd parity), and using
ODDPAR as the byte parity output.
The LEN pin latches the data when asserted with a logical high and
makes the latch transparent when placed at a logic low level.
Features
•9-Bit Latch
•Parity Detection/Generation
•800 ps Max. D to Output
•Reset
•PECL Mode Operating Range: VCC = 4.2 V to 5.5 V
with VEE = 0 V
•NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.5 V
•Internal Input 50 kW Pulldown Resistors
•ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Charged Device MOdel; > 2 kV
•Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
•Moisture Sensitivity Level:
Pb = 1
Pb−Free = 3
For Additional Information, see Application Note AND8003/D
•Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
•Transistor Count = 416 devices
•Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
PLCC−28
FN SUFFIX
CASE 776
MCxxxE175FNG
AWLYYWW
1
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*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
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2
D1
Q8
D0VCCO Q0VCCO
Q7VCCO
VCCO
D8
D7
D6
D5
D4
D3
VEE
LEN
MR
D2
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
11567 8910
Q6
Q5
VCC
Q4
Q3
VCCO
Q2
Q1
ODDPAR
1Pinout: 28-Lead PLCC
(Top View)
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. 28−Lead Pinout Assignment
D0
D8
LEN
MR
Q0
Q8
ODDPAR
BITS
1−7
D
EN
Q
R
D
EN
Q
R
D
EN
Q
R
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
PIN FUNCTION
D0−D
8
LEN
MR
Q0−Q
8
ODDPAR
VCC, VCCO
VEE
NC
ECL Data Inputs
ECL Latch Enable
ECL Master Reset
ECL Data Outputs
ECL Parity Output
Positive Supply
Negative Supply
No Connect
Table 2. FUNCTION TABLE
D EN MR Q ODDPAR
H L L H H if odd no. of Dn HIGH
LLLLH if odd no. of Dn HIGH
X H L Q0Q0
X X H L L
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Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC PECL Mode Power Supply VEE = 0 V 8 V
VEE NECL Mode Power Supply VCC = 0 V −8 V
VIPECL Mode Input Voltage
NECL Mode Input Voltage VEE = 0 V
VCC = 0 V VI v VCC
VI w VEE
6
−6 V
V
Iout Output Current Continuous
Surge 50
100 mA
mA
TAOperating Temperature Range 0 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm PLCC−28
PLCC−28 63.5
43.5
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) Standard Board PLCC−28 22 to 26 °C/W
Tsol Wave Solder Pb
Pb−Free 265
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V, VEE = 0.0 V (Note 1)
Symbo
l
Characteristic
0°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 94 113 94 113 94 113 mA
IEE Power Supply Current 110 132 110 132 110 132 mA
VOH Output HIGH Voltage (Note 2) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mV
VOL Output LOW Voltage (Note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mV
VIH Input HIGH Voltage 3830 3995 4160 3870 4030 4190 3940 4110 4280 mV
VIL Input LOW Voltage 3050 3285 3520 3050 3285 3520 3050 3302 3555 mV
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.3 0.5 0.25 0.3 0.2 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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4
Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 3)
Symbo
l
Characteristic
0°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 110 132 110 132 110 132 mA
VOH Output HIGH Voltage (Note 4) −1020 −930 −840 −980 −895 −810 −910 −815 −720 mV
VOL Output LOW Voltage (Note 4) −1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595 mV
VIH Input HIGH Voltage −1170 −1005 −840 −1130 −970 −810 −1060 −890 −720 mV
VIL Input LOW Voltage −1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445 mV
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.3 0.5 0.065 0.3 0.2 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
4. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 6. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 5)
Symbo
l
Characteristic
0°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 110 132 110 132 127 152 mA
VOH Output HIGH Voltage (Note 6) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mV
VOL Output LOW Voltage (Note 6) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mV
VIH Input HIGH Voltage 3835 3975 4120 3835 3975 4120 3835 3975 4120 mV
VIL Input LOW Voltage 3190 3355 3525 3190 3355 3525 3190 3355 3525 mV
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.3 0.5 0.25 0.5 0.2 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 7. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0 V; VEE = −5.0 V (Note 7)
Symbo
l
Characteristic
0°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 110 132 110 132 127 152 mA
VOH Output HIGH Voltage (Note 8) −1025 −950 −880 −1025 −950 −880 −1025 −950 −880 mV
VOL Output LOW Voltage (Note 8) −1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620 mV
VIH Input HIGH Voltage −1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV
VIL Input LOW Voltage −1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.3 0.5 0.25 0.5 0.2 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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5
Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 9)
Symbo
l
Characteristic
0°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
fMAX Maximum Toggle Frequency 700 1100 700 1100 700 1100 MHz
tPLH
tPHL
Propagation Delay to Output ps
D to Q 550 800 975 550 800 975 550 800 975
D to ODDPAR 950 1400 1600 950 1400 1600 950 1400 1600
LEN to Q 525 800 975 525 800 975 525 800 975
LEN to ODDPAR 525 800 975 525 800 975 525 800 975
MR to Q(tPHL) 525 800 975 525 800 975 525 800 975
MR to ODDPAR(tPHL) 525 800 975 525 800 975 525 800 975
tsSetup Time ps
D (Q) 275 100 275 275
D (ODDPAR) 900 700 900 900
thHold Time ps
D (Q) 175 −100 175 175
D (ODDPAR) − 300 −70 − 300 − 300
tRR Reset Recovery Time 850 600 850 600 850 600 ps
tSKEW Within-Device Skew (Note 10) ps
LEN, MR 75 75 75
D to Q 75 75 75
D to ODDPAR 200 200 200
tJITTER Random Clock Jitter (RMS) < 1 < 1 < 1 ps
tr
tf
Rise/Fall Times ps
(20 - 80%) 300 500 800 300 500 800 300 500 800
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: VEE can vary −0.46 V / −0.06 V.
100 Series: VEE can vary −0.46 V / −0.8 V.
10.Within-device skew is defined as identical transitions on similar paths through a device.
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Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC − 2.0 V
ORDERING INFORMATION
Device Package Shipping†
MC10E175FN PLCC−28 37 Units / Rail
MC10E175FNG PLCC−28
(Pb−Free) 37 Units / Rail
MC10E175FNR2 PLCC−28 500 / Tape & Reel
MC10E175FNR2G PLCC−28
(Pb−Free) 500 / Tape & Reel
MC100E175FN PLCC−28 37 Units / Rail
MC100E175FNG PLCC−28
(Pb−Free) 37 Units / Rail
MC100E175FNR2 PLCC−28 500 / Tape & Reel
MC100E175FNR2G PLCC−28
(Pb−Free) 500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D −ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
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7
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
−N−
−M−
−L−
V
WD
D
Y BRK
28 1
VIEW S
S
L−M
S
0.010 (0.250) N S
T
S
L−M
M
0.007 (0.180) N S
T
0.004 (0.100)
G1
GJ
C
ZR
E
A
SEATING
PLANE
S
L−M
M
0.007 (0.180) N S
T
−T−
B
S
L−M
S
0.010 (0.250) N S
T
S
L−M
M
0.007 (0.180) N S
T
U
S
L−M
M
0.007 (0.180) N S
T
Z
G1X
VIEW D−D
S
L−M
M
0.007 (0.180) N S
T
K1
VIEW S
H
K
FS
L−M
M
0.007 (0.180) N S
T
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.485 0.495 12.32 12.57
B0.485 0.495 12.32 12.57
C0.165 0.180 4.20 4.57
E0.090 0.110 2.29 2.79
F0.013 0.019 0.33 0.48
G0.050 BSC 1.27 BSC
H0.026 0.032 0.66 0.81
J0.020 −−− 0.51 −−−
K0.025 −−− 0.64 −−−
R0.450 0.456 11.43 11.58
U0.450 0.456 11.43 11.58
V0.042 0.048 1.07 1.21
W0.042 0.048 1.07 1.21
X0.042 0.056 1.07 1.42
Y−−− 0.020 −−− 0.50
Z2 10 2 10
G1 0.410 0.430 10.42 10.92
K1 0.040 −−− 1.02 −−−
__ __
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Phone: 81−3−5773−3850
MC10E175/D
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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