PCM1870AYZFR - Texas Instruments - Datasheet.Directory

1

FEATURES

APPLICATIONS

DESCRIPTION

PCM1870A

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................................................................................................................................................................................................. SLAS617 – AUGUST 2008

16-Bit Low-Power Stereo Audio ADC With Microphone Bias and Microphone Amplifier

•Analog Front End: •Pop Noise Reduction Circuit– Stereo Single End Input With MUX •Package:– Mono Differential Input – 24-Pin YZF (2.49 mm × 3.49 mm)– Stereo Programmable Gain Amplifier •Operation Temperature Range: – 40 ° C to 85 ° C– Microphone Boost Amplifier and Bias•Analog Performances Dynamic Range: 90 dB

•Portable Audio Player, Cellular Phone•Power-Supply Voltage

•Video Camcorder, Movie Digital Still Camera– 1.71 V to 3.6 V for Digital I/O Section

•PMP/DMB, Voice Recorder– 1.71 V to 3.6 V for Digital Core Section– 2.4 V to 3.6 V for Analog Section•Low Power Dissipation:

The PCM1870A is a low-power stereo ADC designed– 13 mW in Record, 1.8/2.4 V, 48 kHz, Stereo

for portable digital audio applications, with line-inputamplifier, boost amplifier, microphone bias,– 5.3 mW in Record, 1.8/2.4 V, 8 kHz, Mono

programmable gain control, sound effects, and auto– 3.3 µW in All Power Down

level control (ALC). It is available in a 24-Pin YZF•Sampling Frequency: 5 kHz to 50 kHz

(2.49-mm × 3.49-mm) package to save footprint. ThePCM1870A accepts right-justified, left-justified, I

2

S,•Auto Level Control for Recording

and DSP formats, providing easy interfacing to audio•Operation by Single Clock Input Without PLL

DSP and encoder chips. Sampling rates up to 50 kHz•System Clock: Common Audio Clock

are supported. The user-programmable functions are(256 f

S

/384 f

S

), 12/24, 13/26, 13.5/27, 19.2/38.4,

accessible through a 2- or 3-wire serial control port.19.68/39.36 MHz•2 (I

2

C) or 3 (SPI) Wire Serial Control•Programmable Function by Register Control:– Digital Soft Mute– Hi-Z for LRCK, BCK and DOUT– Power Up/Down Control for Each Module– 30-dB to – 12-dB Gain for Analog Inputs– 0/12/20-dB Boost for Microphone Input– Parameter Settings for ALC– Three-Band Tone Control and 3D Sound– High-Pass Filter and Two-Stage Notch Filter

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

PCM1870A

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

over operating free-air temperature range (unless otherwise noted)

(1)

PCM1870A UNIT

V

DD

, V

IO

, V

CC

Supply voltage – 0.3 to 4 VGround voltage differences: DGND, AGND, PGND ± 0.1 VInput voltage – 0.3 to 4 VInput current (any pins except supplies) ± 10 mAAmbient temperature under bias – 40 to 110 ° CStorage temperature – 55 to 150 ° CJunction temperature 150 ° CLead temperature (soldering) 260 / 5 ° C / sPackage temperature (reflow, peak) 260 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicted under recommended operatingconditions is not impled. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabiltiy.

MIN NOM MAX UNIT

V

CC

Analog supply voltage 2.4 3.3 3.6 VV

DD

, V

IO

Digital supply voltage 1.71 3.3 3.6 VDigital input logic family CMOSSCKI system clock 3.072 18.432 MHzDigital input clock frequency

LRCK sampling clock 8 48 kHzDigital output load capacitance 10 pFT

A

Operating free-air temperature – 40 85 ° C

Product Folder Link(s): PCM1870A

ELECTRICAL CHARACTERISTICS

PCM1870A

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................................................................................................................................................................................................. SLAS617 – AUGUST 2008

All specifications at T

A

= 25 ° C, V

DD

= V

IO

= V

CC

= V

PA

= 3.3 V, f

S

= 48 kHz, system clock = 256 f

S

, and 16-bit data, unlessotherwise noted

PCM1870AYZFPARAMETER TEST CONDITIONS UNITMIN TYP MAX

AUDIO DATA

Data Format

Resolution 16 BitsAudio data interface format I

2

S, left-, right-justified, DSPAudio data bit length 16 BitsAudio data format MSB-first, 2s-complementf

S

Sampling frequency 5 50 kHzV

DD

< 2 V 27System clock MHzV

DD

> 2 V 40

DIGITAL INPUT/OUTPUT

Logic family CMOS compatibleV

IH

0.7 V

IOInput logic level VDCV

IL

0.3 V

IO

I

IH

V

IN

= 3.3 V 10Input logic current µAI

IL

V

IN

= 0 V – 10V

OH

I

OH

= – 2 mA 0.75 V

IOOutput logic level VDCV

OL

I

OL

= 2 mA 0.25 V

IO

LINE INPUT TO DIGITAL OUTPUT THROUGH ADC (AIN1L/R, AIN2L/R AND PGINL/R— ALC = OFF, PG1 = PG2 = PG3 = PG4 = 0 dB

Dynamic Performance

2.828 Vp-pFull-scale input voltage 0 dB

1 VrmsDynamic range EIAJ, A-weighted 90 dBSNR Signal-to-noise ratio EIAJ, A-weighted 83 90 dBChannel separation 87 dBTHD+N Total harmonic distortion + noise – 1 dB 0.009% 0.017%

Analog Input

Center voltage 0.5 V

CC

VAIN1L, AIN1R, AIN2L, and AIN2R 10 20Input impedance PGINL and PGINR, PG3 = PG4 = – 12 dB 70 142 k Ω

PGINL and PGINR, PG3 = PG4 = 30 dB 4.7 9.5

ANALOG OUTPUTS (AOL AND AOR)

Center voltage 0.5 V

CC

VLoad resistance 10 k Ω

Load capacitance 20 pF

MICROPHONE BIAS— ALC = OFF, PG1 = PG2 = PG3 = PG4 = 0 dBBias voltage 0.75 V

CC

VBias source current 2 mAOutput noise 6.5 µV

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PCM1870A

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ELECTRICAL CHARACTERISTICS (continued)All specifications at T

A

= 25 ° C, V

DD

= V

IO

= V

CC

= V

PA

= 3.3 V, f

S

= 48 kHz, system clock = 256 f

S

, and 16-bit data, unlessotherwise noted

PCM1870AYZFPARAMETER TEST CONDITIONS UNITMIN TYP MAX

FILTER CHARACTERISTICS

Decimation Filter for ADC

Pass band 0.408 f

S

Stop band 0.591 f

S

Pass-band ripple ± 0.02 dBStop-band attenuation f < 3.268 f

S

– 60 dBGroup delay 17/f

S

s

High-Pass Filter for ADC

– 3 dB 3.74Frequency response (f

c

= 4 Hz) – 0.5 dB 10.66 Hz– 0.1 dB 24.20– 3 dB 118.77Frequency response (f

c

= 120 Hz) – 0.5 dB 321.75 Hz– 0.1 dB 605.52– 3 dB 235.68Frequency response (f

c

= 240 Hz) – 0.5 dB 609.95 Hz– 0.1 dB 2601.2

POWER SUPPLY AND SUPPLY CURRENT

V

IO

V

IO

1.71 3.3 3.6V

DD

Voltage range V

DD

1.71 3.3 3.6 VDCV

CC

V

CC

2.4 3.3 3.6BPZ input, all active, no load 8 12 mASupply current

All inputs are held static. 1 10 µABPZ input 26.4 39.6 mWPower dissipation

All inputs are held static. 3.3 33 µW

TEMPERATURE CONDITION

Operation temperature – 40 85 ° Cθ

JA

Thermal resistance 35 ° C/W

Product Folder Link(s): PCM1870A

PIN ASSIGNMENTS

PCM1870AYZF

(TopView)

VCOM

AIN2R AIN2L

MODE

DOUT

VIO

VDD

DGND

SCKI

MS/ADR MD/SDA

MC/SCL

PGINL

AOL

PGINR

AOR

TEST

LRCK

BCK

AGND

VCC

MICB

AIN1LAIN1R

A

B

C

D

E

F

1 2 3 4

PCM1870A

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................................................................................................................................................................................................. SLAS617 – AUGUST 2008

Table 1. TERMINAL FUNCTIONS

TERMINAL

NO. I/O DESCRIPTIONNAME

YZF

AGND B4 – Ground for analogAIN1L A2 I Analog input 1 for L-channelAIN1R A1 I Analog input 1 for R-channelAIN2L C4 I Analog input 2 for L-channelAIN2R C3 I Analog input 2 for R-channelAOL C2 O Microphone amplifier output for L-channelAOR C1 O Microphone amplifier output for R-channelBCK F1 I/O Serial bit clockDGND E2 – Ground for digitalDOUT F4 O Serial audio data outputLRCK E1 I/O Left- and right-channel clockMC/SCL E4 I Mode control clock for 3-wire / 2-wire interfaceMD/SDA D4 I/O Mode control data for 3-wire / 2-wire interfaceMICB A3 O Microphone bias source outputMODE D2 I 2- or 3-wire interface selection (LOW: SPI, HIGH: I

2

C)MS/ADR D3 I Mode control select for 3-wire / 2-wire interfacePGINL B2 I Analog input to gain amplifier for L-channelPGINR B1 I Analog input to gain amplifier for R-channelSCKI F2 I System clockTEST D1 I Test Pin. Should be connected to ground.V

CC

B3 – Power supply for analogV

COM

A4 – Common voltage for analogV

DD

F3 – Power supply for digital coreV

IO

E3 – Power supply for digital I/O

Product Folder Link(s): PCM1870A

AIN2L

AIN1L

AIN1R

AIN2R

MS/ADRMC/SCLMD/SDA MODE

Serial Interface (SPI/I C)

2

AGNDDGND

VCOM

MICB

B0231-01

MUX1

VIO VDD VCC

MCB

Mic Bias

COM

PG1

0/+12/+20dB

Power On

Reset

Power Up/Down

Manager

D2S

MUX3

MUX2

MUX4

PG2

COM

VCOM

Module That Can Be Powered Up/Down

SCKI

Audio Interface

ADL

PG3

PG4

+30to –12dB

Clock

Manager

ADR

BCKDOUT LRCK

DS

ADC

DS

ADC

Digital

Filter

Digital

Filter

Mute

ATR

AOL PGINL TEST

AOR PGINR

PCM1870A

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FUNCTIONAL BLOCK DIAGRAM

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TYPICAL PERFORMANCE CURVES

Frequency [ f ]´S

Amplitude – dB

G001

–120

–100

–80

–60

–40

–20

0

0 1 2 3 4

Frequency [ f ]´S

Amplitude – dB

–0.2

–0.1

0

0.1

0.2

0 0.1 0.2 0.3 0.4 0.5

G002

Frequency [ f ]´S

Amplitude – dB

G003

–20

–15

–10

–5

0

5

0 0.0005 0.001 0.0015 0.002

Frequency [ f ]´S

Amplitude – dB

G012

–20

–15

–10

–5

0

5

0 0.005 0.01 0.015 0.02

PCM1870A

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................................................................................................................................................................................................. SLAS617 – AUGUST 2008

All specifications at T

A

= 25 ° C, V

DD

= V

IO

= V

CC

= V

PA

= 3.3 V, f

S

= 8 kHz to 48 kHz, system clock = 256 f

S

and 16-bit data,unless otherwise noted.

DECIMATION FILTER, STOP-BAND DECIMATION FILTER, PASS-BAND

Figure 1. Figure 2.

HIGH-PASS FILTER PASS-BAND CHARACTERISTICS HIGH-PASS FILTER PASS-BAND CHARACTERISTICS(f

C

= 4 Hz at 48 kHz) (f

C

= 120 Hz at 48 kHz)

Figure 3. Figure 4.

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Frequency [ f ]´S

Amplitude – dB

G004

–20

–15

–10

–5

0

5

0 0.01 0.02 0.03 0.04

PCM1870A

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TYPICAL PERFORMANCE CURVES (continued)All specifications at T

A

= 25 ° C, V

DD

= V

IO

= V

CC

= V

PA

= 3.3 V, f

S

= 8 kHz to 48 kHz, system clock = 256 f

S

and 16-bit data,unless otherwise noted.

HIGH-PASS FILTER PASS-BAND CHARACTERISTICS

(f

C

= 240 Hz at 48 kHz)

Figure 5.

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Frequency – Hz

Amplitude – dB

G005

–15

–10

–5

0

5

10

15

0.01 0.1 1 10 1k100 10k 100k

Frequency – Hz

Amplitude – dB

G006

–15

–10

–5

0

5

10

15

0200 600400 800 1k

Frequency – Hz

Amplitude – dB

G007

–15

–10

–5

0

5

10

15

01k 3k2k 4k 5k

Frequency – Hz

Amplitude – dB

G008

–15

–10

–5

0

5

10

15

2k 4k 8k6k 10k 12k 14k

PCM1870A

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................................................................................................................................................................................................. SLAS617 – AUGUST 2008

TYPICAL PERFORMANCE CURVES (continued)All specifications at T

A

= 25 ° C, V

DD

= V

IO

= V

CC

= V

PA

= 3.3 V, f

S

= 44.1 kHz, system clock = 256 f

S

and 16-bit data, unlessotherwise noted.

3 BAND TONE CONTROL (BASS, MID, TREBLE) 3 BAND TONE CONTROL (BASS)

Figure 6. Figure 7.

3 BAND TONE CONTROL (MID) 3 BAND TONE CONTROL (TREBLE)

Figure 8. Figure 9.

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PG3/PG4 Gain – dB

SNR – dB

G009

40

50

60

70

85

90

100

051510 20 25 30

Single Input

Differential Input

f = 1 kHz

IN

PG3/PG4 Gain – dB

SNR – dB

G010

40

45

65

60

55

50

70

75

80

85

90

051510 20 25 30

Single Input

Differential Input

f = 1 kHz

IN

Power Supply – V

THD+N – %

SNR – dB

G011

0.007

0.008

0.009

0.010

0.011

0.012

87

88

89

90

91

92

2 2.5 3.53 4

f = 1 kHz

IN

THD+N

SNR

PCM1870A

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TYPICAL PERFORMANCE CURVES (continued)All specifications at T

A

= 25 ° C, V

DD

= V

IO

= V

CC

= V

PA

= 3.3 V, f

S

= 48 kHz, system clock = 256 f

S

and 16-bit data, unlessotherwise noted.

ADC SNR AT HIGH GAIN (PG1/PG2 = 0 dB) ADC SNR AT HIGH GAIN (PG1/PG2 = 20 dB)

Figure 10. Figure 11.

THD+N/SNR vs POWER SUPPLY(ADC TO DIGITAL OUTPUT)

Figure 12.

Product Folder Link(s): PCM1870A

PCM1870A DESCRIPTION

Analog Input

Gain Setting for Analog Input

A/D Converter

Common Voltage

Microphone Bias

Auto Level Control (ALC) for Recording

3D Sound

3-Band Tone Control

High-Pass Filter and Notch Filter

Digital Monaural Mixing

PCM1870A

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................................................................................................................................................................................................. SLAS617 – AUGUST 2008

The AIN1L, AIN1R, AIN2L and AIN2R pins can be used as microphone or line inputs with selectable 0- or 20-dBboost and 1-Vrms input. All analog inputs have high input impedance (20 k Ω), which is not changed by gainsettings. One pair of inputs is selected by register 87 (AIL[1:0], AIR[1:0]). AIN1L and AIN1R can also be used asa monaural differential input.

Analog signals can be adjusted from 30 dB to – 12 dB in 1-dB steps after the 0-, 12- or 20-dB boost amplifier.Gain level can be set for each channel by register 79, 80 (ALV[5:0], ARV[5:0]).

The ADC includes a multilevel delta-sigma modulator, aliasing filter, decimation filter, high-pass filter and notchfilter and can accept 1 Vrms as full-scale input voltage. The decimation filter has a digital soft mute controlled byregister 81 (RMUL, RMUR), and the high-pass and notch filters can be disabled by register 81 (HPF[1:0]) andregisters 96 through 104 if they are not needed to cancel dc offset or avoid wind noise.

Unbuffered common voltage. The V

COM

pin is normally biased to 0.5 V

CC

, and it provides common voltage tointernal circuitry. Connecting a 4.7- µF capacitor to this pin is recommended to optimize analog performance.

The MICB pin is a microphone bias source for an external microphone, which can provide 2 mA (typ) biascurrent.

The sound when microphone recording should be adjusted to a suitable level without saturation. The digitallycontrolled auto level control (ALC) automatically expands small input signals and compresses large input signalswhile recording. Expansion level, compression level, attack time, and recovery time can be selected by register83. See the bit descriptions of register 83 for detailed settings.

A 3D sound effect is provided by mixing L-channel and R-channel data through a band-pass filter with twocontrol parameters, mixing ratio and band-pass filter characteristic. The control parameters are set in register 95(3DP[3:0], 3FLO). The 3D sound effect is applied to the ADC digital output.

Tone control has bass, midrange, and treble controls that can be adjusted from 12 dB to – 12 dB in 1-dB steps byregister 92 to 94 (LGA[4:0], MGA[4:0] and HGA[4:0]). Register 92 (LPAE), which attenuates the digital inputsignal automatically, can prevent clipping of the output signal at settings higher than 0 dB for bass control. LPAEis not effective for midrange and treble control.

The high-pass filter cuts dc offset in the analog section of the ADC and can be set to 4 Hz, 120 Hz, or 240 Hz at48-kHz sampling by register 81 (HPF[1:0]).

Notch filters remove noise at particular frequencies, CCD noise, motor noise and other mechanical noise in anapplication. The PCM1870A has two notch filters, whose center frequency and frequency bandwidth can beprogrammed by registers 96 to 104.

The audio data can be mixed to monaural digital data from stereo digital data in the internal audio interfacesection by register 96 (MXEN).

Product Folder Link(s): PCM1870A

Zero-Cross Detection

Power Up/Down for Each Module

Digital Interface

Power Supply

High Impedance Mode for LRCK, BCK and DOUT Pins

PCM1870A

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Zero-cross detection minimizes audible zipper noise while changing analog volume and digital attenuation. Thisfunction can be applied to digital input or digital output by register 86 (ZCRS).

Using register 73 (PBIS), register 82 (PAIR, PAIL, PADS, PMCB, PADR, PADL), and register 90 (PCOM),unused modules can be powered down to minimize power consumption (13 mW when recording only).

All digital I/O pins can interface at various power supply voltages. The V

IO

pin can be connected to a 1.71-V to3.6-V power supply.

The V

CC

pin can be connected to 2.4 V to 3.6 V. The V

DD

pin and V

IO

pin can be connected to 1.71 to 3.6 V. Adifferent voltage can be applied to each of these pins (for example, V

DD

= 1.8 V, V

IO

= 3.3 V).

These pins can be set to high impedance by register 84 (BLHZ, DOHZ) to use LRCK, BCK and DOUT as audiointerface bus. If other devices have high impedance mode, audio system can share two or more audio interfacesignals and reduce audio interface port of main DSP.

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DESCRIPTION OF OPERATION

System Clock Input

tw(SCKH)

SCKI

tw(SCKL)

0.7VIO

0.3VIO

T0005-12

Power-On Reset and System Reset

Power On/Off Sequence

PCM1870A

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................................................................................................................................................................................................. SLAS617 – AUGUST 2008

The PCM1870A can accept input clocks of various frequencies without a PLL. The clocks are used for clockingof the digital filters, auto level control, and delta-sigma modulators, and classified into common-audio andapplication-specific clocks. Table 2 shows frequencies of the common audio clock and the application-specificclock. Figure 13 shows timing requirements for system clock inputs. The sampling rate and frequency of thesystem clock are determined by settings in register 86 (MSR[2:0]) and register 85 (NPR[5:0]). Note that thesampling rate of the application-specific clock has a little sampling error. The details are shown in Table 8 .

Table 2. Frequency of Common Audio Clock

FREQUENCY

Common audio clock 11.2896, 12.288, 16.9344, 18.432 MHzApplication-specific clock 12, 13, 13.5, 24, 26, 27, 19.2, 19.68, 38.4, 39.36 MHz

PARAMETERS SYMBOL MIN UNITSystem clock pulse duration, high t

w(SCKH)

14 nsSystem clock pulse duration, low t

w(SCKL)

14 ns

Figure 13. System Clock Timing

The power-on-reset circuit outputs reset signal, typically at V

DD

= 1.2 V, and this circuit does not depend on thevoltage of other power-supplies (V

CC

, V

PA

, and V

IO

). Internal circuits are cleared to default status, then signalsare removed from all analog and digital outputs. The PCM1870A does not require any power supply sequencing.Register data must be written after turning all power supplies on.

System reset is enabled by setting register 85 (SRST), and all registers are cleared automatically. All circuits arereset to their default status at once. Note that the PCM1870A has audible pop noise on the analog outputs whenenabling SRST.

To reduce audible pop noise, a sequence of register settings is required after turning all power supplies on whenpowering up, or before turning the power supplies off when powering down. If some modules are not required fora particular application or operation, they should be placed in the power-down state after performing thepower-on sequence. The recommended power-on and power-off sequences are shown in Table 3 and Table 4 ,respectively.

Product Folder Link(s): PCM1870A

PCM1870A

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Table 3. Recommended Power-On Sequence

REGISTERSTEP NOTESETTINGS

1 — Turn ON all power supplies

(1)

2 5102

H

ADC audio interface format (left-justified)

(2)

3 5A00

H

PG1, PG2 gain control (0 dB)4 4980

H

Analog bias power up5 5601

H

Zero-cross detection enable6 4A01

H

V

COM

power up7 523F

H

Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power up8 5711

H

Analog input (MUX3, MUX4) select. Analog input (MUX1, MUX2) select9 4F0C

H

Analog input L-ch (PG3) volume (0 dB)

(3)

10 500C

H

Analog input R-ch (PG4) volume (0 dB)

(3)

(1) V

DD

should be turned on first or at the same time with other power supplies. It is recommended to set the register data after turning onall power supplies and while the system clock is running.(2) The audio interface format should be set to match the DSP or decoder being used.(3) Any level is acceptable for volume or attenuation. The level should return to that recorded in the register data when system was lastpowered off.

Table 4. Recommended Power-Off Sequence

REGISTERSTEP NOTESETTINGS

1 5132

H

ADC L-ch/R-ch digital soft mute enable, ADC audio interface format (left-justified)

(1)

2 5200

H

Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power down3 4A00

H

V

COM

power down4 4900

H

Analog bias power down5 — Turn OFF all power supplies.

(2)

(1) The audio interface format should be set to match the DSP or decoder being used.(2) Power-supply sequencing is not required. It is recommended to make the required register settings while the system clock is running,then turn off all power supplies.

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Power-Supply Current

PCM1870A

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The current consumption of the PCM1870A depends on the power-up/down status of each circuit module. Inorder to save power consumption, disabling each module is recommended when it is not used in an appliction oroperation. Table 5 shows current consumtption in some states.

Table 5. Power Consumption Table

POWER SUPPLY CURRENT [mA] PD [mW]OPERATION MODE

V

DD

V

DD

V

CC

V

IO

TOTAL TOTAL(1.8 V) (3.3 V) (3.3 V) (3.3 V) (V

DD

= 1.8 V) (V

DD

= 3.3 V)

ALL POWER DOWN 0.000 0.000 0.001 0.000 0.003 0.003

Recording (f

S

= 48 kHz)

Line input (AIN2L/AIN2R) 1.78 3.71 4.58 0.10 18.3 27.7Mic input (AIN1L/AIN1R, 20 dB) 1.79 3.71 5.06 0.10 19.9 29.3Mic input (AIN1L/AIN1R, 20 dB) with ALC 2.73 5.59 5.06 0.10 21.6 35.5Mono mic input (AIN1L, 20 dB) 1.33 2.80 3.56 0.10 14.1 21.3Mono mic input (AIN1L, 20 dB) with ALC 2.21 4.60 3.56 0.10 15.7 27.3Mono diff mic input (AIN1L/AIN1R, 20 dB) 1.33 2.80 3.88 0.10 15.2 22.4Mono diff mic input (AIN1L/AIN1R, 20 dB) with ALC 2.21 4.60 3.88 0.10 16.8 28.3

Recording (f

S

= 22.05 kHz)

Line input (AIN2L/AIN2R) 0.82 1.66 3.71 0.10 13.7 18.1Mic input (AIN1L/AIN1R, 20 dB) 0.82 1.66 4.20 0.10 15.3 19.7Mic input (AIN1L/AIN1R, 20 dB) with ALC 1.26 2.55 4.20 0.10 16.1 22.6Mono mic input (AIN1L, 20 dB) 0.61 1.23 2.74 0.10 10.1 13.4Mono mic input (AIN1L, 20 dB) with ALC 1.03 2.10 2.74 0.10 10.9 1.63Mono diff mic input (AIN1L/AIN1R, 20 dB) 0.61 1.23 3.06 0.10 11.2 14.5Mono diff mic input (AIN1L/AIN1R, 20 dB) with ALC 1.02 2.08 3.06 0.10 11.9 17.3

Recording (f

S

= 16 kHz)

Line input (AIN2L/AIN2R) 0.59 1.18 3.51 0.10 12.7 15.8Mic input (AIN1L/AIN1R, 20 dB) 0.59 1.18 3.99 0.10 14.2 17.4Mic input (AIN1L/AIN1R, 20 dB) with ALC 0.91 1.85 3.99 0.10 14.8 19.6Mono mic input (AIN1L, 20 dB) 0.44 0.87 2.55 0.10 9.2 11.6Mono mic input (AIN1L, 20 dB) with ALC 0.75 1.52 2.55 0.10 9.8 13.8Mono diff mic input (AIN1L/AIN1R, 20 dB) 0.44 0.87 2.87 0.10 10.3 12.7Mono diff mic input (AIN1L/AIN1R, 20 dB) with ALC 0.74 1.50 2.87 0.10 10.8 14.8

Recording (f

S

= 8 kHz)

Line input (AIN2L/AIN2R) 0.29 0.54 3.23 0.10 11.2 12.8Mic input (AIN1L/AIN1R, 20 dB) 0.29 0.54 3.72 0.10 12.8 14.4Mic input (AIN1L/AIN1R, 20 dB) with ALC 0.46 0.88 3.72 0.10 13.1 15.5Mono mic input (AIN1L, 20 dB) 0.22 0.39 2.29 0.10 8.0 9.2Mono mic input (AIN1L, 20 dB) with ALC 0.37 0.70 2.29 0.10 8.2 10.2Mono diff mic input (AIN1L/AIN1R, 20 dB) 0.22 0.39 2.61 0.10 9.0 10.2Mono diff mic input (AIN1L/AIN1R, 20 dB) with ALC) 0.37 0.70 2.61 0.10 9.3 11.3Condition: 256 f

S

, 16 bits, slave mode, zero data input, no load

Product Folder Link(s): PCM1870A

Audio Serial Interface

Audio Data Formats and Timing

tw(BCH)

DOUT

tw(BCL) t(LB)

t(BCY)

LRCK

BCK

50%ofVIO

t(CKDO) t(LRDO)

T0010-12

t(BL)

PCM1870A

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The audio serial interface of the PCM1870A consists of LRCK, BCK and DOUT. Sampling rate (f

S

), left and rightchannel are present on LRCK. DOUT transmits the serial data from the decimation filter for the ADC. BCK isused to transmit the serial audio data on DOUT at its high-to-low transition. BCK and LRCK should besynchronized with audio system clock. Ideally, it is recommended that they are derived from it.

The PCM1870A requires LRCK to be synchronized with the system clock. The PCM1870A do not need a specificphase relationship between LRCK and the system clock.

The PCM1870A has both master mode and slave mode interface formats, which can be selected by register 84(MSTR). LRCK and BCK are generated from the system clock in master mode.

The PCM1870A supports I

2

S, right-justified, left-justified, and DSP formats. The data formats are shown inFigure 16 , and they are selected using resister 70 (RFM[1:0], PFM[1:0]). All formats require binary2s-complement, MSB-first audio data. The default format is I

2

S. Figure 14 shows a detailed timing diagram.

PARAMETERS SYMBOL MIN MAX UNITBCK pulse cycle time (I

2

S, left- and right-justified formats) t

(BCY)

1/(64f

S

)

(1)

BCK pulse cycle time (DSP format) t

(BCY)

1/(256f

S

)

(1)

BCK high-level time t

w(BCH)

35 nsBCK low-level time t

w(BCL)

35 nsBCK rising edge to LRCK edge t

(BL)

10 nsLRCK edge to BCK rising edge t

(LB)

10 nsDOUT delay time from BCK falling edge t

(CKDO)

40 ns

Figure 14. Audio Interface Timing (Slave Mode)

(1) f

S

is the sampling frequency.

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T0011-05

t(DL)

t(BCY)

t(SCY)

t(DS)

LRCK(Output)

50%ofVIO

SCKI

BCK(Output)

DOUT

t(DH)

tw(BCH)

tw(BCL) t(DB)

t(DB)

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PARAMETERS SYMBOL MIN MAX UNITSCKI pulse cycle time t

(SCY)

1/(256f

S

)

(1)

LRCK edge from SCKI rising edge t

(DL)

5 140 nsBCK edge from SCKI rising edge t

(DB)

5 140 nsBCK pulse cycle time t

(BCY)

1/(64f

S

)

(1)

BCK high-level time t

w(BCH)

146 nsBCK low-level time t

w(BCL)

146 nsDOUT setup time t

(DS)

10 nsDOUT hold time t

(DH)

10 ns

Figure 15. Audio Interface Timing (Master Mode)

(1) f

S

is up to 48 kHz. f

S

is the sampling frequency

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LRCK

(b)I SDataFormat;L-Channel=LOW,R-Channel=HIGH

2

(a)Right-JustifiedDataFormat;L-Channel=HIGH,R-Channel=LOW

(c)Left-JustifiedDataFormat;L-Channel=HIGH,R-Channel=LOW

L-Channel R-Channel

BCK

DOUT 15 16

1/fS

11 1112 12

13 13

MSB MSBLSB LSB

1 1

4 4

2 2

5 5

3 3

6 6

7 7

8 89 910 10

14 14

15 1516 16

LRCK L-Channel R-Channel

1/fS

LRCK

(=32f ,48f ,or64f )

S S S

(1)

L-Channel R-Channel

BCK

DOUT

1/fS

11 1112 12

13 13

MSB MSBLSB LSB

111

4 4

222

5 5

3 3

6 6

7 7

8 89 910 10

14 14

15 1516 16

T0009-09

(d)BurstBCKInterfaceFormatinMasterMode;L-Channel=HIGH,R-Channel=LOW

(e)DSP Format

(=32f ,48f ,or64f )

S S S

(1)

BCK

DOUT 11 1112 12

13 13

MSB MSBLSB LSB

111

4 4

222

5 5

3 3

6 6

7 7

8 89 910 10

14 14

15 1516 16

LRCK L-Channel R-Channel

1/fS

(=32f ,48f ,or64f )

S S S

(1)

BCK

DOUT 11 1112 12

13 13

MSB MSBLSB LSB

111

4 4

222

5 5

3 3

6 67 78 89 910 10

14 14

15 1516 16

LRCK

1/fS

(=32f ,48f , or256f )

S S S

64f ,128f

S S

BCK

DOUT 11 1112 12

13 13

MSB MSBLSB LSB

1 1 1

4 4

2 2 2

5 5

3 3

6 67 78 89 910 10

14 14

15 1516 16

(=32f ,48f ,or64f )

S S S

(1)

16-BitRight-Justified

PCM1870A

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(1) All audio interface formats support BCK = 64 f

S

in master mode (register 69, MSTR = 1). When set to multisamplingrate, f

S

of BCK is set to half the rate of the DSM operation frequency.

Figure 16. Audio Data Output Formats

Product Folder Link(s): PCM1870A

THREE-WIRE INTERFACE (SPI, MODE (PIN 28) = LOW)

MSB

0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D000

LSB

Register Index (or Address) Register Data

R0001-01

MC

MS

MD

16Bits

(1)SingleWriteOperation

MSB LSB MSB

(2)ContinuousWriteOperation

MSB

8BitsxNFrames

MC

MS

MD

NFrames

LSB MSB LSB MSB LSB MSB LSB

Register Index

8Bits

Register(N)Data Register(N+1)Data Register(N+2)Data

T0012-03

PCM1870A

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All write operations for the serial control port use 16-bit data words. Figure 17 shows the control data wordformat. The most significant bit must be 0. There are seven bits, labeled IDX[6:0], that set the register addressfor the write operation. The least-significant eight bits, D[7:0], contain the data to be written to the registerspecified by IDX[6:0].

Figure 18 shows the functional timing diagram for writing to the serial control port. To write the data into themode register, the data is clocked into an internal shift register on the rising edge of the MC clock. The serialdata should change on the falling edge of the MC clock and should be LOW during write mode. The rising edgeof MS should be aligned with the falling edge of the last MC clock pulse in the 16-bit frame. The MC can runcontinuously between transactions while MS is in the LOW state.

Figure 17. Control Data Word Format for MD

Figure 18. Register Write Operation

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Three-Wire Interface (SPI) Timing Requirements

tw(MCH)

50%ofVIO

MS

t(MLS)

LSB

50%ofVIO

tw(MCL)

tw(MHH)

t(MLH)

t(MCY)

t(MDH)

t(MDS)

MC

MD

T0013-08

PCM1870A

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Figure 19 shows a detailed timing diagram for the serial control interface. These timing parameters are critical forproper control port operation.

PARAMETERS SYMBOL MIN TYP MAX UNITMC pulse cycle time t

(MCY)

500

(1)

nsMC low-level time t

w(MCL)

50 nsMC high-level time t

w(MCH)

50 nsMS high-level time t

w(MHH)

See

(1)

nsMS falling edge to MC rising edge t

(MLS)

50 nsMS hold time t

(MLH)

20 nsMD hold time t

(MDH)

15 nsMD setup time t

(MDS)

20 ns

Figure 19. SPI Interface Timing

(1) 3/(128 f

S

) s (min), where f

S

is the sampling frequencyA

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TWO-WIRE INTERFACE [I

2

C, MODE (PIN 28) = HIGH]

9

SDA

SCL St

Start

1−7 8 1−8 9 1−8 9 Sp

Stop

Slave Address ACK DATA ACK DATA ACK

ConditionCondition

R/W

Write Operation

Transmitter MM M S S M S M

Data Type St Slave Address R/W ACK ACK DATA ACK Sp

R/W: Read Operation if 1; Otherwise, Write Operation

ACK: Acknowledgement of a Byte if 0

DATA: 8 Bits (Byte)

T0049-03

M: Master Device

St: Start Condition

M

DATA

Read Operation

Transmitter MM M S M S M M

Data Type St Slave Address R/W ACK ACK DATA NACK Sp

S

DATA

S: Slave Device

Sp: Stop Condition

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The PCM1870A supports the I

2

C serial bus and the data transmission protocol for the I

2

C standard as a slavedevice. This protocol is explained in I

2

C specification 2.0.

In I

2

C mode, the control terminals are changed as follows.TERMINAL NAME PROPERTY DESCRIPTION

MS/ADR Input I

2

C addressMD/SDA Input/output I

2

C dataMC/SCL Input I

2

C clock

Slave Address

MSB LSB1 0 0 0 1 1 ADR R/ W

The PCM1870A has its 7-bit slave address. The first six bits (MSBs) of the slave address are factory preset to1000 11. The next bit of the address byte is the device select bit, which can be user-defined by ADR terminal. Amaximum of two PCM1870As can be connected on the same bus at one time. Each PCM1870A responds whenit receives its own slave address.

Packet Protocol

A master device must control packet protocol, which is start condition, slave address with read/write bit, data ifwrite or acknowledgement if read, and stop condition. The PCM1870A supports only slave-receiver andslave-transmitter.

Figure 20. Basic I

2

C Framework

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Transmitter M M

Data Type Slave Address Reg Address Write Data

R0002-01

M: Master Device S: Slave Device

St: Start Condition W: Write ACK: Acknowledge Sp: Stop Condition

M M S M

St W ACK Sp

S

ACK

MS

ACK

R0002-02

M: Master Device S: Slave Device St: Start Condition

Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge

W: Write R: Read

Transmitter M M M S

Data Type St Slave Address W ACK

M

Reg Address

M

Sr

M

Slave Address

S

ACK

M

R

S

ACK

M

Sp

M

NACK

S

Read Data

PCM1870A

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Write Operation

A master can write any PCM1870A registers using single access. The master sends a PCM1870A slave addresswith a write bit, a register address, and the data. When undefined registers are accessed, the PCM1870A doesnot send an acknowledgement. The Figure 21 shows a diagram of the write operation.

Figure 21. Framework for Write Operation

Read Operation

A master can read the PCM1870A register. The value of the register address is stored in an indirect indexregister in advance. The master sends a PCM1870A slave address with a read bit after storing the registeraddress. Then the PCM1870A transfers the data which the index register points to. Figure 22 shows a diagramof the read operation.

NOTE: The slave address after the repeated start condition must be the same as the previous slave address.

Figure 22. Read Operation

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Timing Diagram

SDA

SCL

t(BUF) t(D-SU)

t(D-HD)

Start

t(LOW)

t(S-HD) t(SCL-F)

t(SCL-R)

t(HI) t(RS-SU)

t(RS-HD)

t(SDA-F)

t(SDA-R) t(P-SU)

Stop

t(SP)

T0050-03

PCM1870A

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TIMING CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN MAX UNITf

SCL

SCL clock frequency Standard 100 kHzt

(BUF)

Bus free time between a STOP and START condition Standard 4.7 µst

(LOW)

Low period of the SCL clock Standard 4.7 µst

(HI)

High period of the SCL clock Standard 4 µst

(RS-SU)

Setup time for START condition Standard 4.7 µst

(S-HD)

Hold time for START condition Standard 4 µst

(D-SU)

Data setup time Standard 250 nst

(D-HD)

Data hold time Standard 0 900 nst

(SCL-R)

Rise time of SCL signal Standard 20 + 0.1 C

B

1000 nst

(SCL-F)

Fall time of SCL signal Standard 20 + 0.1 C

B

1000 nst

(SDA-R)

Rise time of SDA signal Standard 20 + 0.1 C

B

1000 nst

(SDA-F)

Fall time of SDA signal Standard 20 + 0.1 C

B

1000 nst

(P-SU)

Setup time for STOP condition Standard 4 µsC

B

Capacitive load for SDA and SCL line 400 pFt

(SP)

Pulse duration of spike suppressed 25 ns

Figure 23. I

2

C Interface Timing

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USER-PROGRAMMABLE MODE CONTROLS

Register Map

PCM1870A

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The mode control register map is shown in Table 6 . Each register includes an index (or address) indicated by theIDX[6:0] bits.

Table 6. Mode Control Register MapIDX [6:0]REGISTER DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0(B14 – B8)

Register 73 49h Analog bias power up/down PBIS RSV RSV RSV RSV RSV RSV RSV

Register 74 4Ah V

COM

power up/down RSV RSV RSV RSV RSV RSV RSV PCOM

Register 79 4Fh Volume for ADC input (L-ch) RSV RSV ALV5 ALV4 ALV3 ALV2 ALV1 ALV0

Register 80 50h Volume for ADC input (R-ch) RSV RSV ARV5 ARV4 ARV3 ARV2 ARV1 ARV0

Register 81 51h ADC high pass-filter, soft mute, audio interface HPF1 HPF0 RMUL RMUR RSV DSMC RFM1 RFM0

Register 82 52h ADC, MCB, PG1, 2, 5, 6, D2S power up/down RSV RSV PAIR PAIL PADS PMCB PADR PADL

Register 83 53h Auto level control for recording RALC RSV RRTC RATC RCP1 RCP0 RLV1 RLV0

Register 84 54h DOUT, BCK, and LRCK config, bit, master mode RSV RSV RSV BLHZ DOHZ MSTR RSV BIT0

Register 85 55h System reset, sampling rate control SRST RSV NPR5 NPR4 NPR3 NPR2 NPR1 NPR0

Register 86 56h BCK config, master mode, zero cross MBST MSR2 MSR1 MSR0 RSV RSV RSV ZCRS

Register 87 57h Analog input select (MUX1, 2, 3, 4) AD2S RSV AIR1 AIR0 RSV RSV AIL1 AIL0

Register 90 5Ah Boost RSV RSV RSV RSV RSV RSV G20R G20L

Register 92 5Ch Bass boost gain level (200 Hz) LPAE RSV RSV LGA4 LGA3 LGA2 LGA1 LGA0

Register 93 5Dh Middle boost gain level (1 kHz) RSV RSV RSV MGA4 MGA3 MGA2 MGA1 MGA0

Register 94 5Eh Treble boost gain level (5 kHz) RSV RSV RSV HGA4 HGA3 HGA2 HGA1 HGA0

Register 95 5Fh Sound effect source select, 3D sound RSV 3DEN RSV 3FL0 3DP3 3DP2 3DP1 3DP0

Register 96 60h 2-stage notch filter, digital monaural mixing NEN2 NEN1 NUP2 NUP1 RSV RSV RSV MXEN

Register 97 61h 1st-stage notch filter lower coefficient (a1) F107 F106 F105 F104 F103 F102 F101 F100

Register 98 62h 1st-stage notch filter upper coefficient (a1) F115 F114 F113 F112 F111 F110 F109 F108

Register 99 63h 1st-stage notch filter lower coefficient (a2) F207 F206 F205 F204 F203 F202 F201 F200

Register 100 64h 1st-stage notch filter upper coefficient (a2) F215 F214 F213 F212 F211 F210 F209 F208

Register 101 65h 2nd-stage notch filter lower coefficient (a1) S107 S106 S105 S104 S103 S102 S101 S100

Register 102 66h 2nd-stage notch filter upper coefficient (a1) S115 S114 S113 S112 S111 S110 S109 S108

Register 103 67h 2nd-stage notch filter lower coefficient (a2) S207 S206 S205 S204 S203 S202 S201 S200

Register 104 68h 2nd-stage notch filter upper coefficient (a2) S215 S214 S213 S212 S211 S210 S209 S208

Register 124 7Ch Mic boost RSV RSV RSV RSV RSV RSV G12R G12L

ADC: A/D converter MCB: Microphone bias

PGx: Analog input buffer D2S: Differential to single-ended amplifier

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Register 73

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 73 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 PBIS RSV RSV RSV RSV RSV RSV RSV

IDX[6:0]: 100 1001b (49h) Register 73

PBIS: Power Up/Down Control for Bias

Default value: 0

This bit is used to control power up/down for the analog bias circuit.PBIS = 0 Power down (default)PBIS = 1 Power up

Register 74

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 74 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV RSV PCOM

IDX[6:0]: 100 1010b (4Ah) Register 74

PCOM: Power Up/Down Control for V

COM

Default value: 0

This bit is used to control power up/down for V

COM

.PCOM = 0 Power down (default)PCOM = 1 Power up

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Register 79 and 80B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 79 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV ALV5 ALV4 ALV3 ALV2 ALV1 ALV0Register 80 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV ARV5 ARV4 ARV3 AR2 ARV1 ARV0

IDX[6:0]: 100 1111b (4Fh) Register 79

IDX[6:0]: 101 0000b (50h) Register 80

ALV[5:0]: Gain Control for PG3 (ADC Analog Input R-Channel)

ARV[5:0]: Gain Control for PG4 (ADC Analog Input L-Channel)

Default value: 00

PG3 and PG4 can be independently controlled for ADC input from 30 dB to – 12 dB in 1-dB steps. ADC outputmay have zipper noise when changing levels. In the PCM1870A, the noise can be reduced when making thechange by using zero-cross detection (Register 85, ZCRS).

Table 7. Gain Level Setting

ALV[5:0], ARV[5:0] ALV[5:0], ARV[5:0]GAIN LEVEL SETTING GAIN LEVEL SETTINGBINARY HEX BINARY HEX

10 1010 2A 30 dB 01 0100 14 8 dB10 1001 29 29 dB 01 0011 13 7 dB10 1000 28 28 dB 01 0010 12 6 dB10 0111 27 27 dB 01 0001 11 5 dB10 0110 26 26 dB 01 0000 10 4 dB10 0101 25 25 dB 00 1111 0F 3 dB10 0100 24 24 dB 00 1110 0E 2 dB10 0011 23 23 dB 00 1101 0D 1 dB10 0010 22 22 dB 00 1100 0C 0 dB10 0001 21 21 dB 00 1011 0B – 1 dB10 0000 20 20 dB 00 1010 0A – 2 dB01 1111 1F 19 dB 00 1001 09 – 3 dB01 1110 1E 18 dB 00 1000 08 – 4 dB01 1101 1D 17 dB 00 0111 07 – 5 dB01 1100 1C 16 dB 00 0110 06 – 6 dB01 1011 1B 15 dB 00 0101 05 – 7 dB01 1010 1A 14 dB 00 0100 04 – 8 dB01 1001 19 13 dB 00 0011 03 – 9 dB01 1000 18 12 dB 00 0010 02 – 10 dB01 0111 17 11 dB 00 0001 01 – 11 dB01 0110 16 10 dB 00 0000 00 – 12 dB (default)01 0101 15 9 dB

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Register 81

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 81 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 HPF1 HPF0 RMUL RMUR RSV DSMC RFM1 RFM0

IDX[6:0]: 101 0001b (51h) Register 81

HPF[1:0]: High-Pass Filter Selection

Default value: 00

The PCM1870A has a digital high-pass filter to remove dc voltage at the input of the ADC. The cutoff frequencyof the high-pass filter can be selected.HPF[1:0] High Pass Filter Selection

0 0 f

C

= 4 Hz at 48 kHz (default)0 1 f

C

= 240 Hz at 48 kHz1 0 f

C

= 120 Hz at 48 kHz1 1 High-pass filter disabled

RMUL: Digital Soft Mute Control for ADC L-Channel

RMUR: Digital Soft Mute Control for ADC R-Channel

Default value: 1

The digital output of the ADC can be independently muted or unmuted. The transition from the current volumelevel to mute, or the return to the previous volume setting from mute, occurs at the rate of one 1-dB step for each8/f

S

time period. When RMUL and RMUR = 0, the digital data is increased from mute to the previous attenuationlevel, and when RMUL and RMUR = 1, the digital data is decreased from the current attenuation level to mute. Inthe PCM1870A, audible zipper noise can be reduced by using zero-cross detection (register 85, ZCRS).RMUL, RMUR = 0 Mute disabledRMUL, RMUR = 1 Mute enabled (default)

DSMC: Waiting Time Turn ADC Mute Off at Power Up

Default value: 0

ADC digital output has waiting time at power up when DSMC = 0. It is recommended to set DSMC = 0.DSMC = 0 10 ms at 48 kHz (default)DSMC = 1 No wait

RFM[1:0]: Audio Interface Selection for ADC (Digital Output)

Default value: 00

The audio interface format for ADC digital output has I

2

S, right-justified, left-justified, and DSP formats.RFM[1:0] Audio Interface Selection for ADC Digital Output

0 0 I

2

S (default)0 1 Right-justified1 0 Left-justified1 1 DSP mode

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Register 82

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 82 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV PAIR PAIL PADS PMCB PADR PADL

IDX[6:0]: 101 0010b (52h) Register 82

PAIR: Power Up/Down for PG2 and PG6 (Gain Amplifier for Analog Input R-Channel)

PAIR: Power Up/Down for PG1 and PG5 (Gain Amplifier for Analog Input L-Channel)

Default value: 0

This bit is used to control power up/down for PG1, -2 and PG5, -6 (gain amplifier for analog input).PAIR, PAIL = 0 Power down (default)PAIR, PAIL = 1 Power up

PADS: Power Up/Down for D2S (Differential Amplifier) of AIN1L and AIN1R

Default value: 0

This bit is used to control power up/down for D2S (differential-to-single amplifier).PADS = 0 Power down (default)PADS = 1 Power up

PMCB: Power Up/Down Control for Microphone Bias Source

Default value: 0

This bit is used to control power up/down for the microphone bias source.PMCB = 0 Power down (default)PMCB = 1 Power up

PADR: Power Up/Down Control for ADR (ADC and Digital Filter R-Channel)

PADL: Power Up/Down Control for ADL (ADC and Digital Filter L-Channel)

Default value: 0

This bit is used to control power up/down for the ADC and decimation filter.PADR, PADL = 0 Power down (default)PADR, PADL = 1 Power up

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Register 83

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 83 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RALC RSV RRTC RATC RCP1 RCP0 RLV1 RLV0

IDX[6:0]: 1010011b (53h) Register 83

RALC: Automatic Level Control (ALC) Enable for Recording

Default value: 0

Auto level control can be enabled with some parameters for microphone input or lower-level analog source.RALC = 0 Disabled (default)RALC = 1 Enabled

RRTC: ALC Recovery Time Control for Recording

Default value: 0

This bit selects the time during which a gain level change completes to compress the signal when the input to theADC increases in amplitude.RRTC = 0 3.4 s (default)RRTC = 1 13.6 s

RATC: ALC Attack Time Control for Recording

Default value: 0

This bit selects the time during which a gain level change completes to expand the signal when the input to theADC decreases in amplitude.RATC = 0 1 ms (default)RATC = 1 2 ms

RCP[1:0]: ALC Compression Level Control for Recording

Default value: 00

Auto level control can set the compression level to – 2, – 6, or – 12 dB. Higher-level signals should be compressedto avoid saturation or degradation of sound quality.RCP[1:0] ALC Compression Level Control for Recording

0 0 – 2 dB (default)0 1 – 6 dB1 0 – 12 dB1 1 Reserved

RLV[1:0]: ALC Expansion Level Control for Recording

Default value: 00

Auto level control can set the expansion level to 0, 6, 14, or 24 dB. Lower-level signals should be expanded tomake a small signal easy to hear. If set to 0 dB, the ALC can be operated only as a limiter.RLV[1:0] ALC Expansion Level Control for Recording

0 0 0 dB (default)0 1 6 dB1 0 14 dB1 1 24 dB

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Register 84 – 86

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 84 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV BLHZ DOHZ MSTR RSV BIT0Register 85 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST RSV NPR5 NPR4 NPR3 NPR2 NPR1 NPR0Register 86 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MBST MSR2 MSR1 MSR0 RSV RSV RSV ZCRS

IDX[6:0]: 101 0100b (54h) Register 84

IDX[6:0]: 101 0101b (55h) Register 85

IDX[6:0]: 101 0110b (56h) Register 86

BLHZ: BCK and LRCK Output Configuration

Default value: 0

This bit is used for control output configuration of LRCK and BCK pin. When BLHZ = 1, the application systemcan connect some devices to these signal lines.BLHZ = 0 Output at master mode or Input at slave mode (default)BLHZ = 1 High Impedance

DOHZ: DOUT Output Configuration

Default value: 0

This bit is used for control output configuration of DOUT pin. When DOHZ = 1, the application system canconnect some devices to this signal line.DOHZ = 0 Output (default)DOHZ = 1 High Impedance

MSTR: Master or Slave Selection for Audio Interface

Default value: 0

This bit is used to select either master or slave mode for the audio interface. In master mode, PCM1870Agenerates LRCK and BCK from the system clock. In slave mode, it receives LRCK and BCK from anotherdevice.

MSTR = 0 Slave interface (default)MSTR = 1 Master interface

BIT0: Bit Length Selection for Audio Interface

Default value: 1

This bit is used to select data bit length for the ADC output.BIT0 = 0 ReservedBIT0 = 1 16 bits (default)

SRST: System Reset

Default value: 0

This bit is used to enable system reset. All circuits are reset by setting SRST = 1. After completing the resetsequence, SRST resets to 0 automatically.SRST = 0 Reset disabled (default)SRST = 1 Reset enabled

NPR[5:0]: System Clock Rate Selection

Default value: 00 0000

These bits are used to select the system clock rate. See Table 8 for details.

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MBST: BCK Output Configuration in Master Mode

Default value: 0

This bit is used to control the BCK output configuration in master mode. V

IO

(I/O cell power supply) powerconsumption can be reduced by adjusting BCK edge to bit number when setting MBST = 1. This is effective inmaster mode (register 69 MSTR = 1).MBST = 0 Normal output (default)MBST = 1 Burst output

MSR[2:0]: System Clock Dividing Rate Selection in Master Mode (Register 70)

Default value: 000

These bits are used to set the dividing rate of the input system clock. See Table 8 for details.

Table 8. System Clock Frequency for Common Audio Clock

REGISTER SETTINGSYSTEM CLOCK ADC SAMPLING RATE DAC SAMPLING RATE BIT CLOCKSCK (MHz) ADC f

S

(kHz) DAC f

S

(kHz) BCK (f

S

)MSR[2:0] NPR[5:0]

24 (SCK/256) 010 00 0000 6416 (SCK/384) 011 00 0000 6412 (SCK/512) 100 00 0000 646.144

8 (SCK/768) 101 00 0000 646 (SCK/1024) 110 00 0000 644 (SCK/1536) 111 00 0000 6432 (SCK/256) 010 00 0000 648.192 16 (SCK/512) 100 00 0000 648 (SCK/1024) 110 00 0000 6448 (SCK/256) 010 00 0000 6432 (SCK/384) 011 00 0000 6424 (SCK/512) 100 00 0000 6412.288

16 (SCK/768) 101 00 0000 6412 (SCK/1024) 110 00 0000 648 (SCK/1536) 111 00 0000 6448 (SCK/384) 011 00 0000 6418.432 24 (SCK/768) 101 00 0000 6412 (SCK/1536) 111 00 0000 6422.05 (SCK/256) 010 00 0000 6414.7 (SCK/384) 011 00 0000 6411.025 (SCK/512) 100 00 0000 645.6448

7.35 (SCK/768) 101 00 0000 645.5125 (SCK/1024) 110 00 0000 643.675 (SCK/1536) 111 00 0000 6444.1 (SCK/256) 010 00 0000 6429.4 (SCK/384) 011 00 0000 6422.05 (SCK/512) 100 00 0000 6411.2896

14.7 (SCK/768) 101 00 0000 6411.025 (SCK/1024) 110 00 0000 647.35 (SCK/1536) 111 00 0000 64NOTE: Other settings are reserved.

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Table 9. System Clock Frequency for Application-Specific Audio Clock

REGISTER SETTINGSYSTEM CLOCK ADC SAMPLING RATE DAC SAMPLING RATE BIT CLOCKSCK (MHz) ADC f

S

(kHz) DAC f

S

(kHz) BCK (f

S

)MSR[2:0] NPR[5:0]

48.214 (SCK/280) 010 00 0010 7044.407 (SCK/304) 010 00 0001 7632.142 (SCK/420) 010 10 0010 7024.107 (SCK/560) 100 00 0010 7013.5

22.203 (SCK/608) 100 00 0001 7616.071 (SCK/840) 100 10 0010 7012.053 (SCK/1120) 110 00 0010 708.035 (SCK/1680) 110 10 0010 7048.214 (SCK/560) 010 01 0010 7044.407 (SCK/608) 010 01 0001 7632.142 (SCK/840) 010 11 0010 7024.107 (SCK/1120) 100 01 0010 7027

22.203 (SCK/1216) 100 01 0001 7616.071 (SCK/1680) 100 11 0010 7012.053 (SCK/2240) 110 01 0010 708.035 (SCK/3360) 110 11 0010 7048.387 (SCK/248) 010 00 0100 6244.117 (SCK/272) 010 00 0011 6832.258 (SCK/372) 010 10 0100 6224.193 (SCK/496) 100 00 0100 6212

22.058 (SCK/544) 100 00 0011 6816.129 (SCK/744) 100 10 0100 6212.096 (SCK/992) 110 00 0100 628.064 (SCK/1488) 110 10 0100 6248.387 (SCK/496) 010 01 0100 6244.117 (SCK/544) 010 01 0011 6832.258 (SCK/744) 010 11 0100 6224.193 (SCK/992) 100 01 0100 6224

22.058 (SCK/1088) 100 01 0011 6816.129 (SCK/1488) 100 11 0100 6212.096 (SCK/1984) 110 01 0100 628.064 (SCK/2796) 110 11 0100 6248.484 (SCK/396) 011 00 0110 6644.444 (SCK/432) 011 00 0101 7232.323 (SCK/594) 011 10 0110 6624.242 (SCK/792) 101 00 0110 6619.2

22.222 (SCK/864) 101 00 0101 7216.161 (SCK/1188) 101 10 0110 6612.121 (SCK/1584) 111 00 0110 668.080 (SCK/2376) 111 10 0110 66

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Table 9. System Clock Frequency for Application-Specific Audio Clock (continued)

REGISTER SETTINGSYSTEM CLOCK ADC SAMPLING RATE DAC SAMPLING RATE BIT CLOCKSCK (MHz) ADC f

S

(kHz) DAC f

S

(kHz) BCK (f

S

)MSR[2:0] NPR[5:0]

48.484 (SCK/792) 011 01 0110 6644.444 (SCK/864) 011 01 0101 7232.323 (SCK/1188) 011 11 0110 6624.242 (SCK/1584) 101 01 0110 6638.4

22.222 (SCK/1728) 101 01 0101 7216.161 (SCK/2376) 101 11 0110 6612.121 (SCK/3168) 111 01 0110 668.080 (SCK/4752) 111 11 0110 6647.794 (SCK/272) 010 00 1000 6843.918 (SCK/296) 010 00 0111 7431.862 (SCK/408) 010 10 1000 6823.897 (SCK/544) 100 00 1000 6813

21.959 (SCK/592) 100 00 0111 7415.931 (SCK/816) 100 10 1000 6811.948 (SCK/1088) 110 00 1000 687.965 (SCK/1632) 110 10 1000 6847.794 (SCK/544) 010 01 1000 6843.918 (SCK/592) 010 01 0111 7431.862 (SCK/816) 010 11 1000 6823.897 (SCK/1088) 100 01 1000 6826

21.959 (SCK/1184) 100 01 0111 7415.931 (SCK/1632) 100 11 1000 6811.948 (SCK/2176) 110 01 1000 687.965 (SCK/3264) 110 11 1000 6848.235 (SCK/408) 011 00 1010 6844.324 (SCK/444) 011 00 1001 7432.156 (SCK/612) 011 10 1010 6824.117 (SCK/816) 101 00 1010 6819.68

22.162 (SCK/888) 101 00 1001 7416.078 (SCK/1224) 101 10 1010 6812.058 (SCK/1632) 111 00 1010 688.039 (SCK/2448) 111 10 1010 6848.235 (SCK/816) 011 01 1010 6844.324 (SCK/888) 011 01 1001 7432.156 (SCK/1224) 011 11 1010 6824.117 (SCK/1632) 101 01 1010 6839.36

22.162 (SCK/1776) 101 01 1001 7416.078 (SCK/2448) 101 11 1010 6812.058 (SCK/3264) 111 01 1010 688.039 (SCK/4896) 111 11 1010 68

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ZCRS: Zero Cross for Digital Attenuation/Mute and Analog Gain Setting

Default value: 0

This bit is used to enable the zero-cross detector, which reduces zipper noise while the digital soft mute oranalog gain setting is being changed. If no zero-cross data is input for a 512/f

S

period (10.6 ms at a 48-kHzsampling rate), then a time-out occurs and the PCM1870A starts changing the attenuation, gain, or volume level.The zero-cross detector cannot be used with continuous-zero and dc data.ZCRS = 0 Zero cross disabled (default)ZCRS = 1 Zero cross enabled

Register 87

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 87 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AD2S RSV AIR1 AIR0 RSV RSV AIL1 AIL0

IDX[6:0]: 101 0111b (57h) Register 87

AD2S: Differential Amplifier Selector (MUX3 and MUX4)

Default value: 0

This bit is used to select whether a single-ended amplifier or differential amplifier (D2S) is used as the input forthe ADC. MUX3 and MUX4 use the single-ended input when AD2S = 0. MUX3 and MUX4 use the monauraldifferential input when AD2S = 1.AD2S = 0 Single-ended amplifier (default)AD2S = 1 Differential amplifier

AIL[1:0]: AIN1L and AIN2L Selector (MUX1)

Default value: 00

MUX1 selects the analog input, AIN1L or AIN2L.AIL[1:0] AIN L-channel Select

0 0 Disconnect (default)0 1 AIN1L1 0 AIN2L1 1 Reserved

AIR[1:0]: AIN1R and AIN2R Selector (MUX2)

Default value: 00

MUX2 selects the analog input, AIN1R or AIN2R.AIR[1:0] AIN R-channel Select

0 0 Disconnect (default)0 1 AIN1R1 0 AIN2R1 1 Reserved

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Register 90

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 90 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV G20R G20L

IDX[6:0]: 101 1010b (5Ah) Register 90

G20R: 20-dB Boost for PG2 (Gain Amplifier for AIN1R and AIN2R)

Default value: 0

This bit is used to boost the microphone signal when the analog input is small.G12R G20R PG2 GAIN(REGISTER 124) (REGISTER 90)

0 0 0 dB (default)0 1 20 dB1 0 12 dB1 1 Reserved

G20L: 20 dB Boost for PG1 (Gain Amplifier for AIN1L and AIN2L)

Default value: 0

This bit is used to boost the microphone signal when the analog input is small.G12L G20L PG1 GAIN(REGISTER 124) (REGISTER 90)

0 0 0 dB (default)0 1 20 dB1 0 12 dB1 1 Reserved

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Register 92

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 92 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 LPAE RSV RSV LGA4 LGA3 LGA2 LGA1 LGA0

IDX[6:0]: 101 1100b (5Ch) Register 92

LPAE: Automatic Attenuation Setting for Bass Boost Gain Control

Default value: 0

A gain setting for bass boost may cause digital data saturation, depending on the input data level. Where thiscould occur, LPAE can be used to set the same attenuation level as the bass boost gain level for the digital inputdata.

LPAE = 0 Disble (default)LPAE = 1 Enable

LGA[4:0]: Bass Boost Gain Control

Default value: 0 0000

These bits are used to set bass boost gain level for the digital data. The center frequency for boost is 200 Hz at44.1 kHz.

LGA[4:0] TONE CONTROL GAIN (BASS) LGA[4:0] TONE CONTROL GAIN (BASS)

0 0000 0 dB (default) 0 1111 0 dB0 0011 12 dB 1 0000 – 1 dB0 0100 11 dB 1 0001 – 2 dB0 0101 10 dB 1 0010 – 3 dB0 0110 9 dB 1 0011 – 4 dB0 0111 8 dB 1 0100 – 5 dB0 1000 7 dB 1 0101 – 6 dB0 1001 6 dB 1 0110 – 7 dB0 1010 5 dB 1 0111 – 8 dB0 1011 4 dB 1 1000 – 9 dB0 1100 3 dB 1 1001 – 10 dB0 1101 2 dB 1 1010 – 11 dB0 1110 1 dB 1 1011 – 12 dB

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Register 93

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 93 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV MGA4 MGA3 MGA2 MGA1 MGA0

IDX[6:0]: 101 1101b (5Dh) Register 93

MGA[4:0]: Middle Boost Gain Control

Default value: 0 0000

These bits are used to set midrange boost gain level for the digital data. The center frequency for boost is 1 kHz.MGA[4:0] TONE CONTROL GAIN (MID) MGA[4:0] TONE CONTROL GAIN (MID)

0 0000 0 dB (default) 0 1111 0 dB0 0011 12 dB 1 0000 – 1 dB0 0100 11 dB 1 0001 – 2 dB0 0101 10 dB 1 0010 – 3 dB0 0110 9 dB 1 0011 – 4 dB0 0111 8 dB 1 0100 – 5 dB0 1000 7 dB 1 0101 – 6 dB0 1001 6 dB 1 0110 – 7 dB0 1010 5 dB 1 0111 – 8 dB0 1011 4 dB 1 1000 – 9 dB0 1100 3 dB 1 1001 – 10 dB0 1101 2 dB 1 1010 – 11 dB0 1110 1 dB 1 1011 – 12 dB

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Register 94

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 94 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV HGA4 HGA3 HGA2 HGA1 HGA0

IDX[6:0]: 101 1110b (5Eh) Register 94

HGA[4:0]: Treble Boost Gain Control

Default value: 0 0000

These bits are used to set treble boost gain level for the digital data. The center frequency for boost is 5 kHz.HGA[4:0] TONE CONTROL GAIN (TREBLE) HGA[4:0] TONE CONTROL GAIN (TREBLE)

0 0000 0 dB (default) 0 1111 0 dB0 0011 12 dB 1 0000 – 1 dB0 0100 11 dB 1 0001 – 2 dB0 0101 10 dB 1 0010 – 3 dB0 0110 9 dB 1 0011 – 4 dB0 0111 8 dB 1 0100 – 5 dB0 1000 7 dB 1 0101 – 6 dB0 1001 6 dB 1 0110 – 7 dB0 1010 5 dB 1 0111 – 8 dB0 1011 4 dB 1 1000 – 9 dB0 1100 3 dB 1 1001 – 10 dB0 1101 2 dB 1 1010 – 11 dB0 1110 1 dB 1 1011 – 12 dB

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Register 95

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 95 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV 3DEN RSV 3FL0 3DP3 3DP2 3DP1 3DP0

IDX[6:0]: 1011111b (5Fh) Register 95

3DEN: 3D Sound Effect Enable

Default value: 0

This bit is used for enabling the 3-D sound effect filter. This filter has two independently controlled parameters.3DEN = 0 Disable (default)3DEN = 1 Enable

3FL0: Filter Selection for 3D Sound

Default value: 0

This bit is used for selecting from two kinds of filter type, narrow and wide. These filters produce different 3-Deffects.

3FL0 = 0 Narrow (default)3FL0 = 1 Wide

3DP[3:0]: Efficiency for 3D Sound Effect

Default value: 0000

These bits are used for adjusting the 3-D sound efficiency. Higher percentages have greater efficiency.3DP[3:0] 3D Sound Effect Efficiency

0000 0% (default)0001 10%0010 20%0011 30%0100 40%0101 50%0110 60%0111 70%1000 80%1001 90%1010 100%1011 Reserved: :1111 Reserved

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Register 96

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 96 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 NEN2 NEN1 NUP2 NUP1 RSV RSV RSV MXEN

IDX[6:0]: 110 0000b (60h) Register 96

NEN2: Second-Stage Notch Filter Enable

Default value: 0

The PCM1870A has a two-stage notch filter. The two stages can separately set filter characteristics. This bit isused to enable the second stage.NEN2 = 0 Disabled (default)NEN2 = 1 Enabled

NEN1: First-Stage Notch Filter Enable

Default value: 0

The PCM1870A has a two-stage notch filter. The two stages can separately set filter characteristics. This bit isused to enable the first stage.NEN1 = 0 Disabled (default)NEN1 = 1 Enabled

NUP2: Second-Stage Notch Filter Coefficients Update

Default value: 0

This bit is used to update the coefficients for the second-stage notch filter. The coefficients written to registers101, 102, 103, 104 are updated when NUP2 = 1.NUP2 = 0 No update (default)NUP2 = 1 Update

NUP1: First-Stage Notch Filter Coefficients Update

Default value: 0

This bit is used to update the coefficients for the first-stage notch filter. The coefficients written to registers 97,98, 99, 100 are updated when NUP1 = 1.NUP1 = 0 No update (default)NUP1 = 1 Update

MXEN: Digital Monaural Mixing

Default value: 0

This bit is used to enable or disable monaural mixing in the section that combines L-ch and R-ch digital data.MXEN = 0 Disabled (stereo, default)MXEN = 1 Enabled (monaural mixing)

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Registers 97 – 100

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 97 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 F107 F106 F105 F104 F103 F102 F101 F100Register 98 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 F115 F114 F113 F112 F111 F110 F109 F108Register 99 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 F207 F206 F205 F204 F203 F202 F201 F200Register 100 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 F215 F214 F213 F212 F211 F210 F209 F208

IDX[6:0]: 110 0001b (61h) Register 97IDX[6:0]: 110 0010b (62h) Register 98IDX[6:0]: 110 0011b (63h) Register 99IDX[6:0]: 110 0100b (64h) Register 100

F[107:100]: Lower 8 Bits of Coefficient a

1

for First-Stage Notch FilterF[115:108]: Upper 8 Bits of Coefficient a

1

for First-Stage Notch FilterF[207:200]: Lower 8 Bits of Coefficient a

2

for First-Stage Notch FilterF[215:208]: Upper 8 Bits of Coefficient a

2

for First-Stage Notch Filter

Default value: 0000 0000

These bits are used to change the characteristics of the first-stage notch filter. See Calculating Filter Coefficientsfor details.

Registers 101 – 104

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 101 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 S107 S106 S105 S104 S103 S102 S101 S100Register 102 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 S115 S114 S113 S112 S111 S110 S109 S108Register 103 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 S207 S206 S205 S204 S203 S202 S201 S200Register 104 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 S215 S214 S213 S212 S211 S210 S209 S208

IDX[6:0]: 110 0101b (65h) Register 101IDX[6:0]: 110 0110b (66h) Register 102IDX[6:0]: 110 0111b (67h) Register 103IDX[6:0]: 110 1000b (68h) Register 104

S[107:100]: Lower 8 Bits of Coefficient a

1

for Second-Stage Notch FilterS[115:108]: Upper 8 Bts of Coefficient a

1

for Second-Stage Notch FilterS[207:200]: Lower 8 Bits of Coefficient a

2

for Second-Stage Notch FilterS[215:208]: Upper 8 Bits of Coefficient a

2

for Second-Stage Notch Filter

Default value: 0000 0000

These bits are used to change the characteristics of the second-stage notch filter. See Calculating FilterCoefficients for details.

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fS+Sampling frequency [Hz]

fC+Center frequency [Hz]

a1+ * ǒ1)a2Ǔcosǒ2pfC

fSǓ

a2+

1*tanǒ2pfbńfS

2Ǔ

1)tanǒ2pfbńfS

2Ǔ

fb+Bandwidth [Hz]

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Calculating Filter Coefficients

The PCM1870A provides a dual-stage notch filter at the digital output of the ADC. The filter characteristics ofeach filter stage can be programmed. The characteristics are determined by calculating coefficients for threeparameters, sampling frequency, center frequency and bandwidth, as shown in the following equations. Allcoefficients must be written as 2s-complement binary data into registers 97, 98, 99, 100, 101, 102, 103, and 104.

Register 124

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Register 124 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV G12R G12L

IDX[6:0]: 111 1100b (7Ch) Register 124

G12R: 12-dB Boost for PG2 (Gain Amplifier for AIN1R and AIN2R)G12L: 12-dB Boost for PG1 (Gain Amplifier for AIN1L and AIN2L)

Default value: 0

These bits are used to boost the microphone signal when the analog input is small. See Register 90 for thedetailed settings.

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CONNECTION DIAGRAM

S0262-01

BCK (F1)

SCKI(F2)

LRCK (E1)

DOUT (F4)

MODE (D2)

MS/ADR (D3)

MD/SDA (D4)

MC/SCL (E4)

(B2)PGINL

(B1)PGINR

AIN1L (A2)

AIN1R (A1)

AIN2L ( C4)

AIN2R (C3)

V (A4)

COM

MICB (A3)

(C2) AOL

(C1) AOR

C6

C1

C2

C3

C4

C5

R1R2

C8

C7

C9

C10

(B3)VCC

(B4) AGND

(F3)VDD

(E2) DGND

(E3)VIO

TEST (D1)

ToRegulator

LoworHigh

PCM1870A

SLAS617 – AUGUST 2008 .................................................................................................................................................................................................

www.ti.com

Figure 24. Connection Diagram

Table 10. Recommended External Parts

C

1

– C

4

1µF – 10 µF C

9

, C

10

1µF – 10 µFC

5

1µF – 4.7 µF R

1

, R

2

2.2 k Ω

C

6

0.1 µFC

7

1µFC

8

1µF – 4.7 µF

Product Folder Link(s): PCM1870A

BOARD DESIGN AND LAYOUT CONSIDERATIONS

V

CC

, V

DD

, and V

IO

Pins

AGND and DGND Pins

AIN1L, AIN1R, AIN2L, and AIN2R Pins

AOL, AOR, PGINL, and PGINR Pins

V

COM

BCK (Master Mode) and DOUT Pins

PCM1870A

www.ti.com

................................................................................................................................................................................................. SLAS617 – AUGUST 2008

The digital and analog power supply lines to the PCM1870A should be bypassed to the corresponding groundpins with 0.1- to 4.7- µF ceramic capacitors or electrolytic capacitors, placed as close to the pins as possible tomaximize the dynamic performance of ADC.

To maximize the dynamic performance of the PCM1870A, the analog and digital grounds are not connectedinternally. These grounds should have very low impedance to avoid digital noise feeding back into the analogground. So, they should be connected directly to each other under the part to reduce the potential of noiseproblems.

AIN1L, AIN1R, AIN2L, and AIN2R are single-ended inputs. AIN1L and AIN1R can also be used as a monauraldifferential input. The anti-aliasing low-pass filters are integrated on these inputs to remove the out-of-band noisefrom the audio. If the performance of these filters is not good enough for an application, appropriate externalanti-aliasing filters are needed. The passive RC filter (100 Ωand 0.01 µF to 1 k Ωand 1000 pF) is used ingeneral. Any pins that are not used in an application should be left open. Do not select open pins throughregister settings.

When AIN1L, AIN1R, AIN2L, and AIN2R pins are used as microphone inputs with high gain, AOL and AOR mayhave a large dc offset. It is recommended to locate a dc-blocking capacitor (1- to 10- µF capacitor) betweenAOL/AOR and PGINL/PGINR. If an application is not affected by dc offset, the PCM1870A does not need thecapacitors.

1- µF to 4.7- µF capacitor is recommended between V

COM

and AGND to ensure low source impedance for theADC common voltage. This capacitor should be located as close as possible to the V

COM

pin to reduce dynamicerrors on the ADC common voltage.

BCK in the master mode and DOUT have adequate load drive capability, but if the BCK and DOUT lines arelong, locating a buffer near the PCM1870A and minimizing load capacitance is recommended in order tominimize crosstalk between digital and analog circuits, maximize the dynamic performance of the ADC, andreduce power consumption.

Product Folder Link(s): PCM1870A

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

PCM1870AYZFR ACTIVE DSBGA YZF 24 2000 Green (RoHS &

no Sb/Br) SNAGCU Level-1-260C-UNLIM

PCM1870AYZFT ACTIVE DSBGA YZF 24 250 Green (RoHS &

no Sb/Br) SNAGCU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 16-Apr-2009

Addendum-Page 1

D: Max =

E: Max =

3.48 mm, Min =

2.48 mm, Min =

3.42 mm

2.42 mm

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