General Description
The MAX144/MAX145 low-power, 12-bit analog-to-
digital converters (ADCs) are available in 8-pin µMAX®
and DIP packages. Both devices operate with a single
+2.7V to +5.25V supply and feature a 7.4µs succes-
sive-approximation ADC, automatic power-down, fast
wake-up (2.5µs), an on-chip clock, and a high-speed,
3-wire serial interface.
Power consumption is only 3.2mW (VDD = +3.6V) at the
maximum sampling rate of 108ksps. At slower through-
put rates, the automatic shutdown (0.2µA) further
reduces power consumption.
The MAX144 provides 2-channel, single-ended opera-
tion and accepts input signals from 0 to VREF. The
MAX145 accepts pseudo-differential inputs ranging
from 0 to VREF. An external clock accesses data-
through the 3-wire serial interface, which is SPI™,
QSPI™, and MICROWIRE™-compatible.
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications, or for other circuits with
demanding power-consumption and space require-
ments. For pin-compatible 10-bit ADCs, see the
MAX157 and MAX159 data sheets.
Applications
Features
♦Single-Supply Operation (+2.7V to +5.25V)
♦Two Single-Ended Channels (MAX144) One
Pseudo-Differential Channel (MAX145)
♦Low Power
0.9mA (108ksps, +3V Supply)
100µA (10ksps, +3V Supply)
10µA (1ksps, +3V Supply)
0.2µA (Power-Down Mode)
♦Internal Track/Hold
♦108ksps Sampling Rate
♦SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial
Interface
♦Space-Saving 8-Pin µMAX Package
♦Pin-Compatible 10-Bit Versions Available
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
________________________________________________________________ Maxim Integrated Products 1
PART TEMP
RANGE
PIN-
PACKAGE
INL
(LSB)
PKG
CODE
MAX144ACUA 0°C to
+70°C 8 µMAX ±0.5 U8-1
MAX144BCUA 0°C to
+70°C 8 µMAX ±1 U8-1
MAX144ACPA 0°C to
+70°C 8 Plastic DIP ±0.5 P8-1
MAX144BCPA 0°C to
+70°C 8 Plastic DIP ±1 P8-1
MAX144BC/D 0°C to
+70°C Dice* ±1 —
MAX144AEUA -40°C to
+85°C 8 µMAX ±0.5 U8-1
MAX144BEUA -40°C to
+85°C 8 µMAX ±1 U8-1
MAX144AEPA -40°C to
+85°C 8 Plastic DIP ±0.5 P8-1
MAX144BEPA -40°C to
+85°C 8 Plastic DIP ±1 P8-1
MAX144AMJA -55°C to
+125°C 8 CERDIP** ±0.5 J8-2
MAX144BMJA -55°C to
+125°C 8 CERDIP** ±1 J8-2
Ordering Information
CS/SHDN
REFGND
1
2
8
7
SCLK
DOUT
( ) ARE FOR MAX145 ONLY
CH0 (CH+)
CH1 (CH-)
VDD
µMAX/DIP
TOP VIEW
3
4
6
5
MAX144
MAX145
Pin Configuration
19-1387; Rev 2; 10/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*Dice are specified at TA= +25°C, DC parameters only.
**Contact factory for availability.
Ordering Information continued at end of data sheet.
Battery-Powered Systems
Portable Data Logging
Isolated Data Acquisition
Process-Control Monitoring
Instrumentation
Test Equipment
Medical Instruments
System Supervision
µMAX is a registered trademark of Maxim Integrated Products, Inc.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX145, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
CH0, CH1 (CH+, CH-) to GND ................. -0.3V to (VDD + 0.3V)
REF to GND .............................................. -0.3V to (VDD + 0.3V)
Digital Inputs to GND. ............................................. -0.3V to +6V
DOUT to GND............................................ -0.3V to (VDD + 0.3V)
DOUT Sink Current ........................................................... 25mA
Continuous Power Dissipation (TA= +70°C)
µMAX (derate 4.1mW/°C above +70°C) .................... 330mW
Plastic DIP (derate 9.09mW/°C above +70°C) ............727mW
CERDIP (derate 8.00mW/°C above +70°C) ............... 640mW
Operating Temperature Ranges (TA)
MAX144/MAX145_C_A .......................................0°C to +70°C
MAX144/MAX145_E_A. ...................................-40°C to +85°C
MAX144/MAX145_M_A ................................ -55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
MAX14_A
MAX14_B
No missing codes over temperature
CONDITIONS
LSB
±0.5
INLRelative Accuracy (Note 2)
Bits
12
RESResolution
±1 LSB±0.75DNLDifferential Nonlinearity
UNITSMIN TYP MAXSYMBOLPARAMETER
ppm/°C±0.8Gain Temperature Coefficient LSB±3 LSB±3Offset Error
Gain Error
LSB±0.05
Channel-to-Channel Offset
Matching
LSB±0.05
Channel-to-Channel Gain
Matching
-3dB rolloff
fIN = 65kHz, VIN = 2.5Vp-p (Note 4)
External clock, fSCLK = 2.17MHz,
16 clocks/conversion cycle
MHz1.0Full-Power Bandwidth MHz2.25 dB-85Channel-to-Channel Crosstalk
Small-Signal Bandwidth
µs
7.4
tCONV
Conversion Time (Note 5)
Total Harmonic Distortion
(including 5th-order harmonic)
dB70SINAD
Signal-to-Noise Plus
Distortion Ratio
dB-80THD
dB80SFDRSpurious-Free Dynamic Range
Internal clock mode, for data transfer only
External clock mode
Internal clock
05
MHz
0.1 2.17
fSCLK
ps<50Aperture Jitter
Serial Clock Frequency
57
µs2.5tACQ
T/H Acquisition Time ns25Aperture Delay
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (fIN(sine-wave) = 10kHz, VIN = 2.5Vp-p, 108ksps, fSCLK = 2.17MHz, CH- = GND for MAX145)
CONVERSION RATE
(Note 3)
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX145, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
VREF = 2.5V
On/off leakage current, VIN = 0 to VDD
kΩ18 25Input Resistance µA100 140
V
0V
DD
+ 50mV
VREF
Input Voltage Range
Input Current
µA0.01 10
CONDITIONS
Shutdown REF Input Current
µA±0.01 ±1Multiplexer Leakage Current
V0V
REF
VIN
Analog Input Voltage Range
pF16CIN
Input Capacitance
UNITS
MIN TYP MAX
SYMBOLPARAMETER
Input Leakage Current IIN ±1 µA
Input Hysteresis VHYS 0.2 V
0.2 5 µA
Input High Voltage VIH 2.0 V
3.0
Input Low Voltage VIL 0.8 V
Positive Supply Current IDD 0.9 2.0 mA
Three-State Output Capacitance COUT 15 pF
Positive Supply Voltage VDD 2.7 5.25 V
Power-Supply Rejection
Shutdown, CS/SHDN = GND
Operating mode
PSR ±0.15 mV
CS/SHDN = VDD (Note 8)
VDD = 2.7V to 5.25V,
VREF
= 2.5V, full-scale input (Note 9)
Three-State Output Leakage
Current ±10 µA
Output High Voltage VOH VDD - 0.5 V
Output Low Voltage
Input Capacitance VIN = 0 or VDD
CIN 15 pF
VOL 0.4 V
0.5
VDD ≤3.6V
VDD > 3.6V
CS/SHDN = VDD
ISOURCE = 0.5mA
(Note 8)
ISINK = 5mA
ISINK = 16mA
ANALOG INPUTS
EXTERNAL REFERENCE
DIGITAL INPUTS (CS/SHDN) AND OUTPUT (DOUT)
POWER REQUIREMENTS
(Note 6)
(Note 7)
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS (Figure 7)
(VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH-= GND
for MAX145, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Wake-Up Time 2.5 µs
CS/SHDN Fall to Output Enable tDV CL = 100pF 120 ns
CS /SHDN Rise to Output Disable tTR CL = 100pF, Figure 1 120 ns
SCLK Fall to Output Data Valid tDO CL = 100pF, Figure 1 20 120 ns
External clock 0.1 2.17
SCLK Clock Frequency fSCLK Internal clock, SCLK for data transfer only 0 5 MHz
External clock 215
SCLK Pulse Width High tCH Internal clock, SCLK for data transfer only
(Note 8) 50 ns
External clock 215
SCLK Pulse Width Low tCL Internal clock, SCLK for data transfer only
(Note 8) 50 ns
SCLK to CS /SHDN Setup tSCLKS 60 ns
CS /SHDN Pulse Width tCS 60 ns
Note 1: Tested at VDD = +2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3: Offset nulled.
Note 4: "On" channel is grounded; sine wave applied to "off" channel (MAX144 only).
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from GND to VDD (MAX145 only).
Note 7: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: Measured as VFS(2.7V) -VFS(5.25V).
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
_______________________________________________________________________________________
5
500
700
900
1100
1300
1500
2.5 3.0 3.5 4.0 4.5 5.55.0
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX144/5-01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
VREF = VDD
RL = ∞
CL = 50pF
CODE = 101010100000
0
200
400
600
800
1000
-60 20 40-20 0-40 60 80 100 120 140
SHUTDOWN CURRENT
vs. TEMPERATURE
MAX144/5-05
TEMPERATURE (°C)
SHUTDOWN CURRENT (nA)
VREF = VDD
500
750
1250
1000
1500
-60 -20 0 20 40-40 60 80 100 120 140
SUPPLY CURRENT
vs. TEMPERATURE
MAX144/5-02
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
VREF = VDD
RL = ∞
CL = 50pF
CODE = 101010100000
0
200
400
600
800
1000
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX144/5-04
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (nA)
2.5 3.0 3.5 4.0 4.5 5.55.0
VREF = VDD
Typical Operating Characteristics
(VDD = +3.0V, VREF = 2.5V, 0.1µF at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX145, TA= +25°C,
unless otherwise noted.)
SUPPLY CURRENT
vs. SAMPLING RATE
MAX144/5-03
SAMPLING RATE (sps)
SUPPLY CURRENT (µA)
10,000
0.1
1
10
100
1000
0.1 100 1k 10k1 10 100k
VDD = VREF
CL = 20pF
CODE = 101010100000
0
0.2
0.4
0.6
0.8
1.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
OFFSET ERROR
vs. SUPPLY VOLTAGE
MAX144/5-06
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
0
0.2
0.1
0.4
0.3
0.6
0.5
0.7
0.9
0.8
1.0
OFFSET ERROR
vs. TEMPERATURE
MAX144/5-07
TEMPERATURE (°C)
OFFSET ERROR (LSB)
-60 -10 15-35 40 65 90 115 140
-0.5
-0.3
-0.4
-0.1
-0.2
0.1
0
0.2
0.4
0.3
0.5
2.5 3.53.0 4.0 4.5 5.0 5.5
GAIN ERROR
vs. SUPPLY VOLTAGE
MAX144/5-08
VDD (V)
GAIN ERROR (LSB)
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = +3.0V, VREF = 2.5V, 0.1µF at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX145, TA= +25°C,
unless otherwise noted.)
Pin Description
External Reference Voltage Input. Sets the analog voltage range. Bypass with a 100nF capacitor close to
the device.
REF5
Active-Low Chip-Select Input/Active-High Shutdown Input. Pulling CS/SHDN high puts the device into
shutdown with a maximum current of 5µA.
CS/SHDN
6
Serial Data Output. Data changes state at SCLK’s falling edge. High impedance when CS/SHDN
is high.
DOUT7
Serial Clock Input. DOUT changes on the falling edge of SCLK.SCLK8
Analog and Digital GroundGND4 Analog Input: MAX144 = single-ended (CH1); MAX145 = differential (CH-)CH1 (CH-)3
PIN
Analog Input: MAX144 = single-ended (CH0); MAX145 = differential (CH+)CH0 (CH+)2 Positive Supply Voltage, +2.7V to +5.25VVDD
1FUNCTIONNAME
-0.20
-0.10
-0.15
0
-0.05
0.05
0.10
0.15
0.20
0 1024 2048 3072 4096
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX144/5-10
OUTPUT CODE
INL (LSB)
0
0.1
0.2
0.3
0.4
0.5
2.5 3.53.0 4.0 4.5 5.0 5.5
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX144/5-11
VDD (V)
INL (LSB)
0
0.1
0.2
0.3
0.4
0.5
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX144/5-12
INL (LSB)
TEMPERATURE (°C)
-60 -10 15-35 40 65 90 115 140
-140
-100
-120
-60
-80
-40
-20
0
20
02754
FFT PLOT
MAX144/5-13
FREQUENCY (kHz)
AMPLITUDE (dB)
VDD = +2.7V
fIN = 10kHz
fSAMPLE = 108ksps
12.0
11.0 1 10 100
EFFECTIVE NUMBER OF BITS
vs. FREQUENCY
11.2
MAX144/5-14
FREQUENCY (kHz)
EFFECTIVE NUMBER OF BITS
11.4
11.6
11.8
VDD = +2.7V
_______________Detailed Description
The MAX144/MAX145 analog-to-digital converters
(ADCs) use a successive-approximation conversion
(SAR) technique and on-chip track-and-hold (T/H)
structure to convert an analog signal to a serial 12-bit
digital output data stream.
This flexible serial interface provides easy interface to
microprocessors (µPs). Figure 2 shows a simplified
functional diagram of the internal architecture for both
the MAX144 (2 channels, single-ended) and the MAX145
(1 channel, pseudo-differential).
Analog Inputs: Single-Ended (MAX144)
and Pseudo-Differential (MAX145)
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit of
Figure 3. In single-ended mode (MAX144), both chan-
nels CH0 and CH1 are referred to GND and can be
connected to two different signal sources. Following the
power-on reset, the ADC is set to convert CH0. After
CH0 has been converted, CH1 will be converted and
the conversions will continue to alternate between
channels. Channel switching is performed by toggling
the CS/SHDN pin. Conversions can be performed on
the same channel by toggling CS/SHDN twice between
conversions. If only one channel is required, CH0 and
CH1 may be connected together; however, the output
data will still contain the channel identification bit
(before the MSB).
For the MAX145, the input channels form a single differ-
ential channel pair (CH+, CH-). This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side IN- must remain stable
within ±0.5LSB (±0.1LSB for optimum results) with
respect to GND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans from when CS/SHDN falls to
the falling edge of the second clock cycle (external
clock mode) or from when CS/SHDN falls to the first
falling edge of SCLK (internal clock mode). At the end
of the acquisition interval, the T/H switch opens, retain-
ing charge on CHOLD as a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLD from the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input.
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
_______________________________________________________________________________________ 7
6k CL
DOUT
a) HIGH-Z TO V0H, V0L TO V0H, AND VOH TO HIGH-Z
6k
CL
DOUT
GNDGND
VDD
b) HIGH-Z TO V0L, V0H TO V0L, AND VOL TO HIGH-Z
Figure 1. Load Circuits for Enable and Disable Time
MAX144
MAX145
12-BIT
SAR
ADC
SCLK
( ) ARE FOR MAX145
IN OUT
ANALOG
INPUT
MUX
(2 CHANNEL)
CH0
(CH+)
CH1
(CH-)
REF
T/H
CONTROL
LOGIC
SCLK
CS/SHDN
INTERNAL
CLOCK
OUTPUT
REGISTER DOUT
Figure 2. Simplified Functional Diagram
CH0
(CH+)
CH1
(CH-)
( ) ARE FOR MAX145
SINGLE-ENDED MODE: CH0, CH1 = IN+; GND = IN-
DIFFERENTIAL-ENDED MODE: CH+ = IN+; CH- = IN-
RIN
9kΩ
ZERO
REF
GND
TRACK HOLD
COMPARATOR
TO SAR
T/H
CHOLD
16pF
INPUT
MUX
12-BIT CAPACITIVE DAC
CSWITCH
CONTROL LOGIC
MAX144
MAX145
Figure 3. Analog Input Channel Structure
MAX144/MAX145
The capacitive digital-to-analog converter (DAC)
adjusts during the remainder of the conversion cycle
to restore node ZERO to 0V within the limits of 12-bit
resolution. This action is equivalent to transferring a
16pF ·[(VIN+) - (VIN-)] charge from CHOLD to the bina-
ry-weighted capacitive DAC, which in turn forms a digi-
tal representation of the analog input signal.
Track/Hold (T/H)
The ADC’s T/H stage enters its tracking mode on the
falling edge of CS/SHDN. For the MAX144 (single-
ended inputs), IN- is connected to GND and the con-
verter samples the positive (“+”) input. For the MAX145
(pseudo-differential inputs), IN- connects to the nega-
tive input (“-”) and the difference of [(VIN+) - (VIN-)] is
sampled. At the end of the conversion, the positive
input connects back to IN+ and CHOLD charges to the
input signal.
The time required for the T/H stage to acquire an input
signal is a function of how fast its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation: tACQ = 9(RS+ RIN)CIN
where RSis the source impedance of the input signal,
RIN (9kΩ) is the input resistance, and CIN (16pF) is the
input capacitance of the ADC. Source impedances
below 1kΩhave no significant impact on the AC perfor-
mance of the MAX144/MAX145.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
Input Bandwidth
The MAX144/MAX145 T/H stage offers a 2.25MHz
small-signal and a 1MHz full-power bandwidth, which
make it possible to use the parts for digitizing high-
speed transients and measuring periodic signals with
bandwidths exceeding the ADCs sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended. Most
aliasing problems can be fixed easily with an external
resistor and a capacitor. However, if DC precision is
required, it is usually best to choose a continuous or
switched-capacitor filter, such as the MAX7410/
MAX7414 (Figure 4). Their Butterworth characteristic
generally provides the best compromise (with regard to
rolloff and attenuation) in filter configurations, is easy to
design, and provides a maximally flat passband response.
Analog Input Protection
Internal protection diodes, which clamp the analog input
to VDD and GND, allow each input channel to swing
within GND - 300mV to VDD + 300mV without damage.
However, for accurate conversions, both inputs must not
exceed VDD + 50mV or be less than GND - 50mV.
If an off-channel analog input voltage exceeds the
supplies, limit the input current to 4mA.
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
8 _______________________________________________________________________________________
SHDN
OUT
2CLK
REF EXTERNAL
REFERENCE
CS/SHDN
DOUT
2
3
8µP/µC
MAX7410
MAX7414
CH0 VDD
VDD
VDD
GNDOS GNDCOM
0.01µF**
0.1µF
470Ω**
0.01µF
CH1
IN
fC = 15kHz
7
4
5
5
7
4
6
8
1
1
63
SCLK
MAX144
1.5MHz
OSCILLATOR
**USED TO ATTENUATE SWITCHED-CAPACITOR FILTER CLOCK NOISE
Figure 4. Analog Input with Anti-Aliasing Filter Structure
Selecting Clock Mode
To start the conversion process on the MAX144/
MAX145, pull CS/SHDN low. At CS/SHDN’s falling
edge, the part wakes up and the internal T/H enters
track mode. In addition, the state of SCLK at
CS/SHDN’s falling edge selects internal (SCLK = high)
or external (SCLK = low) clock mode.
Internal Clock (f
SCLK
< 100kHz or f
SCLK
> 2.17MHz)
In internal clock mode, the MAX144/MAX145 run from
an internal, laser-trimmed oscillator to within 20% of the
2MHz specified clock rate. This releases the system
microprocessor from running the SAR conversion clock
and allows the conversion results to be read back at
the processor’s convenience, at any clock rate from 0
to 5MHz. Operating the MAX144/MAX145 in internal
clock mode is necessary for serial interfaces operating
with clock frequencies lower than 100kHz or greater
than 2.17MHz. Select internal clock mode (Figure 5), by
holding SCLK high during a high/low transition of
CS/SHDN. The first SCLK falling edge samples the data
and initiates a conversion using the integrated on-chip
oscillator. After the conversion, the oscillator shuts off
and DOUT goes high, signaling the end of conversion
(EOC). Data can then be read out with SCLK.
External Clock (f
SCLK
= 100kHz to 2.17MHz)
The external clock mode (Figure 6) is selected by tran-
sitioning CS/SHDN from high to low while SCLK is low.
The external clock signal not only shifts data out, but
also drives the analog-to-digital conversion. The input
is sampled and conversion begins on the falling edge
of the second clock pulse. Conversion must be com-
pleted within 140µs to prevent degradation in the con-
version results caused by droop on the T/H capacitors.
External clock mode provides the best throughput for
clock frequencies between 100kHz and 2.17MHz.
Output Data Format
Table 1 illustrates the 16-bit, serial data stream output
format for both the MAX144 and MAX145. The first
three bits are always logic high (including the EOC bit
for internal clock mode), followed by the channel identi-
fication (CHID = 0 for CH0, CHID = 1 for CH1, CHID = 0
for the MAX145), and then 12 bits of data in MSB-first
format. After the last bit has been read out, additional
SCLK pulses will clock out trailing zeros. DOUT transi-
tions on the falling edge of SCLK. The output remains
high-impedance when CS/SHDN is high.
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
_______________________________________________________________________________________ 9
DOUT D9D10MSBCHID11EOC
SAMPLING INSTANT
HIGH-Z D8 D7 D6 D5 D4 D3 D2 D1 D0 HIGH-Z
SCLK 6789101112345 1213141516
tCONV
tWAKE
(tACQ)
tCS
POWER
DOWN
ACTIVE ACTIVE
CS/SHDN
Figure 5. Internal Clock Mode Timing
DOUT D9D10MSBCHID
SAMPLING INSTANT
HIGH-Z D8 D7 D6 D5 D4 D3 D2 D1 D0 HIGH-Z
SCLK 6789101112345 1213141516
tWAKE
(tACQ)
tCS
POWER
DOWN
ACTIVE POWER
DOWN
ACTIVEACTIVE
CS/SHDN
Figure 6. External Clock Mode Timing
MAX144/MAX145
External Reference
An external reference is required for both the MAX144
and the MAX145. At REF, the DC input resistance is a
minimum of 18kΩ. During a conversion, a reference
must be able to deliver 250µA of DC load current and
have an output impedance of 10Ωor less. Use a 0.1µF
bypass capacitor for best performance. The reference
input structure allows a voltage range of 0 to VDD +
50mV, although noise levels will decrease effective res-
olution at lower reference voltages.
Automatic Power-Down Mode
Whenever the MAX144/MAX145 are not selected
(CS/SHDN = VDD), the parts enter their shutdown
mode. In shutdown all internal circuitry turns off, reduc-
ing supply current to typically less than 0.2µA. With an
external reference stable to within 1LSB, the wake-up
time is 2.5µs. If the external reference is not stable with-
in 1LSB, the wake-up time must be increased to allow
the reference to stabilize.
__________Applications Information
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits): SNR(MAX) = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise which includes all
spectral components minus the fundamental, the first
five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to RMS equivalent of all other ADC out-
put signals:
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists only of quantization noise. With an
input range equal to the full-scale range of the ADC, the
effective number of bits can be calculated as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first five harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.
Connection to Standard Interfaces
The MAX144/MAX145 interface is fully compatible with
SPI, QSPI, and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s seri-
al interface as master so that the CPU generates the
serial clock for the MAX144/MAX145. Select a clock fre-
quency from 100kHz to 2.17MHz (external clock mode).
1) Use a general-purpose I/O line on the CPU to pull
CS/SHDN low while SCLK is low.
2) Wait for the minimum wake-up time (tWAKE) speci-
fied before activating SCLK.
3) Activate SCLK for a minimum of 16 clock cycles.
The serial data stream of three leading ones, the
channel identification, and the MSB of the digitized
input signal begin at the first falling clock edge.
DOUT transitions on SCLK’s falling edge and is
available in MSB-first format. Observe the SCLK to
THD = 20 x log V+V+V+V
V
22324252
1
SINAD(dB) = 20 x log (Noise + Distortion)
SIGNALRMS RMS
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
10 ______________________________________________________________________________________
Table 1. Serial Output Data Stream for Internal and External Clock Mode
SCLK CYCLE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DOUT (Internal Clock) EOC 1 1 CHID D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT (External Clock) 1 1 1 CHID D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT valid timing characteristic. Data should be
clocked into the µP on SCLK’s rising edge.
4) Pull CS/SHDN high at or after the 16th falling clock
edge. If CS/SHDN remains low, trailing zeros will be
clocked out after the LSB.
5) With CS/SHDN high, wait at least 60ns (tCS) before
starting a new conversion by pulling CS/SHDN low.
A conversion can be aborted by pulling CS/SHDN
high before the conversion ends; wait at least 60ns
before starting a new conversion.
Data can be output in two 8-bit sequences or continu-
ously. The bytes will contain the result of the conversion
padded with three leading ones and the channel identi-
fication before the MSB. If the serial clock hasn’t been
idled after the last LSB and CS/SHDN is kept low,
DOUT sends trailing zeros.
SPI and MICROWIRE Interface
When using SPI (Figure 8a) or MICROWIRE (Figure 8b)
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS/SHDN (Figure 8c).
Two consecutive 8-bit readings are necessary to obtain
the entire 12-bit result from the ADC. DOUT data transi-
tions on the serial clock’s falling edge and is clocked
into the µP on SCLK’s rising edge. The first 8-bit data
stream contains three leading ones, the channel identi-
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
______________________________________________________________________________________ 11
• • •
• • •
• • •
CS/SHDN
SCLK
DOUT
tCL
tDV
tCH
tSCLKS
HIGH-Z HIGH-Z
tCS
tDO tTR
Figure 7. Detailed Serial-Interface Timing Sequence
MAX144
MAX145
CS/SHDN
SCLK
DOUT
I/O
SK
SI
MICROWIRE
CS/SHDN
SCLK
DOUT
I/O
SCK
MISO VDD
SS
MAX144
MAX145
SPI
Figure 8a. SPI Connections 8b. MICROWIRE Connections
CHID D11 D10 D9 D8
1 2 3 4 5 6 7 8 9 10111213141516
D7 D6 D5 D4 D3 HIGH-Z
DOUT*
CS/SHDN
SCLK
1ST BYTE READ 2ND BYTE READ
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z MSB LSB
D2 D1 D0
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
MAX144/MAX145
fication, and the first four data bits starting with the
MSB. The second 8-bit data stream contains the
remaining bits, D7 through D0.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX144/MAX145 support a maxi-
mum fSCLK of 2.17MHz. The QSPI circuit in Figure 9a
can be programmed to perform a conversion on each
of the two channels for the MAX144. Figure 9b shows
the QSPI interface timing.
PIC16 with SSP Module and PIC17 Interface
The MAX144/MAX145 are compatible with a PIC16/
PIC17 controller (µC), using the synchronous serial-port
(SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
port control register (SSPCON) and synchronous serial-
port status register (SSPSTAT) to the bit patterns shown
in Tables 2 and 3.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be synchronously transmitted and received simulta-
neously. Two consecutive 8-bit readings (Figure 10b)
are necessary to obtain the entire 12-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µC on SCLK’s rising edge.
The first 8-bit data stream contains three leading ones,
the channel identification, and the first four data bits
starting with the MSB. The second 8-bit data stream
contains the remaining bits, D7 through D0.
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
12 ______________________________________________________________________________________
CHID D11 D10 D9 D8
1 2 3 4 5 6 7 8 9 10111213141516
D7 D6 D5 D4 D3 HIGH-Z
DOUT
CS/SHDN
SCLK
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z MSB LSB
D2 D1 D0
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
CS/SHDN
SCLK
DOUT
CS
SCK
MISO VDD
SS
QSPI
MAX144
MAX145
Figure 9a. QSPI Connections
Table 2. Detailed SSPCON Register Contents
CONTROL BIT MAX144/MAX145
SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL BIT7 X Write Collision Detection Bit
SSPOV BIT6 X Receive Overflow Detect Bit
CKP BIT4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM2 BIT2 0
SSPM1 BIT1 0
SSPM0 BIT0 1
SSPM3 BIT3 0 Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects
fCLK = fOSC / 16.
SSPEN BIT5 1 Synchronous Serial-Port Enable Bit.
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins.
X = Don’t care
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards
(PCBs). Wire-wrap configurations are not recommend-
ed, since the layout should ensure proper separation of
analog and digital traces. Run analog and digital lines
anti-parallel to each other, and don’t lay out digital sig-
nal paths underneath the ADC package. Use separate
analog and digital PCB ground sections with only one
star-point (Figure 11) connecting the two ground systems
(analog and digital). For lowest-noise operation, ensure
the ground return to the star ground’s power supply is
low impedance and as short as possible. Route digital
signals far away from sensitive analog and reference
inputs.
High-frequency noise in the power supply VDD could
influence the proper operation of the ADC’s fast com-
parator. Bypass VDD to the star ground with a network
of two parallel capacitors (0.1µF and 1µF) located as
close as possible to the power supply pin of MAX144/
MAX145. Minimize capacitor lead length for best sup-
ply-noise rejection and add an attenuation resistor
(10Ω) if the power supply is extremely noisy.
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
______________________________________________________________________________________ 13
CONTROL BIT MAX144/MAX145
SETTINGS SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SMP BIT7 0 SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
CKE BIT6 1 SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
D/A BIT5 X Data Address Bit
P BIT4 X Stop Bit
S BIT3 X Start Bit
R/W BIT2 X Read/Write Bit Information
UA BIT1 X Update Address
BF BIT0 X Buffer Full Status Bit
Table 3. Detailed SSPSTAT Register Contents
CHID D11 D10 D9 D8
1 2 3 4 5 6 7 8 9 10111213141516
D7 D6 D5 D4 D3 HIGH-Z
DOUT*
CS/SHDN
SCLK
1ST BYTE READ 2ND BYTE READ
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z MSB LSB
D2 D1 D0
Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3–SSPM0 = 0001)
SCK
SDI
GND GND
I/O
SCLK
DOUT
CS/SHDN
VDD VDD
MAX144
MAX145 PIC16/17
Figure 10a. SPI Interface Connection for a PIC16/PIC17
Controller
X = Don’t care
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
14 ______________________________________________________________________________________
+3V GND+3V
POWER SUPPLIES
DGND+3V
GNDVDD
DIGITAL
CIRCUITRY
R* = 10 W
1mF
0.1 mF
* OPTIONAL FILTER RESISTOR
MAX144
MAX145
PART TEMP
RANGE
PIN-
PACKAGE
INL
(LSB)
PKG
CODE
MAX145ACUA 0°C to
+70°C 8 µMAX ±0.5 U8-1
MAX145BCUA 0°C to
+70°C 8 µMAX ±1 U8-1
MAX145ACPA 0°C to
+70°C 8 Plastic DIP ±0.5 P8-1
MAX145BCPA 0°C to
+70°C 8 Plastic DIP ±1 P8-1
MAX145BC/D 0°C to
+70°C Dice* ±1 —
MAX145AEUA -40°C to
+85°C 8 µMAX ±0.5 U8-1
MAX145BEUA -40°C to
+85°C 8 µMAX ±1 U8-1
MAX145AEPA -40°C to
+85°C 8 Plastic DIP ±0.5 P8-1
MAX145BEPA -40°C to
+85°C 8 Plastic DIP ±1 P8-1
MAX145AMJA 55°C to
+125°C 8 CERDIP** ±0.5 J8-2
MAX145BMJA 55°C to
+125°C 8 CERDIP** ±1 J8-2
Figure 11. Power-Supply Bypassing and Grounding
Chip Information
TRANSISTOR COUNT: 2,058
SUBSTRATE CONNECTED TO GND
Ordering Information (continued)
*Dice are specified at TA= +25°C, DC parameters only.
**Contact factory for availability.
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
______________________________________________________________________________________ 15
8LUMAXD.EPS
________________________________________________________Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 _________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PDIPN.EPS