ADSP-21367BBP-2A - Analog Devices, Inc.

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SHARC Processor

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F Document Feedback

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SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—2M bits of on-chip SRAM and 6M bits of

on-chip mask programmable ROM

Code compatible with all other members of the SHARC family

The ADSP-21367/ADSP-21368/ADSP-21369 are available

with a 400 MHz core instruction rate with unique audiocen-

tric peripherals such as the digital applications interface,

S/PDIF transceiver, serial ports, 8-channel asynchronous

sample rate converter, precision clock generators, and

more. For complete ordering information, see Ordering

Guide on Page 61.

DEDICATED AUDIO COMPONENTS

S/PDIF-compatible digital audio receiver/transmitter

4 independent asynchronous sample rate converters (SRC)

16 PWM outputs configured as four groups of four outputs

ROM-based security features include

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Available in 256-ball BGA_ED and 208-lead LQFP_EP

packages

Figure 1. Functional Block Diagram

Internal Memory I/F

Block 0

RAM/ROM

B0D

64-BIT

Instruction

Cache

5 stage

Sequencer

PEx PEy

PMD

64-BIT IOD0 32-BIT

EPD BUS 32-BIT

Core Bus

Cross Bar

DAI Routing/Pins

S/PDIF

Tx/Rx

PCG

DPI Routing/Pins

SPI/B UART

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

AMI SDRAM

External Port Pin MUX

TIMER

SPORT

ASRC

PWM

DAG1/2 Timer

IDP/

PDAP

TWI

IOD0 BUS

MTM

PCG

PERIPHERAL BUS

32-BIT

CORE

FLAGS

FLAGx/IRQx/

TMREXP JTAG

Internal Memory

DMD

64-BIT

PMD 64-BIT

DMD 64-BIT

CORE

FLAGS

IOD1

32-BIT

PERIPHERAL BUS

B1D

64-BIT

B2D

64-BIT

B3D

64-BIT

DPI Peripherals DAI Peripherals Peripherals External

Port

SIMD Core

Rev. F | Page 2 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

TABLE OF CONTENTS

Summary ............................................................... 1

Dedicated Audio Components ................................. 1

General Description ................................................. 3

SHARC Family Core Architecture ............................ 4

Family Peripheral Architecture ................................ 7

I/O Processor Features ......................................... 10

System Design .................................................... 10

Development Tools ............................................. 11

Additional Information ........................................ 12

Related Signal Chains .......................................... 12

Pin Function Descriptions ....................................... 13

Specifications ........................................................ 16

Operating Conditions .......................................... 16

Electrical Characteristics ....................................... 17

Package Information ........................................... 18

ESD Caution ...................................................... 18

Maximum Power Dissipation ................................. 18

Absolute Maximum Ratings ................................... 18

Timing Specifications ........................................... 18

Output Drive Currents ......................................... 51

Test Conditions .................................................. 51

Capacitive Loading .............................................. 51

Thermal Characteristics ........................................ 53

256-Ball BGA_ED Pinout ......................................... 54

208-Lead LQFP_EP Pinout ....................................... 57

Package Dimensions ............................................... 59

Surface-Mount Design .......................................... 60

Automotive Products .............................................. 61

Ordering Guide ..................................................... 61

REVISION HISTORY

10/13—Rev. E to Rev. F

Updated Development Tools .....................................11

Added Related Signal Chains .....................................12

Corrected EMU pin type from O/T(pu) to O(O/D, pu) in

Pin Function Descriptions ........................................13

Corrected Junction Temperature 256-Ball BGA Min Value at

ambient temperature (–40°C to +85C) from 0 to –40 in

Operating Conditions ..............................................16

Added 400 MHz Min and Max values for Junction Temperature

208-Lead LQFP_EP at ambient temperature 0°C to +70C in

Operating Conditions ..............................................16

Added footnote 2 to Table 24 in Memory Read ..............30

Changed Max values in Table 34 in Pulse-Width Modulation

Generators ............................................................41

Updated timing parameters in Table 40 and in Figure 36 in

SPI Interface—Master ..............................................48

Updated Figure 37 in SPI Interface—Slave ....................49

Changes to Ordering Guide .......................................61

To view product/process change notifications (PCNs) related to

this data sheet revision, please visit the processor’s product page

on the www.analog.com website and use the View PCN link.

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 3 of 64 | October 2013

GENERAL DESCRIPTION

The ADSP-21367/ADSP-21368/ADSP-21369 SHARC

proces-

sors are members of the SIMD SHARC family of DSPs that

feature Analog Devices’ Super Harvard Architecture. These pro-

cessors are source code-compatible with the ADSP-2126x and

ADSP-2116x DSPs as well as with first generation ADSP-2106x

SHARC processors in SISD (single-instruction, single-data)

mode. The processors are 32-bit/40-bit floating-point proces-

sors optimized for high performance automotive audio

applications with its large on-chip SRAM, mask programmable

ROM, multiple internal buses to eliminate I/O bottlenecks, and

an innovative digital applications interface (DAI).

As shown in the functional block diagram on Page 1, the

processors use two computational units to deliver a significant

performance increase over the previous SHARC processors on a

range of DSP algorithms. Fabricated in a state-of-the-art, high

speed, CMOS process, the ADSP-21367/ADSP-21368/

ADSP-21369 processors achieve an instruction cycle time of up

to 2.5 ns at 400 MHz. With its SIMD computational hardware,

the processors can perform 2.4 GFLOPS running at 400 MHz.

Table 1 shows performance benchmarks for these devices.

The diagram on Page 1 shows the two clock domains that make

up the ADSP-21367/ADSP-21368/ADSP-21369 processors. The

core clock domain contains the following features.

• Two processing elements (PEx, PEy), each of which com-

prises an ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting 2x64-bit data

transfers between memory and the core at every core pro-

cessor cycle

• One periodic interval timer with pinout

•On-chip SRAM (2M bit)

•On-chip mask-programmable ROM (6M bit)

• JTAG test access port for emulation and boundary scan.

The JTAG provides software debug through user break-

points which allows flexible exception handling.

Table 1. Processor Benchmarks (at 400 MHz)

Benchmark Algorithm

Speed

(at 400 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 23.2 s

FIR Filter (per tap)

Assumes two files in multichannel SIMD mode.

1.25 ns

IIR Filter (per biquad)

5.0 ns

Matrix Multiply (pipelined)

[3×3] × [3×1]

[4×4] × [4×1]

11.25 ns

20.0 ns

Divide (y/x) 8.75 ns

Inverse Square Root 13.5 ns

Table 2. ADSP-2136x Family Features

Feature

ADSP-21367

ADSP-21368

ADSP-21369/

ADSP-21369W

Frequency 400 MHz

RAM 2M bits

ROM

6M bits

Audio Decoders in ROM Yes

Pulse-Width Modulation Yes

S/PDIF Yes

SDRAM Memory Bus Width 32/16 bits

Serial Ports 8

IDP Yes

DAI Yes

UART 2

DAI Yes

DPI Yes

S/PDIF Transceiver 1

AMI Interface Bus Width 32/16/8 bits

SPI 2

TWI Yes

SRC Performance 128 dB

Package 256 Ball-

BGA,

208-Lead

LQFP_EP

256 Ball-

BGA

256 Ball-

BGA,

208-Lead

LQFP_EP

W = Automotive grade product. See Automotive Products on Page 61 for more

information.

Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,

DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass

management, delay, speaker equalization, graphic equalization, and more.

Decoder/post-processor algorithm combination support varies depending upon

the chip version and the system configurations. Please visit www.analog.com for

complete information.

Table 2. ADSP-2136x Family Features

(Continued)

Feature

ADSP-21367

ADSP-21368

ADSP-21369/

ADSP-21369W

Rev. F | Page 4 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

The block diagram of the ADSP-21368 on Page 1 also shows the

peripheral clock domain (also known as the I/O processor) and

contains the following features:

•IOD0 (peripheral DMA) and IOD1 (external port DMA)

buses for 32-bit data transfers

• Peripheral and external port buses for core connection

• External port with an AMI and SDRAM controller

•4 units for PWM control

• 1 MTM unit for internal-to-internal memory transfers

• Digital applications interface that includes four precision

clock generators (PCG), a input data port (IDP) for serial

and parallel interconnect, an S/PDIF receiver/transmitter,

four asynchronous sample rate converters, eight serial

ports, a flexible signal routing unit (DAI SRU).

• Digital peripheral interface that includes three timers, a 2-

wire interface, two UARTs, two serial peripheral interfaces

(SPI), 2 precision clock generators (PCG) and a flexible sig-

nal routing unit (DPI SRU).

SHARC FAMILY CORE ARCHITECTURE

The ADSP-21367/ADSP-21368/ADSP-21369 are code compati-

ble at the assembly level with the ADSP-2126x, ADSP-21160,

and ADSP-21161, and with the first generation ADSP-2106x

SHARC processors. The ADSP-21367/ADSP-21368/

ADSP-21369 processors share architectural features with the

ADSP-2126x and ADSP-2116x SIMD SHARC processors, as

shown in Figure 2 and detailed in the following sections.

Figure 2. SHARC Core Block Diagram

SIMD Core CACHEINTERRUPT

5 STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

DM ADDRESS 32

DM DATA 64

PM DATA 64

DAG1

16x32

MRF

80-BIT

ALU

MULTIPLIER SHIFTER

Rx/Fx

PEx

16x40-BIT

JTAG

DMD/PMD 64

PM DATA 48

ASTATx

STYKx

ASTATy

STYKy

TIMER

Sx/SFx

PEy

16x40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

FLAG

SYSTEM

I/F

USTAT

4x32-BIT

64-BIT

DAG2

16x32

ALU MULTIPLIER

SHIFTER

DATA

SWAP

PM ADDRESS 24

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 5 of 64 | October 2013

SIMD Computational Engine

The processors contain two computational processing elements

that operate as a single-instruction, multiple-data (SIMD)

engine. The processing elements are referred to as PEX and PEY

and each contains an ALU, multiplier, shifter, and register file.

PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive DSP

algorithms.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing

elements. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each pro-

cessing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

vard architecture, allow unconstrained data flow between

computation units and internal memory. The registers in PEX

are referred to as R0–R15 and in PEY as S0–S15.

Context Switch

Many of the processor’s registers have secondary registers that

can be activated during interrupt servicing for a fast context

switch. The data registers in the register file, the DAG registers,

and the multiplier result registers all have secondary registers.

The primary registers are active at reset, while the secondary

registers are activated by control bits in a mode control register.

Universal Registers

These registers can be used for general-purpose tasks. The

USTAT (4) registers allow easy bit manipulations (Set, Clear,

Toggle, Test, XOR) for all system registers (control/status) of

the core.

The data bus exchange register (PX) permits data to be passed

between the 64-bit PM data bus and the 64-bit DM data bus, or

between the 40-bit register file and the PM data bus. These reg-

isters contain hardware to handle the data width difference.

Timer

A core timer that can generate periodic software Interrupts. The

core timer can be configured to use FLAG3 as a timer expired

signal.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21367/ADSP-21368/ADSP-21369 feature an

enhanced Harvard architecture in which the data memory

(DM) bus transfers data and the program memory (PM) bus

transfers both instructions and data (see Figure 2 on Page 4).

With separate program and data memory buses and on-chip

instruction cache, the processors can simultaneously fetch four

operands (two over each data bus) and one instruction (from

the cache), all in a single cycle.

Instruction Cache

The processors include an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Data Address Generators with Zero-Overhead Hardware

Circular Buffer Support

The ADSP-21367/ADSP-21368/ADSP-21369 have two data

address generators (DAGs). The DAGs are used for indirect

addressing and implementing circular data buffers in hardware.

Circular buffers allow efficient programming of delay lines and

other data structures required in digital signal processing, and

are commonly used in digital filters and Fourier transforms.

The two DAGs contain sufficient registers to allow the creation

of up to 32 circular buffers (16 primary register sets, 16 second-

ary). The DAGs automatically handle address pointer

wraparound, reduce overhead, increase performance, and sim-

plify implementation. Circular buffers can start and end at any

memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations for concise programming. For example, the

ADSP-21367/ADSP-21368/ADSP-21369 can conditionally exe-

cute a multiply, an add, and a subtract in both processing

elements while branching and fetching up to four 32-bit values

from memory—all in a single instruction.

On-Chip Memory

The processors contain two megabits of internal RAM and six

megabits of internal mask-programmable ROM. Each block can

be configured for different combinations of code and data stor-

age (see Table 3 on Page 6). Each memory block supports

single-cycle, independent accesses by the core processor and I/O

Rev. F | Page 6 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

processor. The memory architecture, in combination with its

separate on-chip buses, allows two data transfers from the core

and one from the I/O processor, in a single cycle.

The SRAM can be configured as a maximum of 64k words of

32-bit data, 128k words of 16-bit data, 42k words of 48-bit

instructions (or 40-bit data), or combinations of different word

sizes up to two megabits. All of the memory can be accessed as

16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point

storage format is supported that effectively doubles the amount

of data that can be stored on-chip. Conversion between the

32-bit floating-point and 16-bit floating-point formats is per-

formed in a single instruction. While each memory block can

store combinations of code and data, accesses are most efficient

when one block stores data using the DM bus for transfers, and

the other block stores instructions and data using the PM bus

for transfers.

Using the DM bus and PM buses, with one bus dedicated to

each memory block, assures single-cycle execution with two

data transfers. In this case, the instruction must be available in

the cache.

On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks (assuming

there are no block conflicts). The total bandwidth is realized

using the DMD and PMD buses (2x64-bits, core CLK) and the

IOD0/1 buses (2x32-bit, PCLK).

ROM-Based Security

The ADSP-21367/ADSP-21368/ADSP-21369 have a ROM secu-

rity feature that provides hardware support for securing user

software code by preventing unauthorized reading from the

internal code when enabled. When using this feature, the pro-

cessor does not boot-load any external code, executing

exclusively from internal ROM. Additionally, the processor is

not freely accessible via the JTAG port. Instead, a unique 64-bit

key, which must be scanned in through the JTAG or test access

port will be assigned to each customer. The device will ignore a

wrong key. Emulation features and external boot modes are

only available after the correct key is scanned.

Table 3. Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Long Word (64 Bits)

Extended Precision Normal or

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 BFFF

Block 0 ROM (Reserved)

0x0008 0000–0x0008 FFFF

Block 0 ROM (Reserved)

0x0008 0000–0x0009 7FFF

Block 0 ROM (Reserved)

0x0010 0000–0x0012 FFFF

Reserved

0x0004 F000–0x0004 FFFF

Reserved

0x0009 4000–0x0009 FFFF

Reserved

0x0009 E000–0x0009 FFFF

Reserved

0x0013 C000–0x0013 FFFF

Block 0 SRAM

0x0004 C000–0x0004 EFFF

Block 0 SRAM

0x0009 0000–0x0009 3FFF

Block 0 SRAM

0x0009 8000–0x0009 DFFF

Block 0 SRAM

0x0013 0000–0x0013 BFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 BFFF

Block 1 ROM (Reserved)

0x000A 0000–0x000A FFFF

Block 1 ROM (Reserved)

0x000A 0000–0x000B 7FFF

Block 1 ROM (Reserved)

0x0014 0000–0x0016 FFFF

Reserved

0x0005 F000–0x0005 FFFF

Reserved

0x000B 4000–0x000B FFFF

Reserved

0x000B E000–0x000B FFFF

Reserved

0x0017 C000–0x0017 FFFF

Block 1 SRAM

0x0005 C000–0x0005 EFFF

Block 1 SRAM

0x000B 0000–0x000B 3FFF

Block 1 SRAM

0x000B 8000–0x000B DFFF

Block 1 SRAM

0x0017 0000–0x0017 BFFF

Block 2 SRAM

0x0006 0000–0x0006 0FFF

Block 2 SRAM

0x000C 0000–0x000C 1554

Block 2 SRAM

0x000C 0000–0x000C 1FFF

Block 2 SRAM

0x0018 0000–0x0018 3FFF

Reserved

0x0006 1000– 0x0006 FFFF

Reserved

0x000C 1555–0x000C 3FFF

Reserved

0x000C 2000–0x000D FFFF

Reserved

0x0018 4000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 0FFF

Block 3 SRAM

0x000E 0000–0x000E 1554

Block 3 SRAM

0x000E 0000–0x000E 1FFF

Block 3 SRAM

0x001C 0000–0x001C 3FFF

Reserved

0x0007 1000–0x0007 FFFF

Reserved

0x000E 1555–0x000F FFFF

Reserved

0x000E 2000–0x000F FFFF

Reserved

0x001C 4000–0x001F FFFF

The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details.

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 7 of 64 | October 2013

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-21367/ADSP-21368/ADSP-21369 family contains a

rich set of peripherals that support a wide variety of applications

including high quality audio, medical imaging, communica-

tions, military, test equipment, 3D graphics, speech recognition,

motor control, imaging, and other applications.

External Port

The external port interface supports access to the external mem-

ory through core and DMA accesses. The external memory

address space is divided into four banks. Any bank can be pro-

grammed as either asynchronous or synchronous memory. The

external ports of the ADSP-21367/8/9 processors are comprised

of the following modules.

• An Asynchronous Memory Interface which communicates

with SRAM, FLASH, and other devices that meet the stan-

dard asynchronous SRAM access protocol. The AMI

supports 14M words of external memory in bank 0 and

16M words of external memory in bank 1, bank 2, and

bank 3.

• An SDRAM controller that supports a glueless interface

with any of the standard SDRAMs. The SDC supports 62M

words of external memory in bank 0, and 64M words of

external memory in bank 1, bank 2, and bank 3.

• Arbitration Logic to coordinate core and DMA transfers

between internal and external memory over the external

port.

• A Shared Memory Interface that allows the connection of

up to four ADSP-21368 processors to create shared exter-

nal bus systems (ADSP-21368 only).

SDRAM Controller

The SDRAM controller provides an interface of up to four sepa-

rate banks of industry-standard SDRAM devices or DIMMs, at

speeds up to f

SCLK

. Fully compliant with the SDRAM standard,

each bank has its own memory select line (MS0–MS3), and can

be configured to contain between 16M bytes and 128M bytes of

memory. SDRAM external memory address space is shown in

Table 4.

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. The

memory banks can be configured as either 32 bits wide for max-

imum performance and bandwidth or 16 bits wide for

minimum device count and lower system cost.

The SDRAM controller address, data, clock, and control pins

can drive loads up to distributed 30 pF loads. For larger memory

systems, the SDRAM controller external buffer timing should

be selected and external buffering should be provided so that the

load on the SDRAM controller pins does not exceed 30 pF.

External Memory

The external port provides a high performance, glueless inter-

face to a wide variety of industry-standard memory devices. The

32-bit wide bus can be used to interface to synchronous and/or

asynchronous memory devices through the use of its separate

internal memory controllers. The first is an SDRAM controller

for connection of industry-standard synchronous DRAM

devices and DIMMs (dual inline memory module), while the

second is an asynchronous memory controller intended to

interface to a variety of memory devices. Four memory select

pins enable up to four separate devices to coexist, supporting

any desired combination of synchronous and asynchronous

device types. Non-SDRAM external memory address space is

shown in Table 5.

Shared External Memory

The ADSP-21368 processor supports connecting to common

shared external memory with other ADSP-21368 processors to

create shared external bus processor systems. This support

includes:

• Distributed, on-chip arbitration for the shared external bus

• Fixed and rotating priority bus arbitration

• Bus time-out logic

• Bus lock

Multiple processors can share the external bus with no addi-

tional arbitration logic. Arbitration logic is included on-chip to

allow the connection of up to four processors.

Bus arbitration is accomplished through the BR1–4 signals and

the priority scheme for bus arbitration is determined by the set-

ting of the RPBA pin. Table 8 on Page 13 provides descriptions

of the pins used in multiprocessor systems.

External Port Throughput

The throughput for the external port, based on 166 MHz clock

and 32-bit data bus, is 221M bytes/s for the AMI and 664M

bytes/s for SDRAM.

Table 4. External Memory for SDRAM Addresses

Bank

Size in

Words Address Range

Bank 0 62M 0x0020 0000–0x03FF FFFF

Bank 1 64M 0x0400 0000–0x07FF FFFF

Bank 2 64M 0x0800 0000–0x0BFF FFFF

Bank 3 64M 0x0C00 0000–0x0FFF FFFF

Table 5. External Memory for Non-SDRAM Addresses

Bank

Size in

Words Address Range

Bank 0 14M 0x0020 0000–0x00FF FFFF

Bank 1 16M 0x0400 0000–0x04FF FFFF

Bank 2 16M 0x0800 0000–0x08FF FFFF

Bank 3 16M 0x0C00 0000–0x0CFF FFFF

Rev. F | Page 8 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Asynchronous Memory Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, ROM, flash, and EPROM,

as well as I/O devices that interface with standard memory

control lines. Bank 0 occupies a 14M word window and Banks 1,

2, and 3 occupy a 16M word window in the processor’s address

space but, if not fully populated, these windows are not made

contiguous by the memory controller logic. The banks can also

be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of

interfacing to a range of memories and I/O devices tailored

either to high performance or to low cost and power.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode,

the duty cycle values are programmable only once per PWM

period. This results in PWM patterns that are symmetrical

about the midpoint of the PWM period. In double update

mode, a second updating of the PWM registers is implemented

at the midpoint of the PWM period. In this mode, it is possible

to produce asymmetrical PWM patterns that produce lower

harmonic distortion in 2-phase PWM inverters.

Digital Applications Interface (DAI)

The digital applications interface (DAI ) provide the ability to

connect various peripherals to any of the DSP’s DAI pins

(DAI_P20–1). Programs make these connections using the sig-

nal routing unit (SRU1), shown in Figure 1.

The SRU is amatrix routing unit (or group of multiplexers) that

enable the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

The DAI include eight serial ports, an S/PDIF receiver/trans-

mitter, four precision clock generators (PCG), eight channels of

synchronous sample rate converters, and an input data port

(IDP). The IDP provides an additional input path to the

processor core, configurable as either eight channels of I

S serial

data or as seven channels plus a single 20-bit wide synchronous

parallel data acquisition port. Each data channel has its own

DMA channel that is independent from the processor’s serial

ports.

For complete information on using the DAI, see the

ADSP-21368 SHARC Processor Hardware Reference.

Serial Ports

The processors feature eight synchronous serial ports (SPORTs)

that provide an inexpensive interface to a wide variety of digital

and mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

Serial ports are enabled via 16 programmable and simultaneous

receive or transmit pins that support up to 32 transmit or 32

receive channels of audio data when all eight SPORTs are

enabled, or eight full duplex TDM streams of 128 channels

per frame.

The serial ports operate at a maximum data rate of 50 Mbps.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode with support for packed I

mode

•I

S mode

•Packed I

S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Each of the serial ports supports the left-justified sample pair

and I

S protocols (I

S is an industry-standard interface com-

monly used by audio codecs, ADCs, and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pair or I

S channels (using two stereo

devices) per serial port, with a maximum of up to 32 I

S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I

S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional -law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 9 of 64 | October 2013

The serial ports also contain frame sync error detection logic

where the serial ports detect frame syncs that arrive early (for

example, frame syncs that arrive while the transmission/recep-

tion of the previous word is occurring). All the serial ports also

share one dedicated error interrupt.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the

receiver/transmitter can be formatted as left-justified, I

S, or

right-justified with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources such as the

SPORTs, external pins, the precision clock generators (PCGs),

or the sample rate converters (SRC) and are controlled by the

SRU control registers.

Synchronous/Asynchronous Sample Rate Converter

The sample rate converter (SRC) contains four SRC blocks and

is the same core as that used in the AD1896 192 kHz stereo

asynchronous sample rate converter and provides up to 128 dB

SNR. The SRC block is used to perform synchronous or asyn-

chronous sample rate conversion across independent stereo

channels, without using internal processor resources. The four

SRC blocks can also be configured to operate together to con-

vert multichannel audio data without phase mismatches.

Finally, the SRC can be used to clean up audio data from jittery

clock sources such as the S/PDIF receiver.

Input Data Port

The IDP provides up to eight serial input channels—each with

its own clock, frame sync, and data inputs. The eight channels

are automatically multiplexed into a single 32-bit by eight-deep

FIFO. Data is always formatted as a 64-bit frame and divided

into two 32-bit words. The serial protocol is designed to receive

audio channels in I2S, left-justified sample pair, or right-justi-

fied mode. One frame sync cycle indicates one 64-bit left/right

pair, but data is sent to the FIFO as 32-bit words (that is, one-

half of a frame at a time). The processor supports 24- and 32-bit

S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit

right-justified formats.

Precision Clock Generators

The precision clock generators (PCG) consist of four units, each

of which generates a pair of signals (clock and frame sync)

derived from a clock input signal. The units, A B, C, and D, are

identical in functionality and operate independently of each

other. The two signals generated by each unit are normally used

as a serial bit clock/frame sync pair.

Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two

serial peripheral interface ports (SPI), two universal asynchro-

nous receiver-transmitters (UARTs), a 2-wire interface (TWI),

12 flags, and three general-purpose timers.

Serial Peripheral (Compatible) Interface

The processors contain two serial peripheral interface ports

(SPIs). The SPI is an industry-standard synchronous serial link,

enabling the SPI-compatible port to communicate with other

SPI-compatible devices. The SPI consists of two data pins, one

device select pin, and one clock pin. It is a full-duplex

synchronous serial interface, supporting both master and slave

modes. The SPI port can operate in a multimaster environment

by interfacing with up to four other SPI-compatible devices,

either acting as a master or slave device. The ADSP-21367/

ADSP-21368/ADSP-21369 SPI-compatible peripheral imple-

mentation also features programmable baud rate and clock

phase and polarities. The SPI-compatible port uses open-drain

drivers to support a multimaster configuration and to avoid

data contention.

UART Port

The processors provide a full-duplex universal asynchronous

receiver/transmitter (UART) port, which is fully compatible

with PC-standard UARTs. The UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. The UART also has multiprocessor communication capa-

bility using 9-bit address detection. This allows it to be used in

multidrop networks through the RS-485 data interface

standard. The UART port also includes support for five data bits

to eight data bits, one stop bit or two stop bits, and none, even,

or odd parity. The UART port supports two modes of

operation:

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The UART port’s baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f

SCLK

/1,048,576) to

SCLK

/16) bits per second.

• Supporting data formats from 7 bits to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

Where the 16-bit UART_Divisor comes from the DLH register

(most significant eight bits) and DLL register (least significant

eight bits).

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

Rev. F | Page 10 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Peripheral Timers

Three general-purpose timers can generate periodic interrupts

and be independently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

Each general-purpose timer has one bidirectional pin and four

registers that implement its mode of operation: a 6-bit configu-

ration register, a 32-bit count register, a 32-bit period register,

and a 32-bit pulse width register. A single control and status

independently.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire serial bus used to move 8-bit

data while maintaining compliance with the I

C bus protocol.

The TWI master incorporates the following features:

• Simultaneous master and slave operation on multiple

device systems with support for multimaster data

arbitration

• Digital filtering and timed event processing

• 7-bit and 10-bit addressing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

I/O PROCESSOR FEATURES

The I/O processor provides many channels of DMA, and con-

trols the extensive set of peripherals described in the previous

sections.

DMA Controller

The processor’s on-chip DMA controller allows data transfers

without processor intervention. The DMA controller operates

independently and invisibly to the processor core, allowing

DMA operations to occur while the core is simultaneously exe-

cuting its program instructions. DMA transfers can occur

between the processor’s internal memory and its serial ports, the

SPI-compatible (serial peripheral interface) ports, the IDP

(input data port), the parallel data acquisition port (PDAP), or

the UART.

Thirty four channels of DMA are available on the ADSP-2136x

processors as shown in Table 6.

Delay Line DMA

The ADSP-21367/ADSP-21368/ADSP-21369 processors pro-

vide delay line DMA functionality. This allows processor reads

and writes to external delay line buffers (in external memory,

SRAM, or SDRAM) with limited core interaction.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues.

Program Booting

The internal memory of the processors can be booted up at sys-

tem power-up from an 8-bit EPROM via the external port, an

SPI master or slave, or an internal boot. Booting is determined

by the boot configuration (BOOT_CFG1–0) pins (see Table 7

and the processor hardware reference). Selection of the boot

source is controlled via the SPI as either a master or slave device,

or it can immediately begin executing from ROM.

Power Supplies

The processors have separate power supply connections for the

internal (V

DDINT

), external (V

DDEXT

), and analog (A

VDD

VSS

) power

supplies. The internal and analog supplies must meet the 1.3 V

requirement for the 400 MHz device and 1.2 V for the

333 MHz and 266 MHz devices. The external supply must meet

the 3.3 V requirement. All external supply pins must be con-

nected to the same power supply.

Note that the analog supply pin (A

VDD

) powers the processor’s

internal clock generator PLL. To produce a stable clock, it is rec-

ommended that PCB designs use an external filter circuit for the

VDD

pin. Place the filter components as close as possible to the

VDD

VSS

pins. For an example circuit, see Figure 3. (A recom-

mended ferrite chip is the muRata BLM18AG102SN1D). To

reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V

DDINT

and GND. Use wide traces

to connect the bypass capacitors to the analog power (A

VDD

) and

ground (A

VSS

) pins. Note that the A

VDD

and A

VSS

pins specified in

Figure 3 are inputs to the processor and not the analog ground

plane on the board—the A

VSS

pin should connect directly to dig-

ital ground (GND) at the chip.

Table 6. DMA Channels

Peripheral DMA Channels

SPORTs 16

PDAP 8

SPI 2

UART 4

External Port 2

Memory-to-Memory 2

Table 7. Boot Mode Selection

BOOT_CFG1–0 Booting Mode

00 SPI Slave Boot

01 SPI Master Boot

10 EPROM/FLASH Boot

11 No boot (processor executes from

internal ROM after reset)

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 11 of 64 | October 2013

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21367/

ADSP-21368/ADSP-21369 processors to monitor and control

the target board processor during emulation. Analog Devices

DSP Tools product line of JTAG emulators provides emulation

at full processor speed, allowing inspection and modification of

memory, registers, and processor stacks. The processor’s JTAG

interface ensures that the emulator will not affect target system

loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User’s Guide.”

DEVELOPMENT TOOLS

Analog Devices supports its processors with a complete line of

software and hardware development tools, including integrated

development environments (which include CrossCore

Embed-

ded Studio and/or VisualDSP++

), evaluation products,

emulators, and a wide variety of software add-ins.

Integrated Development Environments (IDEs)

For C/C++ software writing and editing, code generation, and

debug support, Analog Devices offers two IDEs.

The newest IDE, CrossCore Embedded Studio, is based on the

Eclipse

framework. Supporting most Analog Devices proces-

sor families, it is the IDE of choice for future processors,

including multicore devices. CrossCore Embedded Studio

seamlessly integrates available software add-ins to support real

time operating systems, file systems, TCP/IP stacks, USB stacks,

algorithmic software modules, and evaluation hardware board

support packages. For more information visit

www.analog.com/cces.

The other Analog Devices IDE, VisualDSP++, supports proces-

sor families introduced prior to the release of CrossCore

Embedded Studio. This IDE includes the Analog Devices VDK

real time operating system and an open source TCP/IP stack.

For more information visit www.analog.com/visualdsp. Note

that VisualDSP++ will not support future Analog Devices

processors.

EZ-KIT Lite Evaluation Board

For processor evaluation, Analog Devices provides wide range

of EZ-KIT Lite

evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Also available are various EZ-Extenders

, which are

daughter cards delivering additional specialized functionality,

including audio and video processing. For more information

visit www.analog.com and search on “ezkit” or “ezextender”.

EZ-KIT Lite Evaluation Kits

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE(s), a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user’s PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit. This permits

the customer to download, execute, and debug programs for the

EZ-KIT Lite system. It also supports in-circuit programming of

the on-board Flash device to store user-specific boot code,

enabling standalone operation. With the full version of Cross-

Core Embedded Studio or VisualDSP++ installed (sold

separately), engineers can develop software for supported EZ-

KITs or any custom system utilizing supported Analog Devices

processors.

Software Add-Ins for CrossCore Embedded Studio

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend its capabilities

and reduce development time. Add-ins include board support

packages for evaluation hardware, various middleware pack-

ages, and algorithmic modules. Documentation, help,

configuration dialogs, and coding examples present in these

add-ins are viewable through the CrossCore Embedded Studio

IDE once the add-in is installed.

Board Support Packages for Evaluation Hardware

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

Board Support Packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

located on the web page for the associated EZ-KIT or EZ-

Extender product. The link is found in the Product Download

area of the product web page.

Figure 3. Analog Power (A

VDD

) Filter Circuit

HI-Z FERRITE

BEAD CHIP

LOCATE ALL COMPONENTS

CLOSETOA

VDD AND AVSS PINS

AVDD

AVSS

100nF 10nF 1nF ADSP-213xx

VDDINT

Rev. F | Page 12 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Middleware Packages

Analog Devices separately offers middleware add-ins such as

real time operating systems, file systems, USB stacks, and

TCP/IP stacks. For more information see the following web

pages:

•www.analog.com/ucos3

•www.analog.com/ucfs

•www.analog.com/ucusbd

•www.analog.com/lwip

Algorithmic Modules

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with both CrossCore Embedded Studio and

VisualDSP++. For more information visit www.analog.com and

search on “Blackfin software modules” or “SHARC software

modules”.

Designing an Emulator-Compatible DSP Board (Target)

For embedded system test and debug, Analog Devices provides

a family of emulators. On each JTAG DSP, Analog Devices sup-

plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit

emulation is facilitated by use of this JTAG interface. The emu-

lator accesses the processor’s internal features via the

processor’s TAP, allowing the developer to load code, set break-

points, and view variables, memory, and registers. The

processor must be halted to send data and commands, but once

an operation is completed by the emulator, the DSP system is set

to run at full speed with no impact on system timing. The emu-

lators require the target board to include a header that supports

connection of the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the Engineer-to-Engineer

Note “Analog Devices JTAG Emulation Technical Reference”

(EE-68) on the Analog Devices website (www.analog.com)—use

site search on “EE-68.” This document is updated regularly to

keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the

ADSP-21367/ADSP-21368/ADSP-21369 architecture and func-

tionality. For detailed information on the ADSP-2136x family

core architecture and instruction set, refer to the ADSP-21368

SHARC Processor Hardware Reference and the SHARC Processor

Programming Reference.

RELATED SIGNAL CHAINS

A signal chain is a series of signal conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

The Circuits from the Lab

site (www.analog.com/signal

chains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 13 of 64 | October 2013

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 8:

A = asynchronous, G = ground, I = input, O = output,

O/T = output three-state, P = power supply, S = synchronous,

(A/D) = active drive, (O/D) = open-drain, (pd) = pull-down

resistor, (pu) = pull-up resistor.

The ADSP-21367/ADSP-21368/ADSP-21369 SHARC proces-

sors use extensive pin multiplexing to achieve a lower pin count.

For complete information on the multiplexing scheme, see the

ADSP-21368 SHARC Processor Hardware Reference, “System

Design” chapter.

Table 8. Pin Descriptions

Name Type

State During/

After Reset

(ID = 00x) Description

ADDR

23–0

O/T (pu)

Pulled high/

driven low

External Address.

The processors output addresses for external memory and peripher-

als on these pins.

DATA

31–0

I/O (pu)

Pulled high/

pulled high

External Data.

Data pins can be multiplexed to support external memory interface data

(I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins are in EMIF mode

and FLAG(0-3) pins are in FLAGS mode (default). When configured using the IDP_P-

DAP_CTL register, IDP Channel 0 scans the external port data pins for parallel input data.

ACK I (pu)

Memory Acknowledge.

External devices can deassert ACK (low) to add wait states to an

external memory access. ACK is used by I/O devices, memory controllers, or other periph-

erals to hold off completion of an external memory access.

0–1

O/T (pu)

Pulled high/

driven high

Memory Select Lines 0–1.

These lines are asserted (low) as chip selects for the corre-

sponding banks of external memory. The MS

3-0

lines are decoded memory address lines

th at c hang e at the s ame tim e as the oth er ad dres s li nes. When no e xte rna l me mor y a cces s

is occurring, the MS

3-0

lines are inactive; they are active, however, when a conditional

memory access instruction is executed, whether or not the condition is true.

The MS

pin can be used in EPORT/FLASH boot mode. See the processor hardware

reference for more information.

RD O/T (pu)

Pulled high/

driven high

External Port Read Enable.

RD is asserted whenever the processors read a word from

external memory.

WR O/T (pu)

Pulled high/

driven high

External Port Write Enable.

WR is asserted when the processors write a word to ex ternal

memory.

FLAG[0]/IRQ0 I/O FLAG[0] INPUT

FLAG0/Interrupt Request 0.

FLAG[1]/IRQ1 I/O FLAG[1] INPUT

FLAG1/Interrupt Request 1.

FLAG[2]/IRQ2/

I/O with pro-

grammable pu

(for MS mode)

FLAG[2] INPUT

FLAG2/Interrupt Request 2/Memory Select 2.

FLAG[3]/

TMREXP/MS

I/O with pro-

grammable pu

(for MS mode)

FLAG[3] INPUT

FLAG3/Timer Expired/Memory Select 3.

Rev. F | Page 14 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

SDRAS O/T (pu)

Pulled high/

driven high

SDRAM Row Address Strobe.

Connect to SDRAM’s RAS pin. In conjunction with other

SDRAM command pins, defines the operation for the SDRAM to perform.

SDCAS O/T (pu)

Pulled high/

driven high

SDRAM Column Address Select.

Connect to SDRAM’s CAS pin. In conjunction with other

SDRAM command pins, defines the operation for the SDRAM to perform.

SDWE O/T (pu)

Pulled high/

driven high

SDRAM Write Enable.

Connect to SDRAM’s WE or W buffer pin.

SDCKE O/T (pu)

Pulled high/

driven high

SDRAM Clock Enable.

Connect to SDRAM’s CKE pin. Enables and disables the CLK signal.

For details, see the data sheet supplied with the SDRAM device.

SDA10 O/T (pu)

Pulled high/

driven low

SDRAM A10 Pin.

Enables applications to refresh an SDRAM in parallel with non-

SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.

SDCLK0 O/T High-Z/driving

SDRAM Clock Output 0.

Clock driver for this pin differs from all other clock drivers. See

Figure 40 on Page 51.

SDCLK1 O/T

SDRAM Clock Output 1.

Additional clock for SDRAM devices. For systems with multiple

SDRAM devices, handles the increased clock load requirements, eliminating need of off-

chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated. Clock driver

for this pin differs from all other clock drivers. See Figure 40 on Page 51.

The SDCLK1 signal is only available on the SBGA package. SDCLK1 is not available on the

LQFP_EP package.

DAI _P

20–1

I/O with pro-

grammable

Pulled high/

pulled high

Digital Applications Interface

. These pins provide the physical interface to the DAI SRU.

The DAI SRU configuration registers define the combination of on-chip audiocentric

peripheral inputs or outputs connected to the pin, and to the pin’s output enable. The

configuration registers then determines the exact behavior of the pin. Any input or

output signal present in the DAI SRU may be routed to any of these pins. The DAI SRU

provides the connection from the serial ports (8), the SRC module, the S/PDIF module,

input data ports (2), and the precision clock generators (4), to the DAI_P20–1 pins. Pull-

ups can be disabled via the DAI_PIN_PULLUP register.

DPI _P

14–1

I/O with pro-

grammable

Pulled high/

pulled high

Digital Peripheral Interface.

These pins provide the physical interface to the DPI SRU.

The DPI SRU configuration registers define the combination of on-chip peripheral inputs

or outputs connected to the pin and to the pin’s output enable. The configuration

registers of these peripherals then determines the exact behavior of the pin. Any input

or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU

provides the connection from the timers (3), SPIs (2), UARTs (2), flags (12) TWI (1), and

general-purpose I/O (9) to the DPI_P14–1 pins. The TWI output is an open-drain output—

so the pins used for I

C data and clock should be connected to logic level 0. Pull-ups can

be disabled via the DPI_PIN_PULLUP register.

TDI I (pu)

Test Data Input (JTAG).

Provides serial data for the boundary scan logic.

TDO O/T

Test Data Output (JTAG).

Serial scan output of the boundary scan path.

TMS I (pu)

Test Mode Select (JTAG).

Used to control the test state machine.

TCK I

Tes t Clo ck ( JTAG) .

Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed

low) after power-up, or held low for proper operation of the processor

TRST I (pu)

Test Reset (JTAG).

Resets the test state machine. TRST must be asserted (pulsed low) after

power-up or held low for proper operation of the processor.

Table 8. Pin Descriptions (Continued)

Name Type

State During/

After Reset

(ID = 00x) Description

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 15 of 64 | October 2013

EMU O (O/D, pu)

Emulation Status.

Must be connected to the ADSP-21367/ADSP-21368/

ADSP-21369 Analog Devices DSP Tools product line of JTAG emulator target board con-

nectors only.

CLK_CFG

1–0

Core/CLKIN Ratio Control.

These pins set the start-up clock frequency. See the processor

hardware reference for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset.

CLKIN I

Local Clock In.

Used with XTAL. CLKIN is the processor’s clock input. It configures the

processors to use either its internal clock generator or an external clock source. Connect-

ing the necessary components to CLKIN and XTAL enables the internal clock generator.

Connecting the external clock to CLKIN while leaving XTAL unconnected configures the

processor to use an external clock such as an external clock oscillator. CLKIN may not be

halted, changed, or operated below the specified frequency.

XTAL O

Crystal Oscillator Terminal.

Used in conjunction with CLKIN to drive an external crystal.

RESET I

Processor Reset.

Resets the processor to a known state. Upon deassertion, there is a 4096

CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution

from the hardware reset vector address. The RESET i np ut must be as ser te d (l ow) at power-

up.

RESETOUT ODriven low/

driven high

Reset Out.

Drives out the core reset signal to an external device.

BOOT_CFG

1–0

Boot Configuration Select.

These pins select the boot mode for the processor. The

BOOT_CFG pins must be valid before reset is asserted. See the processor hardware

reference for a description of the boot modes.

4–1

I/O (pu)

Pulled high/

pulled high

External Bus Request.

Used by the ADSP-21368 processor to arbitrate for bus master-

ship. A processor only drives its own BR

line (corresponding to the value of its ID2-0

inputs) and monitors all others. In a system with less than four processors, the unused BR

pins should be tied high; the processor’s own BR

line must not be tied high or low

because it is an output.

2–0

I (pd)

Processor ID.

Determines which bus request (BR

4–1

) is used by the ADSP-21368 processor.

ID = 001 corresponds to BR

ID = 010 corresponds to BR

, and so on. Use ID = 000 or 001

in single-processor systems. These lines are a system configuration selection that should

be hardwired or only changed at reset. ID = 101,110, and 111 are reserved.

RPBA I (pu)

Rotating Priority Bus Arbitration Select.

When RPBA is high, rotating priority for the

ADSP-21368 external bus arbitration is selected. When RPBA is low, fixed priority is

selected. This signal is a system configuration selection which must be set to the same

value on every processor in the system.

The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID

2–0

= 00x

Pull-up can be enabled/disabled, value of pull-up cannot be programmed.

Table 8. Pin Descriptions (Continued)

Name Type

State During/

After Reset

(ID = 00x) Description

Rev. F | Page 16 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

SPECIFICATIONS

OPERATING CONDITIONS

Parameter

Specifications subject to change without notice.

Description

400 MHz

366 MHz

350 MHz

333 MHz

266 MHz

Min Max Min Max Min Max Unit

DDINT

Internal (Core) Supply Voltage 1.25 1.35 1.235 1.365 1.14 1.26 V

VDD

Analog (PLL) Supply Voltage 1.25 1.35 1.235 1.365 1.14 1.26 V

DDEXT

External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 3.13 3.47 V

Applies to input and bidirectional pins: DATAx, ACK, RPBA, BRx, IDx, FLAGx, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST.

High Level Input Voltage @ V

DDEXT

= Max 2.0 V

DDEXT

+ 0.5 2.0 V

DDEXT

+ 0.5 2.0 V

DDEXT

+ 0.5 V

Low Level Input Voltage @ V

DDEXT

= Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V

CLKIN

Applies to input pin CLKIN.

High Level Input Voltage @ V

DDEXT

= Max 1.74 V

DDEXT

+ 0.5 1.74 V

DDEXT

+ 0.5 1.74 V

DDEXT

+ 0.5 V

CLKIN

Low Level Input Voltage @ V

DDEXT

= Min –0.5 +1.1 –0.5 +1.1 –0.5 +1.1 V

Junction Temperature 208-Lead LQFP_EP @

AMBIENT

0C to 70C0 95 0 110 0 110 C

Junction Temperature 208-Lead LQFP_EP @

AMBIENT

–40C to +85CN/A N/A N/A N/A –40 +120 C

Junction Temperature 256-Ball BGA_ED @

AMBIENT

0C to 70C 0 95 N/A N/A 0 105 C

Junction Temperature 256-Ball BGA_ED @

AMBIENT

–40C to +85C N/A N/A N/A N/A –40 +105 C

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 17 of 64 | October 2013

ELECTRICAL CHARACTERISTICS

Parameter Description Test Conditions Min Typ Max Unit

High Level Output Voltage @ V

DDEXT

= Min, I

= –1.0 mA

2.4 V

Low Level Output Voltage @ V

DDEXT

= Min, I

= 1.0 mA

0.4 V

3, 4

High Level Input Current @ V

DDEXT

= Max, V

= V

DDEXT

Max 10 μA

5, 6

Low Level Input Current @ V

DDEXT

= Max, V

= 0 V 10 μA

IHPD

High Level Input Current Pull-Down @ V

DDEXT

= Max, V

= 0 V 250 μA

ILPU

Low Level Input Current Pull-Up @ V

DDEXT

= Max, V

= 0 V 200 μA

OZH

7, 8

Three-State Leakage Current @ V

DDEXT

= Max, V

= V

DDEXT

Max 10 μA

OZL

Three-State Leakage Current @ V

DDEXT

= Max, V

= 0 V 10 μA

OZLPU

Three-State Leakage Current Pull-Up @ V

DDEXT

= Max, V

= 0 V 200 μA

INTYP

Supply Current (Internal) t

CCLK

= 3.75 ns, V

DDINT

= 1.2 V, 25°C

CCLK

= 3.00 ns, V

DDINT

= 1.2 V, 25°C

CCLK

= 2.85 ns, V

DDINT

= 1.3 V, 25°C

CCLK

= 2.73 ns, V

DDINT

= 1.3 V, 25°C

CCLK

= 2.50 ns, V

DDINT

= 1.3 V, 25°C

700

900

1050

1080

1100

Supply Current (Analog) A

VDD

= Max 11 mA

12, 13

Input Capacitance f

= 1 MHz, T

CASE

= 25°C, V

= 1.3 V 4.7 pF

Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO.

See Output Drive Currents on Page 51 for typical drive current capabilities.

Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK.

Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST.

Applies to input pins with internal pull-downs: IDx.

Applies to input pins with internal pull-ups disabled: ACK, RPBA.

Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO.

Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU.

Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10

See the Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-21368 SHARC Processors” (EE-299) for further information.

Characterized, but not tested.

Applies to all signal pins.

Guaranteed, but not tested.

Rev. F | Page 18 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

PACKAGE INFORMATION

The information presented in Figure 4 provides details about

the package branding for the ADSP-21367/ADSP-21368/

ADSP-21369 processors. For a complete listing of product avail-

ability, see Ordering Guide on Page 61.

ESD CAUTION

MAXIMUM POWER DISSIPATION

See the Engineer-to-Engineer Note “Estimating Power Dissipa-

tion for ADSP-21368 SHARC Processors” (EE-299) for detailed

thermal and power information regarding maximum power dis-

sipation. For information on package thermal specifications, see

Thermal Characteristics on Page 53.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 10 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 41 on Page 51 under Test Conditions for voltage refer-

ence levels.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 5). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

Voltage Controlled Oscillator

In application designs, the PLL multiplier value should be

selected in such a way that the VCO frequency never exceeds

VCO

specified in Table 13.

• The product of CLKIN and PLLM must never exceed 1/2 of

VCO

(max) in Table 13 if the input divider is not enabled

(INDIV = 0).

Figure 4. Typical Package Brand

Table 9. Package Brand Information

Brand Key Field Description

t Temperature Range

pp Package Type

Z RoHS Compliant Option

cc See Ordering Guide

vvvvvv.x Assembly Lot Code

n.n Silicon Revision

# RoHS Compliant Designation

yyww Date Code

vvvvvv.x n.n

tppZ-cc

ADSP-2136x

#yyww country_of_origin

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid

performance degradation or loss of functionality.

Table 10. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V

DDINT

)–0.3 V to +1.5 V

Analog (PLL) Supply Voltage (A

VDD

)–0.3 V to +1.5 V

External (I/O) Supply Voltage (V

DDEXT

)–0.3 V to +4.6 V

Input Voltage –0.5 V to +3.8 V

Output Voltage Swing –0.5 V to V

DDEXT

+ 0.5 V

Load Capacitance 200 pF

Storage Temperature Range –65C to +150C

Junction Temperature Under Bias 125C

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 19 of 64 | October 2013

• The product of CLKIN and PLLM must never exceed f

VCO

(max) in Table 13 if the input divider is enabled

(INDIV = 1).

The VCO frequency is calculated as follows:

VCO

= 2  PLLM  f

INPUT

CCLK

= (2  PLLM  f

INPUT

)  (2  PLLD)

where:

VCO

= VCO output

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected

using the CLK_CFG pins in hardware.

PLLD = Divider value 1, 2, 4, or 8 based on the PLLD value pro-

grammed on the PMCTL register. During reset this value is 1.

INPUT

= Input frequency to the PLL.

INPUT

= CLKIN when the input divider is disabled or

INPUT

= CLKIN  2 when the input divider is enabled

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in and

Table 11. All of the timing specifications for the ADSP-2136x

peripherals are defined in relation to t

PCLK

. See the peripheral spe-

cific timing section for each peripheral’s timing information.

Figure 5 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, see the processor hardware reference.

Table 11. Clock Periods

Timing

Requirements Description

CLKIN Clock Period

CCLK

Processor Core Clock Period

PCLK

Peripheral Clock Period = 2 × t

CCLK

Figure 5. Core Clock and System Clock Relationship to CLKIN

LOOP

FILTER

CLKIN

PCLK

SDCLK

SDRAM

DIVIDER

PMCTL

(PLLBP)

BYPASS

MUX

DIVIDE

BY 2

PMCTL

(SDCKR)

CCLK

BYPASS

MUX

PLL

XTAL

CLKIN

DIVIDER

PLL

MULTIPLIER

BUF

VCO

BUF

PMCTL

(INDIV)

PLL

DIVIDER

CLK_CFGx/PMCTL (2xPLLM)

PINMUX

CLKOUT (TESTONLY)

DELAY OF

4096 CLKIN

CYCLES

CCLK

PCLK

PMCTL

(PLLBP)

PMCTL

(2xPLLD)

fVCO

fCCLK

fINPUT

Rev. F | Page 20 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Power-Up Sequencing

The timing requirements for processor start-up are given in

Table 12. Note that during power-up, a leakage current of

approximately 200μA may be observed on the RESET pin if it is

driven low before power up is complete. This leakage current

results from the weak internal pull-up resistor on this pin being

enabled during power-up.

Table 12. Power-Up Sequencing Timing Requirements (Processor Start-up)

Parameter Min Max Unit

Timing Requirements

RSTVDD

RESET Low Before V

DDINT

DDEXT

On 0 ns

IVDDEVDD

DDINT

On Before V

DDEXT

–50 +200 ms

CLKVDD

CLKIN Valid After V

DDINT

DDEXT

Valid 0 200 ms

CLKRST

CLKIN Valid Before RESET Deasserted 10

μs

PLLRST

PLL Control Setup Before RESET Deasserted 20 μs

Switching Characteristic

CORERST

Core Reset Deasserted After RESET Deasserted 4096t

+ 2 t

CCLK

3, 4

Valid V

DDINT

DDEXT

assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.

Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate

default states at all I/O pins.

The 4096 cycle count depends on t

srst

specification in Table 14. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles

maximum.

Figure 6. Power-Up Sequencing

tRSTVDD

tCLKVDD

tCLKRST

tCORERST

tPLLRST

VDDEXT

VDDINT

CLKIN

CLK_CFG1–0

RESET

RESETOUT

tIVDDEVDD

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 21 of 64 | October 2013

Clock Input

Table 13. Clock Input

Parameter

400 MHz

Applies to all 400 MHz models. See Ordering Guide on Page 61.

366 MHz

Applies to all 366 MHz models. See Ordering Guide on Page 61.

350 MHz

Applies to all 350 MHz models. See Ordering Guide on Page 61.

333 MHz

Applies to all 333 MHz models. See Ordering Guide on Page 61.

266 MHz

Applies to all 266 MHz models. See Ordering Guide on Page 61.

UnitMin Max Min Max Min Max Min Max Min Max

Timing Requirements

CLKIN Period 15

Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.

100 16.39

100 17.14

100 18

100 22.5

100 ns

CKL

CLKIN Width Low 7.5

45 8.1

45 8.5

45 9

45 11.25

45 ns

CKH

CLKIN Width High 7.5

45 8.1

45 8.5

45 9

45 11.25

45 ns

CKRF

CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 3ns

CCLK

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

CCLK

CCLK Period 2.5

10 2.73

10 2.85

10 3.0

10 3.75

10 ns

VCO

See Figure 5 on Page 19 for VCO diagram.

VCO Frequency 100 800 100 800 100 800 100 800 100 600 MHz

CKJ

9, 10

Actual input jitter should be combined with ac specifications for accurate timing analysis.

Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

CLKIN Jitter Tolerance –250 +250 –250 +250 –250 +250 –250 +250 –250 +250 ps

Figure 7. Clock Input

CLKIN

tCK

tCKL

tCKH

tCKJ

Rev. F | Page 22 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Clock Signals

The processors can use an external clock or a crystal. See the

CLKIN pin description in Table 8 on Page 13. Programs can

configure the processor to use its internal clock generator by

connecting the necessary components to CLKIN and XTAL.

Figure 8 shows the component connections used for a crystal

operating in fundamental mode.

Note that the clock rate is achieved using a 25 MHz crystal and a

PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed

of 400 MHz). To achieve the full core clock rate, programs need

to configure the multiplier bits in the PMCTL register.

Figure 8. 400 MHz Operation (Fundamental Mode Crystal)

22pF Y1

1M⍀*

XTAL

CLKIN

22pF

25.00 MHz

47⍀*

ADSP-2136x

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL

DRIVE POWER. REFER TO CRYSTAL

MANUFACTURER’S SPECIFICATIONS

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 23 of 64 | October 2013

Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts.

Table 14. Reset

Parameter Min Max Unit

Timing Requirements

WRST

RESET Pulse Width Low 4t

SRST

RESET Setup Before CLKIN Low 8 ns

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable

and CLKIN (not including start-up time of external clock oscillator).

Figure 9. Reset

CLKIN

RESET

tSRST

tWRST

Table 15. Interrupts

Parameter Min Max Unit

Timing Requirement

IPW

IRQx Pulse Width 2 × t

PCLK

+2 ns

Figure 10. Interrupts

INTERRUPT

INPUTS

tIPW

Rev. F | Page 24 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (TMREXP).

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in PWM_OUT (pulse-width modulation) mode.

Timer signals are routed to the DPI_P14–1 pins through the

DPI SRU. Therefore, the timing specifications provided below

are valid at the DPI_P14–1 pins.

Table 16. Core Timer

Parameter Min Max Unit

Switching Characteristic

WCTIM

TMREXP Pulse Width 4 × t

PCLK

– 1 ns

Figure 11. Core Timer

FLAG3

(TMREXP)

tWCTIM

Table 17. Timer PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristic

PWMO

Timer Pulse Width Output 2 × t

PCLK

– 1.2 2 × (2

– 1) × t

PCLK

Figure 12. Timer PWM_OUT Timing

PWM

OUTPUTS

tPWMO

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 25 of 64 | October 2013

Timer WDTH_CAP Timing

The following specification applies to Timer0, Timer1, and

Timer2 in WDTH_CAP (pulse width count and capture) mode.

Timer signals are routed to the DPI_P14–1 pins through the

DPI SRU. Therefore, the specification provided in Table 18 is

valid at the DPI_P14–1 pins.

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example, DAI_PB01_I to

DAI_PB02_O).

Table 18. Timer Width Capture Timing

Parameter Min Max Unit

Switching Characteristic

PWI

Timer Pulse Width 2 × t

PCLK

2 × (2

– 1) × t

PCLK

Figure 13. Timer Width Capture Timing

TIMER

CAPTURE

INPUTS

tPWI

Table 19. DAI/DPI Pin to Pin Routing

Parameter Min Max Unit

Timing Requirement

DPIO

Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid 1.5 12 ns

Figure 14. DAI/DPI Pin to Pin Direct Routing

DAI_Pn

DPI_Pn

DAI_Pm

DPI_Pm

tDPIO

Rev. F | Page 26 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01–20).

Table 20. Precision Clock Generator (Direct Pin Routing)

Parameter Min Max Unit

Timing Requirements

PCGIP

Input Clock Period t

PCLK

× 4 ns

STRIG

PCG Trigger Setup Before Falling

Edge of PCG Input Clock

4.5 ns

HTRIG

PCG Trigger Hold After Falling

Edge of PCG Input Clock

3ns

Switching Characteristics

DPCGIO

PCG Output Clock and Frame Sync Active Edge

Delay After PCG Input Clock

2.5 10 ns

DTRIGCLK

PCG Output Clock Delay After PCG Trigger 2.5 + (2.5 × t

PCGIP

) 10 + (2.5 × t

PCGIP

)ns

DTRIGFS

PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × t

PCGIP

) 10 + ((2.5 + D – PH) × t

PCGIP

)ns

PCGOW

Output Clock Period 2 × t

PCGIP

– 1 ns

D = FSxDIV, and PH = FSxPHASE. For more information, see the processor hardware reference, “Precision Clock Generators” chapter.

In normal mode.

Figure 15. Precision Clock Generator (Direct Pin Routing)

DAI_Pn

DPI_Pn

PCG_TRIGx_I

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

DPI_Py

PCG_CLKx_O

DAI_Pz

DPI_Pz

PCG_FSx_O

tDTRIGFS

tDTRIGCLK

tDPCGIO

tSTRIG tHTRIG

tPCGOW

tDPCGIO

tPCGIP

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 27 of 64 | October 2013

Flags

The timing specifications provided below apply to the FLAG3–0

and DPI_P14–1 pins, and the serial peripheral interface (SPI).

See Table 8 on Page 13 for more information on flag use.

Table 21. Flags

Parameter Min Max Unit

Timing Requirement

FIPW

FLAG3–0 IN Pulse Width 2 × t

PCLK

+ 3 ns

Switching Characteristic

FOPW

FLAG3–0 OUT Pulse Width 2 × t

PCLK

– 1.5 ns

Figure 16. Flags

FLAG

INPUTS

FLAG

OUTPUTS

tFOPW

tFIPW

Rev. F | Page 28 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

SDRAM Interface Timing (166 MHz SDCLK)

The 166 MHz access speed is for a single processor. When mul-

tiple ADSP-21368 processors are connected in a shared memory

system, the access speed is 100 MHz.

Table 22. SDRAM Interface Timing

366 MHz 350 MHz

All Other Speed

Grades

Parameter Min Max Min Max Min Max Unit

Timing Requirements

SSDAT

DATA Setup Before SDCLK 500 500 500 ps

HSDAT

DATA Hold After SDCLK 1.23 1.23 1.23 ns

Switching Characteristics

SDCLK

SDCLK Period 6.83 7.14 6.0 ns

SDCLKH

SDCLK Width High 3 3 2.6 ns

SDCLKL

SDCLK Width Low 3 3 2.6 ns

DCAD

Command, ADDR, Data Delay After SDCLK

4.8 4.8 4.8 ns

HCAD

Command, ADDR, Data Hold After SDCLK

1.2 1.2 1.2 ns

DSDAT

Data Disable After SDCLK 5.3 5.3 5.3 ns

ENSDAT

Data Enable After SDCLK 1.3 1.3 1.3 ns

The processor needs to be programmed in t

SDCLK

= 2.5  t

CCLK

mode when operated at 350 MHz, 366 MHz, and 400 MHz.

Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.

Figure 17. SDRAM Interface Timing

SDCLK

DATA (IN)

DATA (OUT)

COMMAND/ADDR

(OUT)

tSDCLKH

tSDCLKL

tHSDAT

tSSDAT

tHCAD

tDCAD

tENSDAT

tDCAD tDSDAT

tHCAD

tSDCLK

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 29 of 64 | October 2013

SDRAM Interface Enable/Disable Timing (166 MHz SDCLK)

Table 23. SDRAM Interface Enable/Disable Timing

For f

CCLK

= 400 MHz (SDCLK ratio = 1:2.5).

Parameter Min Max Unit

Switching Characteristics

DSDC

Command Disable After CLKIN Rise 2 × t

PCLK

+ 3 ns

ENSDC

Command Enable After CLKIN Rise 4.0 ns

DSDCC

SDCLK Disable After CLKIN Rise 8.5 ns

ENSDCC

SDCLK Enable After CLKIN Rise 3.8 ns

DSDCA

Address Disable After CLKIN Rise 9.2 ns

ENSDCA

Address Enable After CLKIN Rise 2 × t

PCLK

– 4 4 × t

PCLK

Figure 18. SDRAM Interface Enable/Disable Timing

tDSDC

tDSDCC

tDSDCA

tENSDC

tENSDCA

tENSDCC

CLKIN

COMMAND

SDCLK

ADDR

COMMAND

SDCLK

ADDR

Rev. F | Page 30 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Memory Read

Use these specifications for asynchronous interfacing to memo-

ries. These specifications apply when the processors are the bus

master accessing external memory space in asynchronous access

mode. Note that timing for ACK, DATA, RD, WR, and strobe

timing parameters only apply to asynchronous access mode.

Table 24. Memory Read

Parameter Min Max Unit

Timing Requirements

DAD

Address, Selects Delay to Data Valid

W + t

SDCLK

–5.12 ns

DRLD

RD Low to Data Valid

W – 3.2 ns

SDS

Data Setup to RD High 2.5 ns

HDRH

Data Hold from RD High

0ns

DAAK

ACK Delay from Address, Selects

1, 5

SDCLK

–9.5 + W ns

DSAK

ACK Delay from RD Low

W – 7.0 ns

Switching Characteristics

DRHA

Address Selects Hold After RD High RH + 0.20 ns

DARL

Address Selects to RD Low

SDCLK

– 3.3 ns

RD Pulse Width W – 1.4 ns

RWR

RD High to WR, RD Low HI + t

SDCLK

– 0.8 ns

W = (number of wait states specified in AMICTLx register) × t

SDCLK

HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) × t

SDCLK

IC = (number of idle cycles specified in AMICTLx register) × t

SDCLK

H = (number of hold cycles specified in AMICTLx register) × t

SDCLK

The falling edge of MSx is referenced.

The maximum limit of timing requirement values for t

DAD

and t

DRLD

parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not used.

Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.

Data hold: User must meet t

HDA

or t

HDRH

in asynchronous access mode. See Test Conditions on Page 51 for the calculation of hold times given capacitive and dc loads.

ACK delay/setup: User must meet t

DAAK

, or t

DSAK

, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet t

DAAK

or t

DSAK

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 31 of 64 | October 2013

Figure 19. Memory Read

ACK

DATA

tDRHA

tRW

tHDRH

tRWR

tDAD

tDARL

tDRLD tSDS

tDSAK

tDAAK

ADDR

MSx

Rev. F | Page 32 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Memory Write

Use these specifications for asynchronous interfacing to memo-

ries. These specifications apply when the processors are the bus

masters, accessing external memory space in asynchronous

access mode. Note that timing for ACK, DATA, RD, WR, and

strobe timing parameters only applies to asynchronous access

mode.

Table 25. Memory Write

Parameter Min Max Unit

Timing Requirements

DAAK

ACK Delay from Address, Selects

1, 2

SDCLK

– 9.7 + W ns

DSAK

ACK Delay from WR Low

1, 3

W – 4.9 ns

Switching Characteristics

DAWH

Address, Selects to WR Deasserted

SDCLK

–3.1+ W ns

DAWL

Address, Selects to WR Low

SDCLK

–2.7 ns

WR Pulse Width W – 1.3 ns

DDWH

Data Setup Before WR High t

SDCLK

–3.0+ W ns

DWHA

Address Hold After WR Deasserted H + 0.15 ns

DWHD

Data Hold After WR Deasserted H + 0.02 ns

WWR

WR High to WR, RD Low t

SDCLK

–1.5+ H ns

DDWR

Data Disable Before RD Low 2t

SDCLK

– 4.11 ns

WDE

Data Enabled to WR Low t

SDCLK

– 3.5 ns

W = (number of wait states specified in AMICTLx register) × t

SDCLK

H = (number of hold cycles specified in AMICTLx register) × t

SDCLK

ACK delay/setup: System must meet t

DAAK

, or t

DSAK

, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet t

DAAK

or t

DSAK

The falling edge of MSx is referenced.

Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.

Figure 20. Memory Write

ACK

DATA

tDAWH tDWHA

tWWR

tDATRWH

tDWHD

tWW

tDDWR

tDDWH

tDAWL

tWDE

tDSAK

tDAAK

ADDR

MSx

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 33 of 64 | October 2013

Asynchronous Memory Interface (AMI) Enable/Disable

Use these specifications for passing bus mastership between

ADSP-21368 processors (BRx).

Table 26. AMI Enable/Disable

Parameter Min Max Unit

Switching Characteristics

ENAMIAC

Address/Control Enable After Clock Rise 4 ns

ENAMID

Data Enable After Clock Rise t

SDCLK

+ 4 ns

DISAMIAC

Address/Control Disable After Clock Rise 8.7 ns

DISAMID

Data Disable After Clock Rise 0 ns

Figure 21. AMI Enable/Disable

CLKIN

ADDR, WR , RD,

MS1–0, DATA

ADDR , WR , RD,

MS1–0, DATA

tDISAMIAC

tDISAMID

tENAMIAC

tENAMID

Rev. F | Page 34 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Shared Memory Bus Request

Use these specifications for passing bus mastership between

ADSP-21368 processors (BRx).

Table 27. Multiprocessor Bus Request

Parameter Min Max Unit

Timing Requirements

SBRI

BRx, Setup Before CLKIN High 9 ns

HBRI

BRx, Hold After CLKIN High 0.5 ns

Switching Characteristics

DBRO

BRx Delay After CLKIN High 9 ns

HBRO

BRx Hold After CLKIN High 1.0 ns

Figure 22. Shared Memory Bus Request

tHBRI

tSBRI

tHBRO

tDBRO

CLKIN

BRX(OUT)

BRX(IN)

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 35 of 64 | October 2013

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Serial port signals SCLK, frame sync (FS), data channel A, data

channel B are routed to the DAI_P20–1 pins using the SRU.

Therefore, the timing specifications provided below are valid at

the DAI_P20–1 pins.

Table 28. Serial Ports—External Clock

400 MHz

366 MHz

350 MHz 333 MHz 266 MHz

Parameter Min Max Min Max Min Max Unit

Timing Requirements

SFSE

FS Setup Before SCLK

(Externally Generated FS in Either

Transmit or Receive Mode)

2.5 2.5 2.5 ns

HFSE

FS Hold After SCLK

(Externally Generated FS in Either

Transmit or Receive Mode)

2.5 2.5 2.5 ns

SDRE

Receive Data Setup Before Receive

SCLK

1.9 2.0 2.5 ns

HDRE

Receive Data Hold After SCLK 2.5 2.5 2.5 ns

SCLKW

SCLK Width (t

PCLK

× 4) ÷ 2 – 0.5 (t

PCLK

× 4) ÷ 2 – 0.5 (t

PCLK

× 4) ÷ 2 – 0.5 ns

SCLK

SCLK Period t

PCLK

× 4 t

PCLK

× 4 t

PCLK

× 4 ns

Switching Characteristics

DFSE

FS Delay After SCLK

(Internally Generated FS in Either

Transmit or Receive Mode)

10.25 10.25 10.25 ns

HOFSE

FS Hold After SCLK

(Internally Generated FS in Either

Transmit or Receive Mode)

222ns

DDTE

Transmit Data Delay After Transmit

SCLK

7.8 9.6 9.8 ns

HDTE

Transmit Data Hold After Transmit

SCLK

222ns

Referenced to sample edge.

Referenced to drive edge.

Rev. F | Page 36 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Table 29. Serial Ports—Internal Clock

Parameter Min Max Unit

Timing Requirements

SFSI

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

7ns

HFSI

FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

2.5 ns

SDRI

Receive Data Setup Before SCLK 7 ns

HDRI

Receive Data Hold After SCLK 2.5 ns

Switching Characteristics

DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode) 4 ns

HOFSI

FS Hold After SCLK (Internally Generated FS in Transmit Mode) –1.0 ns

DFSIR

FS Delay After SCLK (Internally Generated FS in Receive Mode) 9.75 ns

HOFSIR

FS Hold After SCLK (Internally Generated FS in Receive Mode) –1.0 ns

DDTI

Transmit Data Delay After SCLK 3.25 ns

HDTI

Transmit Data Hold After SCLK –1.0 ns

SCLKIW

Transmit or Receive SCLK Width 2 × t

PCLK

– 1.5 2 × t

PCLK

+ 1.5 ns

Referenced to the sample edge.

Referenced to drive edge.

Minimum SPORT divisor register value.

Table 30. Serial Ports—Enable and Three-State

Parameter Min Max Unit

Switching Characteristics

DDTEN

Data Enable from External Transmit SCLK 2 ns

DDTTE

Data Disable from External Transmit SCLK 10 ns

DDTIN

Data Enable from Internal Transmit SCLK –1 ns

Referenced to drive edge.

Table 31. Serial Ports—External Late Frame Sync

Parameter Min Max Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External Transmit FS or External Receive

FS with MCE = 1, MFD = 0

7.75 ns

DDTENFS

Data Enable for MCE = 1, MFD = 0 0.5 ns

The t

DDTLFSE

and t

DDTENFS

parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 37 of 64 | October 2013

Figure 23. Serial Ports

Figure 24. Enable and Three-State

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHOFSI tHFSI

tHDRI

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHFSI

tDDTI

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHOFSE

tHOFSI

tHDTI

tHFSE

tHDTE

tDDTE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHOFSE tHFSE

tHDRE

DATA RECEIVE—EXTERNAL CLOCK

tSCLKIW

tDFSI

tSFSI

tSDRI

tSCLKW

tDFSE

tSFSE

tSDRE

tDFSE

tSFSE

tSFSI

tDFSI

tSCLKIW tSCLKW

DRIVE EDGE

tDDTIN

tDDTEN tDDTTE

DAI_P20–1

(SCLK, INT)

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(SCLK, EXT)

DAI_P20–1

(DATA

CHANNEL A/B)

Rev. F | Page 38 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Figure 25. External Late Frame Sync

This figure reflects changes made to support left-justified sample pair mode.

DRIVE SAMPLE

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

2ND BIT

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

DRIVE

tDDTE/I

tHDTE/I

tDDTLFSE

tDDTENFS

tSFSE/I

DRIVE SAMPLE

LATE EXTERNAL TRANSMIT FS

2ND BIT

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

DRIVE

tDDTE/I

tHDTE/I

tDDTLFSE

tDDTENFS

tSFSE/I

tHFSE/I

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 39 of 64 | October 2013

Input Data Port

The timing requirements for the IDP are given in Table 32. IDP

signals SCLK, frame sync (FS), and SDATA are routed to the

DAI_P20–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DAI_P20–1 pins.

Table 32. IDP

Parameter Min Max Unit

Timing Requirements

SISFS

FS Setup Before SCLK Rising Edge 4 ns

SIHFS

FS Hold After SCLK Rising Edge 2.5 ns

SISD

SDATA Setup Before SCLK Rising Edge 2.5 ns

SIHD

SDATA Hold After SCLK Rising Edge 2.5 ns

IDPCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 1 ns

IDPCLK

Clock Period t

PCLK

× 4 ns

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 26. IDP Master Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tIDPCLK

tIDPCLKW

tSISFS tSIHFS

tSIHD

tSISD

Rev. F | Page 40 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 33. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the IDP, see the IDP

chapter of the ADSP-21368 SHARC Processor Hardware

Reference. Note that the 20 bits of external PDAP data can be

provided through the external port DATA31–12 pins or the

DAI pins.

Table 33. Parallel Data Acquisition Port (PDAP)

Parameter Min Max Unit

Timing Requirements

SPHOLD

PDAP_HOLD Setup Before PDAP_CLK Sample Edge 2.5 ns

HPHOLD

PDAP_HOLD Hold After PDAP_CLK Sample Edge 2.5 ns

PDSD

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3.85 ns

PDHD

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns

PDCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 3 ns

PDCLK

Clock Period t

PCLK

× 4 ns

Switching Characteristics

PDHLDD

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t

PCLK

+ 3 ns

PDSTRB

PDAP Strobe Pulse Width 2 × t

PCLK

– 1 ns

Data Source pins are DATA31–12, or DAI pins. Source pins for SCLK and FS are: 1) DATA11–10 pins, 2) DAI pins.

Figure 27. PDAP Timing

DAI_P20–1

(PDAP_CLK)

SAMPLE EDGE

DAI_P20–1

(PDAP_HOLD)

DAI_P20–1

(PDAP_STROBE)

tPDSTRB

tPDHLDD

tPDHD

tPDSD

tSPHOLD tHPHOLD

tPDCLK

tPDCLKW

DAI_P20–1/

ADDR23–4

(PDAP_DATA)

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 41 of 64 | October 2013

Pulse-Width Modulation Generators

Sample Rate Converter—Serial Input Port

The SRC input signals SCLK, frame sync (FS), and SDATA are

routed from the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided in Table 35 are valid at the

DAI_P20–1 pins.

Table 34. PWM Timing

Parameter Min Max Unit

Switching Characteristics

PWMW

PWM Output Pulse Width t

PCLK

– 2 (2

– 2) × t

PCLK

PWMP

PWM Output Period 2 × t

PCLK

– 1.5 (2

– 1) × t

PCLK

Figure 28. PWM Timing

PWM

OUTPUTS

tPWMW

tPWMP

Table 35. SRC, Serial Input Port

Parameter Min Max Unit

Timing Requirements

SRCSFS

FS Setup Before SCLK Rising Edge 4 ns

SRCHFS

FS Hold After SCLK Rising Edge 5.5 ns

SRCSD

SDATA Setup Before SCLK Rising Edge 4 ns

SRCHD

SDATA Hold After SCLK Rising Edge 5.5 ns

SRCCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 1 ns

SRCCLK

Clock Period t

PCLK

× 4 ns

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Rev. F | Page 42 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Figure 29. SRC Serial Input Port Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS tSRCHFS

tSRCHD

tSRCSD

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 43 of 64 | October 2013

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and it

should meet setup and hold times with regard to SCLK on the

output port. The serial data output, SDATA, has a hold time

and delay specification with regard to SCLK. Note that SCLK

rising edge is the sampling edge and the falling edge is the

drive edge.

Table 36. SRC, Serial Output Port

Parameter Min Max Unit

Timing Requirements

SRCSFS

FS Setup Before SCLK Rising Edge 4 ns

SRCHFS

FS Hold After SCLK Rising Edge 5.5 ns

SRCCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 1 ns

SRCCLK

Clock Period t

PCLK

× 4 ns

Switching Characteristics

SRCTDD

Transmit Data Delay After SCLK Falling Edge 9.9 ns

SRCTDH

Transmit Data Hold After SCLK Falling Edge 1 ns

DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 30. SRC Serial Output Port Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS tSRCHFS

tSRCTDD

tSRCTDH

Rev. F | Page 44 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

S/PDIF Transmitter

Serial data input to the S/PDIF transmitter can be formatted as

left justified, I

S, or right justified with word widths of 16, 18, 20,

or 24 bits. The following sections provide timing for the

transmitter.

S/PDIF Transmitter—Serial Input Waveforms

Figure 31 shows the right-justified mode. LRCLK is high for the

left channel and low for the right channel. Data is valid on the

rising edge of SCLK. The MSB is delayed 12-bit clock periods

(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

mode) from an LRCLK transition, so that when there are 64

SCLK periods per LRCLK period, the LSB of the data is right-

justified to the next LRCLK transition.

Figure 32 shows the default I

S-justified mode. LRCLK is low

for the left channel and high for the right channel. Data is valid

on the rising edge of SCLK. The MSB is left-justified to an

LRCLK transition but with a single SCLK period delay.

Figure 31. Right-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSB LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tRJD

Figure 32. I

S-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tI2SD

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 45 of 64 | October 2013

Figure 33 shows the left-justified mode. LRCLK is high for the

left channel and low for the right channel. Data is valid on the

rising edge of SCLK. The MSB is left-justified to an LRCLK

transition with no MSB delay.

S/PDIF Transmitter Input Data Timing

The timing requirements for the input port are given in

Table 37. Input signals SCLK, frame sync (FS), and SDATA are

routed to the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided below are valid at the

DAI_P20–1 pins.

Figure 33. Left-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tLJD

Table 37. S/PDIF Transmitter Input Data Timing

Parameter Min Max Unit

Timing Requirements

SISFS

FS Setup Before SCLK Rising Edge 3 ns

SIHFS

FS Hold After SCLK Rising Edge 3 ns

SISD

SDATA Setup Before SCLK Rising Edge 3 ns

SIHD

SDATA Hold After SCLK Rising Edge 3 ns

SISCLKW

Clock Width 36 ns

SISCLK

Clock Period 80 ns

SITXCLKW

Transmit Clock Width 9 ns

SITXCLK

Transmit Clock Period 20 ns

DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Rev. F | Page 46 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Figure 34. S/PDIF Transmitter Input Timing

SAMPLE EDGE

DAI_P20–1

(TxCLK)

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSITXCLKW tSITXCLK

tSISCLKW

tSISCLK

tSISFS tSIHFS

tSISD tSIHD

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 47 of 64 | October 2013

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter has an oversampling clock. This TxCLK

input is divided down to generate the biphase clock.

S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 38. Oversampling Clock (TxCLK) Switching Characteristics

Parameter Min Max Unit

TxCLK Frequency for TxCLK = 384 × FS Oversampling Ratio × FS <= 1/t

SITXCLK

MHz

TxCLK Frequency for TxCLK = 256 × FS 49.2 MHz

Frame Rate (FS) 192.0 kHz

Table 39. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter Min Max Unit

Switching Characteristics

DFSI

LRCLK Delay After SCLK 5 ns

HOFSI

LRCLK Hold After SCLK –2 ns

DDTI

Transmit Data Delay After SCLK 5 ns

HDTI

Transmit Data Hold After SCLK –2 ns

SCLKIW

Transmit SCLK Width 40 ns

SCLK frequency is 64 × FS where FS = the frequency of LRCLK.

Figure 35. S/PDIF Receiver Internal Digital PLL Mode Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

DRIVE EDGE

tSCLKIW

tDFSI

tHOFSI

tDDTI

tHDTI

Rev. F | Page 48 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

SPI Interface—Master

The processors contain two SPI ports. The primary has dedi-

cated pins and the secondary is available through the DPI. The

timing provided in Table 40 and Table 41 on Page 49 applies

to both.

Table 40. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements

SSPIDM

Data Input Valid to SPICLK Edge (Data Input Setup Time) 8.2 ns

HSPIDM

SPICLK Last Sampling Edge to Data Input Not Valid 2 ns

Switching Characteristics

SPICLKM

Serial Clock Cycle 8 × t

PCLK

– 2 ns

SPICHM

Serial Clock High Period 4 × t

PCLK

– 2 ns

SPICLM

Serial Clock Low Period 4 × t

PCLK

– 2 ns

DDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time) 2.5 ns

HDSPIDM

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 4 × t

PCLK

– 2 ns

SDSCIM

DPI Pin (SPI Device Select) Low to First SPICLK Edge 4 × t

PCLK

– 2 ns

HDSM

Last SPICLK Edge to DPI Pin (SPI Device Select) High 4 × t

PCLK

– 2 ns

SPITDM

Sequential Transfer Delay 4 × t

PCLK

– 1 ns

Figure 36. SPI Master Timing

tSPICHM

tSDSCIM tSPICLM tSPICLKM tHDSM tSPITDM

tDDSPIDM

tHSPIDM

tSSPIDM

DPI

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

CPHASE = 1

CPHASE = 0

tHDSPIDM

tHSPIDM

tSSPIDM tSSPIDM

tDDSPIDM

tHDSPIDM

SPICLK

(CP = 0,

CP = 1)

(OUTPUT)

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 49 of 64 | October 2013

SPI Interface—Slave

Table 41. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements

SPICLKS

Serial Clock Cycle 4 × t

PCLK

– 2 ns

SPICHS

Serial Clock High Period 2 × t

PCLK

– 2 ns

SPICLS

Serial Clock Low Period 2 × t

PCLK

– 2 ns

SDSCO

SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1 2 × t

PCLK

HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × t

PCLK

SSPIDS

Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 ns

HSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid 2 ns

SDPPW

SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × t

PCLK

Switching Characteristics

DSOE

SPIDS Assertion to Data Out Active 0 6.8 ns

DSOE

SPIDS Assertion to Data Out Active (SPI2) 0 8 ns

DSDHI

SPIDS Deassertion to Data High Impedance 0 6.8 ns

DSDHI

SPIDS Deassertion to Data High Impedance (SPI2) 0 8.6 ns

DDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 ns

HDSPIDS

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t

PCLK

DSOV

SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t

PCLK

The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral

Interface Port” chapter.

Figure 37. SPI Slave Timing

tSPICHS tSPICLS tSPICLKS tHDS tSDPPW

tSDSCO

tDSOE

tDDSPIDS

tDSDHI

tHDSPIDS

tHSPIDS

tSSPIDS

tDSDHI

tDSOV

tHSPIDS

tHDSPIDS

SPIDS

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

CPHASE = 1

CPHASE = 0

SPICLK

(CP = 0,

CP = 1)

(INPUT)

tSSPIDS

Rev. F | Page 50 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

JTAG Test Access Port and Emulation

Table 42. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

TCK

TCK Period t

STAP

TDI, TMS Setup Before TCK High 5 ns

HTAP

TDI, TMS Hold After TCK High 6 ns

SSYS

System Inputs Setup Before TCK High 7 ns

HSYS

System Inputs Hold After TCK High 18 ns

TRSTW

TRST Pulse Width 4t

Switching Characteristics

DTDO

TDO Delay from TCK Low 7 ns

DSYS

System Outputs Delay After TCK Low t

÷ 2 + 7 ns

System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, EMU.

Figure 38. IEEE 1149.1 JTAG Test Access Port

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tTCK

tSTAP tHTAP

tDTDO

tSSYS tHSYS

tDSYS

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 51 of 64 | October 2013

OUTPUT DRIVE CURRENTS

Figure 39 shows typical I-V characteristics for the output driv-

ers and Figure 40 shows typical I-V characteristics for the

SDCLK output drivers. The curves represent the current drive

capability of the output drivers as a function of output voltage.

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 14 on Page 23 through Table 42 on Page 50. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 41.

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 41. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads

of an average of 6 pF on all pins (see Figure 42). Figure 47 and

Figure 48 show graphically how output delays and holds vary

with load capacitance. The graphs of Figure 43 through

Figure 48 may not be linear outside the ranges shown for Typi-

cal Output Delay vs. Load Capacitance and Typical Output Rise

Time (20% to 80%, V = Min) vs. Load Capacitance.

Figure 39. Typical Drive at Junction Temperature

Figure 40. SDCLK1–0 Drive at Junction Temperature

SWEEP (VDDEXT) VOLTAGE (V)

03.50.5 1.0 1.5 2.0 2.5 3.0

SOURCE(V

DDEXT

)CURRENT(mA)

VOL

3.11V, 125°C

3.3V, 25°C

3.47V,

45°C

VOH

3.11V, 125°C

3.3V, 25°C

3.47V,

45°C

3.11V, 105°C

03.50.5 1.0 1.5 2.0 2.5 3.0

SOURCE(V

DDEXT

)CURRENT(mA)

VOL

3.1 3V, 1 2 5 ° C

3.3V, 2 5 °C

3.47V,

45°C

VOH

3.13V, 1 0 5 °C

105

3.13V, 1 2 5 °C

3.3V, 2 5° C

3.47V,

45°C

3.1 3V, 1 0 5 ° C

SWEEP (VDDEXT)VOLTAGE(V)

Figure 41. Voltage Reference Levels for AC Measurements

Figure 42. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

INPUT

OUTPUT

1.5V 1.5V

ZO = 50Ω (impedance)

TD = 4.04 ± 1.18 ns

2pF

TESTER PIN ELECTRONICS

50Ω

0.5pF

70Ω

400Ω

45Ω

4pF

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

1.5V

DUT

OUTPUT

Rev. F | Page 52 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Figure 43. Typical Output Rise/Fall Time

(20% to 80%, V

DDEXT

= Min)

Figure 44. Typical Output Rise/Fall Time

(20% to 80%, V

DDEXT

= Max)

LOAD CAPACITANCE (pF)

0 50 100 150 200 250

RISEANDFALLTIMES(ns)

RISE

FALL

y = 0.049x + 1.5105

y=0.0482x + 1.4604

LOAD CAPACITANCE (pF)

0100 250

RISEANDFALLTIMES(ns)

20015050

FALL

y = 0.0467x + 1.6323

y = 0.045x + 1.524

RISE

Figure 45. SDCLK Typical Output Rise/Fall Time

(20% to 80%, V

DDEXT

= Min)

Figure 46. SDCLK Typical Output Rise/Fall Time

(20% to 80%, V

DDEXT

= Max)

LOAD CAPACITANCE (pF)

0 50 100 150 200 250

RISEANDFALLTIMES(ns)

RISE

FALL

y=0.0372x + 0.228

y = 0.0277x + 0.369

LOAD CAPACITANCE (pF)

0 50 100 150 200 250

RISEANDFALLTIMES(ns)

RISE

FALL

y=0.0364x + 0.197

y = 0.0259x + 0.311

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 53 of 64 | October 2013

THERMAL CHARACTERISTICS

The ADSP-21367/ADSP-21368/ADSP-21369 processors are

rated for performance over the temperature range specified in

Operating Conditions on Page 16.

Table 43 and Table 44 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to-

board measurement complies with JESD51-8. Test board design

complies with JEDEC standards JESD51-9 (BGA_ED) and

JESD51-8 (LQFP_EP). The junction-to-case measurement com-

plies with MIL-STD-883. All measurements use a 2S2P JEDEC

test board.

The LQFP-EP package requires thermal trace squares and ther-

mal vias, to an embedded ground plane, in the PCB. Refer to

JEDEC standard JESD51-5 for more information.

To determine the junction temperature of the device while on

the application PCB, use:

where:

= junction temperature (C)

TOP

= case temperature (C) measured at the top center of the

package



= junction-to-top (of package) characterization parameter is

the typical value from Table 43 and Table 44.

= power dissipation (see Engineer-to-Engineer Note EE-299)

Values of 

are provided for package comparison and PCB

design considerations. 

can be used for a first-order approxi-

mation of T

by the equation:

where:

= ambient temperature (C)

Values of 

are provided for package comparison and PCB

design considerations when an external heat sink is required.

This is only applicable when a heat sink is used.

Values of 

are provided for package comparison and PCB

design considerations. The thermal characteristics values pro-

vided in Table 43 and Table 44 are modeled values @ 2 W.

Figure 47. Typical Output Delay or Hold vs. Load Capacitance

(at Junction Temperature)

Figure 48. SDCLK Typical Output Delay or Hold vs. Load Capacitance

(at Junction Temperature)

LOAD CAPACITANCE (pF)

0 20050 100 150

OUTPUTDELAYORHOLD(ns)

y = 0.0488x

1.5923

LOAD CAPACITANCE

(

)

0100

RISEANDFALLTIMES(ns)

20015050

y = 0.0256x

0.021

Table 43. Thermal Characteristics for 256-Ball BGA_ED

Parameter Condition Typical Unit



Airflow = 0 m/s 12.5 C/W



JMA

Airflow = 1 m/s 10.6 C/W



JMA

Airflow = 2 m/s 9.9 C/W



0.7 C/W



5.3 C/W



Airflow = 0 m/s 0.3 C/W



JMT

Airflow = 1 m/s 0.3 C/W



JMT

Airflow = 2 m/s 0.3 C/W

Table 44. Thermal Characteristics for 208-Lead LQFP EPAD

(With Exposed Pad Soldered to PCB)

Parameter Condition Typical Unit



Airflow = 0 m/s 17.1 C/W



JMA

Airflow = 1 m/s 14.7 C/W



JMA

Airflow = 2 m/s 14.0 C/W



9.6 C/W



Airflow = 0 m/s 0.23 C/W



JMT

Airflow = 1 m/s 0.39 C/W



JMT

Airflow = 2 m/s 0.45 C/W



Airflow = 0 m/s 11.5 C/W



JMB

Airflow = 1 m/s 11.2 C/W



JMB

Airflow = 2 m/s 11.0 C/W

TJTTOP



JT PD



+=

TJTA



JA PD



+=

Rev. F | Page 54 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

256-BALL BGA_ED PINOUT

The following table shows the ADSP-2136x’s pin names and

their default function after reset (in parentheses).

Table 45. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

A01 NC B01 DAI_P05 (SD1A) C01 DAI_P09 (SD2A) D01 DAI_P10 (SD2B)

A02 TDI B02 SDCLK1

C02 DAI_P07 (SCLK1) D02 DAI_P06 (SD1B)

A03 TMS B03 TRST C03 GND D03 GND

A04 CLK_CFG0 B04 TCK C04 V

DDEXT

D04 V

DDEXT

A05 CLK_CFG1 B05 BOOT_CFG0 C05 GND D05 GND

A06 EMU B06 BOOT_CFG1 C06 GND D06 V

DDEXT

A07 DAI_P04 (SFS0) B07 TDO C07 V

DDINT

D07 V

DDINT

A08 DAI_P01 (SD0A) B08 DAI_P03 (SCLK0) C08 GND D08 GND

A09 DPI_P14 (TIMER1) B09 DAI_P02 (SD0B) C09 GND D09 V

DDEXT

A10 DPI_P12 (TWI_CLK) B10 DPI_P13 (TIMER0) C10 V

DDINT

D10 V

DDINT

A11 DPI_P10 (UART0RX) B11 DPI_P11 (TWI_DATA) C11 GND D11 GND

A12 DPI_P09 (UART0TX) B12 DPI_P08 (SPIFLG3) C12 GND D12 V

DDEXT

A13 DPI_P07 (SPIFLG2) B13 DPI_P05 (SPIFLG0) C13 V

DDINT

D13 V

DDINT

A14 DPI_P06 (SPIFLG1) B14 DPI_P04 (SPIDS) C14 GND D14 GND

A15 DPI_P03 (SPICLK) B15 DPI_P01 (SPIMOSI) C15 GND D15 V

DDEXT

A16 DPI_P02 (SPIMISO) B16 RESET C16 V

DDINT

D16 GND

A17 RESETOUT B17 DATA30 C17 V

DDINT

D17 V

DDEXT

A18 DATA31 B18 DATA29 C18 V

DDINT

D18 GND

A19 NC B19 DATA28 C19 DATA27 D19 DATA26

A20 NC B20 NC C20 NC/RPBA

D20 DATA24

E01 DAI_P11 (SD3A) F01 DAI_P14 (SFS3) G01 DAI_P15 (SD4A) H01 DAI_P17 (SD5A)

E02 DAI_P08 (SFS1) F02 DAI_P12 (SD3B) G02 DAI_P13 (SCLK3) H02 DAI_P16 (SD4B)

E03 V

DDINT

F03 GND G03 GND H03 V

DDINT

E04 V

DDINT

F04 GND G04 V

DDEXT

H04 V

DDINT

E17 GND F17 V

DDEXT

G17 V

DDINT

H17 V

DDEXT

E18 GND F18 GND G18 V

DDINT

H18 GND

E19 DATA25 F19 GND/ID2

G19 DATA22 H19 DATA19

E20 DATA23 F20 DATA21 G20 DATA20 H20 DATA18

J01 DAI_P19 (SCLK5) K01 FLAG0 L01 FLAG2 M01 ACK

J02 DAI_P18 (SD5B) K02 DAI_P20 (SFS5) L02 FLAG1 M02 FLAG3

J03 GND K03 GND L03 V

DDINT

M03 GND

J04 GND K04 V

DDEXT

L04 V

DDINT

M04 GND

J17 GND K17 V

DDINT

L17 V

DDINT

M17 V

DDEXT

J18 GND K18 V

DDINT

L18 V

DDINT

M18 GND

J19 GND/ID1

K19 GND/ID0

L19 DATA15 M19 DATA12

J20 DATA17 K20 DATA16 L20 DATA14 M20 DATA13

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 55 of 64 | October 2013

N01 RD P01 SDA10 R01 SDWE T01 SDCKE

N02 SDCLK0 P02 WR R02 SDRAS T02 SDCAS

N03 GND P03 V

DDINT

R03 GND T03 GND

N04 V

DDEXT

P04 V

DDINT

R04 GND T04 V

DDEXT

N17 GND P17 V

DDINT

R17 V

DDEXT

T17 GND

N18 GND P18 V

DDINT

R18 GND T18 GND

N19 DATA11 P19 DATA8 R19 DATA6 T19 DATA5

N20 DATA10 P20 DATA9 R20 DATA7 T20 DATA4

U01 MS0 V01 ADDR22 W01 GND Y01 GND

U02 MS1 V02 ADDR23 W02 ADDR21 Y02 NC

U03 V

DDINT

V03 V

DDINT

W03 ADDR19 Y03 NC

U04 GND V04 GND W04 ADDR20 Y04 ADDR18

U05 V

DDEXT

V05 GND W05 ADDR17 Y05 NC/BR1

U06 GND V06 GND W06 ADDR16 Y06 NC/BR2

U07 V

DDEXT

V07 GND W07 ADDR15 Y07 XTAL

U08 V

DDINT

V08 V

DDINT

W08 ADDR14 Y08 CLKIN

U09 V

DDEXT

V09 GND W09 A

VDD

Y09 NC

U10 GND V10 GND W10 A

VSS

Y10 NC

U11 V

DDEXT

V11 GND W11 ADDR13 Y11 NC/BR3

U12 V

DDINT

V12 V

DDINT

W12 ADDR12 Y12 NC/BR4

U13 V

DDEXT

V13 V

DDEXT

W13 ADDR10 Y13 ADDR11

U14 V

DDEXT

V14 GND W14 ADDR8 Y14 ADDR9

U15 V

DDINT

V15 V

DDINT

W15 ADDR5 Y15 ADDR7

U16 V

DDEXT

V16 GND W16 ADDR4 Y16 ADDR6

U17 V

DDINT

V17 GND W17 ADDR1 Y17 ADDR3

U18 V

DDINT

V18 GND W18 ADDR2 Y18 GND

U19 DATA0 V19 DATA1 W19 ADDR0 Y19 GND

U20 DATA2 V20 DATA3 W20 NC Y20 NC

The SDCLK1 signal is only available on the SBGA package. SDCLK1 is not available on the LQFP_EP package.

Applies to ADSP-21368 models only.

Table 45. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) (Continued)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

Rev. F | Page 56 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Figure 49 shows the bottom view of the BGA_ED ball configu-

ration. Figure 50 shows the top view of the BGA_ED ball

configuration.

Figure 49. 256-Ball BGA_ED Ball Configuration (Bottom View)

1214

15 13

1719

20 18

NO CONNECT

VDDINT

I/O SIGNALSGND

KEY

VDDEXT AVSS

AVDD

BOTTOM

VIEW

Figure 50. 256-Ball BGA_ED Ball Configuration (Top View)

234

12 14

151316

17 19

2018

NO CONNECT

VDDINT

I/O SIGNALSGND

KEY

VDDEXT AVSS

AVDD

TOP

VIEW

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 57 of 64 | October 2013

208-LEAD LQFP_EP PINOUT

The following table shows the ADSP-2136x’s pin names and

their default function after reset (in parentheses).

Table 46. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number)

Lead

No. Signal

Lead

No. Signal

Lead

No. Signal

Lead

No. Signal

Lead

No. Signal

DDINT

43 V

DDINT

85 V

DDEXT

127 V

DDINT

169 CLK_CFG0

2 DATA28 44 DATA4 86 GND 128 GND 170 BOOT_CFG0

3 DATA27 45 DATA5 87 V

DDINT

129 V

DDEXT

171 CLK_CFG1

4 GND 46 DATA2 88 ADDR14 130 DAI_P19 (SCLK5) 172 EMU

DDEXT

47 DATA3 89 GND 131 DAI_P18 (SD5B) 173 BOOT_CFG1

6 DATA26 48 DATA0 90 V

DDEXT

132 DAI_P17 (SD5A) 174 TDO

7 DATA25 49 DATA1 91 ADDR15 133 DAI_P16 (SD4B) 175 DAI_P04 (SFS0)

8DATA24 50 V

DDEXT

92 ADDR16 134 DAI_P15 (SD4A) 176 DAI_P02 (SD0B)

9 DATA23 51 GND 93 ADDR17 135 DAI_P14 (SFS3) 177 DAI_P03 (SCLK0)

10 GND 52 V

DDINT

94 ADDR18 136 DAI_P13 (SCLK3) 178 DAI_P01 (SD0A)

11 V

DDINT

53 V

DDINT

95 GND 137 DAI_P12 (SD3B) 179 V

DDEXT

12 DATA22 54 GND 96 V

DDEXT

138 V

DDINT

180 GND

13 DATA21 55 V

DDEXT

97 ADDR19 139 V

DDEXT

181 V

DDINT

14 DATA20 56 ADDR0 98 ADDR20 140 GND 182 GND

15 V

DDEXT

57 ADDR2 99 ADDR21 141 V

DDINT

183 DPI_P14 (TIMER1)

16 GND 58 ADDR1 100 ADDR23 142 GND 184 DPI_P13 (TIMER0)

17 DATA19 59 ADDR4 101 ADDR22 143 DAI_P11 (SD3A) 185 DPI_P12 (TWI_CLK)

18 DATA18 60 ADDR3 102 MS1 144 DAI_P10 (SD2B) 186 DPI_P11 (TWI_DATA)

19 V

DDINT

61 ADDR5 103 MS0 145 DAI_P08 (SFS1) 187 DPI_P10 (UART0RX)

20 GND 62 GND 104 V

DDINT

146 DAI_P09 (SD2A) 188 DPI_P09 (UART0TX)

21 DATA17 63 V

DDINT

105 V

DDINT

147 DAI_P06 (SD1B) 189 DPI_P08 (SPIFLG3)

22 V

DDINT

64 GND 106 GND 148 DAI_P07 (SCLK1) 190 DPI_P07 (SPIFLG2)

23 GND 65 V

DDEXT

107 V

DDEXT

149 DAI_P05 (SD1A) 191 V

DDEXT

24 V

DDINT

66 ADDR6 108 SDCAS 150 V

DDEXT

192 GND

25 GND 67 ADDR7 109 SDRAS 151 GND 193 V

DDINT

26 DATA16 68 ADDR8 110 SDCKE 152 V

DDINT

194 GND

27 DATA15 69 ADDR9 111 SDWE 153 GND 195 DPI_P06 (SPIFLG1)

28 DATA14 70 ADDR10 112 WR 154 V

DDINT

196 DPI_P05 (SPIFLG0)

29 DATA13 71 GND 113 SDA10 155 GND 197 DPI_P04 (SPIDS)

30 DATA12 72 V

DDINT

114 GND 156 V

DDINT

198 DPI_P03 (SPICLK)

31 V

DDEXT

73 GND 115 V

DDEXT

157 V

DDINT

199 DPI_P01 (SPIMOSI)

32 GND 74 V

DDEXT

116 SDCLK0 158 V

DDINT

200 DPI_P02 (SPIMISO)

33 V

DDINT

75 ADDR11 117 GND 159 GND 201 RESETOUT

34 GND 76 ADDR12 118 V

DDINT

160 V

DDINT

202 RESET

35 DATA11 77 ADDR13 119 RD 161 V

DDINT

203 V

DDEXT

36 DATA10 78 GND 120 ACK 162 V

DDINT

204 GND

37 DATA9 79 V

DDINT

121 FLAG3 163 TDI 205 DATA30

38 DATA8 80 A

VSS

122 FLAG2 164 TRST 206 DATA31

39 DATA7 81 A

VDD

123 FLAG1 165 TCK 207 DATA29

Rev. F | Page 58 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

40 DATA6 82 GND 124 FLAG0 166 GND 208 V

DDINT

41 V

DDEXT

83 CLKIN 125 DAI_P20 (SFS5) 167 V

DDINT

42 GND 84 XTAL 126 GND 168 TMS

Table 46. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) (Continued)

Lead

No. Signal

Lead

No. Signal

Lead

No. Signal

Lead

No. Signal

Lead

No. Signal

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 59 of 64 | October 2013

PACKAGE DIMENSIONS

The ADSP-21367/ADSP-21368/ADSP-21369 processors are

available in 256-ball RoHS compliant and leaded BGA_ED, and

208-lead RoHS compliant LQFP_EP packages.

Figure 51. 208-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]

(SW-208-1)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MS-026-BJB-HD

100907 A

0.15

0.10

0.05 0.08

COPLANARITY

0.20

0.15

0.09

1.45

1.40

1.35

7°

3.5°

0°

VIEW A

ROTATED 90° CCW

0.27

0.22

0.17

0.75

0.60

0.45

0.50

BSC

LEAD PITCH

28.10

28.00 SQ

27.90

30.20

30.00 SQ

29.80

TOP VIEW

(PINS DOWN)

BOTTOM VIEW

(PINS UP)

EXPOSED

PAD

105

104

105

104

156

208

157

156

157

PIN 1

1.60 MAX

1.00 REF

SEATING

PLANE

VIEW A

8.890

REF

8.712

REF

25.50

REF

NOTE:

THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO VSS.

THIS SHOULD BE IMPLEMENTED BY SOLDERING THE EXPOSED PAD TO A VSS PCB LAND THAT IS THE SAME SIZE

AS THE EXPOSED PAD. THE VSS PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE VSS PLANE IN THE PCB

WITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE.

Rev. F | Page 60 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

SURFACE-MOUNT DESIGN

Table 47 is provided as an aide to PCB design. For industry-

standard design recommendations, refer to IPC-7351, Generic

Requirements for Surface-Mount Design and Land Pattern

Standard.

Figure 52. 256-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]

(BP-256)

Dimension shown in millimeters

COMPLIANT TO JEDEC STANDARDS MO-192-BAL-2

0.10 MIN

0.70

0.60

0.50

1.00

0.80

0.60

COPLANARITY

0.20

0.90

0.75

0.60 SEATING

PLANE

BALL DIAMETER

0.25 MIN

(4 )

DETAIL A

1.70 MAX

1.27

BSC

1315

19 2

101214

1820

24.13

BSC SQ BOTTOM

VIEW

A1 CORNER

INDEX AREA

TOP VIEW

27.00

BSC SQ

BALL A1

INDICATOR

DETAIL A

Table 47. BGA_ED Data for Use with Surface-Mount Design

Package Ball Attach Type Solder Mask Opening Ball Pad Size

256-Lead Ball Grid Array BGA_ED

(BP-256)

Solder Mask Defined (SMD) 0.63 mm 0.73 mm

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 61 of 64 | October 2013

AUTOMOTIVE PRODUCTS

An ADSP-21369 model is available for automotive applications

with controlled manufacturing. Note that this special model

may have specifications that differ from the general release

models.

The automotive grade product shown in Table 48 is available for

use in automotive applications. Contact your local ADI account

representative or authorized ADI product distributor for spe-

cific product ordering information. Note that all automotive

products are RoHS compliant.

ORDERING GUIDE

Table 48. Automotive Products

Model

Temperature

Range

Instruction

Rate

On-Chip

SRAM ROM Package Description

Package

Option

AD21369WBSWZ1xx –40°C to +85°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

Referenced temperature is ambient temperature.

Model Notes

Temperature

Range

Referenced temperature is ambient temperature.

Instruction

Rate

On-Chip

SRAM ROM Package Description

Package

Option

ADSP-21367KBP-2A

Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at

www.analog.com/SHARC.

0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21367KBPZ-2A

2, 3

Z = RoHS Compliant Part.

0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21367BBP-2A

–40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21367BBPZ-2A

–40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21367KBPZ-3A

0°C to +70°C 400 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21367KSWZ-1A

0°C to +70°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

ADSP-21367KSWZ-2A

0°C to +70°C 333 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

ADSP-21367KSWZ-4A

0°C to +70°C 350 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

ADSP-21367KSWZ-5A

0°C to +70°C 366 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

ADSP-21367BSWZ-1A

–40°C to +85°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

ADSP-21368KBPZ-2A

0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21368BBPZ-2A

–40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21368KBPZ-3A

0°C to +70°C 400 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21369KBPZ-2A

0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21369BBP-2A –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21369BBPZ-2A

–40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21369KBPZ-3A

0°C to +70°C 400 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21369KSWZ-1A

0°C to +70°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

ADSP-21369KSWZ-2A

0°C to +70°C 333 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

ADSP-21369KSWZ-4A

0°C to +70°C 350 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

ADSP-21369KSWZ-5A

0°C to +70°C 366 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

ADSP-21369KSWZ-6A

0°C to +70°C 400 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

ADSP-21369BSWZ-1A

–40°C to +85°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

ADSP-21369BSWZ-2A

–40°C to +85°C 333 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

Rev. F | Page 62 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

Rev. F | Page 63 of 64 | October 2013

Rev. F | Page 64 of 64 | October 2013

ADSP-21367/ADSP-21368/ADSP-21369

registered trademarks are the property of their respective owners.

D05267-0-10/13(F)