DATASHEET: ZM5202 FULLY INTEGRATED Z-WAVE (R) WIRELESS MODULE Features * * Pad and pin compatible with the ZM3102 and ZM4102 ITU G.9959 compliant Module * * * * * * * The Silicon Labs ZM5202 module is a low-cost fully integrated Z-Wave module in a small 12.5mm x 13.6mm x 1.9mm form factor. It is an ideal solution for home control applications such as access control, appliance control, AV control, building automation, energy management, lighting, security, and sensor networks in the "Internet of Things". It contains all the required passive components, including the crystal and a SAW filter to provide a complete Z-Wave system. The ZM5202 module remains pad and pin compatible with the ZM3102 and the ZM4102 Z-Wave modules. The ZM5202 module is based on an 8-bit 8051 CPU core, which is optimized to handle the data and link management requirements of a Z-Wave node. The patented Z-Wave protocol supports automatic retransmissions, collision avoidance mechanisms, frame acknowledgements, frame CRCs, frequency agility, and full mesh routing to ensure a highly reliable and robust wireless communication solution. An integrated baseband controller, sub-1 GHz radio transceiver, a comprehensive set of hardware peripherals, 16kB of SRAM, and 128kB of Flash memory is available for OEM applications and the Z-Wave protocol stack. DSH12435-15 | 3/2018 * * * * * * * * * * * * Optimized 8051 CPU Core 128kB Flash 16kB SRAM UART with speed up to 230.4kbps SPI with speed up to 8MHz 2 Interrupt Inputs 4-channel 12/8-bit rail-to-rail ADC with VDD/internal/external voltage reference PWM Output 10 General Purpose IOs Hardware AES-128 security engine 1000 step dimmer (TRIAC/FET) Power-On-Reset/Brown-out Detection Supply voltage range from 2.3V to 3.6V for optional battery operation TX mode current typ. 36mA@0dBm RX mode current typ. 32mA Normal mode current typ. 15mA Sleep mode current typ. 1A Wake-up timer current typ. 700nA Less than 1ms cold start-up time Radio Transceiver * * * * * * Receiver sensitivity with SAW filter down to -103dBm @ 9.6kbps Transmit power with SAW filter up to +4dBm Z-Wave 9.6/40/100kbps data rates Supports all Z-Wave sub-1 GHz frequency bands (865.2 MHz to 926.3 MHz) Supports multi-channel frequency agility and listen before talk Regulatory Compliance ACMA: AS/NZS 4268 CE: EN 300 220/489 FCC: CFR 47 Part 15 IC: RSS-GEN/210 MIC: ARIB STD-T108 1 Datasheet: ZM5202 1 CONTENT 2 OVERVIEW .......................................................................................................................................................................... 4 2.1 CPU ...................................................................................................................................................................................... 5 2.2 PERIPHERALS ........................................................................................................................................................................... 5 2.2.1 Advanced Encryption Standard Security Processor ..................................................................................................... 5 2.2.2 Analog-to-Digital Converter ........................................................................................................................................ 5 2.2.3 Brown-Out Detector / Power-On-Reset....................................................................................................................... 6 2.2.4 Crystal Driver and System Clock .................................................................................................................................. 6 2.2.5 Dimmer........................................................................................................................................................................ 6 2.2.6 General Purpose Input/Output .................................................................................................................................... 7 2.2.7 General Purpose Timer / Pulse Width Modulator ....................................................................................................... 7 2.2.8 Interrupt Controller ..................................................................................................................................................... 8 2.2.9 Light-Emitting Diode Contoller .................................................................................................................................... 8 2.2.10 Reset Controller ........................................................................................................................................................... 8 2.2.11 Serial Peripheral Interface ........................................................................................................................................... 9 2.2.12 Timers ........................................................................................................................................................................ 10 2.2.13 Universal Asynchronous Receiver / Transmitter ....................................................................................................... 10 2.2.14 Wake-Up Timer ......................................................................................................................................................... 10 2.2.15 Watchdog .................................................................................................................................................................. 10 2.2.16 Wireless Transceiver.................................................................................................................................................. 11 2.3 MEMORY MAP ...................................................................................................................................................................... 11 2.4 MODULE PROGRAMMING........................................................................................................................................................ 12 2.4.1 Entering In-System Programming Mode ................................................................................................................... 12 2.5 POWER SUPPLY REGULATOR .................................................................................................................................................... 12 3 TYPICAL APPLICATION ...................................................................................................................................................... 13 4 PIN CONFIGURATION ........................................................................................................................................................ 14 4.1 5 PIN FUNCTIONALITY................................................................................................................................................................ 15 ELECTRICAL CHARACTERISTICS .......................................................................................................................................... 18 5.1 TEST CONDITIONS .................................................................................................................................................................. 18 5.1.1 Typical Values............................................................................................................................................................ 18 5.1.2 Minimum and Maximum Values ............................................................................................................................... 18 5.2 ABSOLUTE MAXIMUM RATINGS ................................................................................................................................................ 19 5.3 GENERAL OPERATING RATINGS ................................................................................................................................................. 19 5.4 CURRENT CONSUMPTION ........................................................................................................................................................ 19 5.5 SYSTEM TIMING ..................................................................................................................................................................... 20 5.6 NON-VOLATILE MEMORY ........................................................................................................................................................ 21 5.7 ANALOG-TO-DIGITAL CONVERTER ............................................................................................................................................. 22 5.8 GENERAL PURPOSE INPUT OUTPUT ........................................................................................................................................... 22 5.9 RF CHARACTERISTICS .............................................................................................................................................................. 24 5.9.1 Transmitter................................................................................................................................................................ 24 5.9.2 Receiver ..................................................................................................................................................................... 25 5.9.3 Regulatory Compliance ............................................................................................................................................. 27 6 Z-WAVE FREQUENCIES ...................................................................................................................................................... 28 7 MODULE INFORMATION ................................................................................................................................................... 29 2 DSH12435-15 | 3/2018 Datasheet: ZM5202 7.1 7.2 MODULE MARKING ................................................................................................................................................................ 29 MODULE DIMENSIONS ............................................................................................................................................................ 29 8 PROCESS SPECIFICATION ................................................................................................................................................... 29 9 PCB MOUNTING AND SOLDERING..................................................................................................................................... 30 9.1 RECOMMENDED PCB MOUNTING PATTERN................................................................................................................................ 30 SOLDERING INFORMATION ................................................................................................................................................................... 30 10 ORDERING INFORMATION ............................................................................................................................................ 32 10.1 TAPE AND REEL INFORMATION ................................................................................................................................................. 32 10.1.1 Tape dimensions........................................................................................................................................................ 33 10.1.2 Reel Supplier A .......................................................................................................................................................... 35 10.1.3 Reel Supplier B........................................................................................................................................................... 36 11 ABBREVIATIONS ............................................................................................................................................................ 37 12 REVISION HISTORY ........................................................................................................................................................ 39 13 REFERENCES .................................................................................................................................................................. 41 DSH12435-15 | 3/2018 3 Datasheet: ZM5202 2 OVERVIEW The ZM5202 module is a fully integrated module containing all the hardware and firmware required to add Z-Wave functionality to OEM products. The ZM5202 module contains the SD3502 chip along with all the required passives for supply decoupling, matching, crystal and a SAW filter as illustrated in Figure 2.1. The module only requires a stable DC supply and an antenna matched to 50 for operation. ZM5202 SD3502 Decoupling Voltage Regulator POR / BOD 128kB Flash Memory Power Manager 12kB XRAM Special Function Register 4kB XRAM 256B IRAM 8051W CPU 128B Critical Memory RAM GP Timer / PWM Wake-Up Timer 8051 Timers Watchdog Sub-1 GHz Wireless Transceiver ADC Dimmer Modem GPIO LED Controller Baseband Controller SPI UART Interrupt Controller AES Transceiver Matching / SAW Filter Clock Control XTAL Driver 32MHz XTAL Figure 2.1: Functional block diagram The module is verified to pass regulatory requirements and qualified to meet Z-Wave specifications. The crystal and the SAW filter are key elements that provide frequency stability of the RF output signal, and excellent RF immunity to interfering signals in the receiver path. The ZM5202 module is fully backwards compatible with the ZM4102 and ZM3102 modules in terms of the available GPIOs, hardware peripherals, and footprint. Unlike the ZM4102, it does not require a higher voltage during programming. 4 DSH12435-15 | 3/2018 Datasheet: ZM5202 2.1 CPU The CPU is binary compatible with the industry standard 803x/805x CPU and is operated at 32MHz. Its cycle performance is improved by six times relative to the standard 8051 implementation. The CPU can be placed in 4 main modes as described in Table 2.1. Table 2.1: CPU modes Mode ACTIVE SLEEP PROGRAMMING DURING SUSTAINED RESET EXTERNAL NVM PROGRAMMING 2.2 * * * * * * * * * * * * * * * * Description Code is executed Peripherals are available All I/O's are resistively pulled high Use a short ( up to 4ms) reset-low pulse to enter the reset of active state Wake-up timer available Critical memory retention available I/O's states according to user configuration Use API call to enter from ACTIVE mode Used to program the internal FLASH via SPI1 Code is not executed All I/O's are resistively pulled high Programming requires external control of the reset pin plus the SPI port Used to program an external NVM (FLASH/EPROM) (optionally) wired to the SPI port Code is not executed All I/O's are resistively pulled high External NVM programming requires external control of the RESET pin (plus the NVM-SPI port) PERIPHERALS 2.2.1 ADVANCED ENCRYPTION STANDARD SECURITY PROCESSOR The Z-Wave protocol specifies the use of Advanced Encryption Standard (AES) 128-bit block encryption for secure applications. The built-in Security Processor is a hardware accelerator that encrypts and decrypts data at a rate of 1 byte per 1.5s. It encodes the frame payload and the message authentication code to ensure privacy and authenticity of messages. The processor supports Output FeedBack (OFB), Cipher-Block Chaining (CBC), and Electronic CodeBook (ECB) modes to target variable length messages. Payload data is streamed in OFB mode, and authentication data is processed in CBC mode as required by the Z-Wave protocol. The processor implements two efficient access methods: Direct Memory Access (DMA) and streaming through Special Function Register (SFR) ports. The processor functionality is exposed via the Z-Wave API for application use. 2.2.2 ANALOG-TO-DIGITAL CONVERTER The Analog-to-Digital Converter (ADC) is capable of sampling one of the five available input voltage sources and returns an 8 or 12-bit unsigned representation of the selected input scaled relative to the selected reference voltage, as described by the formula below. = , + - - - + The ADC is capable of operating rail to rail, while the following input configurations apply (VBG = built-in Band-gap 1.25V, VDD = supply voltage, VIN = pin 10 and pin 13 to pin 15): DSH12435-15 | 3/2018 5 Datasheet: ZM5202 Table 2.2: ADC voltage source configuration options Source VIN VREF+ VREF- Description The sampling input voltage The positive node of the reference voltage The negative node of the reference voltage Pin Pin 10, pin 13, pin 14, pin15, VBG Pin 14, VBG, VDD Pin 13, GND If the sampling input voltage crosses a predefined lower or upper voltage threshold, an interrupt is triggered. Setting VIN = VBG and VRFE+ = VDD implements a battery monitor. All inputs (VIN, VREF+, VREF-) must be driven by low impedance (Rsource) voltage sources, to suppress offsets caused by GPIO input leakage of up to 10A. + - - , = 10 2 | | 2. If the output impedance of the signal source is larger than Rsource, an external buffer must be used. 2.2.3 BROWN-OUT DETECTOR / POWER-ON-RESET When a cold start-up occurs, an internal Power-On-Reset (POR) circuit ensures that code execution does not begin unless the supply voltage is sufficient. After which, an internal Brown-Out Detector (BOD) circuit guarantees that faulty code execution does not occur by entering the reset state, if the supply voltage drops below the minimum operating level. These guarantees apply equally in both the active and sleep modes. 2.2.4 CRYSTAL DRIVER AND SYSTEM CLOCK The system clock and RF frequencies are derived from the module mounted 32MHz crystal (XTAL), which internal system performance is factory trimmed to guarantee initial RF frequency precision. The temperature and 5 years aging margin for the internal 32MHz XTAL is 15 ppm. 2.2.5 DIMMER The Dimmer allows you to build leading edge or trailing edge dimmers to cover dimming applications with electronic transformers, halogen or incandescent lamps, wire-wound transformers, etc. The classic leading edge method requires an external TRIAC while the more versatile and electronic transformer friendly trailing edge method requires external Field Effect Transistors (FET) or Insulated-Gate Bipolar Transistors (IGBT). The Dimmer regulates the power-on duration with a precision of 1000 steps in each 50 Hz or 60 Hz half-period. Once the Dimmer has been initialized, it will run at the requested power setting without any assistance from the MCU. 2.2.5.1 LEADING EDGE MODE This is the classic TRIAC mode. Based on the dim-level requested, the Dimmer determines when and how the power is switched on. To ensure reliable handling in presence of inductive loads, multiple trigger pulses are automatically appended when needed. 6 DSH12435-15 | 3/2018 Datasheet: ZM5202 Mains voltage TRIAC firing pulses Current through Figure 2.2: Leading edge mode (TRIAC) 2.2.5.2 TRAILING EDGE MODE When FET/IGBT Mode is enabled, the Dimmer allows power to grow softly after each voltage zero crossing event. The Dimmer controls the turn-off time (or angle) by switching off the FET/IGBT. Mains voltage FET/IGBT firing pulses Current through load Figure 2.3: Trailing edge mode (FET/IGBT) 2.2.5.3 ZERO CROSSING SYNCHRONIZATION The Dimmer detects and synchronizes to the AC voltage via a zero-crossing acquisition signal provided by the dimming application. This signal must be connected to pin 14 and GPIO input level compliant. Multiple single and dual event-per-cycle formats are supported. Fixed phase delays are accepted and easily compensated for through the Z-Wave API. 2.2.6 GENERAL PURPOSE INPUT/OUTPUT There are 10 General Purpose Input/Output (GPIO) pins. These pins can be configured individually as Schmitt triggered inputs with/without internal pull-up or open-drain/push-pull outputs. The GPIO pins can be overridden by peripheral functions and each pin is able to drive loads with a minimum of 8mA. 2.2.7 GENERAL PURPOSE TIMER / PULSE WIDTH MODULATOR A 16-bit General Purpose (GP) auto-reload timer could be provided with either an accurate 4MHz clock or an approximate 32kHz clock. It can be configured to auto-reload a predefined value and may be polled or programmed to generate an interrupt when DSH12435-15 | 3/2018 7 Datasheet: ZM5202 the register wraps around. It also serves as a Pulse Width Modulated (PWM) signal generator on pin 4. A simple low frequency Digital-to-Analog Converter (DAC) could be designed using a few external passive components. 2.2.8 INTERRUPT CONTROLLER Fifteen interrupt sources are supported, including external interrupt sources on the pin 3 and pin 4. The interrupts are shared between the user application and the Z-Wave protocol. Priorities for the interrupts are pre-assigned by the Z-Wave protocol implementation. Therefore, constraints for the user application apply. Table 2.3: Interrupt vector table 00 02 04 05 06 07 08 09 14 Vector Interrupt Name INT0 INT1 UART0 Multi Dimmer General Purpose Timer ADC RF NMI 01 03 05 06 07 08 09 10 00 Priority Resources served External interrupt 0 via pin 4 External interrupt 1 either via pin 3, or pin 3 and pin 4 UART0 end of RX or TX AES, SPI, and many more reserved resources External interrupt via ZEROX pin 14. Supported by the Dimmer API General Purpose Timer overflow Battery monitor, ADC low and high monitor RF DMA Non Maskable Interrupt for debugger and more 2.2.9 LIGHT-EMITTING DIODE CONTOLLER The Light-Emitting Diode (LED) controller provides a single channel PWM generator on pin 5, that can be used to control the current drawn through an LED. Table 2.4: Properties of the LED controller Property Pulse width resolution Frequency No. of channels Placement of the pulse within a single period Drive strength Description 16-bit 488 Hz 1 Normal mode (Pulses of all channels are synchronized to the beginning of a period) Skewed mode (In each consecutive channel, pulses are shifted 25% of the period relative to the previous channel) 8mA 2.2.10 RESET CONTROLLER After a reset event, the MCU is reinitialized in less than 1ms. This delay is mostly due to the charge time of the internal and external supply capacitances, and bringing the XTAL clock into a stable oscillation. Multiple events may cause a reset. Therefore, the actual cause is latched by hardware and may be retrieved via software when the system resumes operation. Some reset methods deliberately leave the state of GPIO pins unchanged, while other GPIO pins are set to high impedance with an internal pull-up. 8 DSH12435-15 | 3/2018 Datasheet: ZM5202 Table 2.5: Supported reset methods Reset Cause BOR INT1 POR RESET_N Software WATCHDOG WUT Description Reset request generated by Brown-OutReset hardware Reset request generated when a signal is received on pin INT1, when the chip is in power down mode Reset request generated by Power-OnReset hardware Reset request generated by the RESET_N pin being de-asserted Reset request generated in software. Reset request generated by the WATCHDOG Timer timing out Reset request generated by the WakeUp-Timer timing out GPIO state High impedance with pull-up Unchanged High impedance with pull-up High impedance with pull-up Unchanged High impedance with pull-up Unchanged Maskable No Yes No No Yes Yes Yes 2.2.11 SERIAL PERIPHERAL INTERFACE SPI1 Serial Peripheral Interface enables synchronous data transfers between devices. Table 2.6: SPI1 signal modes MOSI MISO SCK SPI1 Signal SPI1 Function, master Data output Data input Clock output During data transmission, SCK acts as a clock, while 8 bits of data are exchanged between the two devices within 8 cycles of SCK. MASTER SPI CLOCK GENERATOR SLAVE SCK 0 0 1 0 0 0 1 0 MISO 0 0 1 0 0 0 1 0 MOSI Figure 2.4: Flow of data between SPI master and slave The module acts as a SPI master when controlling an external Non-Volatile Memory (NVM). The slave select (or chip select) of the external NVM could be driven by an available GPIO. SPI1 slave mode is reserved for In-System Programming (ISP). Therefore, SPI1 can only be used as a master. DSH12435-15 | 3/2018 9 Datasheet: ZM5202 External NVM ZM5202 CS_N PX.Y SPI SCK SPI SCK SPI MOSI SPI MOSI SPI MISO SPI MISO Figure 2.5: Typical interface to slave device 2.2.12 TIMERS Timer 0 and Timer 1 are 16-bit counters that can be clocked from a fixed internal source or an external source. Except for the use of external gating signals, the complete set of classic 8051 T0/T1 features is available. Table 2.7: Timer sources Timer 0 Timer 1 Timer Fixed Internal Source 16 MHz 16 MHz External Source Pin 10 Pin 15 2.2.13 UNIVERSAL ASYNCHRONOUS RECEIVER / TRANSMITTER The Universal Asynchronous Receiver / Transmitter (UART) is a hardware block operating independently of the 8051 CPU. It offers full-duplex data exchange, up to 230.4kbps, with an external host microcontroller requiring an industry standard NRZ asynchronous serial data format. The UART0 interface is available over pin 10 and pin15. A data byte is shifted as a start bit, 8 data bits (lsb first), and a stop bit, respectively, with no parity and hardware handshaking. Figure 2.6 shows the waveform of a single serial byte. The UART is compliant with RS-232 when an external level converter is used. START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT Figure 2.6: UART waveform 2.2.14 WAKE-UP TIMER The Wake-Up Timer (WUT) plays an important role in maximizing battery life of applications like Frequently Listening Routing Slave (FLiRS) Z-Wave nodes. It is available to customer applications via the Z-Wave API, and can be configured to wake a sleeping node after 1 to 256 seconds. The programming resolution equals 8-bit fractions of 2 seconds, alternatively 8-bit fractions of 256 seconds. The WUT is automatically calibrated to the system clock when it is operational, maintaining an accuracy of <2%. 2.2.15 WATCHDOG The watchdog helps prevents the CPU from entering a deadlock state. A timer that is enabled by default achieves this by triggering a reset event in case it overflows. The timer overflows in 1 second, therefore it is essential that the software clear the timer periodically. The watchdog is disabled when the chip is in power down mode, and automatically restarts with a cleared timer when waking up to the active mode. 10 DSH12435-15 | 3/2018 Datasheet: ZM5202 2.2.16 WIRELESS TRANSCEIVER The wireless transceiver is a sub-1 GHz ISM narrowband FSK radio, a modem, and a baseband controller. This architecture provides an all-digital direct synthesis transmitter and a low IF digital receiver. The Z-Wave protocol currently utilizes 2-key FSK/GFSK modulation schemes at 9.6/40/100 kbps data rates throughout a span of carrier frequencies from 865.2 to 926.3MHz. The output power of the transmitter is configurable in the range -26dBm to +4dBm (VDD = 2.3V to 3.6V, TA = -10C to +85C). An external front-end could be used to further increase the link budget if necessary. 2.3 MEMORY MAP Figure 2.7 shows an illustration of the byte wise addressable memories that are shared between the user application and the Z-Wave protocol stack. Additional ROM and NVR areas are used for boot code, calibration data, production data, and lock bytes. Table 2.8: Description of memory blocks ID M1-M4 Memory 128kB Flash Address Method Program Memory M5-M6 16kB RAM XRAM Yes M7 M8 256B RAM 128B RAM IRAM XRAM No No M9 256B NVM (API) No M10 256B NVR (API) Yes DSH12435-15 | 3/2018 Exposed during Programming Yes Description Flash memory, mapped in 3 banks of 32kB slices over a 32kB common block, one read access per 2 clock cycles. SRAM's split into 4kB and 12kB contiguous blocks Bit addressable SRAM Critical SRAM for data persistency during sleep mode Cached high endurance non-volatile data registers Flash area reserved for the Z-Wave protocol, calibration data, production data, and lock bytes 11 Datasheet: ZM5202 CODE SPACE (FLASH) IRAM FFFF 32k M2 Bank 1 M3 Bank 2 M1 Common F 0 4FFF 7FFF M1 Common M8: RAM XRAM M4 Bank 3 8000 32k 256 12k M6 RAM 2000 M1 Common 0000 128 M7: RAM 1080 1000 4k M5: RAM 0FFF 0000 Figure 2.7: Non-API addressable memory blocks 2.4 MODULE PROGRAMMING The code space and the NVR of the flash can be programmed and/or read through the SPI1 interface. [1] 2.4.1 ENTERING IN-SYSTEM PROGRAMMING MODE The module can be placed into the In-System Programming (ISP) mode by asserting the active low RESET_N signal for 5.2ms. The programming unit of the module then waits for the "Interface Enable" serial command before activating the ISP mode over the SPI1. 2.5 POWER SUPPLY REGULATOR While the supply to the digital I/O circuits is unregulated, on-chip low-dropout regulators derive all the 1.5 V and 2.5 V internal supplies required by the Micro-Controller Unit (MCU) core logic, non-volatile data registers, flash, and the analogue circuitry. 12 DSH12435-15 | 3/2018 Datasheet: ZM5202 3 TYPICAL APPLICATION An illustration of an application example using the ZM5202 module implementation follows. It is strongly recommended that the power supply is decoupled sufficiently, and a pull-up resistor placed on the RESET_N signal if the host GPIO is unable to drive it. 3V3 3V3 VDD RESET_N INT1 3V3 3V3 ZM5202 RF Matching WP_N VDD HOLD_N NVM GND CS_N PX.Y SCK SCK SI MOSI SO MISO GND Figure 3.1: Example of a standalone application with an external antenna DSH12435-15 | 3/2018 13 Datasheet: ZM5202 4 PIN CONFIGURATION The layout of the pins on the ZM5202 module is shown in Figure 4.1. 2.65mm 4.15mm 5.65mm 7.15mm 8.65mm 10.90mm 0.00mm 6 5 4 3 2 1 12.50mm 12.25mm 9.25mm 7 7.75mm 8 6.25mm 9 4.75mm 10 3.25mm 11 18 Top View 12 13 14 7.75mm 17 6.00mm 16 15 0.25mm 0.00mm 0.00mm 1.00mm 0.74mm 13.60mm 13.35mm 10.90mm 7.15mm 0.50mm 5.65mm 4.15mm 2.65mm 0.25mm 0.00mm 1.00mm Signal Pin 1.30mm 0.65mm Ground Pin Figure 4.1: Pin layout (top view) 14 DSH12435-15 | 3/2018 Datasheet: ZM5202 4.1 PIN FUNCTIONALITY Table 4.1: Power and ground signals Pin Name VDD GND Pin Location 11 1, 6, 12, 16, 17 Type 1 S S Function Module power supply. Ground. Must be connected to the ground plane. Table 4.2: Module control signal Pin Name RESET_N Pin Location 2 Type I Function Active low signal that places the module in a reset/programmable state. Table 4.3: SPI1 interface signals Pin Name SPI1 SCK SPI1 MISO 8 7 SPI1 MOSI 9 Pin Location Type O I O Function in Reset State SPI1 Clock input with internal pull-up. Serial data transmit when in SPI1 ISP mode, high impedance otherwise with internal pull-up. Waits for the "Interface Enable" serial command after 5.2ms. Enters SPI1 ISP mode after command is received from the host. Function in Active State SPI1 Clock. Output in master mode. Master-In-Slave-Out serial data. Input in master mode. Master-Out-Slave-In serial data. Output in master mode. Table 4.4: UART0 interface signals Pin Name UART0 RX UART0 TX Pin Location 10 15 Type I O Function in Reset State High impedance with internal pull-up. High impedance with internal pull-up. Function in Active State Receive data from host serial port. Transmit data to host serial port. Table 4.5: ADC interface signals Pin Name ADC0 ADC1 ADC2 Pin Location 10 15 13 ADC3 14 1 Type I I I Function in Reset State High impedance with internal pull-up. High impedance with internal pull-up. High impedance with internal pull-up. I High impedance with internal pull-up. Function in Active State Analog-to-Digital converter input. Analog-to-Digital converter input. Analog-to-Digital converter input or lower reference voltage. Analog-to-Digital converter input or higher reference voltage. I = Input, O = Output, D+ = Differential Plus, D- = Differential Minus, S = Supply DSH12435-15 | 3/2018 15 Datasheet: ZM5202 Table 4.6: External interrupt interface signals Pin Name INT0 INT1 Pin Location 4 3, 4 Type I I Function in Reset State High impedance with internal pull-up. High impedance with internal pull-up. Function in Active State External interrupt 0 input. High priority. External interrupt 1 input. Low priority. Table 4.7: PWM signal Pin Name PWM 4 Pin Location Type O Function in Reset State High impedance with internal pull-up. Function in Active State Pulse width modulator output. Table 4.8: LED controller interface signal Pin Name PWM LED0 5 Pin Location Type O Function in Reset State High impedance with internal pull-up. Function in Active State LED controller output. Table 4.9: Dimmer interface signals Pin Name TRIAC Pin Location 13 ZEROX 14 Type O Function in Reset State High impedance with internal pull-up. I High impedance with internal pull-up. Function in Active State Dimmer output. Firing pulse to TRIAC/FET/IGBT. Zero-cross detection input. Table 4.10: Timer interface signals Pin Name T0 EXT CLK T1 EXT CLK Pin Location 10 15 Type I I Function in Reset State High impedance with internal pull-up. High impedance with internal pull-up. Function in Active State Timer 0 external clock input. Timer 1 external clock input. Table 4.11: RF interface signal Pin Name RF 2 2 Pin Location 18 Type I/O Function in Reset State High impedance with internal pull-up. Function in Active State RF input and output. Caution: pin is sensitive to electro-static discharge 16 DSH12435-15 | 3/2018 Datasheet: ZM5202 Table 4.12: GPIO signals Pin Name P0.4 P1.0 P1.1 P2.2 5 4 3 9 Pin Location P2.3 7 I/O P2.4 8 I/O P3.4 P3.5 P3.6 P3.7 10 15 13 14 I/O I/O I/O I/O DSH12435-15 | 3/2018 Type I/O I/O I/O I/O Function in Reset State High impedance with internal pull-up. High impedance with internal pull-up. High impedance with internal pull-up. Waits for the "Interface Enable" serial command after 5.2ms. Enters SPI1 ISP mode after command is received from the host. Serial data transmit when in SPI1 ISP mode, high impedance with internal pull-up otherwise. Programmer clock input with internal pull-up. High impedance with internal pull-up. High impedance with internal pull-up. High impedance with internal pull-up. High impedance with internal pull-up. Function in Active State General purpose input and output. General purpose input and output. General purpose input and output. General purpose input and output. General purpose input and output. General purpose input and output. General purpose input and output. General purpose input and output. General purpose input and output. General purpose input and output. 17 Datasheet: ZM5202 5 ELECTRICAL CHARACTERISTICS This section describes the electrical parameters of the ZM5202 module. 5.1 TEST CONDITIONS Characterization in Lab (TA=-10C to +85C, VDD=+2.3V to +3.6V) Sorting criterion specified with Min and Max values Manufactured Modules Statistics with Min, Typ, and Max values Final Test in Production (TA=+25C, VDD=+3.3V) Tested Modules Figure 5.1: Testing flow The following conditions apply for characterization in the lab, unless otherwise noted. 1. 2. 3. 4. 5. Ambient temperature TA = -10C to +85C Supply voltage VDD = +2.3V to +3.6V All tests are carried out on the ZDB5202 Z-Wave Development Board. [2] Conducted transmission power is measured with the SAW filter for 868.4, 908.4, 919.8, and 921.4MHz at 50 Conducted receiver sensitivity is measured with the SAW filter for 868.4, 908.4, 919.8, and 921.4MHz at 50 The following conditions apply for the final test in production, unless otherwise noted. 1. 2. 3. 4. Ambient temperature TA = +25C Supply voltage VDD = +3.3V Conducted transmission power is measured with the SAW filter for 868.4, 908.4, 919.8, and 921.4MHz at 50 Conducted receiver sensitivity is measured with the SAW filter for 868.4, 908.4, 919.8, and 921.4MHz at 50 5.1.1 TYPICAL VALUES Unless otherwise specified, typical data refer to the mean of a data set measured at an ambient temperature of TA=25C and supply voltage of VDD=+3.3V. 5.1.2 MINIMUM AND MAXIMUM VALUES Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by a final test in production on 100% of the devices at an ambient temperature of TA=25C and supply voltage of VDD=+3.3V. For data based on measurements, the minimum and maximum values represent the mean value plus or minus three times the standard deviation (3). 18 DSH12435-15 | 3/2018 Datasheet: ZM5202 5.2 ABSOLUTE MAXIMUM RATINGS The absolute ratings specify the limits beyond which the module may not be functional. Exposure to absolute maximum conditions for extended periods may cause permanent damage to the module. Table 5.1: Voltage characteristics Symbol VDD-GND VIN-GND IIN PRF-IN ESDHBM ESDMM ESDCDM Description Main supply voltage Voltage applied on any I/O pin Current limit when over driving the input (VIN-GND > VDD-GND) Radio receiver input power JEDEC JESD22-A114F Human Body Model JEDEC JESD22-A115C Machine Model JEDEC JESD22-C101E Field-Induced Charged-Device Model Min -0.3 -0.3 - Max +3.6 +3.6 +20.0 +10.0 +2000.0 +200.0 +500.0 Unit V V mA dBm V V V -120 Max +120 - Unit mA mA Max +125 Unit C Table 5.2: Current characteristics Symbol IVDD IGND Description Current into VDD power supply pin Sum of the current out of all GND ground pins Min Table 5.3: Thermal characteristics TJ Symbol 5.3 Description Junction temperature Min -55 GENERAL OPERATING RATINGS The operating ratings indicate the conditions where the module is guaranteed to be functional. Table 5.4: Recommended operating conditions Symbol VDD fSYS TA 5.4 Description Standard operating supply voltage Internal clock frequency Ambient operating temperature Min +2.3 -10.0 Typ +3.3 32.0 +25.0 Max +3.6 +85.0 Unit V MHz C CURRENT CONSUMPTION Measured at an ambient temperature of TA=-10C to +85C and a supply voltage of VDD=+2.3V to +3.6V. DSH12435-15 | 3/2018 19 Datasheet: ZM5202 Table 5.5: Current consumption in active modes Symbol IDD_ACTIVE IDD_RX IDD_TX_-26 IDD_TX_4 Description MCU running at 32MHz MCU and radio receiver active MCU and radio transmitter active, -26dBm MCU and radio transmitter active, +4dBm Min - Typ 14.9 32.4 27.5 42.1 Max 15.9 35.1 - Unit mA mA mA mA 45 Current Consumption (mA) 43 41 39 37 35 33 31 29 27 25 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 3 Transmit Power (dBm) Figure 5.2: Typical current consumption vs. transmit power Table 5.6: Current consumption in power saving modes Symbol IDD_SLEEP IDD_WUT IDD_WUT_RAM Description Module in sleep state Module in sleep state with wake-up timer active Module in sleep state with wake-up timer and 128 bytes of critical RAM active Min - Typ 1.0 2.0 2.1 Max - Unit A A A - Unit mA Table 5.7: Current consumption during programming Symbol IDD_PGM_SPI 5.5 Programming via SPI1 Description Min - Typ 15 Max SYSTEM TIMING Measured at an ambient temperature of TA=-10C to +85C and a supply voltage of VDD=+2.3V to +3.6V. 20 DSH12435-15 | 3/2018 Datasheet: ZM5202 Table 5.8: Transition between operating modes Symbol tACTIVE_SLEEP tSLEEP_ACTIVE Description Transition time from the active state to the sleep state Transition time from the sleep state to the active state ready to execute code Min - Typ - Max 125 160 Unit ns s - Max +2.3 Unit V - 1.0 ms - Max 40 Unit ms - 2 % - Unit ns Max 44.1 1.4 Unit ms s Table 5.9: System start-up time VPOR Symbol tRESET_ACTIVE Description Power-on-Reset (POR) threshold on rising supply voltage at which the reset signal is deasserted Transition time from the reset state to the active state ready to execute code with a power rise time not exceeding 10s Min - Typ - Table 5.10: Wake-up timer accuracy Symbol tWUT_OFFSET tWUT_SCALE Description Wake-up timer offset, Y-axis intercept of time vs. setting curve Wake-up timer absolute error Min - Typ - Table 5.11: Reset timing requirements Symbol tRST_PULSE Description Duration to assert RESET_N to guarantee a full system reset Min 20 Typ Min Typ - Max Table 5.12: Programming time Symbol tERASE_FULL tPGM_FULL 5.6 Description Time taken to erase the entire flash memory Time taken to program the entire flash memory over SPI1 at 4MHz including a full erase - - NON-VOLATILE MEMORY Qualified for an ambient temperature of TA=+25C and a supply voltage of VDD=+3.3V. The on-chip memory is based on SuperFlash(R) technology. DSH12435-15 | 3/2018 21 Datasheet: ZM5202 Table 5.13: On-chip flash Symbol ENDFLASH RETFLASH-LT RETFLASH-HT Description Endurance, erase cycles before failure Data retention Data retention (Qualified for a junction temperature of TJ=-10C to +85C) Min 10000 100 10 Typ Min 100000 100 10 Typ - Max - Unit cycles years years - Unit cycles years years Table 5.14: On-chip M9 high endurance NVM Symbol ENDNVM RETNVM-LT RETNVM-HT 5.7 Description Endurance, erase cycles before failure Data retention Data retention (Qualified for a junction temperature of TJ=-10C to +85C) - Max ANALOG-TO-DIGITAL CONVERTER Measured at an ambient temperature of TA=-10C to +85C and a supply voltage of VDD=+2.3V to +3.6V. Table 5.15: 12 bit ADC characteristics Symbol VBG VREF+ VREFIADCIN DNLADC ACC8b ACC12b fS-8b fS-12b 5.8 Description Internal reference voltage Upper reference input voltage Lower reference input voltage Input current (0 VIN VDD) Differential non-linearity Accuracy when sampling 20ksps with 8 bit resolution Accuracy when sampling 10ksps with 12 bit resolution 8 bit sampling rate 12 bit sampling rate Min +1.20 VDD - 0.90 0.00 -10.00 -1.00 -2.00 -5.00 - Max +1.30 VDD +1.20 +10.00 +1.00 +2.00 +5.00 0.02 0.01 Unit V V V A LSB LSB LSB Msps Msps GENERAL PURPOSE INPUT OUTPUT Measured at an ambient temperature of TA=-10C to +85C. 22 DSH12435-15 | 3/2018 Datasheet: ZM5202 Table 5.16: Digital input characteristics, supply voltage of VDD=+2.3V to +3.0V Symbol VIH VIL VIF VIR VHYS IIH IIL-NPU IIL-PU PUIN CIN Description Logical 1 input voltage high level Logical 0 input voltage low level Falling input trigger threshold Rising edge trigger threshold Schmitt trigger voltage hysteresis Logical 1 input high level current leakage Logical 0 input low level current leakage (no internal pull-up resistor) Logical 0 input low level current leakage (with internal pull-up resistor) Internal pull-up resistance (TA=+25C) Pin input capacitance Min +1.85 +0.75 +1.35 +0.55 -7.00 +35.00 20.00 - Max Unit V V V V V A A A k pF Max Unit V V mA mA mA mA Max Unit V V V V V A A A k pF Max Unit V V mA mA mA mA +0.75 +1.05 +1.85 +0.85 +7.00 +90.00 30.00 15.00 Table 5.17: Digital output characteristics, supply voltage of VDD=+2.3V to +3.0V Symbol VOH VOL IOH-LP IOL-LP IOH-HP IOL-HP Description Logical 1 output voltage high level Logical 0 output voltage low level Logical 1 output high level current sourcing Logical 0 output low level current sinking Logical 1 output high level current sourcing (pin 10 and pin 13 to pin 15) Logical 0 output low level current sinking (pin 10 and pin 13 to pin 15) Min +1.9 -6.0 -12.0 +0.4 +6.0 +12.0 - Table 5.18: Digital input characteristics, supply voltage of VDD=+3.0V to +3.6V Symbol VIH VIL VIF VIR VHYS IIH IIL-NPU IIL-PU PUIN CIN Description Logical 1 input voltage high level Logical 0 input voltage low level Falling input trigger threshold Rising edge trigger threshold Schmitt trigger voltage hysteresis Logical 1 input high level current leakage Logical 0 input low level current leakage (no internal pull-up resistor) Logical 0 input low level current leakage (with internal pull-up resistor) Internal pull-up resistance (TA=+25C) Pin input capacitance Min +2.10 +0.90 +1.60 +0.65 -10.00 +40.00 15.00 - +0.90 +1.30 +2.10 +0.95 +10.00 +120.00 20.00 15.00 Table 5.19: Digital output characteristics, supply voltage of VDD=+3.0V to +3.6V Symbol VOH VOL IOH-LP IOL-LP IOH-HP IOL-HP Description Logical 1 output voltage high level Logical 0 output voltage low level Logical 1 output high level current sourcing Logical 0 output low level current sinking Logical 1 output high level current sourcing (pin 10 and pin 13 to pin 15) Logical 0 output low level current sinking (pin 10 and pin 13 to pin 15) DSH12435-15 | 3/2018 Min +2.4 -8.0 -16.0 +0.4 +8.0 +16.0 - 23 Datasheet: ZM5202 5.9 RF CHARACTERISTICS 5.9.1 TRANSMITTER Measured at an ambient temperature of TA=-10C to +85C and a supply voltage of VDD=+2.3V to +3.6V. The transmission power is adjusted by setting the value of the RFPOW register. Table 5.20: Transmitter performance Symbol Description RF output power delivered to the antenna, RFPOW=63 RF output power delivered to the antenna, RFPOW=01 2nd harmonic, RFPOW=63 2nd harmonic, RFPOW=48 2nd harmonic, RFPOW=32 2nd harmonic, RFPOW=20 2nd harmonic, RFPOW=8 3rd harmonic, RFPOW=63 3rd harmonic, RFPOW=48 3rd harmonic, RFPOW=32 3rd harmonic, RFPOW=20 3rd harmonic, RFPOW=8 Phase noise at 30kHz Phase noise at 100kHz Phase noise at 1MHz Phase noise at 10MHz Phase noise at 100MHz Channel bandwidth, 9.6kbps Channel bandwidth, 40kbps Channel bandwidth, 100kbps Transmit Power (dBm) P63 P01 PH2-63 PH2-48 PH2-32 PH2-20 PH2-8 PH3-63 PH3-48 PH3-32 PH3-20 PH3-8 PN30kHz PN100kHz PN1MHz PN10MHz PN20MHz BW9.6 BW40 BW100 Min +2.9 -29.0 - Typ +4.0 -26.1 -57.3 -60.2 -61.9 -59.6 -51.3 -45.4 -45.8 -45.6 -47.6 -46.6 -88.1 -95.2 -107.3 -113.1 -113.8 90.0 90.0 110.0 Max - Unit dBm dBm dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz kHz kHz kHz 6 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 0 5 10 15 20 25 30 35 40 45 50 55 60 RFPOW Setting Figure 5.3: Typical transmit power vs. RFPOW setting The transmitter is calibrated from factory. Refer to [3] for more information. 24 DSH12435-15 | 3/2018 Datasheet: ZM5202 5.9.2 RECEIVER Measured over an ambient temperature of TA=+25C and a supply voltage of VDD=+2.3V to +3.6V. Table 5.21: Receiver sensitivity P9.6 P40 P100 Symbol Description Sensitivity at 9.6kbps, FER < 1% Sensitivity at 40kbps, FER < 1% Sensitivity at 100kbps, FER < 1% Min - Typ -102.7 -99.0 -93.0 Max -101.0 -97.2 -91.8 Unit dBm dBm dBm Sensitivity (dBm) -91 -94 -97 9.6 kbps 40 kbps -100 100 kbps -103 -106 -25 0 25 50 75 100 Temperature (C) Figure 5.4: Typical sensitivity vs. temperature DSH12435-15 | 3/2018 25 Datasheet: ZM5202 Table 5.22: Receiver performance Symbol CCR9.6 BI1MHZ-9.6 BI2MHZ-9.6 BI5MHZ-9.6 BI10MHZ-9.6 BI100MHZ-9.6 CCR40 BI1MHZ-40 BI2MHZ-40 BI5MHZ-40 BI10MHZ-40 BI100MHZ-40 CCR100 BI1MHZ-100 BI2MHZ-100 BI5MHZ-100 BI10MHZ-100 BI100MHZ-100 RSSIRANGE RSSILSB PLO IIP3 BW9.6 BW40 BW100 Description Co-channel rejection, 9.6kbps Blocking immunity 3 at f=1MHz, 9.6kbps Blocking immunity at f=2MHz, 9.6kbps Blocking immunity at f=5MHz, 9.6kbps Blocking immunity at f=10MHz, 9.6kbps Blocking immunity at f=100MHz, 9.6kbps Co-channel rejection, 40kbps Blocking immunity at f=1MHz, 40kbps Blocking immunity at f=2MHz, 40kbps Blocking immunity at f=5MHz, 40kbps Blocking immunity at f=10MHz, 40kbps Blocking immunity at f=100MHz, 40kbps Co-channel rejection, 100kbps Blocking immunity at f=1MHz, 100kbps Blocking immunity at f=2MHz, 100kbps Blocking immunity at f=5MHz, 100kbps Blocking immunity at f=10MHz, 100kbps Blocking immunity at f=100MHz, 100kbps Dynamic range of the RSSI measurement Resolution of the RSSI measurement LO leakage at f=200kHz and f=325kHz Input 3rd order intercept point Intermediate frequency filter bandwidth, 9.6kbps Intermediate frequency filter bandwidth, 40kbps Intermediate frequency filter bandwidth, 100kbps Min - Typ -3.9 43.5 52.6 70.6 73.9 85.7 -9.1 40.2 48.0 65.2 67.7 82.0 -8.1 30.2 35.2 59.0 62.6 76.0 70.0 1.5 -84.4 -12.0 300.0 300.0 600.0 Max -80.0 - Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB dB dBm dBm kHz kHz kHz 3 Blocker level is defined relative to the wanted receiving signal and measured with the wanted receiving signal 3dB above the sensitivity level 26 DSH12435-15 | 3/2018 Received Power (dBm) Datasheet: ZM5202 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 -96 -102 -108 -114 -120 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 Received Signal Strength Indicator Value (RSSI) Figure 5.5: Typical input power vs. RSSI value First-order approximation: [] 1.56 x - 161.45, 5.9.3 REGULATORY COMPLIANCE [40,80] The ZM5202 has been tested on the ZDP03A Z-Wave Development Platform to be compliant with the following regulatory standards. [4] * * * * * ACMA COMPLIANCE o AS/NZS 4268 o CISPR 22 CE COMPLIANCE o EN 300 220-1/2 o EN 301 489-1/3 o EN 55022 o EN 60950-1 o EN 61000-4-2/3 o EN 62479 FCC COMPLIANCE o FCC CFR 47 Part 15 Subpart C 15.249 IC COMPLIANCE o RSS-GEN o RSS-210 o ANSI C63.10 MIC COMPLIANCE O ARIB STD-T108 DSH12435-15 | 3/2018 27 Datasheet: ZM5202 6 Z-WAVE FREQUENCIES Table 6.1: Z-Wave RF specification Data rate 9.6kbps 40kbps 100kbps Modulation Frequency deviation Frequency accuracy Coding Frequency Shift Keying (FSK) fC20kHz fC13ppm Manchester encoded FSK fC20kHz fC13ppm Non-return to Zero (NRZ) Gaussian Frequency Shift Keying (GFSK) fC29.3kHz fC13ppm NRZ United Arab Emirates 868.42 MHz 868.40 MHz 869.85 MHz E Australia 921.42 MHz 921.40 MHz 919.80 MHz H Brazil 921.42 MHz 921.40 MHz 919.80 MHz H Canada 908.42 MHz 908.40 MHz 916.00 MHz U Chile 908.42 MHz 908.40 MHz 916.00 MHz U China 868.42 MHz 868.40 MHz 869.85 MHz E European Union 868.42 MHz 868.40 MHz 869.85 MHz E Hong Kong 919.82 MHz 919.80 MHz 919.80 MHz H Israel 916.02 MHz 916.00 MHz - U India 865.20 MHz 865.20 MHz 865.20 MHz E Japan - - 922.50 MHz H - - 923.90 MHz H - - 926.30 MHz H - - 920.90 MHz H - - 921.70 MHz H - - 923.10 MHz H Mexico 908.42 MHz 908.40 MHz 916.00 MHz U Malaysia 868.12 MHz 868.10 MHz 868.10 MHz E New Zealand 921.42 MHz 921.40 MHz 919.80 MHz H Russia 869.02 MHz 869.00 MHz - E Singapore 868.42 MHz 868.40 MHz 869.85 MHz E - - 922.50 MHz H - - 923.90 MHz H - - 926.30 MHz H United States 908.42 MHz 908.40 MHz 916.00 MHz U South Africa 868.42 MHz 868.40 MHz 869.85 MHz E Korea Taiwan 28 DSH12435-15 | 3/2018 Datasheet: ZM5202 7 MODULE INFORMATION 7.1 MODULE MARKING Table 7.1: Marking description Regional information REGION: E U H Figure 7.1: Marking placement 7.2 MODULE DIMENSIONS Table 7.2: Dimensions Length 13.6mm +/- 0.3 mm Width 12.5mm +/- 0.3 mm Height 1.9mm +/- 0.3 mm 8 PROCESS SPECIFICATION Specification Description MSL 3 Moisture Sensitivity Level designed and manufactured according to JEDEC J-STD-020C REACH REACH is a European Community Regulation on chemicals and their safe use (EC 1907/2006). It deals with the Registration, Evaluation, Authorisation and Restriction of Chemical substances RoHS Designed in compliance with The Restriction of Hazardous Substances Directive (RoHS) DSH12435-15 | 3/2018 29 Datasheet: ZM5202 9 9.1 PCB MOUNTING AND SOLDERING RECOMMENDED PCB MOUNTING PATTERN 2.65mm 4.15mm 5.65mm 7.15mm 8.65mm 10.90mm 0.00mm 6 5 4 3 2 1 12.91mm 12.50mm 9.25mm 7 7.75mm 8 6.25mm 9 4.75mm 10 3.25mm 11 18 Top View 12 13 14 7.75mm 17 6.00mm 16 15 0.00mm -0.41mm 0.00mm 1.40mm 1.66mm 1.40mm 0.55mm Signal Pattern 14.01mm 13.60mm 10.90mm 7.15mm 5.65mm 4.15mm 2.65mm 0.00mm -0.41mm 1.10mm 0.70mm Ground Pattern Figure 9.1: Top view of land pattern SOLDERING INFORMATION The soldering details to properly solder the ZM5202 module on standard PCBs are described below. The information provided is intended only as a guideline and Silicon Labs is not liable if a selected profile does not work. See IPC/JEDEC J-STD-020D.1 for more information. 30 DSH12435-15 | 3/2018 Datasheet: ZM5202 Table 9.1: Soldering details PCB solder mask expansion from landing pad edge PCB paste mask expansion from landing pad edge PCB process PCB finish Stencil aperture Stencil thickness Solder paste used Flux cleaning process 0.1 mm 0.0 mm Pb-free (Lead free for RoHS 4compliance) Defined by the manufacturing facility (EMS) or customer Defined by the manufacturing facility (EMS) or customer Defined by the manufacturing facility (EMS) or customer Defined by the manufacturing facility (EMS) or customer Defined by the manufacturing facility (EMS) or customer Figure 9.2: Typical reflow profile 4 RoHS = Restriction of Hazardous Substances Directive, EU DSH12435-15 | 3/2018 31 Datasheet: ZM5202 10 ORDERING INFORMATION Table 10.1: Ordering codes Orderable Device Status ZM5202AE-CME3R ACTIVE Package Type SOM 18 Minimum Order Quantity 1000 pcs. ZM5202AU-CME3R ACTIVE SOM 18 1000 pcs. ZM5202AH-CME3R ACTIVE SOM 18 1000 pcs. Pins Description ZM5202 module, RevA, 868MHz Band, Tape and Reel ZM5202 module, RevA, 908MHz Band, Tape and Reel ZM5202 module, RevA, 921MHz Band, Tape and Reel 10.1 TAPE AND REEL INFORMATION Shipment will be provided in tape with dimensions according to specifications in the following sections. Reel can be from two alternative sources A or B with following dimensions and design. Main difference between alternatives is design and visual look. Dimensions has been kept as equal as possible. 32 DSH12435-15 | 3/2018 Datasheet: ZM5202 10.1.1 TAPE DIMENSIONS Figure 10.1: Tape information DSH12435-15 | 3/2018 33 Datasheet: ZM5202 Parameter Pin 1 Quadrant 34 Value Pocket Quadrant Q3 DSH12435-15 | 3/2018 Datasheet: ZM5202 10.1.2 REEL SUPPLIER A Figure 10.2: Reel information DSH12435-15 | 3/2018 35 Datasheet: ZM5202 10.1.3 REEL SUPPLIER B A N 36 DSH12435-15 | 3/2018 Datasheet: ZM5202 11 ABBREVIATIONS Abbreviation 2FSK 2GFSK ACM ACMA ADC AES API APM AV BOD CBC CDC CE COM CPU CRC D DD+ DAC DC DMA ECB EMS ESD FCC FER FET FLiRS FSK GFSK GP GPIO I I/O IC IF IGBT INT IPC IR IRAM ISM ISP ITU JEDEC LED lsb LSB MCU MIC DSH12435-15 | 3/2018 Description 2-key Frequency Shift Keying 2-key Gaussian Frequency Shift Keying Abstract Control Model Australian Communications and Media Authority Analog-to-Digital Converter Advanced Encryption Standard Application Programming Interface Auto Programming Mode Audio Video Brown-Out Detector Cipher-Block Chaining Communications Device Class Conformite Europeenne Communication Central Processing Unit Cyclic Redundancy Check Differential Differential Minus Differential Plus Digital-to-Analog Converter Direct Current Direct Memory Access Electronic CodeBook Electronic Manufacturing Services Electro-Static Discharge Federal Communications Commission Frame Error Rate Field Effect Transistor Frequently Listening Routing Slave Frequency Shift Keying Gaussian Frequency Shift Keying General Purpose General Purpose Input Output Input Input / Output Integrated Circuit Intermediate Frequency Insulated-Gate Bipolar Transistor Interrupt Interconnecting and Packaging Circuits Infrared Indirectly addressable Random Access Memory Industrial, Scientific, and Medical In-System Programming International Telecommunications Union Joint Electron Device Engineering Council Light-Emitting Diode Least Significant Bit Least Significant Byte Micro-Controller Unit Ministry of Internal affairs and Communications, Japan 37 Datasheet: ZM5202 Abbreviation MISO MOSI msb MSB NMI NRZ NVM NVR O OEM OFB Pb PCB POR PWM RAM RF RoHS ROM RS-232 RX S SAW SCK SFR SiP SOM SPI SRAM T0 T1 TX UART USB WUT XRAM XTAL ZEROX 38 Description Master In, Slave Out Master Out, Slave In Most Significant Bit Most Significant Byte Non-Maskable Interrupt Non-Return-to-Zero Non-Volatile Memory Non-Volatile Registers Output Original Equipment Manufacturer Output FeedBack Lead Printed Circuit Board Power-On Reset Pulse Width Modulator Random Access Memory Radio Frequency Restriction of Hazardous Substances Read Only Memory Recommended Standard 232 Receive Supply Surface Acoustic Wave Serial Clock Special Function Register System-in-Package System-On-Module Serial Peripheral Interface Static Random Access Memory Timer 0 Timer 1 Transmit Universal Asynchronous Receiver Transmitter Universal Serial Bus Wake-Up Timer External Random Access Memory Crystal Zero Crossing DSH12435-15 | 3/2018 Datasheet: ZM5202 12 REVISION HISTORY Date 2018/02/19 2017/06/27 2017/04/11 Version 15 14 13 2017/02/09 2016/12/20 2016/11/24 2016/10/26 2016/4/29 12 11 10 9 8 2015/4/28 7 2015/1/30 2013/12/13 2013/12/12 6B 5 4A 2013/10/31 3B 2013/10/29 3A DSH12435-15 | 3/2018 Affected 6, Table 6.1 5.9.1 Figure 4.1 Figure 9.1 10.1.1 Table 5.5 10 Table 6.1 $2.2.4 Figure 9.1 Table 9.2 8 10.1 Figure 4.1 7.2, Table 7.2 Table 6.1 Table 2.1 Table 2.1, 2.4.1 Cover, Figure 2.1, Table 2.3, Figure 2.7, Table 4.3, 5.1, Table 5.5, Figure 5.2, Table 5.20, Figure 5.3, Table 5.22, 5.9.2 Cover, Figure 2.1, 2.1, Table 2.2, Table 2.3, 2.2.2, 2.2.9, Figure 2.5, 2.2.12, 4.1, Table 4.3, Table 4.8, Table 4.10, Table 5.1, Table 5.5, Figure 5.2, Table 5.12, Table 5.16, Table 5.18, Table 5.20, Figure 5.3, 5.9.1, Revision Updated Korea frequency Clarified transmitter is calibrated from factory Figure 4.1 updated with to scale drawing, and placement of pads, some notations changed from diameter to radius. Figure 9.1 updated dimensions and placement of land patterns to fit module pads. Pin 1 Quadrant corrected to "Q3" Cleaned up "TDB" Add Reel information from source B Corrected frequency accuracy to worst case figure Updated wording in section 2.2.4 Crystal driver and system clock Updated to align with SD3502 recommendation. Removed - information included in updated Figure 9.1 Added section Process Specification Added orientation of component in tape Corrected length of Signal Pin and Ground Pin Added tolerances to module dimensions Added frequency accuracy Entries in table of CPU modes rephrased Reduced the RESET_N high time Increased the RESET_N low time Updated performance values Added LED controller Updated INT1 pins Updated caption Changed to master I/O mode Updated final test description Updated TX current consumption Updated TX power and performance Updated LO leakage Updated equation for 1st-order approximation Updated performance values Updated matching description Added CPU modes Updated pin numbers Added source impedance formula Added LED controller Updated SPI slave connection Added Timers Removed `weak' from pull-up description Updated pin names Added LED interface pin Added Timer interface pins Added maximum RF input Updated current consumption values Updated transmit current consumption Updated programming time Added pull-up resistor value Updated TX power and harmonics Added mandatory TX calibration 39 Datasheet: ZM5202 Date Version 2013/09/12 2A 2013/06/03 1G 2013/05/31 2013/05/20 2013/02/22 2013/02/18 1E 1C 1A 1A 40 Affected Table 5.21, Figure 5.4, Table 5.22, Figure 5.5, Figure 7.1 Cover, 2.2.5, 2.2.10, 2.2.11, Figure 4.1, 5.9, Table 5.15, Table 5.18, 6, Table 7.2 Table 2.3, Table 5.8 All All All All Revision Updated sensitivity values Updated blocking and LO leakage Updated RSSI values Updated module marking Updated the features and module items Added GPIO description Added peripheral designators Added pin dimensions Removed impedance plots Changed the supply voltage range and clock speed of external NVM Corrected Korean frequency Added module dimensions Removed empty line from interrupt table Added state transition times Updated IO characteristics Updated layout, and data from the latest corner tests Preliminary draft released Initial draft DSH12435-15 | 3/2018 DATASHEET: ZM5202 13 REFERENCES [1] [2] [3] [4] INS11681, Instruction, "500 Series Z-Wave Chip Programming Mode" DSH12436, Datasheet, "ZDB5202 Z-Wave Development Board" INS12213, Instruction, "500 Series Hardware Integration Guide" DSH11243, Datasheet, "ZDP03A, Z-Wave Development Platform" DSH12435-15 | 3/2018 41 Smart. Connected. Energy-Friendly. Products Quality www.silabs.com/products www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. 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