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DATASHEET: ZM5202

DSH12435-15 | 3/2018 1

FULLY INTEGRATED Z-WAVE® WIRELESS MODULE

The Silicon Labs ZM5202 module is a low-cost fully integrated Z-Wave

module in a small 12.5mm x 13.6mm x 1.9mm form factor. It is an ideal

solution for home control applications such as access control, appliance

control, AV control, building automation, energy management, lighting,

security, and sensor networks in the “Internet of Things”.

It contains all the required passive components, including the crystal and a

SAW filter to provide a complete Z-Wave system. The ZM5202 module

remains pad and pin compatible with the ZM3102 and the ZM4102

Z-Wave modules.

The ZM5202 module is based on an 8-bit 8051 CPU core, which is

optimized to handle the data and link management requirements of a

Z-Wave node. The patented Z-Wave protocol supports automatic

retransmissions, collision avoidance mechanisms, frame

acknowledgements, frame CRCs, frequency agility, and full mesh routing to

ensure a highly reliable and robust wireless communication solution.

An integrated baseband controller, sub-1 GHz radio transceiver, a

comprehensive set of hardware peripherals, 16kB of SRAM, and 128kB of

Flash memory is available for OEM applications and the Z-Wave protocol

stack.

Features

• Pad and pin compatible with the ZM3102

and ZM4102

• ITU G.9959 compliant

Module

• Optimized 8051 CPU Core

• 128kB Flash

• 16kB SRAM

• UART with speed up to 230.4kbps

• SPI with speed up to 8MHz

• 2 Interrupt Inputs

• 4-channel 12/8-bit rail-to-

rail ADC with

VDD/internal/external voltage reference

• PWM Output

• 10 General Purpose IOs

• Hardware AES-128 security engine

• 1000 step dimmer (TRIAC/FET)

• Power-On-Reset/Brown-out Detection

• Supply voltage range from 2.3V to 3.6V for

optional battery operation

• TX mode current typ. 36mA@0dBm

• RX mode current typ. 32mA

• Normal mode current typ. 15mA

• Sleep mode current typ. 1µA

• Wake-up timer current typ. 700nA

• Less than 1ms cold start-up time

Radio Transceiver

• Receiver sensitivity with SAW filter down

to -103dBm @ 9.6kbps

• Transmit power with SAW filter up to

+4dBm

• Z-Wave 9.6/40/100kbps data rates

• Supports all Z-Wave sub-1 GHz frequency

bands (865.2 MHz to 926.3 MHz)

• Supports multi-channel frequency agility

and listen before talk

• Regulatory Compliance

ACMA: AS/NZS 4268

CE: EN 300 220/489

FCC: CFR 47 Part 15

IC: RSS-GEN/210

MIC: ARIB STD-T108

Datasheet: ZM5202

2 DSH12435-15 | 3/2018

1 CONTENT

2 OVERVIEW .......................................................................................................................................................................... 4

2.1 CPU ...................................................................................................................................................................................... 5

2.2 PERIPHERALS ........................................................................................................................................................................... 5

2.2.1 Advanced Encryption Standard Security Processor ..................................................................................................... 5

2.2.2 Analog-to-Digital Converter ........................................................................................................................................ 5

2.2.3 Brown-Out Detector / Power-On-Reset ....................................................................................................................... 6

2.2.4 Crystal Driver and System Clock .................................................................................................................................. 6

2.2.5 Dimmer........................................................................................................................................................................ 6

2.2.6 General Purpose Input/Output .................................................................................................................................... 7

2.2.7 General Purpose Timer / Pulse Width Modulator ....................................................................................................... 7

2.2.8 Interrupt Controller ..................................................................................................................................................... 8

2.2.9 Light-Emitting Diode Contoller .................................................................................................................................... 8

2.2.10 Reset Controller ........................................................................................................................................................... 8

2.2.11 Serial Peripheral Interface ........................................................................................................................................... 9

2.2.12 Timers ........................................................................................................................................................................ 10

2.2.13 Universal Asynchronous Receiver / Transmitter ....................................................................................................... 10

2.2.14 Wake-Up Timer ......................................................................................................................................................... 10

2.2.15 Watchdog .................................................................................................................................................................. 10

2.2.16 Wireless Transceiver.................................................................................................................................................. 11

2.3 MEMORY MAP ...................................................................................................................................................................... 11

2.4 MODULE PROGRAMMING ........................................................................................................................................................ 12

2.4.1 Entering In-System Programming Mode ................................................................................................................... 12

2.5 POWER SUPPLY REGULATOR .................................................................................................................................................... 12

3 TYPICAL APPLICATION ...................................................................................................................................................... 13

4 PIN CONFIGURATION ........................................................................................................................................................ 14

4.1 PIN FUNCTIONALITY ................................................................................................................................................................ 15

5 ELECTRICAL CHARACTERISTICS .......................................................................................................................................... 18

5.1 TEST CONDITIONS .................................................................................................................................................................. 18

5.1.1 Typical Values ............................................................................................................................................................ 18

5.1.2 Minimum and Maximum Values ............................................................................................................................... 18

5.2 ABSOLUTE MAXIMUM RATINGS ................................................................................................................................................ 19

5.3 GENERAL OPERATING RATINGS ................................................................................................................................................. 19

5.4 CURRENT CONSUMPTION ........................................................................................................................................................ 19

5.5 SYSTEM TIMING ..................................................................................................................................................................... 20

5.6 NON-VOLATILE MEMORY ........................................................................................................................................................ 21

5.7 ANALOG-TO-DIGITAL CONVERTER ............................................................................................................................................. 22

5.8 GENERAL PURPOSE INPUT OUTPUT ........................................................................................................................................... 22

5.9 RF CHARACTERISTICS .............................................................................................................................................................. 24

5.9.1 Transmitter................................................................................................................................................................ 24

5.9.2 Receiver ..................................................................................................................................................................... 25

5.9.3 Regulatory Compliance ............................................................................................................................................. 27

6 Z-WAVE FREQUENCIES ...................................................................................................................................................... 28

7 MODULE INFORMATION ................................................................................................................................................... 29

Datasheet: ZM5202

DSH12435-15 | 3/2018 3

7.1 MODULE MARKING ................................................................................................................................................................ 29

7.2 MODULE DIMENSIONS ............................................................................................................................................................ 29

8 PROCESS SPECIFICATION ................................................................................................................................................... 29

9 PCB MOUNTING AND SOLDERING..................................................................................................................................... 30

9.1 RECOMMENDED PCB MOUNTING PATTERN ................................................................................................................................ 30

SOLDERING INFORMATION ................................................................................................................................................................... 30

10 ORDERING INFORMATION ............................................................................................................................................ 32

10.1 TAPE AND REEL INFORMATION ................................................................................................................................................. 32

10.1.1 Tape dimensions........................................................................................................................................................ 33

10.1.2 Reel Supplier A .......................................................................................................................................................... 35

10.1.3 Reel Supplier B ........................................................................................................................................................... 36

11 ABBREVIATIONS ............................................................................................................................................................ 37

12 REVISION HISTORY ........................................................................................................................................................ 39

13 REFERENCES .................................................................................................................................................................. 41

Datasheet: ZM5202

4 DSH12435-15 | 3/2018

2 OVERVIEW

The ZM5202 module is a fully integrated module containing all the hardware and firmware required to add Z-Wave functionality

to OEM products. The ZM5202 module contains the SD3502 chip along with all the required passives for supply decoupling,

matching, crystal and a SAW filter as illustrated in Figure 2.1. The module only requires a stable DC supply and an antenna

matched to 50Ω for operation.

ZM5202

Voltage

Regulator

UARTSPI

SD3502

Decoupling

ADC

POR / BOD

Power

Manager

128kB Flash

Memory

12kB XRAM

4kB XRAM

256B IRAM

128B Critical

Memory

RAM

Interrupt

Controller

8051W CPU

Sub-1 GHz

Wireless

Transceiver

Matching /

SAW Filter

32MHz

XTAL

GPIO

XTAL Driver

Clock

Control

GP Timer /

PWM

8051 Timers

Wake-Up

Timer

Watchdog

Dimmer

AES

Special

Function

Baseband

Controller

Modem

LED

Controller

Figure 2.1: Functional block diagram

The module is verified to pass regulatory requirements and qualified to meet Z-Wave specifications. The crystal and the SAW

filter are key elements that provide frequency stability of the RF output signal, and excellent RF immunity to interfering signals

in the receiver path. The ZM5202 module is fully backwards compatible with the ZM4102 and ZM3102 modules in terms of the

available GPIOs, hardware peripherals, and footprint. Unlike the ZM4102, it does not require a higher voltage during

programming.

Datasheet: ZM5202

DSH12435-15 | 3/2018 5

2.1 CPU

The CPU is binary compatible with the industry standard 803x/805x CPU and is operated at 32MHz. Its cycle performance is

improved by six times relative to the standard 8051 implementation.

The CPU can be placed in 4 main modes as described in Table 2.1.

Table 2.1: CPU modes

Mode

Description

ACTIVE

• Code is executed

• Peripherals are available

• All I/O’s are resistively pulled high

•

Use a short ( up to 4ms) reset-low pulse to enter the reset of active state

SLEEP

• Wake-up timer available

• Critical memory retention available

• I/O’s states according to user configuration

•

Use API call to enter from ACTIVE mode

PROGRAMMING

DURING

SUSTAINED

RESET

• Used to program the internal FLASH via SPI1

• Code is not executed

• All I/O’s are resistively pulled high

•

Programming requires external control of the reset pin plus the SPI port

EXTERNAL NVM

PROGRAMMING

• Used to program an external NVM (FLASH/EPROM) (optionally) wired to the SPI port

• Code is not executed

• All I/O’s are resistively pulled high

•

External NVM programming requires external control of the RESET pin (plus the NVM-SPI port)

2.2 PERIPHERALS

2.2.1 ADVANCED ENCRYPTION STANDARD SECURITY PROCESSOR

The Z-Wave protocol specifies the use of Advanced Encryption Standard (AES) 128-bit block encryption for secure applications.

The built-in Security Processor is a hardware accelerator that encrypts and decrypts data at a rate of 1 byte per 1.5µs. It encodes

the frame payload and the message authentication code to ensure privacy and authenticity of messages. The processor supports

Output FeedBack (OFB), Cipher-Block Chaining (CBC), and Electronic CodeBook (ECB) modes to target variable length messages.

Payload data is streamed in OFB mode, and authentication data is processed in CBC mode as required by the Z-Wave protocol.

The processor implements two efficient access methods: Direct Memory Access (DMA) and streaming through Special Function

2.2.2 ANALOG-TO-DIGITAL CONVERTER

The Analog-to-Digital Converter (ADC) is capable of sampling one of the five available input voltage sources and returns an 8 or

12-bit unsigned representation of the selected input scaled relative to the selected reference voltage, as described by the

formula below.

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

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,

 

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The ADC is capable of operating rail to rail, while the following input configurations apply (VBG = built-in Band-gap 1.25V,

VDD = supply voltage, VIN = pin 10 and pin 13 to pin 15):

Datasheet: ZM5202

6 DSH12435-15 | 3/2018

Table 2.2: ADC voltage source configuration options

Source

Description

The sampling input voltage

Pin 10, pin 13, pin 14, pin15, V

VREF+

The positive node of the reference voltage

Pin 14, VBG, VDD

VREF-

The negative node of the reference voltage

Pin 13, GND

If the sampling input voltage crosses a predefined lower or upper voltage threshold, an interrupt is triggered. Setting VIN = VBG

and VRFE+ = VDD implements a battery monitor. All inputs (VIN, VREF+, VREF-) must be driven by low impedance (Rsource) voltage

sources, to suppress offsets caused by GPIO input leakage of up to 10µA.

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 

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If the output impedance of the signal source is larger than Rsource, an external buffer must be used.

2.2.3 BROWN-OUT DETECTOR / POWER-ON-RESET

When a cold start-up occurs, an internal Power-On-Reset (POR) circuit ensures that code execution does not begin unless the

supply voltage is sufficient. After which, an internal Brown-Out Detector (BOD) circuit guarantees that faulty code execution

does not occur by entering the reset state, if the supply voltage drops below the minimum operating level. These guarantees

apply equally in both the active and sleep modes.

2.2.4 CRYSTAL DRIVER AND SYSTEM CLOCK

The system clock and RF frequencies are derived from the module mounted 32MHz crystal (XTAL), which internal system

performance is factory trimmed to guarantee initial RF frequency precision. The temperature and 5 years aging margin for the

internal 32MHz XTAL is 15 ppm.

2.2.5 DIMMER

The Dimmer allows you to build leading edge or trailing edge dimmers to cover dimming applications with electronic

transformers, halogen or incandescent lamps, wire-wound transformers, etc. The classic leading edge method requires an

external TRIAC while the more versatile and electronic transformer friendly trailing edge method requires external Field Effect

Transistors (FET) or Insulated-Gate Bipolar Transistors (IGBT). The Dimmer regulates the power-on duration with a precision of

1000 steps in each 50 Hz or 60 Hz half-period. Once the Dimmer has been initialized, it will run at the requested power setting

without any assistance from the MCU.

2.2.5.1 LEADING EDGE MODE

This is the classic TRIAC mode. Based on the dim-level requested, the Dimmer determines when and how the power is switched

on. To ensure reliable handling in presence of inductive loads, multiple trigger pulses are automatically appended when needed.

Datasheet: ZM5202

DSH12435-15 | 3/2018 7

Figure 2.2: Leading edge mode (TRIAC)

2.2.5.2 TRAILING EDGE MODE

When FET/IGBT Mode is enabled, the Dimmer allows power to grow softly after each voltage zero crossing event. The Dimmer

controls the turn-off time (or angle) by switching off the FET/IGBT.

Figure 2.3: Trailing edge mode (FET/IGBT)

2.2.5.3 ZERO CROSSING SYNCHRONIZATION

The Dimmer detects and synchronizes to the AC voltage via a zero-crossing acquisition signal provided by the dimming

application. This signal must be connected to pin 14 and GPIO input level compliant. Multiple single and dual event-per-cycle

formats are supported. Fixed phase delays are accepted and easily compensated for through the Z-Wave API.

2.2.6 GENERAL PURPOSE INPUT/OUTPUT

There are 10 General Purpose Input/Output (GPIO) pins. These pins can be configured individually as Schmitt triggered inputs

with/without internal pull-up or open-drain/push-pull outputs. The GPIO pins can be overridden by peripheral functions and

each pin is able to drive loads with a minimum of 8mA.

2.2.7 GENERAL PURPOSE TIMER / PULSE WIDTH MODULATOR

A 16-bit General Purpose (GP) auto-reload timer could be provided with either an accurate 4MHz clock or an approximate 32kHz

clock. It can be configured to auto-reload a predefined value and may be polled or programmed to generate an interrupt when

Mains voltage

TRIAC firing pulses

Current through

Mains voltage

FET/IGBT firing pulses

Current through load

Datasheet: ZM5202

8 DSH12435-15 | 3/2018

the register wraps around. It also serves as a Pulse Width Modulated (PWM) signal generator on pin 4. A simple low frequency

Digital-to-Analog Converter (DAC) could be designed using a few external passive components.

2.2.8 INTERRUPT CONTROLLER

Fifteen interrupt sources are supported, including external interrupt sources on the pin 3 and pin 4. The interrupts are shared

between the user application and the Z-Wave protocol. Priorities for the interrupts are pre-assigned by the Z-Wave protocol

implementation. Therefore, constraints for the user application apply.

Table 2.3: Interrupt vector table

Vector

Interrupt Name

Priority

Resources served

INT0

External interrupt 0 via pin 4

INT1

External interrupt 1 either via pin 3, or pin 3 and pin 4

UART0

UART0 end of RX or TX

Multi

AES, SPI, and many more reserved resources

Dimmer

External interrupt via ZEROX pin 14. Supported by the Dimmer API

General Purpose Timer

General Purpose Timer overflow

ADC

Battery monitor, ADC low and high monitor

RF DMA

NMI

Non Maskable Interrupt for debugger and more

2.2.9 LIGHT-EMITTING DIODE CONTOLLER

The Light-Emitting Diode (LED) controller provides a single channel PWM generator on pin 5, that can be used to control the

current drawn through an LED.

Table 2.4: Properties of the LED controller

Property

Description

Pulse width resolution

16-bit

Frequency

488 Hz

No. of channels

Placement of the pulse within a single period

Normal mode (Pulses of all channels are synchronized to the beginning of a

period)

Skewed mode (In each consecutive channel, pulses are shifted 25% of the

period relative to the previous channel)

Drive strength

8mA

2.2.10 RESET CONTROLLER

After a reset event, the MCU is reinitialized in less than 1ms. This delay is mostly due to the charge time of the internal and

external supply capacitances, and bringing the XTAL clock into a stable oscillation. Multiple events may cause a reset. Therefore,

the actual cause is latched by hardware and may be retrieved via software when the system resumes operation. Some reset

methods deliberately leave the state of GPIO pins unchanged, while other GPIO pins are set to high impedance with an internal

pull-up.

Datasheet: ZM5202

DSH12435-15 | 3/2018 9

Table 2.5: Supported reset methods

Reset Cause

Description

GPIO state

Maskable

BOR

Reset request generated by Brown-Out-

Reset hardware

High impedance with

pull-up

INT1

Reset request generated when a signal is

received on pin INT1, when the chip is in

power down mode

Unchanged

Yes

POR

Reset request generated by Power-On-

Reset hardware

High impedance with

pull-up

RESET_N

Reset request generated by the RESET_N

pin being de-asserted

High impedance with

pull-up

Software

Reset request generated in software.

Unchanged

Yes

WATCHDOG

Reset request generated by the

WATCHDOG Timer timing out

High impedance with

pull-up

Yes

WUT

Reset request generated by the Wake-

Up-Timer timing out

Unchanged

Yes

2.2.11 SERIAL PERIPHERAL INTERFACE

SPI1 Serial Peripheral Interface enables synchronous data transfers between devices.

Table 2.6: SPI1 signal modes

SPI1 Signal

SPI1 Function, master

MOSI

Data output

MISO

Data input

SCK

Clock output

During data transmission, SCK acts as a clock, while 8 bits of data are exchanged between the two devices within 8 cycles of SCK.

Figure 2.4: Flow of data between SPI master and slave

The module acts as a SPI master when controlling an external Non-Volatile Memory (NVM). The slave select (or chip select) of

the external NVM could be driven by an available GPIO. SPI1 slave mode is reserved for In-System Programming (ISP). Therefore,

SPI1 can only be used as a master.

SPI CLOCK

GENERATOR

MASTER

SCK

MISO

MOSI

SLAVE

Datasheet: ZM5202

10 DSH12435-15 | 3/2018

ZM5202

PX.Y

SPI SCK

SPI MOSI

SPI MISO

External NVM

CS_N

SPI SCK

SPI MOSI

SPI MISO

Figure 2.5: Typical interface to slave device

2.2.12 TIMERS

Timer 0 and Timer 1 are 16-bit counters that can be clocked from a fixed internal source or an external source. Except for the

use of external gating signals, the complete set of classic 8051 T0/T1 features is available.

Table 2.7: Timer sources

Timer

Fixed Internal Source

External Source

Timer 0

16 MHz

Pin 10

Timer 1

16 MHz

Pin 15

2.2.13 UNIVERSAL ASYNCHRONOUS RECEIVER / TRANSMITTER

The Universal Asynchronous Receiver / Transmitter (UART) is a hardware block operating independently of the 8051 CPU. It

offers full-duplex data exchange, up to 230.4kbps, with an external host microcontroller requiring an industry standard NRZ

asynchronous serial data format. The UART0 interface is available over pin 10 and pin15. A data byte is shifted as a start bit, 8

data bits (lsb first), and a stop bit, respectively, with no parity and hardware handshaking. Figure 2.6 shows the waveform of a

single serial byte. The UART is compliant with RS-232 when an external level converter is used.

START

BIT D0 D1D2D3 D4 D5 D6 D7 STOP

BIT

Figure 2.6: UART waveform

2.2.14 WAKE-UP TIMER

The Wake-Up Timer (WUT) plays an important role in maximizing battery life of applications like Frequently Listening Routing

Slave (FLiRS) Z-Wave nodes. It is available to customer applications via the Z-Wave API, and can be configured to wake a sleeping

node after 1 to 256 seconds. The programming resolution equals 8-bit fractions of 2 seconds, alternatively 8-bit fractions of 256

seconds. The WUT is automatically calibrated to the system clock when it is operational, maintaining an accuracy of <2%.

2.2.15 WATCHDOG

The watchdog helps prevents the CPU from entering a deadlock state. A timer that is enabled by default achieves this by

triggering a reset event in case it overflows. The timer overflows in 1 second, therefore it is essential that the software clear the

timer periodically. The watchdog is disabled when the chip is in power down mode, and automatically restarts with a cleared

timer when waking up to the active mode.

Datasheet: ZM5202

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2.2.16 WIRELESS TRANSCEIVER

The wireless transceiver is a sub-1 GHz ISM narrowband FSK radio, a modem, and a baseband controller. This architecture

provides an all-digital direct synthesis transmitter and a low IF digital receiver. The Z-Wave protocol currently utilizes 2-key

FSK/GFSK modulation schemes at 9.6/40/100 kbps data rates throughout a span of carrier frequencies from 865.2 to 926.3MHz.

The output power of the transmitter is configurable in the range -26dBm to +4dBm (VDD = 2.3V to 3.6V, TA = -10°C to +85°C). An

external front-end could be used to further increase the link budget if necessary.

2.3 MEMORY MAP

Figure 2.7 shows an illustration of the byte wise addressable memories that are shared between the user application and the

Z-Wave protocol stack. Additional ROM and NVR areas are used for boot code, calibration data, production data, and lock bytes.

Table 2.8: Description of memory blocks

Memory

Address Method

Exposed during Programming

Description

M1-M4

128kB Flash

Program

Memory

Yes

Flash memory, mapped in 3 banks of 32kB

slices over a 32kB common block, one read

access per 2 clock cycles.

M5-M6

16kB RAM

XRAM

Yes

SRAM’s split into 4kB and 12kB contiguous

blocks

256B RAM

IRAM

Bit addressable SRAM

128B RAM

XRAM

Critical SRAM for data persistency during

sleep mode

256B NVM

(API)

Cached high endurance non-volatile data

registers

M10

256B NVR

(API)

Yes

Flash area reserved for the Z-Wave

protocol, calibration data, production data,

and lock bytes

Datasheet: ZM5202

12 DSH12435-15 | 3/2018

2.4 MODULE PROGRAMMING

The code space and the NVR of the flash can be programmed and/or read through the SPI1 interface. [1]

2.4.1 ENTERING IN-SYSTEM PROGRAMMING MODE

The module can be placed into the In-System Programming (ISP) mode by asserting the active low RESET_N signal for 5.2ms. The

programming unit of the module then waits for the “Interface Enable” serial command before activating the ISP mode over the

SPI1.

2.5 POWER SUPPLY REGULATOR

While the supply to the digital I/O circuits is unregulated, on-chip low-dropout regulators derive all the 1.5 V and 2.5 V internal

supplies required by the Micro-Controller Unit (MCU) core logic, non-volatile data registers, flash, and the analogue circuitry.

CODE SPACE (FLASH)

0000

7FFF

Common

32k

8000

FFFF

Bank 3

Bank 2

Bank 1

32k

XRAM

128

12k

M7: RAM

RAM

M5: RAM

0000

0FFF

1000

1080

2000

4FFF

IRAM

256

M8: RAM

Figure 2.7: Non-API addressable memory blocks

Datasheet: ZM5202

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3 TYPICAL APPLICATION

An illustration of an application example using the ZM5202 module implementation follows. It is strongly recommended that the

power supply is decoupled sufficiently, and a pull-up resistor placed on the RESET_N signal if the host GPIO is unable to drive it.

ZM5202

RESET_N

INT1

GND

Matching

3V3

NVM

CS_N

SCK

3V3

VDD

HOLD_N

WP_N

3V3

VDD

PX.Y

SCK

MOSI

MISO

GND

Figure 3.1: Example of a standalone application with an external antenna

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14 DSH12435-15 | 3/2018

4 PIN CONFIGURATION

The layout of the pins on the ZM5202 module is shown in Figure 4.1.

Top View

0.00mm

0.50mm

1.00mm

0.74mm

1.30mm

1.00mm

0.65mm

Signal

Pin Ground

3.25mm

4.75mm

6.25mm

7.75mm

9.25mm

12.50mm

0.00mm

2.65mm

4.15mm

5.65mm

7.15mm

10.90mm

13.60mm

0.00mm

6.00mm

7.75mm

0.00mm

2.65mm

4.15mm

5.65mm

7.15mm

10.90mm

8.65mm

1514

0.25mm

12.25mm

13.35mm

Figure 4.1: Pin layout (top view)

Datasheet: ZM5202

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4.1 PIN FUNCTIONALITY

Table 4.1: Power and ground signals

Pin Name

Pin Location

Type1

Function

VDD

Module power supply.

GND

1, 6, 12, 16, 17

Ground. Must be connected to the

ground plane.

Table 4.2: Module control signal

Pin Name

Pin Location

Type

Function

RESET_N

Active low signal that places the module

in a reset/programmable state.

Table 4.3: SPI1 interface signals

Pin Name

Pin Location

Type

Function in Reset State

Function in Active State

SPI1 SCK

SPI1 Clock input with internal pull-up.

SPI1 Clock. Output in master mode.

SPI1 MISO

Serial data transmit when in SPI1 ISP

mode, high impedance otherwise with

internal pull-up.

Master-In-Slave-Out serial data. Input in

master mode.

SPI1 MOSI

Waits for the ”Interface Enable” serial

command after 5.2ms. Enters SPI1 ISP

mode after command is received from the

host.

Master-Out-Slave-In serial data. Output in

master mode.

Table 4.4: UART0 interface signals

Pin Name

Pin Location

Type

Function in Reset State

Function in Active State

UART0 RX

High impedance with internal pull-up.

Receive data from host serial port.

UART0 TX

High impedance with internal pull-up.

Transmit data to host serial port.

Table 4.5: ADC interface signals

Pin Name

Pin Location

Type

Function in Reset State

Function in Active State

ADC0

High impedance with internal pull-up.

Analog-to-Digital converter input.

ADC1

High impedance with internal pull-up.

Analog-to-Digital converter input.

ADC2

High impedance with internal pull-up.

Analog-to-Digital converter input or

lower reference voltage.

ADC3

High impedance with internal pull-up.

Analog-to-Digital converter input or

higher reference voltage.

1 I = Input, O = Output, D+ = Differential Plus, D- = Differential Minus, S = Supply

Datasheet: ZM5202

16 DSH12435-15 | 3/2018

Table 4.6: External interrupt interface signals

Pin Name

Pin Location

Type

Function in Reset State

Function in Active State

INT0

High impedance with internal pull-up.

External interrupt 0 input. High priority.

INT1

3, 4

High impedance with internal pull-up.

External interrupt 1 input. Low priority.

Table 4.7: PWM signal

Pin Name

Pin Location

Type

Function in Reset State

Function in Active State

PWM

High impedance with internal pull-up.

Pulse width modulator output.

Table 4.8: LED controller interface signal

Pin Name

Pin Location

Type

Function in Reset State

Function in Active State

PWM LED0

High impedance with internal pull-up.

LED controller output.

Table 4.9: Dimmer interface signals

Pin Name

Pin Location

Type

Function in Reset State

Function in Active State

TRIAC

High impedance with internal pull-up.

Dimmer output. Firing pulse to

TRIAC/FET/IGBT.

ZEROX

High impedance with internal pull-up.

Zero-cross detection input.

Table 4.10: Timer interface signals

Pin Name

Pin Location

Type

Function in Reset State

Function in Active State

T0 EXT CLK

High impedance with internal pull-up.

Timer 0 external clock input.

T1 EXT CLK

High impedance with internal pull-up.

Timer 1 external clock input.

Table 4.11: RF interface signal

Pin Name

Pin Location

Type

Function in Reset State

Function in Active State

RF2

I/O

High impedance with internal pull-up.

RF input and output.

2 Caution: pin is sensitive to electro-static discharge

Datasheet: ZM5202

DSH12435-15 | 3/2018 17

Table 4.12: GPIO signals

Pin Name

Pin Location

Type

Function in Reset State

Function in Active State

P0.4

I/O

High impedance with internal pull-up.

General purpose input and output.

P1.0

I/O

High impedance with internal pull-up.

General purpose input and output.

P1.1

I/O

High impedance with internal pull-up.

General purpose input and output.

P2.2

I/O

Waits for the ”Interface Enable” serial

command after 5.2ms. Enters SPI1 ISP

mode after command is received from the

host.

General purpose input and output.

P2.3

I/O

Serial data transmit when in SPI1 ISP

mode, high impedance with internal

pull-up otherwise.

General purpose input and output.

P2.4

I/O

Programmer clock input with internal

pull-up.

General purpose input and output.

P3.4

I/O

High impedance with internal pull-up.

General purpose input and output.

P3.5

I/O

High impedance with internal pull-up.

General purpose input and output.

P3.6

I/O

High impedance with internal pull-up.

General purpose input and output.

P3.7

I/O

High impedance with internal pull-up.

General purpose input and output.

Datasheet: ZM5202

18 DSH12435-15 | 3/2018

5 ELECTRICAL CHARACTERISTICS

This section describes the electrical parameters of the ZM5202 module.

5.1 TEST CONDITIONS

Final Test in Production

=+25°C, V

=+3.3V)

Characterization in Lab

=-10°C to +85°C, V

=+2.3V to +3.6V)

Statistics with Min,

Typ, and Max values

Sorting criterion

specified with Min and

Max values

Manufactured

Modules

Tested

Modules

Figure 5.1: Testing flow

The following conditions apply for characterization in the lab, unless otherwise noted.

1. Ambient temperature TA = -10°C to +85°C

2. Supply voltage VDD = +2.3V to +3.6V

3. All tests are carried out on the ZDB5202 Z-Wave Development Board. [2]

4. Conducted transmission power is measured with the SAW filter for 868.4, 908.4, 919.8, and 921.4MHz at 50Ω

5. Conducted receiver sensitivity is measured with the SAW filter for 868.4, 908.4, 919.8, and 921.4MHz at 50Ω

The following conditions apply for the final test in production, unless otherwise noted.

1. Ambient temperature TA = +25°C

2. Supply voltage VDD = +3.3V

3. Conducted transmission power is measured with the SAW filter for 868.4, 908.4, 919.8, and 921.4MHz at 50Ω

4. Conducted receiver sensitivity is measured with the SAW filter for 868.4, 908.4, 919.8, and 921.4MHz at 50Ω

5.1.1 TYPICAL VALUES

Unless otherwise specified, typical data refer to the mean of a data set measured at an ambient temperature of TA=25°C and

supply voltage of VDD=+3.3V.

5.1.2 MINIMUM AND MAXIMUM VALUES

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature,

supply voltage and frequencies by a final test in production on 100% of the devices at an ambient temperature of TA=25°C and

supply voltage of VDD=+3.3V.

For data based on measurements, the minimum and maximum values represent the mean value plus or minus three times the

standard deviation (µ±3σ).

Datasheet: ZM5202

DSH12435-15 | 3/2018 19

5.2 ABSOLUTE MAXIMUM RATINGS

The absolute ratings specify the limits beyond which the module may not be functional. Exposure to absolute maximum

conditions for extended periods may cause permanent damage to the module.

Table 5.1: Voltage characteristics

Symbol

Description

Min

Max

Unit

VDD-GND

Main supply voltage

-0.3

+3.6

VIN-GND

Voltage applied on any I/O pin

-0.3

+3.6

Current limit when over driving the input (V

IN-GND

> V

DD-GND

)

+20.0

PRF-IN

Radio receiver input power

+10.0

dBm

ESDHBM

JEDEC JESD22-A114F Human Body Model

+2000.0

ESDMM

JEDEC JESD22-A115C Machine Model

+200.0

ESDCDM

JEDEC JESD22-C101E Field-Induced Charged-Device Model

+500.0

Table 5.2: Current characteristics

Symbol

Description

Min

Max

Unit

IVDD

Current into VDD power supply pin

+120

IGND

Sum of the current out of all GND ground pins

-120

Table 5.3: Thermal characteristics

Symbol

Description

Min

Max

Unit

Junction temperature

-55

+125

°C

5.3 GENERAL OPERATING RATINGS

The operating ratings indicate the conditions where the module is guaranteed to be functional.

Table 5.4: Recommended operating conditions

Symbol

Description

Min

Typ

Max

Unit

Standard operating supply voltage

+2.3

+3.3

+3.6

fSYS

Internal clock frequency

32.0

MHz

Ambient operating temperature

-10.0

+25.0

+85.0

°C

5.4 CURRENT CONSUMPTION

Measured at an ambient temperature of TA=-10°C to +85°C and a supply voltage of VDD=+2.3V to +3.6V.

Datasheet: ZM5202

20 DSH12435-15 | 3/2018

Table 5.5: Current consumption in active modes

Symbol

Description

Min

Typ

Max

Unit

DD_ACTIVE

MCU running at 32MHz

14.9

15.9

IDD_RX

MCU and radio receiver active

32.4

35.1

IDD_TX_-26

MCU and radio transmitter active, -26dBm

27.5

IDD_TX_4

MCU and radio transmitter active, +4dBm

42.1

Figure 5.2: Typical current consumption vs. transmit power

Table 5.6: Current consumption in power saving modes

Symbol

Description

Min

Typ

Max

Unit

IDD_SLEEP

Module in sleep state

1.0

µA

IDD_WUT

Module in sleep state with wake-up timer active

2.0

µA

DD_WUT_RAM

Module in sleep state with wake-up timer and 128 bytes of

critical RAM active

2.1

µA

Table 5.7: Current consumption during programming

Symbol

Description

Min

Typ

Max

Unit

IDD_PGM_SPI

Programming via SPI1

5.5 SYSTEM TIMING

Measured at an ambient temperature of TA=-10°C to +85°C and a supply voltage of VDD=+2.3V to +3.6V.

-27 -24 -21 -18 -15 -12 -9 -6 -3 0 3

Current Consumption (mA)

Transmit Power (dBm)

Datasheet: ZM5202

DSH12435-15 | 3/2018 21

Table 5.8: Transition between operating modes

Symbol

Description

Min

Typ

Max

Unit

ACTIVE_SLEEP

Transition time from the active state to the sleep state

125

SLEEP_ACTIVE

Transition time from the sleep state to the active state ready

to execute code

160

µs

Table 5.9: System start-up time

Symbol

Description

Min

Typ

Max

Unit

POR

Power-on-Reset (POR) threshold on rising supply voltage at

which the reset signal is deasserted

+2.3

RESET_ACTIVE

Transition time from the reset state to the active state ready

to execute code with a power rise time not exceeding 10µs

1.0

Table 5.10: Wake-up timer accuracy

Symbol

Description

Min

Typ

Max

Unit

WUT_OFFSET

Wake-up timer offset, Y-axis intercept of time vs. setting

curve

tWUT_SCALE

Wake-up timer absolute error

Table 5.11: Reset timing requirements

Symbol

Description

Min

Typ

Max

Unit

RST_PULSE

Duration to assert RESET_N to guarantee a full system reset

Table 5.12: Programming time

Symbol

Description

Min

Typ

Max

Unit

tERASE_FULL

Time taken to erase the entire flash memory

44.1

PGM_FULL

Time taken to program the entire flash memory over SPI1 at

4MHz including a full erase

1.4

5.6 NON-VOLATILE MEMORY

Qualified for an ambient temperature of TA=+25°C and a supply voltage of VDD=+3.3V. The on-chip memory is based on

SuperFlash® technology.

Datasheet: ZM5202

22 DSH12435-15 | 3/2018

Table 5.13: On-chip flash

Symbol

Description

Min

Typ

Max

Unit

END

FLASH

Endurance, erase cycles before failure

10000

cycles

RETFLASH-LT

Data retention

100

years

RET

FLASH-HT

Data retention (Qualified for a junction temperature of

TJ=-10°C to +85°C)

years

Table 5.14: On-chip M9 high endurance NVM

Symbol

Description

Min

Typ

Max

Unit

END

NVM

Endurance, erase cycles before failure

100000

cycles

RETNVM-LT

Data retention

100

years

RET

NVM-HT

Data retention (Qualified for a junction temperature of

TJ=-10°C to +85°C)

years

5.7 ANALOG-TO-DIGITAL CONVERTER

Measured at an ambient temperature of TA=-10°C to +85°C and a supply voltage of VDD=+2.3V to +3.6V.

Table 5.15: 12 bit ADC characteristics

Symbol

Description

Min

Max

Unit

VBG

Internal reference voltage

+1.20

+1.30

VREF+

Upper reference input voltage

VDD - 0.90

VDD

REF-

Lower reference input voltage

0.00

+1.20

IADCIN

Input current (0 ≤ V

≤ V

)

-10.00

+10.00

µA

DNLADC

Differential non-linearity

-1.00

+1.00

LSB

ACC8b

Accuracy when sampling 20ksps with 8 bit resolution

-2.00

+2.00

LSB

ACC

12b

Accuracy when sampling 10ksps with 12 bit resolution

-5.00

+5.00

LSB

fS-8b

8 bit sampling rate

0.02

Msps

fS-12b

12 bit sampling rate

0.01

Msps

5.8 GENERAL PURPOSE INPUT OUTPUT

Measured at an ambient temperature of TA=-10°C to +85°C.

Datasheet: ZM5202

DSH12435-15 | 3/2018 23

Table 5.16: Digital input characteristics, supply voltage of VDD=+2.3V to +3.0V

Symbol

Description

Min

Max

Unit

VIH

Logical 1 input voltage high level

+1.85

VIL

Logical 0 input voltage low level

+0.75

Falling input trigger threshold

+0.75

+1.05

Rising edge trigger threshold

+1.35

+1.85

VHYS

Schmitt trigger voltage hysteresis

+0.55

+0.85

IIH

Logical 1 input high level current leakage

+7.00

µA

IIL-NPU

Logical 0 input low level current leakage (no internal pull-up resistor)

-7.00

µA

IL-PU

Logical 0 input low level current leakage (with internal pull-up resistor)

+35.00

+90.00

µA

PUIN

Internal pull-up resistance (T

=+25°C)

20.00

30.00

kΩ

CIN

Pin input capacitance

15.00

Table 5.17: Digital output characteristics, supply voltage of VDD=+2.3V to +3.0V

Symbol

Description

Min

Max

Unit

VOH

Logical 1 output voltage high level

+1.9

Logical 0 output voltage low level

+0.4

IOH-LP

Logical 1 output high level current sourcing

+6.0

IOL-LP

Logical 0 output low level current sinking

-6.0

IOH-HP

Logical 1 output high level current sourcing (pin 10 and pin 13 to pin 15)

+12.0

OL-HP

Logical 0 output low level current sinking (pin 10 and pin 13 to pin 15)

-12.0

Table 5.18: Digital input characteristics, supply voltage of VDD=+3.0V to +3.6V

Symbol

Description

Min

Max

Unit

VIH

Logical 1 input voltage high level

+2.10

VIL

Logical 0 input voltage low level

+0.90

VIF

Falling input trigger threshold

+0.90

+1.30

Rising edge trigger threshold

+1.60

+2.10

VHYS

Schmitt trigger voltage hysteresis

+0.65

+0.95

IIH

Logical 1 input high level current leakage

+10.00

µA

IIL-NPU

Logical 0 input low level current leakage (no internal pull-up resistor)

-10.00

µA

IIL-PU

Logical 0 input low level current leakage (with internal pull-up resistor)

+40.00

+120.00

µA

Internal pull-up resistance (T

=+25°C)

15.00

20.00

kΩ

CIN

Pin input capacitance

15.00

Table 5.19: Digital output characteristics, supply voltage of VDD=+3.0V to +3.6V

Symbol

Description

Min

Max

Unit

VOH

Logical 1 output voltage high level

+2.4

Logical 0 output voltage low level

+0.4

OH-LP

Logical 1 output high level current sourcing

+8.0

IOL-LP

Logical 0 output low level current sinking

-8.0

IOH-HP

Logical 1 output high level current sourcing (pin 10 and pin 13 to pin 15)

+16.0

IOL-HP

Logical 0 output low level current sinking (pin 10 and pin 13 to pin 15)

-16.0

Datasheet: ZM5202

24 DSH12435-15 | 3/2018

5.9 RF CHARACTERISTICS

5.9.1 TRANSMITTER

Measured at an ambient temperature of TA=-10°C to +85°C and a supply voltage of VDD=+2.3V to +3.6V. The transmission power

is adjusted by setting the value of the RFPOW register.

Table 5.20: Transmitter performance

Symbol

Description

Min

Typ

Max

Unit

P63

RF output power delivered to the antenna, RFPOW=63

+2.9

+4.0

dBm

P01

RF output power delivered to the antenna, RFPOW=01

-29.0

-26.1

dBm

H2-63

2nd harmonic, RFPOW=63

-57.3

dBc

PH2-48

2nd harmonic, RFPOW=48

-60.2

dBc

PH2-32

2nd harmonic, RFPOW=32

-61.9

dBc

PH2-20

2nd harmonic, RFPOW=20

-59.6

dBc

H2-8

2nd harmonic, RFPOW=8

-51.3

dBc

PH3-63

3rd harmonic, RFPOW=63

-45.4

dBc

PH3-48

3rd harmonic, RFPOW=48

-45.8

dBc

PH3-32

3rd harmonic, RFPOW=32

-45.6

dBc

PH3-20

3rd harmonic, RFPOW=20

-47.6

dBc

H3-8

3rd harmonic, RFPOW=8

-46.6

dBc

PN30kHz

Phase noise at 30kHz

-88.1

dBc/Hz

PN100kHz

Phase noise at 100kHz

-95.2

dBc/Hz

PN1MHz

Phase noise at 1MHz

-107.3

dBc/Hz

PN10MHz

Phase noise at 10MHz

-113.1

dBc/Hz

20MHz

Phase noise at 100MHz

-113.8

dBc/Hz

BW9.6

Channel bandwidth, 9.6kbps

90.0

kHz

BW40

Channel bandwidth, 40kbps

90.0

kHz

BW100

Channel bandwidth, 100kbps

110.0

kHz

Figure 5.3: Typical transmit power vs. RFPOW setting

The transmitter is calibrated from factory. Refer to [3] for more information.

-27

-24

-21

-18

-15

-12

-9

-6

-3

0 5 10 15 20 25 30 35 40 45 50 55 60

Transmit Power (dBm)

RFPOW Setting

Datasheet: ZM5202

DSH12435-15 | 3/2018 25

5.9.2 RECEIVER

Measured over an ambient temperature of TA=+25°C and a supply voltage of VDD=+2.3V to +3.6V.

Table 5.21: Receiver sensitivity

Symbol

Description

Min

Typ

Max

Unit

P9.6

Sensitivity at 9.6kbps, FER < 1%

-102.7

-101.0

dBm

P40

Sensitivity at 40kbps, FER < 1%

-99.0

-97.2

dBm

P100

Sensitivity at 100kbps, FER < 1%

-93.0

-91.8

dBm

Figure 5.4: Typical sensitivity vs. temperature

-106

-103

-100

-97

-94

-91

-25 025 50 75 100

Sensitivity (dBm)

Temperature (°C)

9.6 kbps

40 kbps

100 kbps

Datasheet: ZM5202

26 DSH12435-15 | 3/2018

Table 5.22: Receiver performance

Symbol

Description

Min

Typ

Max

Unit

CCR

9.6

Co-channel rejection, 9.6kbps

-3.9

dBc

BI1MHZ-9.6

Blocking immunity3 at Δf=1MHz, 9.6kbps

43.5

dBc

BI2MHZ-9.6

Blocking immunity at Δf=2MHz, 9.6kbps

52.6

dBc

BI5MHZ-9.6

Blocking immunity at Δf=5MHz, 9.6kbps

70.6

dBc

BI10MHZ-9.6

Blocking immunity at Δf=10MHz, 9.6kbps

73.9

dBc

100MHZ-9.6

Blocking immunity at Δf=100MHz, 9.6kbps

85.7

dBc

CCR40

Co-channel rejection, 40kbps

-9.1

dBc

BI1MHZ-40

Blocking immunity at Δf=1MHz, 40kbps

40.2

dBc

BI2MHZ-40

Blocking immunity at Δf=2MHz, 40kbps

48.0

dBc

BI5MHZ-40

Blocking immunity at Δf=5MHz, 40kbps

65.2

dBc

10MHZ-40

Blocking immunity at Δf=10MHz, 40kbps

67.7

dBc

BI100MHZ-40

Blocking immunity at Δf=100MHz, 40kbps

82.0

dBc

CCR100

Co-channel rejection, 100kbps

-8.1

dBc

BI1MHZ-100

Blocking immunity at Δf=1MHz, 100kbps

30.2

dBc

2MHZ-100

Blocking immunity at Δf=2MHz, 100kbps

35.2

dBc

5MHZ-100

Blocking immunity at Δf=5MHz, 100kbps

59.0

dBc

BI10MHZ-100

Blocking immunity at Δf=10MHz, 100kbps

62.6

dBc

BI100MHZ-100

Blocking immunity at Δf=100MHz, 100kbps

76.0

dBc

RSSIRANGE

Dynamic range of the RSSI measurement

70.0

RSSI

LSB

Resolution of the RSSI measurement

1.5

PLO

LO leakage at Δf=200kHz and Δf=325kHz

-84.4

-80.0

dBm

IIP3

Input 3rd order intercept point

-12.0

dBm

BW9.6

Intermediate frequency filter bandwidth, 9.6kbps

300.0

kHz

BW40

Intermediate frequency filter bandwidth, 40kbps

300.0

kHz

100

Intermediate frequency filter bandwidth, 100kbps

600.0

kHz

3 Blocker level is defined relative to the wanted receiving signal and measured with the wanted receiving signal 3dB above the

sensitivity level

Datasheet: ZM5202

DSH12435-15 | 3/2018 27

Figure 5.5: Typical input power vs. RSSI value

First-order approximation:

  []1.56 × 161.45,  [40,80]

5.9.3 REGULATORY COMPLIANCE

The ZM5202 has been tested on the ZDP03A Z-Wave Development Platform to be compliant with the following regulatory

standards. [4]

• ACMA COMPLIANCE

o AS/NZS 4268

o CISPR 22

• CE COMPLIANCE

o EN 300 220-1/2

o EN 301 489-1/3

o EN 55022

o EN 60950-1

o EN 61000-4-2/3

o EN 62479

• FCC COMPLIANCE

o FCC CFR 47 Part 15 Subpart C §15.249

• IC COMPLIANCE

o RSS-GEN

o RSS-210

o ANSI C63.10

• MIC COMPLIANCE

O ARIB STD-T108

-120

-114

-108

-102

-96

-90

-84

-78

-72

-66

-60

-54

-48

-42

-36

-30

33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83

Received Power (dBm)

Received Signal Strength Indicator Value (RSSI)

Datasheet: ZM5202

28 DSH12435-15 | 3/2018

6 Z-WAVE FREQUENCIES

Table 6.1: Z-Wave RF specification

Data rate 9.6kbps 40kbps 100kbps

Modulation Frequency Shift Keying (FSK) FSK Gaussian Frequency Shift Keying (GFSK)

Frequency deviation

Frequency accuracy

±20kHz

fC±13ppm

±20kHz

fC±13ppm

±29.3kHz

fC±13ppm

Coding Manchester encoded Non-return to Zero (NRZ) NRZ

United Arab Emirates 868.42 MHz 868.40 MHz 869.85 MHz

Australia 921.42 MHz 921.40 MHz 919.80 MHz

Brazil 921.42 MHz 921.40 MHz 919.80 MHz

Canada 908.42 MHz 908.40 MHz 916.00 MHz

Chile 908.42 MHz 908.40 MHz 916.00 MHz

China 868.42 MHz 868.40 MHz 869.85 MHz

European Union 868.42 MHz 868.40 MHz 869.85 MHz

Hong Kong 919.82 MHz 919.80 MHz 919.80 MHz

Israel 916.02 MHz 916.00 MHz -

India 865.20 MHz 865.20 MHz 865.20 MHz

Japan - - 922.50 MHz

- - 923.90 MHz

- - 926.30 MHz

Korea - - 920.90 MHz

- - 921.70 MHz

- - 923.10 MHz

Mexico 908.42 MHz 908.40 MHz 916.00 MHz

Malaysia 868.12 MHz 868.10 MHz 868.10 MHz

New Zealand 921.42 MHz 921.40 MHz 919.80 MHz

Russia 869.02 MHz 869.00 MHz -

Singapore 868.42 MHz 868.40 MHz 869.85 MHz

Taiwan - - 922.50 MHz

- - 923.90 MHz

- - 926.30 MHz

United States 908.42 MHz 908.40 MHz 916.00 MHz

South Africa 868.42 MHz 868.40 MHz 869.85 MHz

Datasheet: ZM5202

DSH12435-15 | 3/2018 29

7 MODULE INFORMATION

7.1 MODULE MARKING

Figure 7.1: Marking placement

Table 7.1: Marking description

Regional information

REGION:

7.2 MODULE DIMENSIONS

Table 7.2: Dimensions

Length

13.6mm +/- 0.3 mm

Width

12.5mm +/- 0.3 mm

Height

1.9mm +/- 0.3 mm

8 PROCESS SPECIFICATION

Specification Description

MSL 3 Moisture Sensitivity Level designed and manufactured according to JEDEC J-STD-020C

REACH REACH is a European Community Regulation on chemicals and their safe use (EC 1907/2006).

It deals with the Registration, Evaluation, Authorisation and Restriction of Chemical

substances

RoHS Designed in compliance with The Restriction of Hazardous Substances Directive (RoHS)

Datasheet: ZM5202

30 DSH12435-15 | 3/2018

9 PCB MOUNTING AND SOLDERING

9.1 RECOMMENDED PCB MOUNTING PATTERN

Top View

0.00mm

0.55mm

1.10mm

1.40mm

1.66mm

0.70mm

Signal

Pattern Ground

Pattern

3.25mm

4.75mm

6.25mm

7.75mm

9.25mm

12.50mm

0.00mm

2.65mm

4.15mm

5.65mm

7.15mm

10.90mm

13.60mm

0.00mm

6.00mm

7.75mm

0.00mm

2.65mm

4.15mm

5.65mm

7.15mm

10.90mm

8.65mm

6 1

2345

1514

-0.41mm

12.91mm

14.01mm

Figure 9.1: Top view of land pattern

SOLDERING INFORMATION

The soldering details to properly solder the ZM5202 module on standard PCBs are described below. The information provided is

intended only as a guideline and Silicon Labs is not liable if a selected profile does not work.

See IPC/JEDEC J-STD-020D.1 for more information.

Datasheet: ZM5202

DSH12435-15 | 3/2018 31

Table 9.1: Soldering details

PCB solder mask expansion from landing pad edge

0.1 mm

PCB paste mask expansion from landing pad edge

0.0 mm

PCB process

Pb-free (Lead free for RoHS 4compliance)

PCB finish

Defined by the manufacturing facility (EMS) or customer

Stencil aperture

Defined by the manufacturing facility (EMS) or customer

Stencil thickness

Defined by the manufacturing facility (EMS) or customer

Solder paste used

Defined by the manufacturing facility (EMS) or customer

Flux cleaning process

Defined by the manufacturing facility (EMS) or customer

Figure 9.2: Typical reflow profile

4 RoHS = Restriction of Hazardous Substances Directive, EU

Datasheet: ZM5202

32 DSH12435-15 | 3/2018

10 ORDERING INFORMATION

Table 10.1: Ordering codes

Orderable Device Status

Package

Type

Pins

Minimum Order

Quantity

Description

ZM5202AE-CME3R

ACTIVE

SOM

1000 pcs.

ZM5202 module, RevA, 868MHz Band, Tape

and Reel

ZM5202AU-CME3R

ACTIVE

SOM

1000 pcs.

ZM5202 module, RevA, 908MHz Band, Tape

and Reel

ZM5202AH-CME3R

ACTIVE

SOM

1000 pcs.

ZM5202 module, RevA, 921MHz Band, Tape

and Reel

10.1 TAPE AND REEL INFORMATION

Shipment will be provided in tape with dimensions according to specifications in the following sections. Reel can be from two

alternative sources A or B with following dimensions and design. Main difference between alternatives is design and visual look.

Dimensions has been kept as equal as possible.

Datasheet: ZM5202

DSH12435-15 | 3/2018 33

10.1.1 TAPE DIMENSIONS

Figure 10.1: Tape information

Datasheet: ZM5202

34 DSH12435-15 | 3/2018

Parameter

Value

Pin 1 Quadrant

Pocket Quadrant Q3

Datasheet: ZM5202

DSH12435-15 | 3/2018 35

10.1.2 REEL SUPPLIER A

Figure 10.2: Reel information

Datasheet: ZM5202

36 DSH12435-15 | 3/2018

10.1.3 REEL SUPPLIER B

Datasheet: ZM5202

DSH12435-15 | 3/2018 37

11 ABBREVIATIONS

Abbreviation

Description

2FSK

2-key Frequency Shift Keying

2GFSK

2-key Gaussian Frequency Shift Keying

ACM

Abstract Control Model

ACMA

Australian Communications and Media Authority

ADC

Analog-to-Digital Converter

AES

Advanced Encryption Standard

API

Application Programming Interface

APM

Auto Programming Mode

Audio Video

BOD

Brown-Out Detector

CBC

Cipher-Block Chaining

CDC

Communications Device Class

Conformité Européenne

COM

Communication

CPU

Central Processing Unit

CRC

Cyclic Redundancy Check

Differential

D-

Differential Minus

D+

Differential Plus

DAC

Digital-to-Analog Converter

Direct Current

DMA

Direct Memory Access

ECB

Electronic CodeBook

EMS

Electronic Manufacturing Services

ESD

Electro-Static Discharge

FCC

Federal Communications Commission

FER

Frame Error Rate

FET

Field Effect Transistor

FLiRS

Frequently Listening Routing Slave

FSK

Frequency Shift Keying

GFSK

Gaussian Frequency Shift Keying

General Purpose

GPIO

General Purpose Input Output

Input

I/O

Input / Output

Integrated Circuit

Intermediate Frequency

IGBT

Insulated-Gate Bipolar Transistor

INT

Interrupt

IPC

Interconnecting and Packaging Circuits

Infrared

IRAM

Indirectly addressable Random Access Memory

ISM

Industrial, Scientific, and Medical

ISP

In-System Programming

ITU

International Telecommunications Union

JEDEC

Joint Electron Device Engineering Council

LED

Light-Emitting Diode

lsb

Least Significant Bit

LSB

Least Significant Byte

MCU

Micro-Controller Unit

MIC

Ministry of Internal affairs and Communications, Japan

Datasheet: ZM5202

38 DSH12435-15 | 3/2018

Abbreviation

Description

MISO

Master In, Slave Out

MOSI

Master Out, Slave In

msb

Most Significant Bit

MSB

Most Significant Byte

NMI

Non-Maskable Interrupt

NRZ

Non-Return-to-Zero

NVM

Non-Volatile Memory

NVR

Non-Volatile Registers

Output

OEM

Original Equipment Manufacturer

OFB

Output FeedBack

Lead

PCB

Printed Circuit Board

POR

Power-On Reset

PWM

Pulse Width Modulator

RAM

Random Access Memory

Radio Frequency

RoHS

Restriction of Hazardous Substances

ROM

Read Only Memory

RS-232

Recommended Standard 232

Receive

Supply

SAW

Surface Acoustic Wave

SCK

Serial Clock

SFR

Special Function Register

SiP

System-in-Package

SOM

System-On-Module

SPI

Serial Peripheral Interface

SRAM

Static Random Access Memory

Timer 0

Timer 1

Transmit

UART

Universal Asynchronous Receiver Transmitter

USB

Universal Serial Bus

WUT

Wake-Up Timer

XRAM

External Random Access Memory

XTAL

Crystal

ZEROX

Zero Crossing

Datasheet: ZM5202

DSH12435-15 | 3/2018 39

12 REVISION HISTORY

Date

Version

Affected

Revision

2018/02/19

§6, Table 6.1

Updated Korea frequency

2017/06/27

§ 5.9.1

Clarified transmitter is calibrated from factory

2017/04/11

Figure 4.1

Figure 9.1

Figure 4.1 updated with to scale drawing, and placement of

pads, some notations changed from diameter to radius.

Figure 9.1 updated dimensions and placement of land

patterns to fit module pads.

2017/02/09

§ 10.1.1

Pin 1 Quadrant corrected to “Q3”

2016/12/20

Table 5.5

Cleaned up “TDB”

2016/11/24

§ 10

Add Reel information from source B

2016/10/26

Table 6.1

Corrected frequency accuracy to worst case figure

2016/4/29

$2.2.4

Updated wording in section 2.2.4 Crystal driver and system

clock

2015/4/28

Figure 9.1

Table 9.2

§8

§10.1

Figure 4.1

§7.2, Table 7.2

Updated to align with SD3502 recommendation.

Removed – information included in updated Figure 9.1

Added section Process Specification

Added orientation of component in tape

Corrected length of Signal Pin and Ground Pin

Added tolerances to module dimensions

2015/1/30

2013/12/13

Table 6.1

Table 2.1

Added frequency accuracy

Entries in table of CPU modes rephrased

2013/12/12

Table 2.1,

§2.4.1

Reduced the RESET_N high time

Increased the RESET_N low time

2013/10/31

§Cover,

Figure 2.1,

Table 2.3,

Figure 2.7,

Table 4.3,

§5.1,

Table 5.5, Figure 5.2,

Table 5.20, Figure 5.3,

Table 5.22,

§5.9.2

Updated performance values

Added LED controller

Updated INT1 pins

Updated caption

Changed to master I/O mode

Updated final test description

Updated TX current consumption

Updated TX power and performance

Updated LO leakage

Updated equation for 1

-order approximation

2013/10/29

§Cover,

Figure 2.1,

§2.1,

Table 2.2, Table 2.3,

§2.2.2,

§2.2.9,

Figure 2.5,

§2.2.12,

§4.1,

Table 4.3,

Table 4.8,

Table 4.10,

Table 5.1,

Table 5.5,

Figure 5.2,

Table 5.12,

Table 5.16, Table 5.18,

Table 5.20, Figure 5.3,

§5.9.1,

Updated performance values

Updated matching description

Added CPU modes

Updated pin numbers

Added source impedance formula

Added LED controller

Updated SPI slave connection

Added Timers

Removed ‘weak’ from pull-up description

Updated pin names

Added LED interface pin

Added Timer interface pins

Added maximum RF input

Updated current consumption values

Updated transmit current consumption

Updated programming time

Added pull-up resistor value

Updated TX power and harmonics

Added mandatory TX calibration

Datasheet: ZM5202

40 DSH12435-15 | 3/2018

Date

Version

Affected

Revision

Table 5.21, Figure 5.4,

Table 5.22,

Figure 5.5,

Figure 7.1

Updated sensitivity values

Updated blocking and LO leakage

Updated RSSI values

Updated module marking

2013/09/12

§Cover,

§2.2.5,

§2.2.10, §2.2.11,

Figure 4.1,

§5.9,

Table 5.15, Table 5.18,

§6,

Table 7.2

Updated the features and module items

Added GPIO description

Added peripheral designators

Added pin dimensions

Removed impedance plots

Changed the supply voltage range and clock speed of external

NVM

Corrected Korean frequency

Added module dimensions

2013/06/03

Table 2.3,

Table 5.8

Removed empty line from interrupt table

Added state transition times

2013/05/31

§All

Updated IO characteristics

2013/05/20

§All

Updated layout, and data from the latest corner tests

2013/02/22

§All

Preliminary draft released

2013/02/18

§All

Initial draft

DATASHEET: ZM5202

DSH12435-15 | 3/2018 41

13 REFERENCES

[1] INS11681, Instruction, “500 Series Z-Wave Chip Programming Mode”

[2] DSH12436, Datasheet, “ZDB5202 Z-Wave Development Board”

[3] INS12213, Instruction, “500 Series Hardware Integration Guide”

[4] DSH11243, Datasheet, “ZDP03A, Z-Wave Development Platform”

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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes

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