REJ09B0009-0100Z M16C/6N4 Group 16 Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES Before using this material, please visit our website to confirm that this is the most current document available. Rev. 1.00 Revision date: May 30, 2003 www.renesas.com Keep safety first in your circuit designs! * Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. 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How to Use This Manual This hardware manual provides detailed information on features in the M16C/6N4 Group microcomputer. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputer. Each register diagram contains bit functions with the following symbols and descriptions. XXX register b7 b6 b5 b4 b3 b2 b1 *1 b0 0 Symbol XXX Bit symbol Address XXX After reset 0016 Bit name Function RW b1 b0 XXX0 XXX bit XXX1 0 0: XXX 0 1: XXX 1 0: Avoid this setting 1 1: XXX (b2) Nothing is assigned. When write, set to "0", When read, its content is indeterminate. (b3) Reserved bit Set to "0" XXX4 XXX5 XXX bit Function varies depending on each operation mode *2 RW RW RW XXX6 XXX7 RW *3 WO RW XXX bit 0: XXX 1: XXX RO *1 Blank:Set to "0" or "1" according to your intended use 0: Set to "0" 1: Set to "1" X: Nothing is assigned *2 RW: RO: WO: -: Read and write Read only Write only Nothing is assigned *3 Terms to use here are explained as follows. * Nothing is assigned Nothing is assigned to the bit concerned. When write, set to "0" for new function in future plan. * Reserved bit Reserved bit. Set the specified value. * Avoid this setting The operation at having selected is not guaranteed. * Function varies depending on each operation mode Bit function varies depending on peripheral function mode. Refer to register diagrams in each mode. M16C Family Documents The following document is prepared with the M16C family. Document Short Sheet Data Sheet Hardware Manual Software Manual Application Note Contents Hardware overview Hardware overview and electrical characteristics Hardware specifications (pin assignments, memory maps, specifications of peripheral functions, electrical characteristics, timing charts) Detailed description about instructions and microcomputer performance by each instruction * Application examples of peripheral functions * Sample programs * Introductory description about basic functions in M16C family * Programming method with the assembly and C languages Table of Contents Quick Reference to Pages Classified by Address Overview ................................................................................................................................... 1 Applications ........................................................................................................................................................ 1 Performance Outline .......................................................................................................................................... 2 Block Diagram .................................................................................................................................................... 3 Product List ........................................................................................................................................................ 4 Pin Configuration ............................................................................................................................................... 5 Pin Description ................................................................................................................................................... 6 Memory ..................................................................................................................................... 8 Central Processing Unit (CPU) ................................................................................................. 9 (1) Data Registers (R0, R1, R2, and R3) ........................................................................................................... 9 (2) Address Registers (A0 and A1) .................................................................................................................... 9 (3) Frame Base Register (FB) .......................................................................................................................... 10 (4) Interrupt Table Register (INTB) ................................................................................................................... 10 (5) Program Counter (PC) ................................................................................................................................ 10 (6) User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ............................................................................ 10 (7) Static Base Register (SB) ........................................................................................................................... 10 (8) Flag Register (FLG) .................................................................................................................................... 10 SFR ......................................................................................................................................... 11 Reset ....................................................................................................................................... 27 Hardware Reset ............................................................................................................................................... 27 Software Reset ................................................................................................................................................ 27 Watchdog Timer Reset ..................................................................................................................................... 27 Oscillation Stop Detection Reset ..................................................................................................................... 27 Processor Mode ...................................................................................................................... 30 (1) Types of Processor Mode ........................................................................................................................... 30 (2) Setting Processor Modes ........................................................................................................................... 30 Bus .......................................................................................................................................... 36 Bus Mode ......................................................................................................................................................... 36 Bus Control ...................................................................................................................................................... 37 (1) Address Bus .......................................................................................................................................... 37 (2) Data Bus ................................................................................................................................................ 37 (3) Chip Select Signal ................................................................................................................................. 37 (4) Read and Write Signals ......................................................................................................................... 39 (5) ALE Signal ............................................................................................................................................. 39 ________ (6) The RDY Signal ..................................................................................................................................... 40 __________ (7) HOLD Signal .......................................................................................................................................... 41 (8) BCLK Output ......................................................................................................................................... 41 (9) External Bus Status When Internal Area Accessed............................................................................... 43 (10) Software Wait ...................................................................................................................................... 43 A-1 Clock Generation Circuit ......................................................................................................... 47 (1) Main Clock ............................................................................................................................................. 55 (2) Sub Clock .............................................................................................................................................. 56 (3) Ring Oscillator Clock ............................................................................................................................. 57 (4) PLL Clock .............................................................................................................................................. 57 CPU Clock and Peripheral Function Clock ...................................................................................................... 59 (1) CPU Clock and BCLK ............................................................................................................................ 59 (2) Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fCAN0, fCAN1, fC32)................................... 59 Clock Output Function ..................................................................................................................................... 59 Power Control .................................................................................................................................................. 60 (1) Normal Operation Mode ........................................................................................................................ 60 (2) Wait Mode ............................................................................................................................................. 62 (3) Stop Mode ............................................................................................................................................. 64 Oscillation Stop and Re-oscillation Detection Function ................................................................................... 69 Protection ................................................................................................................................ 71 Interrupts ................................................................................................................................. 72 Type of Interrupts ............................................................................................................................................. 72 Software Interrupts ........................................................................................................................................... 73 Hardware Interrupts ......................................................................................................................................... 74 Interrupts and Interrupt Vector ......................................................................................................................... 75 Interrupt Control ............................................................................................................................................... 77 ______ INT Interrupt ..................................................................................................................................................... 85 ______ NMI Interrupt .................................................................................................................................................... 87 Key Input Interrupt ........................................................................................................................................... 87 CAN0/1 Wake-up Interrupt ............................................................................................................................... 87 Address Match Interrupt ................................................................................................................................... 88 Watchdog Timer ...................................................................................................................... 90 DMAC ...................................................................................................................................... 92 1. Transfer Cycle .............................................................................................................................................. 97 2. DMA Transfer Cycles ................................................................................................................................... 99 3. DMA Enable ............................................................................................................................................... 100 4. DMA Request ............................................................................................................................................. 100 5. Channel Priority and DMA Transfer Timing ................................................................................................ 101 Timers ................................................................................................................................... 102 Timer A ........................................................................................................................................................... 104 1. Timer Mode ........................................................................................................................................... 108 2. Event Counter Mode ............................................................................................................................. 109 3. One-shot Timer Mode ........................................................................................................................... 114 4. Pulse Width Modulation (PWM) Mode .................................................................................................. 116 Timer B ........................................................................................................................................................... 119 1. Timer Mode ........................................................................................................................................... 122 2. Event Counter Mode ............................................................................................................................. 123 3. Pulse Period and Pulse Width Measurement Mode ............................................................................. 124 Three-phase Motor Control Timer Function .......................................................................... 127 A-2 Serial I/O ............................................................................................................................... 138 UARTi (i = 0 to 2) ........................................................................................................................................... 138 Clock Synchronous Serial I/O Mode ......................................................................................................... 147 Clock Asynchronous Serial I/O (UART) Mode .......................................................................................... 154 Special Mode 1 (I2C Mode) ....................................................................................................................... 161 Special Mode 2 ......................................................................................................................................... 170 Special Mode 3 (IE Mode) ........................................................................................................................ 175 Special Mode 4 (SIM Mode) (UART2) ...................................................................................................... 177 SI/O3 .............................................................................................................................................................. 182 A-D Converter ....................................................................................................................... 187 (1) One-shot Mode ......................................................................................................................................... 191 (2) Repeat Mode ............................................................................................................................................ 193 (3) Single Sweep Mode .................................................................................................................................. 195 (4) Repeat Sweep Mode 0 ............................................................................................................................. 197 (5) Repeat Sweep Mode 1 ............................................................................................................................. 199 D-A Converter ....................................................................................................................... 203 CRC Calculation .................................................................................................................... 205 CAN Module .......................................................................................................................... 207 CAN Module-Related Registers ..................................................................................................................... 208 CANi Message Box (i = 0, 1) .................................................................................................................... 209 Acceptance Mask Registers ..................................................................................................................... 211 CAN SFR Registers .................................................................................................................................. 212 Operational Modes ......................................................................................................................................... 220 Configuration of the CAN Module System Clock ........................................................................................... 222 CAN Bus Timing Control ................................................................................................................................ 222 Acceptance Filtering Function and Masking Function ................................................................................... 224 Acceptance Filter Support Unit (ASU) ........................................................................................................... 225 Basic CAN Mode ............................................................................................................................................ 226 Return from Bus off Function ......................................................................................................................... 227 Time Stamp Counter and Time Stamp Function ............................................................................................ 227 Listen-Only Mode ........................................................................................................................................... 227 Reception and Transmission .......................................................................................................................... 228 CAN Interrupts ............................................................................................................................................... 231 Programmable I/O Ports ....................................................................................................... 232 (1) Port Pi Direction Register (PDi Register, i = 0 to 10) ................................................................................ 232 (2) Port Pi Register (Pi Register, i = 0 to 10) .................................................................................................. 232 (3) Pull-up Control Register j (PURj Register, j = 0 to 2) ................................................................................ 232 (4) Port Control Register (PCR Register) ....................................................................................................... 232 Electrical Characteristics ....................................................................................................... 244 Flash Memory ....................................................................................................................... 262 Flash Memory Performance ........................................................................................................................... 262 Memory Map .................................................................................................................................................. 263 Boot Mode ...................................................................................................................................................... 264 Functions to Prevent Flash Memory from Rewriting ...................................................................................... 264 CPU Rewrite Mode ........................................................................................................................................ 266 Standard Serial I/O Mode .............................................................................................................................. 283 Parallel I/O Mode ........................................................................................................................................... 287 CAN I/O Mode ................................................................................................................................................ 288 Electrical Characteristics ................................................................................................................................ 291 A-3 Package Dimension .............................................................................................................. 292 Register Index ....................................................................................................................... 293 M16C/6N4 Group Usage Note Reference Book For the most current Usage Notes Reference Book, please visit our website. Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition. A-4 Quick Reference to Pages Classified by Address Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Register Symbol Page Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Chip select control register Address match interrupt enable register Protect register PM0 PM1 CM0 CM1 CSR AIER PRCR 31 32 49 50 37 89 71 Oscillation stop detection register CM2 51 Watchdog timer start register Watchdog timer control register WDTS WDC 91 91 Address match interrupt register 0 RMAD0 89 Address match interrupt register 1 RMAD1 89 Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 Chip select expansion control register CSE PLL control register 0 PLC0 43 54 Processor mode register 2 PM2 53 DMA0 source pointer SAR0 96 DMA0 destination pointer DAR0 96 DMA0 transfer counter TCR0 96 DMA0 control register DM0CON 95 DMA1 source pointer DMA1 destination pointer SAR1 DAR1 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 96 96 DMA1 transfer counter TCR1 96 DMA1 control register DM1CON 95 The blank areas are reserved. B-1 Register Symbol Page CAN0/1 wake up interrupt control register CAN0 successful reception interrupt control register CAN0 successful transmission interrupt control register INT3 interrupt control register Timer B5 interrupt control register Timer B4 interrupt control register UART1 bus collision detection interrupt control register Timer B3 interrupt control register UART0 bus collision detection interrupt control register CAN1 successful reception interrupt control register INT5 interrupt control register CAN1 successful transmission interrupt control register SI/O3 interrupt control register INT4 interrupt control register UART2 bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register CAN0/1 error interrupt control register A-D conversion interrupt control register Key input interrupt control register UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register C01WKIC C0RECIC C0TRMIC INT3IC TB5IC TB4IC U1BCNIC TB3IC U0BCNIC C1RECIC INT5IC C1TRMIC S3IC INT4IC U2BCNIC DM0IC DM1IC C01ERRIC ADIC KUPIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC 77 77 77 78 77 77 77 77 77 78 78 78 78 78 77 77 77 77 77 77 77 77 77 77 77 77 77 77 77 77 77 77 77 77 78 78 78 CAN0 message box 0: Identifier / DLC CAN0 message box 0: Data field CAN0 message box 0: Time stamp CAN0 message box 1: Identifier / DLC CAN0 message box 1: data Field CAN0 message box 1: Time stamp 209 210 Address 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16 Register Symbol Page Address 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 CAN0 message box 2: Identifier / DLC CAN0 message box 2: Data field CAN0 message box 2: Time stamp CAN0 message box 3: Identifier / DLC CAN0 message box 3: Data field CAN0 message box 3: Time stamp 209 210 CAN0 message box 4: Identifier / DLC CAN0 message box 4: Data field CAN0 message box 4: Time stamp CAN0 message box 5: Identifier / DLC CAN0 message box 5: Data field CAN0 message box 5: Time stamp B-2 Register Symbol Page CAN0 message box 6: Identifier / DLC CAN0 message box 6: Data field CAN0 message box 6: Time stamp CAN0 message box 7: Identifier / DLC CAN0 message box 7: Data field CAN0 message box 7: Time stamp CAN0 message box 8: Identifier / DLC CAN0 message box 8: Data field CAN0 message box 8: Time stamp CAN0 message box 9: Identifier / DLC CAN0 message box 9: Data field CAN0 message box 9: Time stamp 209 210 Address 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 011816 011916 011A16 011B16 011C16 011D16 011E16 011F16 012016 012116 012216 012316 012416 012516 012616 012716 012816 012916 012A16 012B16 012C16 012D16 012E16 012F16 013016 013116 013216 013316 013416 013516 013616 013716 013816 013916 013A16 013B16 013C16 013D16 013E16 013F16 Register Symbol Address 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A16 014B16 014C16 014D16 014E16 014F16 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A16 015B16 015C16 015D16 015E16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A16 016B16 016C16 016D16 016E16 016F16 017016 017116 017216 017316 017416 017516 017616 017716 017816 017916 017A16 017B16 017C16 017D16 017E16 017F16 Page CAN0 message box 10: Identifier / DLC CAN0 message box 10: Data field CAN0 message box 10: Time stamp CAN0 message box 11: Identifier / DLC CAN0 message box 11: Data field CAN0 message box 11: Time stamp 209 210 CAN0 message box 12: Identifier / DLC CAN0 message box 12: Data field CAN0 message box 12: Time stamp CAN0 message box 13: Identifier / DLC CAN0 message box 13: Data field CAN0 message box 13: Time stamp The blank areas are reserved. B-3 Register Symbol Page CAN0 message box 14: Identifier /DLC CAN0 message box 14: Data field CAN0 message box 14: Time stamp 209 210 CAN0 message box 15: Identifier /DLC CAN0 message box 15: Data field CAN0 message box 15: Time stamp CAN0 global mask register C0GMR 211 CAN0 local mask A register C0LMAR 211 CAN0 local mask B register C0LMBR 211 Address 018016 018116 018216 018316 018416 018516 018616 018716 018816 018916 018A16 018B16 018C16 018D16 018E16 018F16 019016 019116 019216 019316 019416 019516 019616 019716 019816 019916 019A16 019B16 019C16 019D16 019E16 019F16 01A016 01A116 01A216 01A316 01A416 01A516 01A616 01A716 01A816 01A916 01AA16 01AB16 01AC16 01AD16 01AE16 01AF16 01B016 01B116 01B216 01B316 01B416 01B516 01B616 01B716 01B816 01B916 01BA16 01BB16 01BC16 01BD16 01BE16 01BF16 Register Symbol Flash memory control register 1 FMR1 269 Flash memory control register 0 FMR0 269 Address match interrupt register 2 RAMD2 89 Address match interrupt enable register 2 AIER2 89 Address match interrupt register 3 89 RAMD3 Address 01C016 01C116 01C216 01C316 01C416 01C516 01C616 01C716 01C816 01C916 01CA16 01CB16 01CC16 01CD16 01CE16 01CF16 01D016 01D116 01D216 01D316 01D416 01D516 01D616 01D716 01D816 01D916 01DA16 01DB16 01DC16 01DD16 01DE16 01DF16 01E016 01E116 01E216 01E316 01E416 01E516 01E616 01E716 01E816 01E916 01EA16 01EB16 01EC16 01ED16 01EE16 01EF16 01F016 01F116 01F216 01F316 01F416 01F516 01F616 01F716 01F816 01F916 01FA16 01FB16 01FC16 01FD16 01FE16 01FF16 Page The blank areas are reserved. B-4 Register Timer B3,4,5 count start flag Symbol TBSR Timer A1-1 register TA11 132 Timer A2-1 register TA21 132 Timer A4-1 register TA41 132 Three-phase PWM control register 0 Three-phase PWM control register 1 Three-phase output buffer register 0 Three-phase output buffer register 1 Dead time timer Timer B2 interrupt occurrence frequency set counter INVC0 INVC1 IDB0 IDB1 DTT ICTB2 129 130 131 131 131 133 Timer B3 register TB3 120 Timer B4 register TB4 120 Timer B5 register TB5 120 Timer B3 mode register Timer B4 mode register Timer B5 mode register Interrupt cause select register 0 Interrupt cause select register 1 SI/O3 transmit/receive register TB3MR TB4MR TB5MR IFSR0 IFSR1 S3TRR 120 122 123 125 86 86 183 SI/O3 control register SI/O3 bit rate generator S3C S3BRG 183 183 UART0 special mode register 4 UART0 special mode register 3 UART0 special mode register 2 UART0 special mode register UART1 special mode register 4 UART1 special mode register 3 UART1 special mode register 2 UART1 special mode register UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 bit rate generator U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG 146 145 145 144 146 145 145 144 146 145 145 144 142 141 UART2 transmit buffer register U2TB 141 UART2 transmit/receive mode register 0 U2C0 UART2 transmit/receive mode register 1 U2C1 142 143 UART2 receive buffer register 141 U2RB Page 121 Address 020016 020116 020216 020316 020416 020516 020616 020716 020816 020916 020A16 020B16 020C16 020D16 020E16 020F16 021016 021116 021216 021316 021416 021516 021616 021716 021816 021916 021A16 021B16 021C16 021D16 021E16 021F16 022016 022116 022216 022316 022416 022516 022616 022716 022816 022916 022A16 022B16 022C16 022D16 022E16 022F16 023016 023116 023216 023316 023416 023516 023616 023716 023816 023916 023A16 023B16 023C16 023D16 023E16 023F16 Register CAN0 message control register 0 CAN0 message control register 1 CAN0 message control register 2 CAN0 message control register 3 CAN0 message control register 4 CAN0 message control register 5 CAN0 message control register 6 CAN0 message control register 7 CAN0 message control register 8 CAN0 message control register 9 CAN0 message control register 10 CAN0 message control register 11 CAN0 message control register 12 CAN0 message control register 13 CAN0 message control register 14 CAN0 message control register 15 Symbol Page C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 212 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 CAN0 control register C0CTLR 213 CAN0 status register C0STR 214 CAN0 slot status register C0SSTR 215 CAN0 interrupt control register C0ICR 216 CAN0 extended register C0IDR 216 CAN0 configuration register C0CONR 217 CAN0 receive error count register CAN0 transmit error count register C0RECR C0TECR 218 218 CAN0 time stamp register C0TSR 219 CAN1 message control register 0 CAN1 message control register 1 CAN1 message control register 2 CAN1 message control register 3 CAN1 message control register 4 CAN1 message control register 5 CAN1 message control register 6 CAN1 message control register 7 CAN1 message control register 8 CAN1 message control register 9 CAN1 message control register 10 CAN1 message control register 11 CAN1 message control register 12 CAN1 message control register 13 CAN1 message control register 14 CAN1 message control register 15 C1MCTL0 C1MCTL1 C1MCTL2 C1MCTL3 C1MCTL4 C1MCTL5 C1MCTL6 C1MCTL7 212 C1MCTL8 C1MCTL9 C1MCTL10 C1MCTL11 C1MCTL12 C1MCTL13 C1MCTL14 C1MCTL15 CAN1 control register C1CTLR 213 CAN1 status register C1STR 214 CAN1 slot status register C1SSTR 215 CAN1 interrupt control register C1ICR 216 CAN1 extended register C1IDR 216 CAN1 configuration register C1CONR 217 CAN1 receive error count register CAN1 transmit error count register C1RECR C1TECR 218 218 CAN1 time stamp register C1TSR 219 Address 024016 024116 024216 024316 024416 024516 024616 024716 024816 024916 024A16 024B16 024C16 024D16 024E16 024F16 025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 025B16 025C16 025D16 025E16 025F16 026016 026116 026216 026316 026416 026516 026616 026716 026816 026916 026A16 026B16 026C16 026D16 026E16 026F16 027016 027116 027216 027316 027416 027516 027616 027716 027816 027916 027A16 027B16 027C16 027D16 027E16 027F16 The blank areas are reserved. B-5 Register Symbol Page CAN0 acceptance filter support register C0AFS 219 CAN1 acceptance filter support register C1AFS 219 Peripheral function clock select register PCLKR CAN0/1 clock select register CCLKR 52 52 CAN1 message box 0: Identifier / DLC CAN1 message box 0: Data field CAN1 message box 0:Time stamp CAN1 message box 1: Identifier / DLC CAN1 message box 1: Data field CAN1 message box 1:Time stamp 209 210 Address 028016 028116 028216 028316 028416 028516 028616 028716 028816 028916 028A16 028B16 028C16 028D16 028E16 028F16 029016 029116 029216 029316 029416 029516 029616 029716 029816 029916 029A16 029B16 029C16 029D16 029E16 029F16 02A016 02A116 02A216 02A316 02A416 02A516 02A616 02A716 02A816 02A916 02AA16 02AB16 02AC16 02AD16 02AE16 02AF16 02B016 02B116 02B216 02B316 02B416 02B516 02B616 02B716 02B816 02B916 02BA16 02BB16 02BC16 02BD16 02BE16 02BF16 Register Symbol Page Address 02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 02EB16 02EC16 02ED16 02EE16 02EF16 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA16 02FB16 02FC16 02FD16 02FE16 02FF16 CAN1 message box 2: Identifier / DLC CAN1 message box 2: Data field CAN1 message box 2: Time stamp CAN1 message box 3: Identifier / DLC CAN1 message box 3: Data field CAN1 message box 3: Time stamp 209 210 CAN1 message box 4: Identifier / DLC CAN1 message box 4: Data field CAN1 message box 4: Time stamp CAN1 message box 5: Identifier / DLC CAN1 message box 5: Data field CAN1 message box 5: Time stamp B-6 Register Symbol Page CAN1 message box 6: Identifier / DLC CAN1 message box 6: Data field CAN1 message box 6: Time stamp CAN1 message box 7: Identifier / DLC CAN1 message box 7: Data field CAN1 message box 7: Time stamp CAN1 message box 8: Identifier / DLC CAN1 message box 8: Data field CAN1 message box 8: Time stamp CAN1 message box 9: Identifier / DLC CAN1 message box 9: Data field CAN1 message box 9: Time stamp 209 210 Address 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 Register Symbol Address 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 Page CAN1 message box 10: Identifier / DLC CAN1 message box 10: Data field CAN1 message box 10: Time stamp CAN1 message box 11: Identifier / DLC CAN1 message box 11: Data field CAN1 message box 11: Time stamp 209 210 CAN1 message box 12: Identifier / DLC CAN1 message box 12: Data field CAN1 message box 12: Time stamp CAN1 message box 13: Identifier / DLC CAN1 message box 13: Data field CAN1 message box 13: Time stamp The blank areas are reserved. B-7 Register Symbol Page CAN1 message box 14: Identifier / DLC CAN1 message box 14: Data field CAN1 message box 14: Time stamp 209 210 CAN1 message box 15: Identifier / DLC CAN1 message box 15: Data field CAN1 message box 15: Time stamp CAN1 global mask register C0GMR 211 CAN1 local mask A register C0LMAR 211 CAN1 local mask B register C0LMBR 211 Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 Register Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag Symbol TABSR CPSRF ONSF TRGSR UDF Page 106,121,134 107,121 107 107,134 106 Timer A0 register TA0 Timer A1 register TA1 Timer A2 register TA2 105 132 105 132 Timer A3 register TA3 105 Timer A4 register TA4 105 132 Timer B0 register TB0 120 Timer B1 register TB1 120 Timer B2 register TB2 120 132 Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Timer B2 special mode register TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC 105 105 108 135 110 112,135 115 112 117 112,135 120,122 123,125 135 133 UART0 transmit/receive mode register U0MR UART0 bit rate generator U0BRG 142 141 UART0 transmit buffer register U0TB 141 UART0 transmit/receive control register 0 U0C0 UART0 transmit/receive control register 1 U0C1 142 143 UART0 receive buffer register 141 U0RB Address 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 UART1 transmit/receive mode register U1MR UART1 bit rate generator U1BRG 142 141 UART1 transmit buffer register U1TB 141 UART1 transmit/receive control register 0 U1C0 UART1 transmit/receive control register 1 U1C1 142 143 UART1 receive buffer register U1RB 141 UART transmit/receive control register 2 UCON 144 DMA0 request cause select register DM0SL 94 DMA1 request cause select register DM1SL 95 CRC data register CRCD 205 CRC input register CRCIN 205 The blank areas are reserved. B-8 Register Symbol Page A-D register 0 AD0 A-D register 1 AD1 A-D register 2 AD2 A-D register 3 AD3 A-D register 4 AD4 A-D register 5 AD5 A-D register 6 AD6 A-D register 7 AD7 A-D control register 2 ADCON2 190 A-D control register 0 A-D control register 1 D-A register 0 ADCON0 ADCON1 DA0 189,192,194 196,198,200 204 D-A register 1 DA1 204 D-A control register DACON 204 Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 239 239 238 238 239 239 238 238 239 239 238 238 239 239 238 238 239 239 238 238 239 Port P10 direction register PD10 238 Pull-up control register 0 Pull-up control register 1 Pull-up control register 2 Port control register PUR0 PUR1 PUR2 PCR 240 240 240 241 190 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Overview Overview The M16C/6N4 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using an M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Being equipped with two CAN (Controller Area Network) modules in M16C/6N4 group, the microcomputer is suited to drive automotive and industrial control systems. The CAN modules comply with the 2.0B specification. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations. Applications Automotive, industrial control systems and other autmobile, other Rev.1.00 2003.05.30 page 1 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Overview Performance Outline Table 1.1.1 lists a performance outline of M16C/6N4 group. Table 1.1.1 Performance outline of M16C/6N4 Group Item Performance Number of basic instructions Shortest instruction execution time 91 instructions 50.0 ns (f(BCLK)=20MHz, 1/1 prescaler, without software wait) Memory capacity ROM RAM (Refer to the product list) (Refer to the product list) I/O port Input port P0 to P10 (except P85) P85 8 bits 10, 7 bits 1 _______ 1 bit 1 (NMI pin level judgment) Multifunction timer TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2, TB3, TB4, TB5 Output: 16 bits 5 channels Input: 16 bits 6 channels Serial I/O UART0, UART1, UART2 3 channels: UART, clock synchronous, I C-bus (Note 1) (option) or IEBus (Note 2) (option) SI/O3 A-D converter 1 channel: Clock synchronous 10 bits (8 3 + 2) channels D-A converter DMAC 8 bits 2 channels 2 channels (trigger: 24 sources) CRC calculation circuit CAN Module 1 circuit: CRC-CCITT 2 channels with 2.0B specification Watchdog timer Interrupt 15 bits 1 (with prescaler) 31 internal and 9 external sources, Clock generation circuit 2 4 software sources, 7 levels 4 circuits * Main clock These circuit contain a built-in feedback resistor; and external ceramic/quartz oscillator * Sub clock } * Ring oscillator * PLL frequency synthesizer Main clock oscillation stop and re-oscillation detection function Power supply voltage Flash memory Program/erase voltage 4.2 to 5.5V (f(BCLK) = 20MHz, 1/1 prescaler, without software wait) 5.0 0.5 V Number of program/erase 100 times Mask ROM version: 18 mA Power consumption (Vcc=5V, (f(BCLK)=20MHz, 1/1 prescaler, without software wait) Flash memory version: 20 mA I/O characteristics I/O withstand voltage (Vcc=5V, (f(BCLK)=20MHz, 1/1 prescaler, without software wait) 5.0 V Output current Operating ambient temperature 5 mA -40 to 85C (T version) Memory expansion -40 to 125C (V version) (option) Available (to 1 Mbyte) Device configuration Package CMOS high performance silicon gate 100-pin plastic mold QFP Note 1: I2C-bus is a registered trademark of Koninklijke Philips Electronics N.V. Note 2: IEBus is a registered trademark of NEC Electronics Corporation. option: If you desire this option, please so specify. Rev.1.00 2003.05.30 page 2 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Overview Block Diagram Figure 1.1.1 shows a block diagram of M16C/6N4 group. 8 Port P0 8 Port P1 Port P2 8 Port P3 Clock synchronous serial I/O (8 bits 1 channel) Three-phase motor control circuit CRC arithmetic circuit (CCITT) (Polynomial: X16+X12+X5+1) CAN module (2 channels) 2003.05.30 page 3 ISP RAM (Note 2) INTB PC FLG Multiplier 8 Figure 1.1.1 Block Diagram ROM (Note 1) USP 8 Note 1: ROM size depends on microcomputer type. Note 2: RAM size depends on microcomputer type. SB R0H R0L R1H R1L R1H R1L R1H R1L R2 R2 R3 A0 A1 FB Port P10 D-A converter (8 bits 2 channels) Memory Port P9 DMAC (2 channels) M16C/60 series CPU core Port P85 UART or Clock synchronous serial I/O (8 bits 3 channels) Port P6 7 System clock generator XIN-XOUT XCIN-XCOUT PLL frequency synthesizer Ring oscillator Output (timer A): 5 Input (timer B): 6 Watchdog timer (15 bits) Rev.1.00 Port P5 8 8 Timer (16 bits) Port P4 8 Port P8 A-D converter (10 bits 8 channels Expandable up to 26 channels) 8 Port P7 Internal peripheral functions 8 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Overview Product List Table 1.1.2 lists the M16C/6N4 group products and Figure 1.1.2 shows the type numbers, memory sizes and packages. Table 1.1.2 Product List Type No. ROM capacity RAM capacity Package type M306N4MCT-XXXFP ** 128 Kbytes 5 Kbytes 100P6S-A M306N4MCV-XXXFP * M306N4FCTFP ** M306N4FCVFP As of May 2003 Remarks Mask ROM version Flash memory version * M306N4MGT-XXXFP * 256 Kbytes 10 Kbytes Mask ROM version M306N4MGV-XXXFP * M306N4FGTFP ** M306N4FGVFP * Flash memory version *: Under planning **: Under development Type No. M306N4 M C T XXX FP Package type: FP : Package 100P6S-A ROM No. Omitted on flash memory version Temperature Range T : Automotive 85oC version V : Automotive 125oC version ROM capacity: C : 128 Kbytes G : 256 Kbytes Memory type: M : Mask ROM version F : Flash ROM version M16C/6N4 Group Shows the number of CAN module, RAM capacity, pin count, etc. (The value itself has no specific meaning) M16C Family Figure 1.1.2 Type No., Memory Size, and Package Rev.1.00 2003.05.30 page 4 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Overview Pin Configuration Figures 1.1.3 shows the pin configuration (top view). P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/AN20/A0/(D0/-) P21/AN21/A1/(D1/D0) P22/AN22/A2/(D2/D1) P23/AN23/A3/(D3/D2) P24/AN24/A4/(D4/D3) P25/AN25/A5/(D5/D4) P26/AN26/A6/(D6/D5) P27/AN27/A7/(D7/D6) Vss P30/A8(/-/D7) Vcc2 P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 PIN CONFIGURATION (top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P07/AN07/D7 P06/AN06/D6 P05/AN05/D5 P04/AN04/D4 P03/AN03/D3 P02/AN02/D2 P01/AN01/D1 P00/AN00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 M16C/6N4 Group 100 2 3 4 5 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0/SCL0 P63/TXD0 /SDA0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1/SCL1 P67/TXD1/SDA1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P96/ANEX1/CTX0 P95/ANEX0/CRX0 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 (Note) P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC1 P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN/CRX1 P76/TA3OUT/CTX1 P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V (Note) P71/RxD2/SCL2/TA0IN/TB5IN P70/TXD2/SDA2/TA0 OUT 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Note: P71 and P91 are N channel open-drain output pins. Package: 100P6S-A Figure 1.1.3 Pin Configuration (Top View) Rev.1.00 2003.05.30 page 5 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Overview Pin Description Tables 1.1.3 and 1.1.4 list the pin descriptions. Table 1.1.3 Pin Description (1) Pin name Signal name I/O type Function VCC1, VCC2 VSS CNVSS Power supply input CNVSS Apply 4.2 V to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is that VCC2 = VCC1. This pin switches between processor modes. Connect this pin to the VSS pin when after a reset you want to start operation in single-chip mode (memory expansion mode) or the VCC1 pin when starting operation in microprocessor mode. Input RESET Reset input Input "L" on this input resets the microcomputer. These pins are provided for the main clock generating circuit input/output. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. XIN Clock input Input XOUT Clock output Output BYTE External data bus width select input Input AVCC Analog power supply input This pin is a power supply input for the A-D converter. Connect this pin to VCC1. AVSS Analog power supply input Reference voltage input This pin is a power supply input for the A-D converter. Connect this pin to VSS. This pin is a reference voltage input for the A-D converter and D-A converter. VREF Input This pin selects the width of an external data bus. A 16-bit width is selected when this input is "L"; an 8-bit width is selected when this input is "H". This input must be fixed to either "H" or "L". Connect this pin to the VSS pin when operating in single-chip mode. This is an 8-bit CMOS I/O port. This port has an input/output select direction register, allowing each pin in that port to be directed for input or output individually. If any port is set for input, selection can be made for it in a program whether or not to have a pull-up resistor in 4-bit unit. This selection is unavailable in memory expansion and microprocessor modes. This port can function as input pins for the A-D converter when so selected in a program. I/O port P0 Input/output Input/output When set as a separate bus, these pins input and output data (D0 to D7). I/O port P1 Input/output This is an 8-bit I/O port equivalent to P0. P15 to P17 also function as INT interrupt input pins as selected by a program. Input/output When set as a separate bus, these pins input and output data (D8 to D15). I/O port P2 Input/output This is an 8-bit I/O port equivalent to P0. This port can function as input pins for the A-D converter when so selected in a program. A0 to A7 Output These pins output 8 low-order address bits (A0 to A7). A0/D0 to A7/D7 Input/output If the external bus is set as an 8-bit width multiplexed bus, these pins input and output data (D0 to D7) and output 8 low-order address bits (A0 to A7) separated in time by multiplexing. A0 , A1/D0 to A7/D6 Output Input/output If the external bus is set as a 16-bit width multiplexed bus, these pins input and output data (D0 to D6) and output address (A1 to A7) separated in time by multiplexing. They also output address (A0). Input/output This is an 8-bit I/O port equivalent to P0. P00 to P07 D0 to D7 P10 to P17 D8 to D15 P20 to P27 P30 to P37 I/O port P3 A8 to A15 Output These pins output 8 middle-order address bits (A8 to A15). A8/D7, A9 to A15 Input/output Output If the external bus is set as a 16-bit width multiplexed bus, these pins input and output data (D 7 ) and output address (A 8 ) separated in time by multiplexing. They also output address (A9 to A15). Input/output This is an 8-bit I/O port equivalent to P0. Output Output These pins output A16 to A19 and CS0 to CS3 signals. A16 to A19 are 4 high-order address bits. CS0 to CS3 are chip select signals used to specify an access space. P40 to P47 I/O port P4 A16 to A19, CS0 to CS3 Rev.1.00 2003.05.30 page 6 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Overview Table 1.1.4 Pin Description (2) Pin name P50 to P57 Signal name I/O port P5 WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, ALE, RDY I/O type Function Input/output This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by program. Output Output Output Output Output Input Output Input Output WRL/WR, WRH/BHE, RD, BCLK, HLDA, and ALE signals. WRL/WR and WRH/BHE are switchable in a program. Note that WRL and WRH are always used as a pair, so as WR and BHE. WRL, WRH, and RD selected If the external data bus is a 16-bit width, data are written to even addresses when the WRL signal is low, and written to odd addresses when the WRH signal is low. Data are read out when the RD signal is low. WR, BHE, and RD selected Data are written when the WR signal is low, or read out when the RD signal is low. Odd addresses are accessed when the BHE signal is low. Use this mode when the external data bus is an 8-bit width. The microcomputer goes to a hold state when input to the HOLD pin is held low. While in the hold state, HLDA outputs a low level. ALE is used to latch the address. While the input level of the RDY pin is low, the bus of the microcomputer goes to a wait state. P60 to P67 I/O port P6 Input/output This is an 8-bit I/O port equivalent to P0. Pins in this port also function as UART0 and UART1 I/O pins as selected by program. P70 to P77 I/O port P7 Input/output This is an 8-bit I/O port equivalent to P0 (P71 is an N channel open-drain output). This port can function as input/output pins for timers A0 to A3 when so selected in a program. Furthermore, P70 to P73, P71, P72 to P75 and P76, P77 can also function as input/output pins for UART2, an input pin for timer B5, output pins for the three-phase motor control timer, and input/output pin for the CAN1, respectively. P80 to P84, P86, P87 I/O port P8 Input/output Input/output Input/output P80 to P84, P86 and P87 are I/O ports with the same functions as P0. When so selected in a program, P80, P81, and P82 to P84 can function as input/output pins for timer A4 or output pins for the three-phase motor control timer and INT interrupt input pins, respectively. P86 and P87, when so selected in a program, both can function as input/output pins for the sub clock oscillator circuit. In that case, connect a crystal resonator between P86 (XCOUT pin) and P87 (XCIN pin). P85 Input port P85 Input P85 is an input-only port shared with NMI. An NMI interrupt request is generated when input on this pin changes state from high to low. The NMI function cannot be disabled in a program. A pull-up cannot be set for this pin. P90 to P97 I/O port P9 Input/output This is an 8-bit I/O port equivalent to P0 (P91 is an N channel open-drain output). Pins in this port also function as input/output pins for SI/O3, input pins for times B0 to B4, output pins for D-A converter, and input pins for A-D converter or input/output pins for CAN0, or input pins for A-D trigger as selected by program. P100 to P107 I/O port P10 Input/output This is an 8-bit I/O port equivalent to P0. Pins in this port also function as input pins for A-D converter as selected by program. Furthermore, P104 to P107 also function as input pins for the key input interrupt function. Rev.1.00 2003.05.30 page 7 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Memory Memory Figure 1.2.1 shows a memory map of the M16C/6N4 group. The address space extends the 1 Mbyte from address 0000016 to FFFFF16. The internal ROM is allocated in a lower address direction beginning with address FFFFF16. For example, a 128-Kbyte internal ROM is allocated to the addresses from E000016 to FFFFF16. The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 0040016. For example, a 5-Kbyte internal RAM is allocated to the addresses from 0040016 to 017FF16. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users. The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used by the JMPS or JSRS instruction. For details, refer to the "M16C/60 and M16C/20 Series Software Manual". In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. 0000016 SFR 0040016 FFE0016 Internal RAM XXXXX16 Reserved area (Note 1) Special page vector table 0800016 External area 2700016 Reserved area FFFDC16 2800016 8000016 Internal RAM Size Internal ROM Address XXXXX16 Size Address YYYYY16 5 Kbytes 017FF16 128 Kbytes E000016 10 Kbytes 02BFF16 256 Kbytes C000016 BRK instruction Address match Single step Reserved area (Note 2) Oscillation stop and re-oscillation detection / watchdog timer YYYYY16 Internal ROM FFFFF16 Undefined instruction Overflow External area FFFFF16 DBC NMI Reset Note 1: During memory expansion and microprocessor modes, can not be used. Note 2: In memory expansion mode, can not be used. Note 3: Shown here is a memory map for the case where the PM13 bit in the PM1 register is "0". However, this shows the case where the PM13 bit is "1" on the devices whose internal ROM is 192 Kbytes or more. Figure 1.2.1 Memory Map Rev.1.00 2003.05.30 page 8 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CPU Central Processing Unit (CPU) Figure 1.3.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b31 b15 b8 b7 b0 R2 R0H (R0's high bits) R0L (R0's low bits) R3 R1H (R1's high bits) R1L (R1's low bits) Data registers (Note) R2 R3 A0 Address registers (Note) A1 FB Frame base registers (Note) b19 b0 INTBH Interrupt table register INTBL The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. b19 b0 Program counter PC b15 b0 USP User stack pointer ISP Interrupt stack pointer SB Static base register b15 b0 FLG b15 Flag register b8 b7 IPL U b0 I O B S Z D C Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Note: These registers comprise a register bank. There are two register banks. Figure 1.3.1 CPU Registers (1) Data Registers (R0, R1, R2, and R3) The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is the same as R2R0. (2) Address Registers (A0 and A1) The A0 register consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0. In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0). Rev.1.00 2003.05.30 page 9 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CPU (3) Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. (4) Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. (5) Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. (6) User Stack Pointer (USP), Interrupt Stack Pointer (ISP) Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG. (7) Static Base Register (SB) SB is configured with 16 bits, and is used for SB relative addressing. (8) Flag Register (FLG) FLG consists of 11 bits, indicating the CPU status. * Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. * Debug Flag (D Flag) This flag is used exclusively for debugging purpose. During normal use, it must be set to "0". * Zero Flag (Z Flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, it is "0". * Sign Flag (S Flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, it is "0". * Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". * Overflow Flag (O Flag) This flag is set to "1" when the operation resulted in an overflow; otherwise, it is "0". * Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is "0", and are enabled when the I flag is "1". The I flag is set to "0" when the interrupt request is accepted. * Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is "0" ; USP is selected when the U flag is "1". The U flag is set to "0" when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. * Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt request is enabled. * Reserved Area When white to this bit, write "0". When read, its content is indeterminate. Rev.1.00 2003.05.30 page 10 Under development This document is under development and its contents are subject to change. M16C/6N4 Group SFR SFR Figures 1.4.1 to 1.4.16 show the location of peripheral function control registers and the value after reset. Address 000016 000116 000216 000316 Register Symbol After reset 000000002 (CNVSS pin is "L") 000000112 (CNVSS pin is "H") 0XXX10002 010010002 001000002 000000012 XXXXXX002 XX0000002 000416 Processor mode register 0 (Note 1) PM0 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Processor mode register 1 System clock control register 0 System clock control register 1 Chip select control register Address match interrupt enable register Protect register PM1 CM0 CM1 CSR AIER PRCR Oscillation stop detection register (Note 2) CM2 0X00X0002 Watchdog timer start register Watchdog timer control register WDTS WDC Address match interrupt register 0 RMAD0 XX16 00XXXXXX2 0016 0016 X016 Address match interrupt register 1 RMAD1 Chip select expansion control register PLL control register 0 CSE PLC0 0016 0001X0102 Processor mode register 2 PM2 XXX000002 DMA0 source pointer SAR0 XX16 XX16 XX16 DMA0 destination pointer DAR0 XX16 XX16 XX16 DMA0 transfer counter TCR0 XX16 XX16 DMA0 control register DM0CON DMA1 source pointer SAR1 XX16 XX16 XX16 DMA1 destination pointer DAR1 XX16 XX16 XX16 DMA1 transfer counter TCR1 XX16 XX16 DMA1 control register DM1CON 0016 0016 X016 00000X002 00000X002 X: Undefined Note 1: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. Note 2: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset. Note 3: The blank areas are reserved and cannot be accessed by users. Figure 1.4.1 Location of Peripheral Function Control Registers and Value at After Reset (1) Rev.1.00 2003.05.30 page 11 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 SFR Register CAN0/1 wake up interrupt control register CAN0 successful reception interrupt control register CAN0 successful transmission interrupt control register INT3 interrupt control register Timer B5 interrupt control register Timer B4 interrupt control register UART1 bus collision detection interrupt control register Timer B3 interrupt control register UART0 bus collision detection interrupt control register CAN1 successful reception interrupt control register INT5 interrupt control register CAN1 successful transmission interrupt control register SI/O3 interrupt control register INT4 interrupt control register UART2 bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register CAN0/1 error interrupt control register A-D conversion interrupt control register Key input interrupt control register UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register CAN0 message box 0: Identifier / DLC CAN0 message box 0: Data field CAN0 message box 0: Time stamp CAN0 message box 1: Identifier / DLC CAN0 message box 1: data Field CAN0 message box 1: Time stamp Symbol C01WKIC C0RECIC C0TRMIC INT3IC TB5IC TB4IC U1BCNIC TB3IC U0BCNIC C1RECIC INT5IC C1TRMIC S3IC INT4IC U2BCNIC DM0IC DM1IC C01ERRIC ADIC KUPIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC After reset XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002 XX00X0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002 XX00X0002 XX00X0002 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Undefined Note: The blank area is reserved and cannot be accessed by users. Figure 1.4.2 Location of Peripheral Function Control Registers and Value at After Reset (2) Rev.1.00 2003.05.30 page 12 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16 SFR Register CAN0 message box 2: Identifier / DLC CAN0 message box 2: Data field CAN0 message box 2: Time stamp CAN0 message box 3: Identifier / DLC CAN0 message box 3: Data field CAN0 message box 3: Time stamp CAN0 message box 4: Identifier / DLC CAN0 message box 4: Data field CAN0 message box 4: Time stamp CAN0 message box 5: Identifier / DLC CAN0 message box 5: Data field CAN0 message box 5: Time stamp Symbol After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Undefined Figure 1.4.3 Location of Peripheral Function Control Registers and Value at After Reset (3) Rev.1.00 2003.05.30 page 13 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 SFR Register CAN0 message box 6: Identifier / DLC CAN0 message box 6: Data field CAN0 message box 6: Time stamp CAN0 message box 7: Identifier / DLC CAN0 message box 7: Data field CAN0 message box 7: Time stamp CAN0 message box 8: Identifier / DLC CAN0 message box 8: Data field CAN0 message box 8: Time stamp CAN0 message box 9: Identifier / DLC CAN0 message box 9: Data field CAN0 message box 9: Time stamp Symbol After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Undefined Figure 1.4.4 Location of Peripheral Function Control Registers and Value at After Reset (4) Rev.1.00 2003.05.30 page 14 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 011816 011916 011A16 011B16 011C16 011D16 011E16 011F16 012016 012116 012216 012316 012416 012516 012616 012716 012816 012916 012A16 012B16 012C16 012D16 012E16 012F16 013016 013116 013216 013316 013416 013516 013616 013716 013816 013916 013A16 013B16 013C16 013D16 013E16 013F16 SFR Register CAN0 message box 10: Identifier / DLC CAN0 message box 10: Data field CAN0 message box 10: Time stamp CAN0 message box 11: Identifier / DLC CAN0 message box 11: Data field CAN0 message box 11: Time stamp CAN0 message box 12: Identifier / DLC CAN0 message box 12: Data field CAN0 message box 12: Time stamp CAN0 message box 13: Identifier / DLC CAN0 message box 13: Data field CAN0 message box 13: Time stamp Symbol After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Undefined Figure 1.4.5 Location of Peripheral Function Control Registers and Value at After Reset (5) Rev.1.00 2003.05.30 page 15 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A16 014B16 014C16 014D16 014E16 014F16 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A16 015B16 015C16 015D16 015E16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A16 016B16 016C16 016D16 016E16 016F16 017016 017116 017216 017316 017416 017516 017616 017716 017816 017916 017A16 017B16 017C16 017D16 017E16 017F16 SFR Register Symbol CAN0 message box 14: Identifier /DLC CAN0 message box 14: Data field CAN0 message box 14: Time stamp CAN0 message box 15: Identifier /DLC CAN0 message box 15: Data field CAN0 message box 15: Time stamp CAN0 global mask register C0GMR CAN0 local mask A register C0LMAR CAN0 local mask B register C0LMBR After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Undefined Note: The blank areas are reserved and cannot be accessed by users. Figure 1.4.6 Location of Peripheral Function Control Registers and Value at After Reset (6) Rev.1.00 2003.05.30 page 16 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 018016 018116 018216 018316 018416 018516 018616 018716 018816 018916 018A16 018B16 018C16 018D16 018E16 018F16 019016 019116 019216 019316 019416 019516 019616 019716 019816 019916 019A16 019B16 019C16 019D16 019E16 019F16 01A016 01A116 01A216 01A316 01A416 01A516 01A616 01A716 01A816 01A916 01AA16 01AB16 01AC16 01AD16 01AE16 01AF16 01B016 01B116 01B216 01B316 01B416 01B516 01B616 01B716 01B816 01B916 01BA16 01BB16 01BC16 01BD16 01BE16 01BF16 SFR Register Symbol After reset Flash memory control register 1 (Note 1) FMR1 0X00XX0X2 Flash memory control register 0 (Note 1) FMR0 Address match interrupt register 2 RAMD2 Address match interrupt enable register 2 AIER2 Address match interrupt register 3 RAMD3 XX0000012 0016 0016 X016 XXXXXX002 0016 0016 X016 X: Undefined Note 1: This register is included in flash memory version. Note 2: The blank areas are reserved and cannot be accessed by users. Figure 1.4.7 Location of Peripheral Function Control Registers and Value at After Reset (7) Rev.1.00 2003.05.30 page 17 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 01C016 01C116 01C216 01C316 01C416 01C516 01C616 01C716 01C816 01C916 01CA16 01CB16 01CC16 01CD16 01CE16 01CF16 01D016 01D116 01D216 01D316 01D416 01D516 01D616 01D716 01D816 01D916 01DA16 01DB16 01DC16 01DD16 01DE16 01DF16 01E016 01E116 01E216 01E316 01E416 01E516 01E616 01E716 01E816 01E916 01EA16 01EB16 01EC16 01ED16 01EE16 01EF16 01F016 01F116 01F216 01F316 01F416 01F516 01F616 01F716 01F816 01F916 01FA16 01FB16 01FC16 01FD16 01FE16 01FF16 SFR Register Timer B3,4,5 count start flag Symbol TBSR After reset 000XXXXX2 Timer A1-1 register TA11 Timer A2-1 register TA21 Timer A4-1 register TA41 Three-phase PWM control register 0 Three-phase PWM control register 1 Three-phase output buffer register 0 Three-phase output buffer register 1 Dead time timer Timer B2 interrupt occurrence frequency set counter INVC0 INVC1 IDB0 IDB1 DTT ICTB2 Timer B3 register TB3 Timer B4 register TB4 Timer B5 register TB5 Timer B3 mode register Timer B4 mode register Timer B5 mode register Interrupt cause select register 0 Interrupt cause select register 1 SI/O3 transmit/receive register TB3MR TB4MR TB5MR IFSR0 IFSR1 S3TRR 00XX00002 00XX00002 00XX00002 00XXX0002 0016 XX16 SI/O3 control register SI/O3 bit rate generator S3C S3BRG 010000002 XX16 UART0 special mode register 4 UART0 special mode register 3 UART0 special mode register 2 UART0 special mode register UART1 special mode register 4 UART1 special mode register 3 UART1 special mode register 2 UART1 special mode register UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 bit rate generator U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG UART2 transmit buffer register U2TB UART2 transmit/receive mode register 0 UART2 transmit/receive mode register 1 U2C0 U2C1 UART2 receive buffer register U2RB 0016 000X0X0X2 X00000002 X00000002 0016 000X0X0X2 X00000002 X00000002 0016 000X0X0X2 X00000002 X00000002 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 0016 0016 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Undefined Note: The blank areas are reserved and cannot be accessed by users. Figure 1.4.8 Location of Peripheral Function Control Registers and Value at After Reset (8) Rev.1.00 2003.05.30 page 18 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 020016 020116 020216 020316 020416 020516 020616 020716 020816 020916 020A16 020B16 020C16 020D16 020E16 020F16 021016 021116 021216 021316 021416 021516 021616 021716 021816 021916 021A16 021B16 021C16 021D16 021E16 021F16 022016 022116 022216 022316 022416 022516 022616 022716 022816 022916 022A16 022B16 022C16 022D16 022E16 022F16 023016 023116 023216 023316 023416 023516 023616 023716 023816 023916 023A16 023B16 023C16 023D16 023E16 023F16 SFR Register CAN0 message control register 0 CAN0 message control register 1 CAN0 message control register 2 CAN0 message control register 3 CAN0 message control register 4 CAN0 message control register 5 CAN0 message control register 6 CAN0 message control register 7 CAN0 message control register 8 CAN0 message control register 9 CAN0 message control register 10 CAN0 message control register 11 CAN0 message control register 12 CAN0 message control register 13 CAN0 message control register 14 CAN0 message control register 15 Symbol C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 CAN0 control register C0CTLR CAN0 status register C0STR CAN0 slot status register C0SSTR CAN0 interrupt control register C0ICR CAN0 extended register C0IDR CAN0 configuration register C0CONR CAN0 receive error count register CAN0 transmit error count register C0RECR C0TECR CAN0 time stamp register C0TSR CAN1 message control register 0 CAN1 message control register 1 CAN1 message control register 2 CAN1 message control register 3 CAN1 message control register 4 CAN1 message control register 5 CAN1 message control register 6 CAN1 message control register 7 CAN1 message control register 8 CAN1 message control register 9 CAN1 message control register 10 CAN1 message control register 11 CAN1 message control register 12 CAN1 message control register 13 CAN1 message control register 14 CAN1 message control register 15 C1MCTL0 C1MCTL1 C1MCTL2 C1MCTL3 C1MCTL4 C1MCTL5 C1MCTL6 C1MCTL7 C1MCTL8 C1MCTL9 C1MCTL10 C1MCTL11 C1MCTL12 C1MCTL13 C1MCTL14 C1MCTL15 CAN1 control register C1CTLR CAN1 status register C1STR CAN1 slot status register C1SSTR CAN1 interrupt control register C1ICR CAN1 extended register C1IDR CAN1 configuration register C1CONR CAN1 receive error count register CAN1 transmit error count register C1RECR C1TECR CAN1 time stamp register C1TSR After reset 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 X00000012 XX0X00002 0016 X00000012 0016 0016 0016 0016 0016 0016 XX16 XX16 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 X00000012 XX0X00002 0016 X00000012 0016 0016 0016 0016 0016 0016 XX16 XX16 0016 0016 0016 0016 X: Undefined Figure 1.4.9 Location of Peripheral Function Control Registers and Value at After Reset (9) Rev.1.00 2003.05.30 page 19 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 024016 024116 024216 024316 024416 024516 024616 024716 024816 024916 024A16 024B16 024C16 024D16 024E16 024F16 025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 025B16 025C16 025D16 025E16 025F16 026016 026116 026216 026316 026416 026516 026616 026716 026816 026916 026A16 026B16 026C16 026D16 026E16 026F16 027016 027116 027216 027316 027416 027516 027616 027716 027816 027916 027A16 027B16 027C16 027D16 027E16 027F16 SFR Register Symbol CAN0 acceptance filter support register C0AFS CAN1 acceptance filter support register C1AFS Peripheral function clock select register CAN0/1 clock select register PCLKR CCLKR CAN1 message box 0: Identifier / DLC CAN1 message box 0: Data field CAN1 message box 0:Time stamp CAN1 message box 1: Identifier / DLC CAN1 message box 1: Data field CAN1 message box 1:Time stamp After reset XX16 XX16 XX16 XX16 0016 0016 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Undefined Note: The blank areas are reserved and cannot be accessed by users. Figure 1.4.10 Location of Peripheral Function Control Registers and Value at After Reset (10) Rev.1.00 2003.05.30 page 20 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 028016 028116 028216 028316 028416 028516 028616 028716 028816 028916 028A16 028B16 028C16 028D16 028E16 028F16 029016 029116 029216 029316 029416 029516 029616 029716 029816 029916 029A16 029B16 029C16 029D16 029E16 029F16 02A016 02A116 02A216 02A316 02A416 02A516 02A616 02A716 02A816 02A916 02AA16 02AB16 02AC16 02AD16 02AE16 02AF16 02B016 02B116 02B216 02B316 02B416 02B516 02B616 02B716 02B816 02B916 02BA16 02BB16 02BC16 02BD16 02BE16 02BF16 SFR Register CAN1 message box 2: Identifier / DLC CAN1 message box 2: Data field CAN1 message box 2: Time stamp CAN1 message box 3: Identifier / DLC CAN1 message box 3: Data field CAN1 message box 3: Time stamp CAN1 message box 4: Identifier / DLC CAN1 message box 4: Data field CAN1 message box 4: Time stamp CAN1 message box 5: Identifier / DLC CAN1 message box 5: Data field CAN1 message box 5: Time stamp Symbol After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Undefined Figure 1.4.11 Location of Peripheral Function Control Registers and Value at After Reset (11) Rev.1.00 2003.05.30 page 21 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 02EB16 02EC16 02ED16 02EE16 02EF16 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA16 02FB16 02FC16 02FD16 02FE16 02FF16 SFR Register CAN1 message box 6: Identifier / DLC CAN1 message box 6: Data field CAN1 message box 6: Time stamp CAN1 message box 7: Identifier / DLC CAN1 message box 7: Data field CAN1 message box 7: Time stamp CAN1 message box 8: Identifier / DLC CAN1 message box 8: Data field CAN1 message box 8: Time stamp CAN1 message box 9: Identifier / DLC CAN1 message box 9: Data field CAN1 message box 9: Time stamp Symbol After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Undefined Figure 1.4.12 Location of Peripheral Function Control Registers and Value at After Reset (12) Rev.1.00 2003.05.30 page 22 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 SFR Register CAN1 message box 10: Identifier / DLC CAN1 message box 10: Data field CAN1 message box 10: Time stamp CAN1 message box 11: Identifier / DLC CAN1 message box 11: Data field CAN1 message box 11: Time stamp CAN1 message box 12: Identifier / DLC CAN1 message box 12: Data field CAN1 message box 12: Time stamp CAN1 message box 13: Identifier / DLC CAN1 message box 13: Data field CAN1 message box 13: Time stamp Symbol After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Undefined Figure 1.4.13 Location of Peripheral Function Control Registers and Value at After Reset (13) Rev.1.00 2003.05.30 page 23 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 SFR Register Symbol CAN1 message box 14: Identifier / DLC CAN1 message box 14: Data field CAN1 message box 14: Time stamp CAN1 message box 15: Identifier / DLC CAN1 message box 15: Data field CAN1 message box 15: Time stamp CAN1 global mask register C1GMR CAN1 local mask A register C1LMAR CAN1 local mask B register C1LMBR After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Undefined Note: The blank areas are reserved and cannot be accessed by users. Figure 1.4.14 Location of Peripheral Function Control Registers and Value at After Reset (14) Rev.1.00 2003.05.30 page 24 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 SFR Register Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag Symbol TABSR CPSRF ONSF TRGSR UDF After reset 0016 0XXXXXXX2 0016 0016 0016 Timer A0 register TA0 Timer A1 register TA1 Timer A2 register TA2 Timer A3 register TA3 Timer A4 register TA4 Timer B0 register TB0 Timer B1 register TB1 Timer B2 register TB2 Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Timer B2 special mode register TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC UART0 transmit/receive mode register UART0 bit rate generator U0MR U0BRG UART0 transmit buffer register U0TB UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 U0C0 U0C1 UART0 receive buffer register U0RB UART1 transmit/receive mode register UART1 bit rate generator U1MR U1BRG UART1 transmit buffer register U1TB UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 U1C0 U1C1 UART1 receive buffer register U1RB UART transmit/receive control register 2 UCON 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 X00000002 DMA0 request cause select register DM0SL 0016 DMA1 request cause select register DM1SL 0016 CRC data register CRCD CRC input register CRCIN XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 0016 0016 0016 00XX00002 00XX00002 00XX00002 XXXXXX002 XX16 XX16 XX16 X: Undefined Note: The blank areas are reserved and cannot be accessed by users. Figure 1.4.15 Location of Peripheral Function Control Registers and Value at After Reset (15) Rev.1.00 2003.05.30 page 25 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Address 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 SFR Register Symbol After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 A-D register 0 AD0 A-D register 1 AD1 A-D register 2 AD2 A-D register 3 AD3 A-D register 4 AD4 A-D register 5 AD5 A-D register 6 AD6 A-D register 7 AD7 A-D control register 2 ADCON2 0016 A-D control register 0 A-D control register 1 D-A register 0 ADCON0 ADCON1 DA0 00000XXX2 0016 XX16 D-A register 1 DA1 XX16 D-A control register DACON 0016 Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 00X000002 0016 XX16 Port P10 direction register PD10 0016 Pull-up control register 0 PUR0 03FD16 Pull-up control register 1 PUR1 03FE16 03FF16 Pull-up control register 2 Port control register PUR2 PCR 0016 000000002 (Note 1) 000000102 0016 0016 X: Undefined Note 1: At hardware reset, the register is as follows: "000000002" where "L" is input to the CNVSS pin "000000102" where "H" is input to the CNVSS pin At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows: "000000002" where the PM01 to PM00 bits in the PM0 register are "002" (single-chip mode) "000000102" where the PM01 to PM00 bits in the PM0 register are "012" (memory expansion mode) or "112" (microprocessor mode) Note 2: The blank areas are reserved and cannot be accessed by users. Figure 1.4.16 Location of Peripheral Function Control Registers and Value at After Reset (16) Rev.1.00 2003.05.30 page 26 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Reset Reset There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscillation stop detection reset. Hardware Reset ____________ ____________ A reset is applied using the RESET pin. When an "L" signal is applied to the RESET pin while the power supply voltage is within____________ the recommended operating condition, the pins are initialized (refer to "Table 1.5.1 Pin Status When RESET Pin Level is ____________ "L" "). The oscillation circuit is initialized and the main clock starts oscillating. When the input level at the RESET pin is released from "L" to "H", the CPU and SFR are initialized, and the program is executed starting from the address indicated by the reset vector. The ____________ internal RAM is not initialized. If the RESET pin is pulled "L" while writing to the internal RAM, the internal RAM becomes indeterminate. Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence. Table 1.5.1 shows ____________ the statuses of the other pins while the RESET pin is "L". Figure 1.5.3 shows the CPU register status after reset. Refer to "SFR" for SFR status after reset. 1. When the power supply is ____________ stable (1) Apply an "L" signal to the RESET pin. (2) Supply a clock for 20 cycles or more to the XIN pin. ____________ (3) Apply an "H" signal to the RESET pin. 2. Power on ____________ (1) Apply an "L" signal to the RESET pin. (2) Let the power supply voltage increase until it meets the recommended operating condition. (3) Wait for td(P-R) or more until the internal power supply stabilizes. (4) Supply a clock for 20 cycles or more to the XIN pin. ____________ (5) Apply an "H" signal to the RESET pin. Software Reset When the PM03 bit in the PM0 register is set to "1" (microcomputer reset), the microcomputer has its pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset vector. Select the main clock for the CPU clock source, and set the PM03 bit to "1" with main clock oscillation satisfactorily stable. At software reset, some SFR's are not initialized. Refer to "SFR". Also, since the PM01 to PM00 bits in the PM0 register are not initialized, the processor mode remains unchanged. Watchdog Timer Reset Where the PM12 bit in the PM1 register is "1" (reset when watchdog timer underflows), the microcomputer initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed starting from the address indicated by the reset vector. At watchdog timer reset, some SFR's are not initialized. Refer to "SFR". Also, since the PM01 to PM00 bits in the PM0 register are not initialized, the processor mode remains unchanged. Oscillation Stop Detection Reset Where the CM27 bit in the CM2 register is "0" (reset at oscillation stop, re-oscillation detection), the microcomputer initializes its pins, CPU and SFR, coming to a halt if it detects main clock oscillation circuit stop. Refer to "Oscillation Stop and Re-oscillation Detection Function". At oscillation stop detection reset, some SFR's are not initialized. Refer to "SFR". Also, since the PM01 to PM00 bits in the PM0 register are not initialized, the processor mode remains unchanged. Rev.1.00 2003.05.30 page 27 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Reset VCC1 Recommended operating voltage 0V VCC1 RESET RESET Equal to or less than 0.2VCC1 Equal to or less than 0.2VCC1 0V More than 20 cycles of XIN + td(P-R) are needed. Figure 1.5.1 Example Reset Circuit VCC1 XIN td(P-R) More than 20 cycles are needed Microprocessor mode BYTE = H RESET BCLK 28cycles BCLK Content of reset vector FFFFC16 Address FFFFD16 FFFFE16 RD WR CS0 Microprocessor mode BYTE = L Content of reset vector FFFFC16 Address FFFFE16 RD WR CS0 Single-chip mode FFFFC16 FFFFE16 Address Figure 1.5.2 Reset Sequence Rev.1.00 2003.05.30 Content of reset vector page 28 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Reset ____________ Table 1.5.1 Pin Status When RESET Pin Level is "L" Status Pin name CNVSS = VCC1 (Note) BYTE = VSS BYTE = VCC1 CNVSS = VSS P0 P1 P2, P3, P40 to P43 P44 P45 to P47 P50 P51 P52 P53 P54 Input port Input port Input port Input port Input port Input port Input port Input port Input port Input port Input port Data input Data input Address output (undefined) ______ CS0 output ("H" is output) Input port (Pulled high) ______ WR output ("H" is output) ________ BHE output (undefined) ______ RD output ("H" is output) BCLK output ___________ HLDA output (The output value depends on __________ the input to the HOLD pin) __________ HOLD input Data input Input port Address output (undefined) ______ CS0 output ("H" is output) Input port (Pulled high) ______ WR output ("H" is output) ________ BHE output (undefined) ______ RD output ("H" is output) BCLK output ___________ HLDA output (The output value depends on __________ the input to the HOLD pin) __________ HOLD input P55 P56 P57 Input port Input port ALE output ("L" is output) ________ RDY input ALE output ("L" is output) ________ RDY input Input port Input port P6, P7, P80 to P84, Input port P86, P87, P9, P10 Note: Shown here is the valid pin state when the internal power supply voltage has stabilized after power-on. When CNVSS = VCC1, the pin state is indeterminate until the internal power supply voltage stabilizes. b15 b0 000016 Data register (R0) 000016 Data register (R1) 000016 Data register (R2) 000016 Data register (R3) 000016 Address register (A0) 000016 Address register (A1) 000016 Frame base register (FB) b19 b0 Interrupt table register (INTB) 0000016 Content of addresses FFFFE16 to FFFFC16 b15 b0 000016 User stack pointer (USP) 000016 Interrupt stack pointer (ISP) 000016 Static base register (SB) b15 b0 000016 b15 U b0 I O B S Figure 1.5.3 CPU Register Status After Reset Rev.1.00 2003.05.30 Flag register (FLG) b8 b7 IPL page 29 Program counter (PC) Z D C Under development This document is under development and its contents are subject to change. M16C/6N4 Group Processor Mode Processor Mode (1) Types of Processor Mode Three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode. Table 1.6.1 shows the features of these processor modes. Table 1.6.1 Features of Processor Modes Processor mode Single-chip mode Access space Pins which are assigned I/O ports SFR, internal RAM, internal ROM All pins are I/O ports or peripheral function I/O pins Memory expansion mode SFR, internal RAM, internal ROM, Some pins serve as bus control pins (Note) external area (Note) Microprocessor mode SFR, internal RAM, external area (Note) Some pins serve as bus control pins (Note) Note: Refer to "Bus". (2) Setting Processor Modes Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register. Table 1.6.2 shows the processor mode after hardware reset. Table 1.6.3 shows the PM01 to PM00 bits set values and processor modes. Table 1.6.2 Processor Mode After Hardware Reset CNVSS pin input level VSS Single-chip mode VCC1 (Notes 1, 2) Microprocessor mode Processor mode Note 1: If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin, the internal ROM cannot be accessed regardless of PM01 to PM00 bits. _____ Note 2: The multiplexed bus cannot be assigned to the entire CS space. Table 1.6.3 PM01 to PM00 Bits Set Values and Processor Modes PM01 to PM 00 bits Processor mode 002 Single-chip mode 012 Memory expansion mode 102 Must not be set 112 Microprocessor mode Rewriting the PM01 to PM00 bits places the microcomputer in the corresponding processor mode regardless of whether the input level on the CNVSS pin is "H" or "L". Note, however, that the PM01 to PM00 bits cannot be rewritten to "012" (memory expansion mode) or "112" (microprocessor mode) at the same time the PM07 to PM02 bits are rewritten. Note also that these bits cannot be rewritten to enter microprocessor mode in the internal ROM, nor can they be rewritten to exit microprocessor mode in areas overlapping the internal ROM. If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset), the internal ROM cannot be accessed regardless of PM01 to PM00 bits. Figures 1.6.1 and 1.6.2 show the processor mode related registers. Figure 1.6.3 shows the memory map _____ in single-chip mode. Figures 1.6.4 to 1.6.7 show the memory map and CS area in memory expansion mode and microprocessor mode. Rev.1.00 2003.05.30 page 30 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Processor Mode Processor mode register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PM0 Bit symbol Address 000416 After reset (Note 2) 000000002 (CNVSS pin = L) 000000112 (CNVSS pin = H) Bit name Function RW b1 b0 Processor mode bit (Note 2) 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Must not be set 1 1 : Microprocessor mode PM02 R/W mode select bit (Note 3) 0 : RD, BHE, WR 1 : RD, WRH, WRL RW PM03 Software reset bit Setting this bit to "1" resets the microcomputer. When read, its . content is "0" RW PM00 PM01 RW RW b5 b4 0 0 : Multiplexed bus is unused PM04 Multiplexed bus space select bit (Note 3) PM05 PM06 Port P40 to P43 function select bit (Note 3) PM07 BCLK output disable bit (Note 3) RW (Separate bus in the entire CS space) 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space RW 1 1 : Allocated to the entire CS space (Note 4) 0 : Address output 1 : Port function (Address is not output) 0 : BCLK is output 1 : BCLK is not output (Pin is left high-impedance) RW RW Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable). Note 2: The PM01 to PM00 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. Note 3: Effective when the PM01 to PM00 bits are set to "012" (memory expansion mode) or "112" (microprocessor mode). Note 4: To set the PM01 to PM00 bits are "012" and the PM05 to PM04 bits are "112" (multiplexed bus assigned to the entire CS space), apply an "H" signal to the BYTE pin (external data bus is 8-bit width). While the CNVSS pin is held "H" (VCC1), do not rewrite the PM05 to PM04 bits to "112" after reset. If the PM05 to PM04 bits are set to "112" during memory expansion mode, P31 to P37 and P40 to P43 become I/O ports, in which case the accessible area for each CS is 256 bytes. Figure 1.6.1 PM0 Register Rev.1.00 2003.05.30 page 31 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Processor Mode Processor mode register 1 (Note 1) b7 b6 b5 0 0 b4 b3 b2 b1 b0 0 Symbol PM1 Address 000516 After reset 0XXX10002 Bit symbol Bit name PM10 CS2 area switch bit (data block enable bit) (Note 2) 0 : 0800016 to 26FFF16 (block A disable) 1 : 1000016 to 26FFF16 (block A enable) RW PM11 Port P37 to P34 function select bit (Note 3) 0 : Address output 1 : Port function RW PM12 Watchdog timer function select bit 0 : Watchdog timer interrupt 1 : Watchdog timer reset (Note 4) RW PM13 Internal reserved area expansion bit (Note 5) Internal ROM area is: 0 : 192 Kbytes or smaller 1 : Expanded over 192 Kbytes RW Reserved bit Set to "0". RW 0 : No wait state 1 : With wait state (1 wait) RW (b6-b4) PM17 Wait bit (Note 6) Function RW Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable). Note 2: For the mask ROM version, this bit must be set to "0". For the flash memory version, the PM10 bit also controls block A by enabling or disabling it. However, the PM10 bit is automatically set to "1" when the FMR01 bit in the FMR0 register is "1" (CPU rewrite mode). Note 3: Effective when the PM01 to PM00 bits are set to "012" (memory expansion mode) or "112" (microprocessor mode). Note 4: The PM12 bit is set to "1" by writing a "1" in a program. (Writing a "0" has no effect.) Note 5: Be sure to set this bit to "0" except for products with internal ROM area over 192 Kbytes. The PM13 bit is automatically set to "1" when the FMR01 bit in the FMR0 register is "1" (CPU rewrite mode). Note 6: When the PM17 bit is set to "1" (with wait state), one wait state is inserted when accessing the internal RAM, internal ROM, or an external area. If the CSiW bit (i = 0 to 3) in the CSR register is "0" (with wait state), the CSi area is always accessed with one or more wait states regardless of whether the PM17 bit is set or not. Where the RDY signal is used or multiplexed bus is used, set the CSiW bit to "0" (with wait state). Figure 1.6.2 PM1 Register Rev.1.00 2003.05.30 page 32 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Processor Mode Single-chip mode 0000016 SFR 0040016 Internal RAM XXXXX16 Can not use YYYYY16 Internal ROM FFFFF16 PM13 = 0 Internal RAM Internal ROM Capacity Address XXXXX16 Capacity Address YYYYY16 5 Kbytes 017FF16 128 Kbytes E000016 10 Kbytes 02BFF16 256 Kbytes D000016 (Note 1) PM13 = 1 Internal RAM Internal ROM Capacity Address XXXXX16 Capacity Address YYYYY16 017FF16 128 Kbytes E000016 5 Kbytes 02BFF16 256 Kbytes C000016 10 Kbytes Note 1: When the PM13 bit in the PM1 register = 0, 192 Kbytes or smaller of the internal ROM can be used. Note 2: For the mask ROM version, set the PM10 bit in the PM1 register to "0" (0800016 to 26FFF16 for CS2 area). Figure 1.6.3 Memory Map in Single-chip Mode Rev.1.00 2003.05.30 page 33 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Processor Mode When PM13 = 0 and PM10 = 0 (A memory space of 1MB) Memory expansion mode Microprocessor mode 0000016 SFR SFR Internal RAM Internal RAM Reserved area Reserved area 0040016 XXXXX16 0400016 CS3 (16 Kbytes) 0800016 2700016 CS2 (124 Kbytes) Reserved area Reserved area 2800016 CS1 (32 Kbytes) 3000016 External area External area CS0 8000016 Memory expansion mode: 640 Kbytes Microprocessor mode: 832 Kbytes Reserved area YYYYY16 Internal ROM FFFFF16 Internal RAM Capacity Internal ROM Address XXXXX16 Capacity Address YYYYY16 5 Kbytes 017FF16 128 Kbytes E000016 10 Kbytes 02BFF16 256 Kbytes D000016 (Note) Note: When the PM13 bit in the PM1 register = 0, 192 Kbytes or smaller of the internal ROM can be used. _____ Figure 1.6.4 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (1) When PM13 = 1 and PM10 = 0 (A memory space of 1MB) Memory expansion mode Microprocessor mode 0000016 SFR SFR Internal RAM Internal RAM Reserved area Reserved area Reserved area Reserved area 0040016 XXXXX16 0800016 2700016 CS2 (124 Kbytes) 2800016 CS1 (32 Kbytes) 3000016 External area External area CS0 8000016 Memory expansion mode: 320 Kbytes Microprocessor mode: 832 Kbytes Reserved area YYYYY16 Internal ROM FFFFF16 Internal RAM Capacity Address XXXXX16 Internal ROM Capacity Address YYYYY16 5 Kbytes 017FF16 128 Kbytes E000016 10 Kbytes 02BFF16 256 Kbytes C000016 _____ Figure 1.6.5 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (2) Rev.1.00 2003.05.30 page 34 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Processor Mode When PM13 = 0 and PM10 = 1 (A memory space of 1MB) Memory expansion mode Microprocessor mode 0000016 SFR SFR Internal RAM Internal RAM Reserved area Reserved area Reserved area Reserved area Reserved area Reserved area 0040016 XXXXX16 0400016 0800016 CS3 (16 Kbytes) 1000016 2700016 CS2 (92 Kbytes) 2800016 CS1 (32 Kbytes) 3000016 External area External area 8000016 CS0 Memory expansion mode: 640 Kbytes Microprocessor mode: 832 Kbytes Reserved area YYYYY16 Internal ROM FFFFF16 Internal RAM Capacity Internal ROM Address XXXXX16 Capacity 5 Kbytes 017FF16 128 Kbytes E000016 10 Kbytes 02BFF16 256 Kbytes D000016 (Note) Address YYYYY16 Note: When the PM13 bit in the PM1 register = 0, 192 Kbytes or smaller of the internal ROM can be used. _____ Figure 1.6.6 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (3) When PM13 = 1 and PM10 = 1 (A memory space of 1MB) Memory expansion mode Microprocessor mode 0000016 SFR SFR Internal RAM Internal RAM Reserved area Reserved area Reserved area Reserved area 0040016 XXXXX16 1000016 2700016 CS2 (92 Kbytes) 2800016 CS1 (32 Kbytes) 3000016 External area External area CS0 8000016 Memory expansion mode: 320 Kbytes Microprocessor mode: 832 Kbytes Reserved area YYYYY16 Internal ROM FFFFF16 Internal RAM Capacity Address XXXXX16 Internal ROM Capacity Address YYYYY16 5 Kbytes 017FF16 128 Kbytes E000016 10 Kbytes 02BFF16 256 Kbytes C000016 _____ Figure 1.6.7 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (4) Rev.1.00 2003.05.30 page 35 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Bus Bus During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform _______ data input/output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0 to _______ _____ ________ ______ ________ ________ ________ __________ _________ CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK. Bus Mode The bus mode, either multiplexed or separate, can be selected using the PM05 to PM04 bits in the PM0 register. Separate Bus In this bus mode, data and address are separate. Multiplexed Bus In this bus mode, data and address are multiplexed. * When the input level on BYTE pin is high (8-bit data bus) D0 to D7 and A0 to A7 are multiplexed. * When the input level on BYTE pin is low (16-bit data bus) D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15. External buses connecting to a multiplexed bus are allocated to only the even addresses of the microcomputer. Odd addresses cannot be accessed. Rev.1.00 2003.05.30 page 36 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Bus Control Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait. Table 1.7.1 PM06 and PM11 Bits Set Value and Address Bus Width (1) Address Bus The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or 20 bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 1.7.1 shows the PM06 and PM11 bits set values and address bus widths. When processor mode is changed from singlechip mode to memory expansion mode, the address bus is indeterminate until any external area is accessed. Set value (Note) Pin function Address bus width PM11 = 1 P34 to P37 12 bits PM06 = 1 PM11 = 0 P40 to P43 A12 to A15 16 bits PM06 = 1 PM11 = 0 P40 to P43 A12 to A15 20 bits PM06 = 0 A16 to A19 Note: No values other than those shown above can be set. (2) Data Bus When input on the BYTE pin is high (data bus is an 8-bit width), 8 lines D0 to D7 comprise the data bus; when input on the BYTE pin is low (data bus is a 16-bit width), 16 lines D0 to D15 comprise the data bus. Do not change the input level on the BYTE pin while in operation. (3) Chip Select Signal ______ ______ The chip select (hereafter referred to as the CSi) signals are output from the CSi (i = 0 to 3) pins. These _____ pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register. Figure 1.7.1 shows the CSR register. ______ During 1 ______ Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output from the CSi pin. ______ Figure 1.7.2 shows the example of address bus and CSi signal output in 1 Mbyte mode. Chip select control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CSR Bit symbol Address 000816 Bit name CS0 CS0 output enable bit CS1 CS1 output enable bit CS2 CS3 CS2 output enable bit After reset 0116 Function 0 : Chip select output disabled (functions as I/O port) 1 : Chip select output enabled CS0 wait bit CS1W CS1 wait bit CS2W CS2 wait bit CS3W CS3 wait bit RW RW RW RW CS3 output enable bit CS0W RW 0 : With wait state 1 : Without wait state (Notes 1, 2, 3) RW RW RW RW Note 1: Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplexed bus is used, set the CSiW bit to "0" (Wait state). Note 2: If the PM17 bit in the PM1 register is set to "1" (with wait state), the external area indicated by CS0 to CS3 is always accessed with one wait state even when the CSiW bit is "1" (without wait state). Note 3: When the CSiW bit is "0" (with wait state), the number of wait states (in terms of clock cycles) can be selected using the CSEi1W to CSEi0W bits in the CSE register. Figure 1.7.1 CSR Register Rev.1.00 2003.05.30 page 37 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Bus Control Example 1 Example 2 To access the external area indicated by CSj in the next cycle after accessing the external area indicated by CSi. To access the internal ROM or internal RAM in the next cycle after accessing the external area indicated by CSi. The address bus and the chip select signal both change state between these two cycles. The chip s elect s ignal c hanges state but the address bus does not change state. Access to the external area indicated by CSi Access to the external area indicated by CSi Access to the external area indicated by CSj BCLK BCLK Read signal Read signal Data bus Address bus Data Data bus Data Address Address Address bus CSi Access to the internal ROM or internal RAM Data Address CSi CSj Example 3 Example 4 To a ccess the external area indicated by CSi in the next cycle after accessing the external area indicated by the same CSi. Not to access any area (nor instruction prefetch generated) in the next cycle after accessing the external area indicated by CSi. The address bus changes state but t he c hip select signal does not change state. Neither the address bus nor the chip select signal changes state between these two cycles. Access to the external area indicated by CSi Access to the same external area Access to the external area indicated by CSi BCLK BCLK Read signal Read signal Data bus Address bus Data Data bus Data Address Address Address bus No access Data Address CSi CSi Note : These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle may be extended more than two cycles depending on a combination of these examples. Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3 (not including i, however) ______ Figure 1.7.2 Example of Address Bus and CSi Signal Output in 1 Mbyte Mode Rev.1.00 2003.05.30 page 38 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Bus Control (4) Read and Write Signals _____ When the data bus is 16-bit width, the read and write signals can be chosen to be a combination of RD, ______ ________ _____ ________ ________ WR and BHE or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When _____ ______ ________ the data bus is 8-bit width, use a combination of RD, WR and BHE. _____ ________ _________ _____ Table 1.7.2 shows the operation of RD, WRL, and WRH signals. Table 1.7.3 shows the operation of RD, ______ ________ WR, and BHE signals. _____ ________ _________ Table 1.7.2 Operation of RD, WRL and WRH Signals _____ ________ _________ Data bus width RD WRL WRH 16 bits L H H (BYTE pin H L H input = L) H H L L L H _____ ______ Status of external data bus Read data Write 1 byte of data to an even address Write 1 byte of data to an odd address Write data to both even and odd addresses ________ Table 1.7.3 Operation of RD, WR and BHE Signals _____ ______ ________ Data bus width RD WR BHE A0 H H L L 16 bits H L L H (BYTE pin L H H L input = L) L L H H L H L L L L L H 8 bits H to L H - (Note) L (BYTE pin input = H) L - (Note) H to L H Note: Do not use. Status of external data bus Write 1 byte of data to an odd address Read 1 byte of data from an odd address Write 1 byte of data to an even address Read 1 byte of data from an even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1 byte of data Read 1 byte of data (5) ALE Signal The ALE signal latches the address when accessing the multiplexed bus space. Latch the address when the ALE signal falls. Figure 1.7.3 shows the ALE signal, address bus and data bus. When BYTE pin input = H When BYTE pin input = L ALE ALE A0/D0 to A7/D7 Address Data A1/D0 to A8/D7 A8 to A19 Address A0 Address A9 to A19 Note: If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports. Figure 1.7.3 ALE Signal, Address Bus, Data Bus Rev.1.00 2003.05.30 Data Address (Note) page 39 Address Under development This document is under development and its contents are subject to change. M16C/6N4 Group Bus Control ________ (6) The RDY Signal This signal is provided for accessing external devices which need to be accessed at low speed. If input on ________ the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in ________ the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY signal was acknowledged. ______ ______ ______ ________ ________ ______ ________ __________ A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA ________ Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle is executed. Figure 1.7.4 shows example in which the wait state was inserted into the read cycle by the ________ ________ RDY signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register ________ ________ to "0" (with wait state). When not using the RDY signal, process the RDY pin as an unused pin. In an instance of separate bus BCLK RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) Accept timing of RDY signal In an instance of multiplexed bus BCLK RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) : Wait using RDY signal Accept timing of RDY signal : Wait using software tSU(RDY-BCLK): RDY input setup time Shown above is the case where CSEi1W to CSEi0W (i = 0 to 3) bits in the CSE register are "002" (one wait state). ________ Figure 1.7.4 Example in which Wait State was Inserted into Read Cycle by RDY Signal Rev.1.00 2003.05.30 page 40 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Bus Control __________ (7) HOLD Signal This signal is used to transfer control of the bus from CPU or DMAC to an external circuit. When the input __________ on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in __________ process finishes. The microcomputer remains in a hold state while the HOLD pin is held low, during which __________ time the HLDA pin outputs a low-level signal. Table 1.7.4 shows the microcomputer status in the hold state. __________ Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence (refer to "Figure 1.7.5 Bus-using Priorities"). However, if the CPU is accessing an odd address in word units, the DMAC cannot gain control of the bus during two separate accesses. __________ HOLD > DMAC > CPU Figure 1.7.5 Bus-using Priorities Table 1.7.4 Microcomputer Status in Hold State Item Status BCLK Output ______ ______ ______ _________ _________ _______ ________ A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE High-impedance I/O ports P0, P1, P3, P4 (Note 1) High-impedance P6 to P10 Maintains status when hold signal is received __________ HLDA Output "L" Internal peripheral circuits ON (but watchdog timer stops (Note 2)) ALE signal Undefined Note 1: When I/O port function is selected. Note 2: The watchdog timer does not stop when the PM22 bit in the PM2 register is set to "1" (the count source for the watchdog timer is the ring oscillator clock). (8) BCLK Output If the PM07 bit in the PM0 register is set to "0" (output enable), a clock with the same frequency as that of the CPU clock is output as BCLK from the BCLK pin. Refer to "CPU Clock and Peripheral Function Clock". Table 1.7.5 shows the pin functions for each processor mode. Rev.1.00 2003.05.30 page 41 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Bus Control Table 1.7.5 Pin Functions for Each Processor Mode Processor mode Memory expansion mode or microprocessor mode Memory expansion mode ______ PM05 to PM04 bits 002 (separate bus) Data bus width 8 bits BYTE pin P00 to P07 P10 to P17 P20 P21 to P27 "H" D0 to D 7 I/O ports A0 A1 to A7 012 (CS2 is for multiplexed bus and 112 (multiplexed bus others are for separate bus) ______ for the entire space) 102 (CS1 is for multiplexed bus and (Note 1) others are for separate bus) 16 bits 8 bits 16 bits "L" "H" D0 to D7 (Note I/O ports A0/D0 (Note 2) A1 to A7/D1 to D7 "L" "H" 4) I/O ports D8 to D15 (Note 4) I/O ports A0 A0/D0 A1 to A7/D0 to D6 A1 to A7/D1 to D7 (Note 2) (Note 2) A8/D7 (Note 2) A8 I/O ports I/O ports D8 to D15 P30 A8 P31 to P33 A9 to A11 P34 to P37 PM11 = 0 A12 to A15 PM11 = 1 I/O ports P40 to P43 PM06 = 0 A16 to A19 PM06 = 1 I/O ports P44 P45 CS0 = 0 CS0 = 1 P46 CS1 = 0 CS1 = 1 CS2 = 0 P47 CS2 = 1 CS3 = 0 8 bits I/O ports I/O ports CS0 ______ I/O ports CS1 I/O ports ______ ______ CS2 I/O ports ______ P50 CS3 = 1 CS3 _______ PM02 = 0 WR PM02 = 1 - (Note 3) ________ WRL ________ - (Note 3) WRL - (Note 3) ________ P51 P52 P53 P54 P55 P56 PM02 = 0 BHE PM02 = 1 - (Note 3) ______ RD BCLK ___________ HLDA ___________ HOLD ALE _________ WRH _________ - (Note 3) WRH - (Note 3) _________ P57 RDY I/O ports: Function as I/O ports or peripheral function I/O pins. Note 1: For setting the PM01 to PM00 bits to "012" (memory expansion mode) and the PM05 to PM04 bits to _____ "112" (multiplexed bus assigned to the entire CS space), apply "H" to the BYTE pin (external data bus is an 8-bit width). While the CNVSS pin is held "H" (VCC1), do not rewrite the PM05 to PM04 bits to "112" after reset. If the PM05 to PM04 bits are set to "112" during memory expansion mode, P31 to P37 and _____ P40 to P43 become I/O ports, in which case the accessible area for each CS is 256 bytes. Note 2: In separate bus mode, these pins serve as the address bus. _____ ________ ______ Note 3: If the data bus is 8-bit width, make sure the PM02 bit is set to "0" (RD, BHE, WR). Note 4: When accessing the area that uses a multiplexed bus, these pins output an indeterminate value during a write. Rev.1.00 2003.05.30 page 42 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Bus Control (9) External Bus Status When Internal Area Accessed Table 1.7.6 shows the external bus status when the internal area is accessed. Table 1.7.6 External Bus Status When Internal Area Accessed Item SFR accessed Internal ROM, internal RAM accessed A0 to A19 Address output When read High-impedance Maintain status before accessed address of external area or SFR High-impedance When write Output data _________ _____ ______ _________ __________ RD, WR, WRL, WRH RD, WR, WRL, WRH output ________ ________ BHE BHE output Undefined Output "H" Maintain status before accessed status of D0 to D15 _____ ______ _______ ________ external area or SFR Output "H" Output "L" _______ CS0 to CS3 ALE Output "H" Output "L" (10) Software Wait Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. Refer to "Table 1.7.7 Bit and Bus Cycle Related to Software Wait " for details. ________ To use the RDY signal, set the corresponding CS3W to CS0W bit to "0" (with wait state). Figure 1.7.6 shows the CSE register. Table 1.7.7 shows the software wait related bits and bus cycles. Figures 1.7.7 and 1.7.8 show the typical bus timings using software wait. Chip select expansion control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CSE Bit symbol Address 001B16 After reset 0016 Bit name Function RW 0 0 : 1 wait 0 1 : 2 waits 1 0 : 3 waits 1 1 : Must not be set RW b1 b0 CSE00W CS0 wait expansion bit CSE01W (Note) RW b3 b2 CSE10W CS1 wait expansion bit CSE11W (Note) 0 0 : 1 wait 0 1 : 2 waits 1 0 : 3 waits 1 1 : Must not be set RW RW b5 b4 CSE20W CS2 wait expansion bit (Note) CSE21W 0 0 : 1 wait 0 1 : 2 waits 1 0 : 3 waits 1 1 : Must not be set RW RW b7 b6 CSE30W CS3 wait expansion bit (Note) CSE31W 0 0 : 1 wait 0 1 : 2 waits 1 0 : 3 waits 1 1 : Must not be set RW RW Note: Set the CSiW bit (i = 0 to 3) in the CSR register to "0" (with wait state) before writing to the CSEi1W to CSEi0W bits. If the CSiW bit needs to be set to "1" (without wait state), set the CSEi1W to CSEi0W bits to "002" before setting it. Figure 1.7.6 CSE Register Rev.1.00 2003.05.30 page 43 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Bus Control Table 1.7.7 Software Wait Related Bits and Bus Cycles CSR register CSE register CS3W bit (Note 1) CS31W to CS30W bits Area Bus mode PM2 Register PM1 Register CS2W bit (Note 1) CS21W to CS20W bits Software PM20 bit PM17 bit CS1W bit (Note 1) CS11W to CS10W bits wait Bus cycle CS0W bit (Note 1) CS01W to CS00W bits SFR Internal ROM, RAM - 0 - - - - 2 BCLK cycles (Note 4) - 1 - - - - 3 BCLK cycles (Note 4) - - - - - 0 1 - - No wait 1 BCLK cycle (Note 3) 1 wait 2 BCLK cycles - 0 1 002 No wait 1 BCLK cycle (read) External Separate area bus 2 BCLK cycles (write) - - 0 002 1 wait 2 BCLK cycles (Note 3) - - 0 012 2 waits 3 BCLK cycles - - 0 102 3 waits 4 BCLK cycles 1 wait 2 BCLK cycles - 1 Multiplexed - - 1 0 002 002 bus - - 0 012 2 waits 3 BCLK cycles - 0 102 3 waits 4 BCLK cycles - 1 0 002 1 wait (Note 2) 1 wait 3 BCLK cycles 3 BCLK cycles ________ Note 1: To use the RDY signal, set this bit to "0 ". Note 2: To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to "0" (with wait state). Note 3: After reset, the PM17 bit is set to "0" (without wait state), all of the CS0W to CS3W bits are set to "0" ______ ______ (with wait state), and the CSE register is set to "0016" (one wait state for CS0 to CS3). Therefore, the internal RAM and internal ROM are accessed with no wait state, and all external areas are accessed with one wait state. Note 4: When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by the PM20 bit in the PM2 register. When using a 16 MHz or higher PLL clock, be sure to set the PM20 bit to "0" (2 wait cycles). Rev.1.00 2003.05.30 page 44 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Bus Control (1) Separate bus, No wait setting Bus cycle (Note) Bus cycle (Note) BCLK Write signal Read signal Data bus Address bus Output Address Input Address CS (2) Separate bus, 1-wait setting Bus cycle (Note) Bus cycle (Note) BCLK Write signal Read signal Data bus Address bus Output Input Address Address CS (3) Separate bus, 2-wait setting Bus cycle (Note) Bus cycle (Note) BCLK Write signal Read signal Data bus Address bus Output Address Input Address CS Note: These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in succession. Figure 1.7.7 Typical Bus Timings Using Software Wait (1) Rev.1.00 2003.05.30 page 45 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Bus Control (1) Separate bus, 3-wait setting Bus cycle (Note) Bus cycle (Note) BCLK Write signal Read signal Data bus Input Output Address Address bus Address CS (2)Multiplexed bus, 1- or 2-wait setting Bus cycle (Note) Bus cycle (Note) Address Address BCLK Write signal Read signal ALE Address bus Address bus/ Data bus Address Data output Address Input CS (3)Multiplexed bus, 3-wait setting Bus cycle (Note) Bus cycle (Note) BCLK Write signal Read signal ALE Address bus Address bus/ Data bus Address Address Address Data output Address Input CS Note: These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in succession. Figure 1.7.8 Typical Bus Timings Using Software Wait (2) Rev.1.00 2003.05.30 page 46 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit Clock Generation Circuit The clock generation circuit contains four oscillator circuits as follows: (1) Main clock oscillation circuit (2) Sub clock oscillation circuit (3) Ring oscillator (4) PLL frequency synthesizer Table 1.8.1 lists the clock generation circuit specifications. Figure 1.8.1 shows the clock generation circuit. Figures 1.8.2 to 1.8.8 show the clock-related registers. Table 1.8.1 Clock Generation Circuit Specifications Main clock Sub clock Item oscillation circuit oscillation circuit Use of clock * CPU clock source * CPU clock source Ring oscillator PLL frequency synthesizer * CPU clock source * CPU clock source * Peripheral function * Peripheral function * Peripheral function * Timer A, B's clock clock source source clock source * CPU and peripheral clock source function clock sources when the main clock stops oscillating Clock frequency 0 to 16 MHz 20 MHz 32.768 kHz About 1 MHz Usable *Ceramic oscillator *Crystal oscillator oscillator *Crystal oscillator XCIN, XCOUT - - Oscillation stop Present and re-oscillation detection function Present Present Present Oscillation status Oscillating after reset Stopped Stopped Stopped - - Pins to connect XIN, XOUT oscillator Other Rev.1.00 Externally derived clock can be input 2003.05.30 page 47 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit Sub clock oscillation circuit XCIN I/O ports XCOUT CM04 CM01-CM00=002 PM01-PM00=002, CM01-CM00=012 PM01-PM00=002, CM01-CM00=102 fC32 1/32 Sub clock CLKOUT PM01-PM00=002, CM01-CM00=112 fC fCAN0 By CCLK0,1 and 2 fCAN1 By CCLK4,5 and 6 f1 PCLK0=1 f2 PCLK0=0 f8 f32 CM21 Ring oscillator Ring oscillator clock PCLK0=1 fAD PCLK0=0 f1SIO Oscillation stop, re-oscillation detection circuit CM10=1 (stop mode) f2SIO PCLK1=1 PCLK1=0 f8SIO f32SIO S Q XIN XOUT PLL frequency synthesizer R Main clock CM05 PLL clock b c d ef a CM21=1 CPU clock fC CM21=0 Main clock oscillation circuit CM07=0 g Divider 1 0 BCLK CM07=1 CM11 CM02 S Q WAIT instruction R b a RESET Software reset 1/2 c 1/2 1/2 d 1/2 1/4 e 1/2 1/8 NMI CM06=0 CM06=1 CM06=0 CM17-CM16=102 CM06=0 CM17-CM16=012 CM17-CM16=002 Interrupt request level judgment output f 1/2 1/32 1/16 CM06=0 CM17-CM16=112 g Details of divider CM02, CM04, CM05, CM06, CM07 : CM0 register's bits CM10, CM11, CM16, CM17 : CM1 register's bits PCLK0, PCLK1 : PCLKR register's bits CM21, CM27 : CM2 register's bits CCLK0 to CCLK2 and CCLK4 to CCLK6 : CCLKR register's bits Oscillation stop, re-oscillation detection circuit Main clock Pulse generation circuit for clock edge detection and charge, discharge control Charge, discharge circuit CM27 = 0 Reset generation circuit Oscillation stop detection reset Oscillation stop, CM27 = 1 re-oscillation detection interrupt generating circuit Oscillation stop, re-oscillation detection interrupt signal CM21 switch signal PLL frequency synthesizer Programmable counter Main clock Phase comparator Charge pump Voltage control oscillator (VCO) Internal lowpass filter Figure 1.8.1 Clock Generation Circuit Rev.1.00 2003.05.30 page 48 1/2 PLL clock Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit System clock control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset CM0 000616 010010002 Bit symbol Bit name Function RW b1 b0 Clock output function select bit (Valid only in single-chip mode) 0 0 : I/O port P57 0 1 : fC output 1 0 : f8 output 1 1 : f32 output CM02 WAIT peripheral function clock stop bit 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 2) RW CM03 XCIN-XCOUT drive capacity select bit (Note 3) 0 : LOW 1 : HIGH RW CM04 Port XC select bit (Note 3) 0 : I/O port P86, P87 1 : XCIN-XCOUT generation function (Note 4) RW CM05 Main clock stop bit (Notes 5, 6, 7) 0 : On 1 : Off (Notes 8, 9) RW CM06 Main clock division select bit 0 (Notes 7, 10, 12) 0 : CM16 and CM17 valid 1 : Division by 8 mode RW CM07 System clock select bit (Notes 6, 11) 0 : Main clock, PLL clock, or ring oscillator clock 1 : Sub clock RW CM00 CM01 RW RW Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable). Note 2: The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to "1" (peripheral clock turned off when in wait mode). Note 3: The CM03 bit is set to "1" (high) when the CM04 bit is set to "0" (I/O port) or the microcomputer goes to stop mode. Note 4: To use a sub clock, set this bit to "1". Also make sure ports P86 and P87 are directed for input, with no pull-ups. Note 5: This bit is provided to stop the main clock when the low power dissipation mode or ring oscillator low power dissipation mode is selected. This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock, the following setting is required: (1) Set the CM07 bit to "1" (sub clock select) or the CM21 bit of CM2 register to "1" (ring oscillator select) with the sub clock stably oscillating. (2) Set the CM20 bit of CM2 register to "0" (oscillation stop, re-oscillation detection function disabled). (3) Set the CM05 bit to "1" (stop). Note 6: To use the main clock as the clock source for the CPU clock, follow the procedure below. (1) Set the CM05 bit to "0" (oscillate) (2) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer. (3) Set the CM11, CM21 and CM07 bits all to "0". Note 7: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High). Note 8: During external clock input, only the clock oscillation buffer is turned off and clock input is accepted if the sub clock is not selected as a CPU clock. Note 9: When CM05 bit is set to "1", the XOUT pin goes "H". Furthermore, because the internal feedback resistor remains connected, the XIN pin is pulled "H" to the same level as XOUT via the feedback resistor. Note 10: When entering stop mode from high- or middle-speed mode, ring oscillator mode or ring oscillator low power mode, the CM06 bit is set to "1" (divide-by-8 mode). Note 11: After setting the CM04 bit to "1" (XCIN-XCOUT oscillator function), wait until the sub clock oscillates stably before switching the CM07 bit from "0" to "1" (sub clock). Note 12: To return from ring oscillator mode to high-speed or middle-speed mode, set the CM06 and CM15 bits both to "1". Figure 1.8.2 CM0 Register Rev.1.00 2003.05.30 page 49 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit System clock control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol Address After reset CM1 000716 001000002 Bit symbol Bit name CM10 All clock stop control bit (Notes 2, 3) 0 : Clock on 1 : All clocks off (stop mode) RW CM11 System clock select bit 1 (Notes 3, 4) 0 : Main clock 1 : PLL clock (Note 5) RW (b4-b2) Reserved bit Set to "0" RW CM15 XIN-XOUT drive capacity select bit (Note 6) 0 : LOW 1 : HIGH RW - Function RW b7 b6 CM16 CM17 Main clock division select bit 1 (Note 7) 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode RW RW Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable) Note 2: If the CM10 bit is "1" (stop mode), XOUT goes "H" and the internal feedback resistor is disconnected. The XCIN and XCOUT pins are placed in the high-impedance state. When the CM11 bit is set to "1" (PLL clock), or the CM20 bit of CM2 register is set to "1" (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to "1". Note 3: When the PM22 bit of PM2 register is set to "1" (watchdog timer count source is ring oscillator clock), writing to the CM10 bit has no effect. Note 4: Effective when CM07 bit is "0" and CM21 bit is "0". Note 5: After setting the PL07 bit in PLC0 register to "1" (PLL operation), wait until tsu(PLL) elapses before setting the CM11 bit to "1" (PLL clock). Note 6: When entering stop mode from high- or middle-speed mode, or when the CM05 bit is set to "1" (main clock turned off) in low-speed mode, the CM15 bit is set to "1" (drive capability high). Note 7: Effective when the CM06 bit is "0" (CM16 and CM17 bits enabled). Figure 1.8.3 CM1 Register Rev.1.00 2003.05.30 page 50 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit Oscillation stop detection register (Note 1) b7 b6 b5 b4 0 0 b3 b2 b1 b0 Symbol Address CM2 000C16 0X00X0002 (Note 2) Bit name Function Bit symbol CM20 CM21 CM22 CM23 After reset Oscillation stop, re-oscillation 0 : Oscillation stop, re-oscillation detection function disabled detection enable bit (Notes 2, 3, 4) 1 : Oscillation stop, re-oscillation detection function enabled 0 : Main clock or PLL clock System clock select bit 2 (Ring oscillator turned off) (Notes 2, 5, 6, 7, 8, 11) 1 : Ring oscillator clock (Ring oscillator oscillating) 0 : Main clock stop, re-oscillation not detected Oscillation stop, re-oscillation detection flag (Note 9) 1 : Main clock stop, re-oscillation detected 0 : Main clock oscillating XIN monitor flag (Note 10) 1 : Main clock turned off - Reserved bit - Nothing is assigned. When write, set to "0". When read, its content is indeterminate. (b5-b4) (b6) CM27 Set to "0" 0 : Oscillation stop detection reset Operation select bit (behavior if oscillation stop, 1 : Oscillation stop, re-oscillation detection interrupt re-oscillation is detected) (Note 2) RW RW RW RW RO RW - RW Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable). Note 2: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset. Note 3: Set the CM20 bit to "0" (disable) before entering stop mode. After exiting stop mode, set the CM20 bit back to "1" (enable). Note 4: Set the CM20 bit to "0" (disable) before setting the CM05 bit of CM0 register Note 5: When the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1" (oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit is set to "1" (ring oscillator clock) if the main clock stop is detected. Note 6: If the CM20 bit is "1" and the CM23 bit is "1" (main clock turned off), do not set the CM21 bit to "0". Note 7: Effective when the CM07 bit of CM0 register is "0". Note 8: Where the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1" (oscillation stop, re-oscillation detection interrupt), and the CM11 bit is "1" (the CPU clock source is PLL clock), the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is "0" under these conditions, oscillation stop, re-oscillation detection interrupt generate at main clock stop detection; it is, therefore, necessary to set the CM21 bit to "1" (ring oscillator clock) inside the interrupt routine. Note 9: This bit is set to "1" when the main clock is detected to have stopped and when the main clock is detected to have restarted oscillating. When this bit changes state from "0" to "1", an oscillation stop, re-oscillation detection interrupt request is generated. Use this bit in an interrupt routine to discriminate the causes of interrupts between the oscillation stop, re-oscillation detection interrupt and the watchdog timer interrupt. This bit is set to "0" by writing "0" in a program. (Writing "1" has no effect. Nor is it set to "0" by an oscillation stop, re-oscillation detection interrupt request acknowledged.) If an oscillation stop or a re-oscillation is detected when the CM22 bit = 1, no oscillation stop and re-oscillation detection interrupt requests are generated. Note 10: Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main clock status. Note 11: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High). Figure 1.8.4 CM2 Register Rev.1.00 2003.05.30 page 51 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit Peripheral clock select register (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PCLKR 0 0 0 0 0 0 Address 025E16 After reset 0016 Bit symbol Bit name PCLK0 Timers A, B, and A-D clock select bit (Clock source for the timers A, B, the dead time timer and A-D) 0 : Divide-by-2 of fAD2, f2 1 : fAD, f1 RW PCLK1 SI/O clock select bit (Clock source for UART0 to UART2, SI/O3) 0 : f2SIO 1 : f1SIO RW Set to "0" RW (b7-b2) Function Reserved bit RW Note: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable). Figure 1.8.5 PCLKR Register CAN0/1 clock select register (Notes 1, 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset CCLKR 025F16 0016 Bit symbol Bit name Function RW b2 b1 b0 CCLK0 CCLK1 CAN0 clock select bits CCLK2 CCLK3 0 0 0 No division 0 0 1 : Divide-by-2 0 1 0 : Divide-by-4 0 1 1 : Divide-by-8 1 0 0: Divide-by-16 101: 110: Inhibited 111: CAN0 CPU interface sleep bit 0: CAN0 CPU interface operating 1: CAN0 CPU interface in sleep CAN1 clock select bits 0 0 0 No division 0 0 1 : Divide-by-2 0 1 0 : Divide-by-4 0 1 1 : Divide-by-8 1 0 0: Divide-by-16 101: 110: Inhibited 111: RW RW RW RW b6 b5 b4 CCLK4 CCLK5 CCLK6 CCLK7 CAN1 CPU interface sleep bit 0: CAN1 CPU interface operating 1: CAN1 CPU interface in sleep RW RW RW RW Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable). Note 2: Configuration of this register can be done only when the Reset bit of C0CTLR, C1CTLR registers = 1 (Reset/Initialization mode). Figure 1.8.6 CCLKR Register Rev.1.00 2003.05.30 page 52 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit Processor mode register 2 (Note 1) b7 b6 b5 b4 b3 0 0 b2 b1 b0 0 Symbol PM2 Address 001E16 After reset XXX000002 Bit symbol Bit name PM20 Specifying wait when accessing SFR at PLL operation (Note 2) 0 : 2 waits 1 : 1 wait RW Reserved bit Set to "0" RW WDT count source protective bit (Notes 3, 4) 0 : CPU clock is used for the watchdog timer count source 1 : Ring oscillator clock is used for RW the watchdog timer count source Reserved bit Set to "0" (b1) PM22 (b4-b3) (b7-b5) Function Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW - Note 1: Write to this register after setting the PRC1 bit of PRCR register to "1" (write enable). Note 2: This bit can only be rewritten while the PLC07 bit is "0" (PLL turned off). Also, to select a 16 MHz or higher PLL clock, set this bit to "0" (2 waits). Note that if the clock source for the CPU clock is to be changed from the PLL clock to another, the PLC07 bit must be set to "0" before setting the PM20 bit. Note 3: Once this bit is set to "1", it cannot be set to "0" in a program. Note 4: Setting the PM22 bit to "1" results in the following conditions: The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source. The CM10 bit of CM1 register is disabled against write. (Writing a "1" has no effect, nor is stop mode entered.) The watchdog timer does not stop when in wait mode or hold state. Figure 1.8.7 PM2 Register Rev.1.00 2003.05.30 page 53 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit PLL control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PLC0 0 0 1 Bit symbol Address 001C16 After reset 0001X0102 Function Bit name RW b2 b1 b0 PLC00 PLC01 PLL multiplying factor select bit (Note 2) PLC02 (b3) - 0 0 0 : Must not be set 0 0 1 : Multiply by 2 0 1 0 : Multiply by 4 0 1 1 : Multiply by 6 1 0 0 : Multiply by 8 101: 110: Must not be set 111: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW - Reserved bit Set to "1" RW (b6-b5) Reserved bit Set to "0" RW PLC07 Operation enable bit (Note 3) 0 : PLL Off 1 : PLL On RW (b4) - Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable). Note 2: These three bits can only be modified when the PLC07 bit = 0 (PLL turned off). The value once written to this bit cannot be modified. Note 3: Before setting this bit to "1", set the CM07 bit to "0" (main clock), set the CM17 to CM16 bits to "002" (main clock undivided mode), and set the CM06 bit to "0" (CM16 and CM17 bits enable). Figure 1.8.8 PLC0 Register Rev.1.00 2003.05.30 page 54 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit The following describes the clocks generated by the clock generation circuit. (1) Main Clock This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally generated clock to the XIN pin. Figure 1.8.9 shows the examples of main clock connection circuit. After reset, the main clock divided by 8 is selected for the CPU clock. The power consumption in the chip can be reduced by setting the CM05 bit of CM0 register to "1" (main clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or ring oscillator clock. In this case, XOUT goes "H". Furthermore, because the internal feedback resistor remains on, XIN is pulled "H" to XOUT via the feedback resistor. Note, that if an externally generated clock is fed into the XIN pin, the main clock cannot be turned off by setting the CM05 bit to "1" unless the sub clock is selected as a CPU clock. If necessary, use an external circuit to turn off the clock. During stop mode, all clocks including the main clock are turned off. Refer to "power control". Microcomputer Microcomputer (Built-in feedback resistor) (Built-in feedback resistor) XIN XIN XOUT XOUT Open (Note) Rd Externally derived clock CIN COUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction. Figure 1.8.9 Examples of Main Clock Connection Circuit Rev.1.00 2003.05.30 page 55 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit (2) Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. In addition, an fC clock with the same frequency as that of the sub clock can be output from the CLKOUT pin. The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure 1.8.10 shows the examples of sub clock connection circuit. After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscillator circuit. To use the sub clock for the CPU clock, set the CM07 bit of CM0 register to "1 " (sub clock) after the sub clock becomes oscillating stably. During stop mode, all clocks including the sub clock are turned off. Refer to "power control". Microcomputer Microcomputer (Built-in feedback resistor) (Built-in feedback resistor) XCIN XCOUT XCIN XCOUT Open (Note) RCd Externally derived clock CCIN CCOUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN and XCOUT following the instruction. Figure 1.8.10 Examples of Sub Clock Connection Circuit Rev.1.00 2003.05.30 page 56 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit (3) Ring Oscillator Clock This clock, approximately 1 MHz, is supplied by a ring oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit of PM2 register is "1" (ring oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (refer to "Watchdog Timer * Count source protective mode"). After reset, the ring oscillator is turned off. It is turned on by setting the CM21 bit of CM2 register to "1" (ring oscillator clock), and is used as the clock source for the CPU and peripheral function clocks, in place of the main clock. If the main clock stops oscillating when the CM20 bit of CM2 register is "1" (oscillation stop, re-oscillation detection function enabled) and the CM27 bit is "1" (oscillation stop, re-oscillation detection interrupt), the ring oscillator automatically starts operating, supplying the necessary clock for the microcomputer. (4) PLL Clock The PLL clock is generated by a PLL frequency synthesizer. This clock is used as the clock source for the CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthesizer is activated by setting the PLC07 bit to "1" (PLL operation). When the PLL clock is used as the clock source for the CPU clock, wait a fixed period of tsu(PLL) for the PLL clock to be stable, and then set the CM11 bit in the CM1 register to "1". Before entering wait mode or stop mode, be sure to set the CM11 bit to "0" (CPU clock source is the main clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to "0" (PLL stops). Figure 1.8.11 shows the procedure for using the PLL clock as the clock source for the CPU. The PLL clock frequency is determined by the equation below. Figure 1.8.11 shows the procedure for using the PLL clock as the clock source for the CPU. The PLL clock frequency is determined by the equation below. PLL clock frequency = f(XIN) (multiplying factor set by the PLC02 to PLC00 bits of the PLC0 register) (However, PLL clock frequency = 20 MHz) The PLC02 to PLC00 bits can be set only once after reset. Table 1.8.2 shows the example for setting PLL clock frequencies. Table 1.8.2 Example for Setting PLL Clock Frequencies XIN Multiply PLL clock PLC02 PLC01 PLC00 (MHz) factor (MHz) (Note) 10 5 0 0 0 1 1 0 2 4 Note: PLL clock frequency = 20 MHz Rev.1.00 2003.05.30 page 57 20 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit Using the PLL clock as the clock source for the CPU Set the CM07 bit to "0" (main clock), the CM17 to CM16 bits to "002" (main clock undivided), and the CM06 bit to "0" (CM16 and CM17 bits enabled). (Note) Set the PLC02 to PLC00 bits (multiplying factor). (To select a 16 MHz or higher PLL clock) Set the PM20 bit to "0" (2-wait state). Set the PLC07 bit to "1" (PLL operation). Wait until the PLL clock becomes stable (tsu(PLL)). Set the CM11 bit to "1" (PLL clock for the CPU clock source). END Note: PLL operation mode can be entered from high-speed mode. Figure 1.8.11 Procedure to Use PLL Clock as CPU Clock Source Rev.1.00 2003.05.30 page 58 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit CPU Clock and Peripheral Function Clock There are existing two type clocks: The CPU clock to operate the CPU and the peripheral function clocks to operate the peripheral functions. (1) CPU Clock and BCLK These are operating clocks for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, sub clock, ring oscillator clock or the PLL clock. If the main clock or ring oscillator clock is selected as the clock source for the CPU clock, the selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit of CM0 register and the CM17 to CM16 bits of CM1 register to select the divide-by-n value. When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to "0" and the CM17 to CM16 bits to "002" (undivided). After reset, the main clock divided by 8 provides the CPU clock. During memory expansion or microprocessor mode, a BCLK signal with the same frequency as the CPU clock can be output from the BCLK pin by setting the PM07 bit of PM0 register to "0" (output enabled). Note that when entering stop mode from high- or middle-speed mode, ring oscillator mode or ring oscillator low power dissipation mode, or when the CM05 bit of CM0 register is set to "1" (main clock turned off) in low-speed mode, the CM06 bit of CM0 register is set to "1" (divide-by-8 mode). (2) Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fCAN0, fCAN1, fC32) These are operating clocks for the peripheral functions. Two of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or ring oscillator clock by dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial I/O. The f8 and f32 clocks can be output from the CLKOUT pin. The fAD clock is produced from the main clock, PLL clock or ring oscillator clock, and is used for the A-D converter. The fCANi (i = 0, 1) clock is derived from the main clock, PLL clock or ring oscillator clock by dividing them by 1 (undivided), 2, 4, 8 or 16, and is used for the CAN module. When the WAIT instruction is executed after setting the CM02 bit of CM0 register to "1" (peripheral function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode, the fi, fiSIO, fAD, fCAN0 and fCAN1 clocks are turned off (Note). The fC32 clock is derived from the sub clock, and is used for timers A and B. This clock can be used when the sub clock is activated. Note: fCAN0 and fCAN1 clocks stop at "H" in CAN0, 1 sleep mode. Clock Output Function During single-chip mode, the f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to CM00 bits of CM0 register to select. Rev.1.00 2003.05.30 page 59 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit Power Control There are three power control modes. For convenience' sake, all modes other than wait and stop modes are referred to as normal operation mode here. (1) Normal Operation Mode Normal operation mode is further classified into seven sub modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are turned off, the power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source to which switched must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a sufficient wait time in a program until it becomes oscillating stably. Note that operation modes cannot be changed directly from low speed or low power dissipation mode to ring oscillator or ring oscillator low power dissipation mode. Nor can operation modes be changed directly from ring oscillator or ring oscillator low power dissipation mode to low speed or low power dissipation mode. Where the CPU clock source is changed from the ring oscillator to the main clock, change the operation mode to the medium-speed mode (divide-by-8 mode) after the clock was divided by 8 (the CM06 bit of CM0 register was set to "1") in the ring oscillator mode. * High-speed Mode The main clock divided by 1 provides the CPU clock. If the sub clock is activated, fC32 can be used as the count source for timers A and B. * PLL Operation Mode The main clock multiplied by 2, 4, 6 or 8 provides the PLL clock, and this PLL clock serves as the CPU clock. If the sub clock is activated, fC32 can be used as the count source for timers A and B. PLL operation mode can be entered from high speed mode. If PLL operation mode is to be changed to wait or stop mode, first go to high speed mode before changing. * Medium-speed Mode The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is activated, fC32 can be used as the count source for timers A and B. * Low-speed Mode The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral function clock when the CM21 bit is set to "0" (ring oscillator turned off), and the ring oscillator clock is used when the CM21 bit is set to "1" (ring oscillator oscillating). The fC32 clock can be used as the count source for timers A and B. * Low Power Dissipation Mode In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides the CPU clock. The fC32 clock can be used as the count source for timers A and B. Simultaneously when this mode is selected, the CM06 bit of CM0 register becomes "1" (divide-by-8 mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium speed (divide-by-8) mode is to be selected when the main clock is operated next. Rev.1.00 2003.05.30 page 60 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit * Ring Oscillator Mode The ring oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The ring oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is activated, fC32 can be used as the count source for timers A and B. * Ring Oscillator Low Power Dissipation Mode The main clock is turned off after being placed in ring oscillator mode. The CPU clock can be selected like in the ring oscillator mode. The ring oscillator clock is the clock source for the peripheral function clocks. If the sub clock is activated, fC32 can be used as the count source for timers A and B. When the operation mode is returned to the high- and medium-speed modes, set the CM06 bit to "1" (divide-by8 mode). Table 1.8.3 lists the setting clock related bit and modes Table 1.8.3 Setting Clock Related Bit and Modes CM2 register CM1 register Modes CM21 CM11 CM17, CM16 PLL operation mode 0 1 002 High-speed mode 0 0 002 Medium- divided by 2 0 0 012 CM0 register CM06 CM05 0 0 0 0 0 0 CM04 - 0 0 102 0 0 0 - mode divided by 8 divided by 16 Low-speed mode Low power dissipation mode 0 0 - 0 0 - 112 - 0 0 1 1 1 0 1 (Note 1) 0 0 0 1 (Note 1) 1 1 divided by 1 Ring oscillator divided by 2 1 1 - 002 012 0 0 0 0 0 0 - mode 1 - 102 0 0 0 - 1 1 1 - 112 (Note 2) 0 0 0 1 0 (Note 2) 0 0 1 - speed divided by 4 CM07 0 0 0 divided by 4 divided by 8 divided by 16 Ring oscillator low power dissipation mode Note 1: When the CM05 bit is set to "1" (main clock turned off) in low-speed mode, the mode goes to low power dissipation mode and CM06 bit is set to "1" (divide-by-8 mode) simultaneously. Note 2: The divide-by-n value can be selected the same way as in ring oscillator mode. Rev.1.00 2003.05.30 page 61 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit (2) Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. However, if the PM22 bit of PM2 register is "1" (ring oscillator clock for the watchdog timer count source), the watchdog timer remains active. Because the main clock, sub clock, ring oscillator clock and PLL clock all are on, the peripheral functions using these clocks keep operating. * Peripheral Function Clock Stop Function If the CM02 bit is "1" (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO, f8SIO, f32SIO, fAD, fCAN0 and fCAN1 clocks are turned off when in wait mode, with the power consumption reduced that much. However, fC32 remains on. * Entering Wait Mode The microcomputer is placed into wait mode by executing the WAIT instruction. When the CM11 bit = 1 (CPU clock source is the PLL clock), be sure to set the CM11 bit to "0" (CPU clock source is the main clock) before going to wait mode. The power consumption of the chip can be reduced by setting the PLC07 bit to "0" (PLL stops). * Pin Status During Wait Mode Table 1.8.4 lists the pin status during wait mode. Table 1.8.4 Pin Status During Wait Mode Pin A0 to A19, D0 to D15, _______ _______ ________ CS0 to CS3, BHE ______ _______ _________ _________ RD, WR, WRL, WRH ___________ HLDA, BCLK ALE I/O ports CLKOUT When fC selected When f8, f32 selected Memory expansion mode Microprocessor mode Retains status before wait mode - "H" "H" "H" Retains status before wait mode - Retains status before wait mode Does not stop - *CM02 bit = 0: Does not stop Single-chip mode *CM02 bit = 1: Retains status before wait mode * Exiting Wait Mode ______ The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral function interrupt. ______ If the microcomputer is to be moved out of exit wait mode by a hardware reset or NMI interrupt, set the peripheral function interrupt priority ILVL2 to ILVL0 bits to "0002" (interrupts disabled) before executing the WAIT instruction. The peripheral function interrupts are affected by the CM02 bit. If the CM02 bit is "0" (peripheral function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait mode. If the CM02 bit is "1" (peripheral function clocks turned off during wait mode), the peripheral functions using the peripheral function clocks stop operating, so that only the peripheral functions clocked by external signals can be used to exit wait mode. Table 1.8.5 lists the interrupts to exit wait mode. Rev.1.00 2003.05.30 page 62 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit Table 1.8.5 Interrupts to Exit Wait Mode Interrupt CM02 = 0 _______ NMI interrupt Can be used Serial I/O interrupt Can be used when operating with internal or external clock Key input interrupt Can be used A-D conversion interrupt Can be used in one-shot mode or single sweep mode Timer A interrupt Can be used in all modes Timer B interrupt ______ INT interrupt Can be used CAN0/1 Wake-up interrupt Can be used CM02 = 1 Can be used Can be used when operating with external clock Can be used - (Do not use) Can be used in event counter mode or when the count source is fc32 Can be used Can be used If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the following before executing the WAIT instruction. 1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit wait mode. Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0 bits to "0002" (interrupt disable). 2. Set the I flag to "1". 3. Enable the peripheral function whose interrupt is to be used to exit wait mode. In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an interrupt routine is executed. The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU clock that was on when the WAIT instruction was executed. Rev.1.00 2003.05.30 page 63 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit (3) Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode. If the voltage applied to VCC is VRAM or more, the internal RAM is retained. However, the peripheral functions clocked by external signals keep operating. The following interrupts can be used to exit stop mode. ______ * NMI interrupt * Key interrupt ______ * INT interrupt * Timer A, Timer B interrupt (when counting external pulses in event counter mode) * Serial I/O interrupt (when external clock is selected) * CAN0/1 Wake-up interrupt * Entering Stop Mode The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to "1" (all clocks turned off). At the same time, the CM06 bit of CM0 register is set to "1" (divide-by-8 mode) and the CM15 bit of CM1 register is set to "1" (main clock oscillator circuit drive capability high). Before entering stop mode, set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disabled). Also, if the CM11 bit is "1" (PLL clock for the CPU clock source), set the CM11 bit to "0" (main clock for the CPU clock source) and the PLC07 bit to "0" (PLL turned off) before entering stop mode. * Pin Status During Stop Mode Table 1.8.6 lists the pin status during stop mode. Table 1.8.6 Pin Status During Stop Mode Pin A0 to A19, D0 to D15, _______ _______ ________ CS0 to CS3, BHE ______ _______ _________ _________ RD, WR, WRL, WRH ___________ HLDA, BCLK ALE I/O ports CLKOUT When fC selected When f8, f32 selected Rev.1.00 2003.05.30 page 64 Memory expansion mode Microprocessor mode Retains status before stop mode - "H" "H" "H" Retains status before stop mode - Retains status before stop mode "H" - Retains status before stop mode Single-chip mode Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit * Exiting Stop Mode ______ The microcomputer is moved out of stop mode by a hardware reset, NMI interrupt or peripheral function interrupt. ______ If the microcomputer is to be moved out of stop mode by a hardware reset or NMI interrupt, set the peripheral function interrupt priority ILVL2 to ILVL0 bits to "0002" (interrupts disable) before setting the CM10 bit to "1". If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the following before setting the CM10 bit to "1". 1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit stop mode. Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0 bits to "0002". 2. Set the I flag to "1". 3. Enable the peripheral function whose interrupt is to be used to exit stop mode. In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an interrupt service routine is executed. ______ Which CPU clock will be used after exiting stop mode by a peripheral function or NMI interrupt is determined by the CPU clock that was on when the microcomputer was placed into stop mode as follows: * If the CPU clock before entering stop mode was derived from the sub clock: sub clock * If the CPU clock before entering stop mode was derived from the main clock: main clock divide-by-8 * If the CPU clock before entering stop mode was derived from the ring oscillator clock: ring oscillator clock divide-by-8 Rev.1.00 2003.05.30 page 65 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit Figure 1.8.12 shows the state transition from normal operation mode to stop mode and wait mode. Figure 1.8.13 shows the state transition in normal operation mode. Table 1.8.7 shows a state transition matrix describing allowed transition and setting. The vertical line shows current state and horizontal line show state after transition. Reset All oscillators stopped CM10=1 (Note 5) Stop mode Interrupt CM07=0 CM06=1 CM05=0 CM11=0 CM10=1 (Note 3) WAIT instruction Medium-speed mode (divided-by-8 mode) CPU operation stopped Wait mode Interrupt Interrupt WAIT instruction Stop mode High-speed, mediumspeed mode CM10=1 (Note 5) When low power When dissipation lowmode speed mode (Notes 1, 2) PLL operation mode CM10=1 (Note 5) Stop mode Interrupt CM10=1 (Note 5) Stop mode Wait mode Interrupt Low-speed, low power dissipation mode Ring oscillator, Ring oscillator dissipation mode Interrupt (Note 4) WAIT instruction Wait mode Interrupt WAIT instruction Interrupt Wait mode Normal mode CM05, CM06, CM07 : CM0 register's bits CM10, CM11 : CM1 register's bits Note 1: Do not go directly from PLL operation mode to wait or stop mode. Note 2: PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode. Note 3: Write to the CM0 register and CM1 register simultaneously by accessing in word unit while CM21 = 0 (ring oscillator turned off). Note 4: The ring oscillator clock divided by 8 provides the CPU clock. Note 5: Before entering stop mode, be sure to set the CM20 bit in the CM2 register to "0" (oscillation stop, re-oscillation detection function disabled). Figure 1.8.12 State Transition to Stop Mode and Wait Mode Rev.1.00 2003.05.30 page 66 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit Main clock oscillation Ring oscillator clock oscillation PLL operation mode PLC07=1 CM11=1 (Note 6) CPU clock: f(PLL) CM07=0 CM06=0 CM17=0 PLC07=0 CM11=0 (Note 7) CM16=0 CM04=1 High-speed mode CPU clock: f(XIN) PLL operation mode CM16=0 CPU clock: f(XIN)/2 CPU clock: f(XIN)/4 CM07=0 CM07=0 CM06=0 CM06=0 CM06=0 CM17=0 CM17=0 CM17=1 CM16=0 CM16=1 CM16=0 Middle-speed mode Middle-speed mode (divide by 8) (divide by 16) CPU clock: f(XIN)/8 PLC07=1 CM11=1 (Note 6) PLC07=0 CM11=0 (Note 7) High-speed mode CPU clock: f(XIN) CPU clock: f(XIN)/16 CM21=0 (Note 8) CM06=0 CM17=1 CM06=1 CM16=1 CM21=1 CM04=0 Middle-speed mode (divide by 2) Middle-speed mode (divide by 4) CPU clock: f(XIN)/2 CPU clock: f(XIN)/4 CM07=0 CM07=0 CM07=0 CM06=0 CM06=0 CM06=0 CM17=0 CM17=0 CM17=1 CM16=0 CM16=1 CM16=0 CPU clock f(Ring) f(Ring)/2 f(Ring)/4 f(Ring)/8 f(Ring)/16 CM04=1 CPU clock: f(XIN)/16 CM07=0 CM06=1 CM21=0 (Note 8) CM07=0 CM06=0 CM17=1 CM16=1 CM05=0 CM05=1 (Note 1) CM04=0 CM21=1 CPU clock f(Ring) f(Ring)/2 f(Ring)/4 f(Ring)/8 f(Ring)/16 CPU clock f(Ring) f(Ring)/2 f(Ring)/4 f(Ring)/8 f(Ring)/16 CM04=1 CM04=0 Ring oscillator low power dissipation mode Ring oscillator mode Middle-speed mode Middle-speed mode (divide by 8) (divide by 16) CPU clock: f(XIN)/8 Ring oscillator low power dissipation mode Ring oscillator mode CM07=0 CM07=0 CM04=1 CM06=0 CM17=0 Middle-speed mode (divide by 4) CM07=0 CM04=0 CPU clock: f(PLL) CM07=0 Middle-speed mode (divide by 2) CM05=0 CPU clock f(Ring) f(Ring)/2 f(Ring)/4 f(Ring)/8 f(Ring)/16 CM05=1 (Note 1) CM07=1 (Note 3) CM07=0 (Notes 2, 4) Low-speed mode CM21=0 Low-speed mode CPU clock: f(XCIN) CPU clock: f(XCIN) CM07=1 CM07=1 CM21=1 CM05=1 (Notes 1, 9) CM05=0 Low power dissipation mode CPU clock: f(XCIN) CM07=1 CM06=1 CM15=1 Sub clock oscillation CM04, CM05, CM06, CM07 : CM0 register's bits CM11, CM15, CM16, CM17 : CM1 register's bits CM20, CM21 : CM2 register's bits PLC07 : PLC0 register's bit Note 1: Avoid making a transition when the CM20 bit is set to "1" (oscillation stop, re-oscillation detection function enabled). Set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disabled) before transiting. Wait for td(M-L) or the main clock oscillation stabilization time whichever is longer before switching over. Switch clock after oscillation of sub clock is sufficiently stable. Change CM17 and CM16 before changing CM06. Transit in accordance with arrow. PLL operation mode can only be entered from high speed mode. Also, wait until the PLL clock is sufficiently stable before changing operation modes. To select a 16 MHz or higher PLL clock, set the PM20 bit to "0" (SFR accessed with two wait states) before setting PLC07 to "1" (PLL operation). Note 7: PLL operation mode can only be changed to high speed mode. If the PM20 bit = 0 (SFR accessed with two wait states), set PLC07 to "0" (PLL turned off) before setting the PM20 bit to "1" (SFR accessed with one wait state). Note 8: Set the CM06 bit to "1" (division by 8 mode) before changing back the operation mode from ring oscillator mode to high- or middle-speed mode. Note 9: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High). Note 2: Note 3: Note 4: Note 5: Note 6: Figure 1.8.13 State Transition in Normal Operation Mode Rev.1.00 2003.05.30 page 67 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit Table 1.8.7 Allowed Transition and Setting State after transition High-speed mode, Low-speed Low power PLL operation Ring oscillator Ring oscillator middle-speed mode mode low power mode mode (Note 2) dissipation mode (Note 2) dissipation mode High-speed mode, Middle-speed mode Low-speed mode (Note 8) (11) (10) (12) mode (Note 2) Ring oscillator (Note 3) (14) mode (Note 4) Ring oscillator low power dissipation mode Stop mode (18) (Note 5) Wait mode (18) - - - - - - - - - (11) (16) (Note 1) (Note 1) (Note 8) (16) (Note 1) - - - - (Note 8) - - - (10) (18) (18) - (18) (18) - -: Cannot transit Note 1: Avoid making a transition when the CM20 bit = 1 (oscillation stop, re-oscillation detection function enabled). Set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disabled) before transiting. Note 2: Ring oscillator clock oscillates and stops in low-speed mode. In this mode, the ring oscillator can be used as peripheral function clock. Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as peripheral function clock. Note 3: PLL operation mode can only be entered from and changed to high-speed mode. Note 4: Set the CM06 bit to "1" (division by 8 mode) before transiting from ring oscillator mode to high- or middle-speed mode. Note 5: When exiting stop mode, the CM06 bit is set to "1" (division by 8 mode). Note 6: If the CM05 bit is set to "1" (main clock stop), then the CM06 bit is set to "1" (division by 8 mode). Note 7: A transition can be made only when sub clock is oscillating. Note 8: State transitions within the same mode (divide-by-n values changed or sub clock oscillation turned on or off) are shown in the table below. Sub clock oscillating Sub clock turned off Sub clock turned off Sub clock oscillating No Divided Divided Divided Divided No Divided Divided Divided Divided division by 2 by 4 by 8 by 16 division by 2 by 4 by 8 by 16 No division (4) (5) (7) (6) (1) - - - - (5) (7) (7) (6) (6) - (1) - (1) - - (6) - - - (1) - (1) (4) (5) (5) (7) (7) (6) (6) (7) (6) (6) Divided by 2 Divided by 4 (3) (3) (4) Divided by 8 Divided by 16 (3) (3) (4) (4) (5) (5) (7) No division (2) Divided by 2 - (2) - - - (3) Divided by 4 Divided by 8 - - (2) - (2) - (3) (3) (4) (4) (5) Divided by 16 - - - - (2) (3) (4) (5) Note 9: ( ):setting method. Refer to right table. Rev.1.00 2003.05.30 page 68 (7) (16) - - - Wait mode (15) (Note 3) (Notes 1, 6) - dissipation mode PLL operation (13) - (Note 7) (8) (Note 2) Low power Current state (9) Stop mode (Note 1) (16) (Note 1) (16) (Note 1) (18) (18) (Note 5) (Note 5) (18) (18) Setting (1) CM04=0 (2) CM04=1 (3) CM06=0 CM17=0 CM16=0 (4) CM06=0 CM17=0 CM16=1 (5) CM06=0 CM17=1 CM16=0 (6) CM06=0 CM17=1 CM16=1 (7) CM06=1 (8) CM07=0 (9) (10) (11) (12) CM07=1 CM05=0 CM05=1 PLC07=0 CM11=0 ( 13) PLC07=1 CM11=1 (14) CM21=0 (17) (17) (17) (17) (17) - - Operation Sub clock turned off Sub clock oscillating CPU clock no division mode CPU clock division by 2 mode CPU clock division by 4 mode CPU clock division by 16 mode CPU clock division by 8 mode Main clock, PLL clock or ring oscillator clock selected Sub clock selected Main clock oscillating Main clock turned off Main clock selected PLL clock selected Main clock or PLL clock selected Ring oscillator clock selected Transition to stop mode Transition to wait mode ( 15) CM21=1 (16) CM10=1 (17) WAIT instruction (18) Hardware Exit stop mode or wait interrupt mode CM04, CM05, CM06, CM07:CM0 register's bits CM10, CM11, CM16, CM17:CM1 register's bits CM20, CM21 :CM2 register's bits PLC07 :PLC0 register's bit Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit Oscillation Stop and Re-oscillation Detection Function The oscillation stop and re-oscillation detection function is such that main clock oscillation circuit stop and re-oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, reoscillation detection interrupt are generated. Which one is to be generated can be selected using the CM27 bit of CM2 register. The oscillation stop and re-oscillation detection function can be enabled or disabled using the CM20 bit of CM2 register. Table 1.8.8 lists a specification overview of the oscillation stop and re-oscillation detection function. Table 1.8.8 Specification Overview of Oscillation Stop and Re-oscillation Detection Function Item Specification Oscillation stop detectable clock and f(XIN) 2 MHz frequency bandwidth Enabling condition for oscillation stop Set CM20 bit to "1" (enable) and re-oscillation detection function Operation at oscillation stop, *Reset occurs (when CM27 bit = 0) re-oscillation detection *Oscillation stop, re-oscillation detection interrupt occurs (when the CM27 bit =1) (1) Operation When CM27 Bit = 0 (Oscillation Stop Detection Reset) Where main clock stop is detected when the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to "SFR", "Reset"). This status is reset with hardware reset. Also, even when re-oscillation is detected, the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage. (During main clock stop, do not set the CM20 bit to "1" and the CM27 bit to "0".) (2) Operation When CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt) Where the main clock corresponds to the CPU clock source and the CM20 bit is "1" (oscillation stop, reoscillation detection function enabled), the system is placed in the following state if the main clock comes to a halt: * Oscillation stop, re-oscillation detection interrupt request occurs. * The ring oscillator starts oscillation, and the ring oscillator clock becomes the clock source for CPU clock and peripheral functions in place of the main clock. * CM21 bit = 1 (ring oscillator clock is the clock source for CPU clock) * CM22 bit = 1 (main clock stop detected) * CM23 bit = 1 (main clock stopped) Where the PLL clock corresponds to the CPU clock source and the CM20 bit is "1", the system is placed in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to "1" (ring oscillator clock) inside the interrupt routine. * Oscillation stop, re-oscillation detection interrupt request occurs. * CM22 bit = 1 (main clock stop detected) * CM23 bit = 1 (main clock stopped) * CM21 bit remains unchanged Where the CM20 bit is "1", the system is placed in the following state if the main clock re-oscillates from the stop condition: * Oscillation stop, re-oscillation detection interrupt request occurs. * CM22 bit = 1 (main clock re-oscillation detected) * CM23 bit = 0 (main clock oscillation) * CM21 bit remains unchanged Rev.1.00 2003.05.30 page 69 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Clock Generation Circuit How to Use Oscillation Stop and Re-oscillation Detection Function * The oscillation stop, re-oscillation detection interrupt shares the vector with the watchdog timer interrupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt. * Where the main clock re-oscillated after oscillation stop, the clock source for CPU clock and peripheral function must be switched to the main clock in the program. Figure 1.8.14 shows the procedure to switch the clock source from the ring oscillator to the main clock. * Simultaneously with oscillation stop, re-oscillation detection interrupt request occurrence, the CM22 bit becomes "1". When the CM22 bit is set at "1", oscillation stop, re-oscillation detection interrupt are disabled. By setting the CM22 bit to "0" in the program, oscillation stop, re-oscillation detection interrupt are enabled. * If the main clock stops during low speed mode where the CM20 bit is "1", an oscillation stop, re-oscillation detection interrupt request is generated. At the same time, the ring oscillator starts oscillating. In this case, although the CPU clock is derived from the sub clock as it was before the interrupt occurred, the peripheral function clocks now are derived from the ring oscillator clock. * To enter wait mode while using the oscillation stop and re-oscillation detection function, set the CM02 bit to "0" (peripheral function clocks not turned off during wait mode). * Since the oscillation stop and re-oscillation detection function is provided in preparation for main clock stop due to external factors, set the CM20 bit to "0" (Oscillation stop, re-oscillation detection function disabled) where the main clock is stopped or oscillated in the program, that is where the stop mode is selected or the CM05 bit is altered. * This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit to "0". Main clock switch Inspect the CM23 bit 1 (Main clock stop) 0 (Main clock oscillation) Do this check a number of times The main clock is confirmed to be active a number of times. Set the CM22 bit to "0" (main clock stop, re-oscillation not detected). Set the CM21 bit to "0" (main clock for the CPU clock source) (Note) End CM21, CM22, CM 23 bits are the CM2 register bits Note: If the clock source for CPU clock is to be changed to PLL clock, set to PLL operation mode after set to high-speed mode. Figure 1.8.14 Procedure to Switch Clock Source from Ring Oscillator to Main Clock Rev.1.00 2003.05.30 page 70 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Protection Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 1.9.1 shows the PRCR register. The following lists the registers protected by the PRCR register. * Registers protected by the PRC0 bit: CM0, CM1, CM2, PLC0, PCLKR and CCLKR registers * Registers protected by the PRC1 bit: PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers * Registers protected by the PRC2 bit: PD7, PD9 and S3C registers Set the PRC2 bit to "1" (write enabled) and then write to any address, and the PRC2 bit will be set to "0" (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to "1". Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to "1" and the next instruction. The PRC0 and PRC1 bits are not automatically set to "0" by writing to any address. They can only be set to "0" in a program. Protect register b7 b6 b5 b4 0 0 b3 b2 b1 b0 0 Symbol Address After reset PRCR 000A16 XX0000002 Bit symbol Bit name RW Function Enable write to CM0, CM1, CM2, PLC0, PCLKR, CCLKR registers RW 0 : Write protected 1 : Write enabled Enable write to PM0, PM1, PM2, TB2SC, INVC0, INVC1 registers RW 0 : Write protected 1 : Write enabled Enable write to PD7, PD9, S3C registers RW 0 : Write protected 1 : Write enabled (Note) PRC0 Protect bit 0 PRC1 Protect bit 1 PRC2 Protect bit 2 (b5-b3) Reserved bit (b7-b6) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Set to "0" RW - Note: The PRC2 bit is set to "0" by writing to any address after setting it to "1". Other bits are not set to "0" by writing to any address, and must therefore be set in a program. Figure 1.9.1 PRCR Register Rev.1.00 2003.05.30 page 71 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Interrupts Type of Interrupts Figure 1.10.1 shows the types of interrupts. Hardware Special (Non-maskable interrupt) Interrupt Software (Non-maskable interrupt) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction _______ NMI DBC (Note 2) Oscillation stop and re-oscillation detection Watchdog timer Single step (Note 2) Address match ________ Peripheral function (Note 1) (Maskable interrupt) Note 1: Peripheral function interrupts are generated by the microcomputer's internal functions. Note 2: Do not normally use this interrupt because it is provided exclusively for use by development support tools. Figure 1.10.1 Interrupts * Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. * Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. Rev.1.00 2003.05.30 page 72 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. * Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. * Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to "1" (the operation resulted in an overflow). The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB * BRK Interrupt A BRK interrupt occurs when executing the BRK instruction. * INT Instruction Interrupt An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63 can be specified for the INT instruction. Because software interrupt Nos. 1 to 31 are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction. In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is set to "0" (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not change state during instruction execution, and the SP then selected is used. Rev.1.00 2003.05.30 page 73 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Hardware Interrupts Hardware interrupts are classified into two types -- special interrupts and peripheral function interrupts. (1) Special Interrupts Special interrupts are non-maskable interrupts. _______ * NMI Interrupt _______ _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details, _______ refer to "NMI Interrupt". ________ * DBC Interrupt Do not normally use this interrupt because it is provided exclusively for use by development support tools. * Watchdog Timer Interrupt Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. For details about the watchdog timer, refer to "Watchdog Timer". * Oscillation Stop and Re-oscillation Detection Interrupt Generated by the oscillation stop and re-oscillation detection function. For details about the oscillation stop and re-oscillation detection function, refer to "Clock Generation Circuit". * Single-step Interrupt Do not normally use this interrupt because it is provided exclusively for use by development support tools. * Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMAD0 to RMAD3 registers that corresponds to one of the AIER register's AIER0 or AIER1 bit or the AIER2 register's AIER20 or AIER21 bit which is "1" (address match interrupt enabled). For details, refer to "Address Match Interrupt". (2) Peripheral Function Interrupts Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal functions. The interrupt sources for peripheral function interrupts are listed in "Table 1.10.2 Relocatable Vector Tables". For details about the peripheral functions, refer to the description of each peripheral function in this manual. Rev.1.00 2003.05.30 page 74 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 1.10.2 shows the interrupt vector. MSB Vector address (L) LSB Low address Medium address Vector address (H) 0000 High address 0000 0000 Figure 1.10.2 Interrupt Vector * Fixed Vector Tables The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 1.10.1 lists the fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed vectors are used by the ID code check function. For details, refer to "Functions to Prevent Flash Memory from Rewriting". Table 1.10.1 Fixed Vector Tables Interrupt source Vector table addresses Address (L) to address (H) Remarks Reference Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction M16C/60, M16C/20 Overflow FFFE0 16 to FFFE316 Interrupt on INTO instruction series software manual BRK instruction FFFE416 to FFFE716 If the contents of address FFFE716 is FF16, program execution starts from the address shown by the vector in the relocatable vector table. FFFE816 to FFFEB16 Address match interrupt FFFEC16 to FFFEF16 FFFF016 to FFFF316 Clock generation circuit Address match Single step (Note) Oscillation stop and re-oscillation detection, Watchdog timer _________ DBC (Note) FFFF416 to FFFF716 ________ NMI FFFF816 to FFFFB16 Reset FFFFC16 to FFFFF16 Watchdog timer ________ NMI interrupt Reset Note: Do not normally use this interrupt because it is provided exclusively for use by development support tools. Rev.1.00 2003.05.30 page 75 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts * Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector table area. Table 1.10.2 lists the relocatable vector tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses. Table 1.10.2 Relocatable Vector Tables Vector address (Note 1) Interrupt source Address (L) to address (H) Software interrupt number BRK instruction (Note 2) +0 to +3(000016 to 000316) 0 CAN0/1 wake-up CAN0 successful reception CAN0 successful transmission +4 to +7 (000416 to 000716) +8 to +11 (000816 to 000B16) +12 to +15 (000C16 to 000F16) +16 to +19 (001016 to 001316) +20 to +23 (001416 to 001716) +24 to +27 (001816 to 001B16) +28 to +31 (001C16 to 001F16) +32 to +35 (002016 to 002316) +36 to +39 (002416 to 002716) +40 to +43 (002816 to 002B16) +44 to +47 (002C16 to 002F16) +48 to +51 (003016 to 003316) +52 to +55 (003416 to 003716) +56 to +59 (003816 to 003B16) +60 to +63 (003C16 to 003F16) +64 to +67 (004016 to 004316) +68 to +71 (004416 to 004716) +72 to +75 (004816 to 004B16) +76 to +79 (004C16 to 004F16) +80 to +83 (005016 to 005316) +84 to +87 (005416 to 005716) +88 to +91 (005816 to 005B16) +92 to +95 (005C16 to 005F16) +96 to +99 (006016 to 006316) +100to +103 (006416 to 006716) +104to +107 (006816 to 006B16) +108to +111 (006C16 to 006F16) +112to +115 (007016 to 007316) +116to +119 (007416 to 007716) +120to +123 (007816 to 007B16) +124to +127 (007C16 to 007F16) +128to +131 (008016 to 008316) ** * 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ** * +252to +255 (00FC16 to 00FF16) 63 ________ INT3 Timer B5 Timer B4, UART1 bus collision detection (Note 3. 9) Timer B3, UART0 bus collision detection (Note 4, 9) ________ CAN1 successful reception, INT5 (Note 5) ________ SIO3, CAN1 successful transmission, INT4 (Note 6) UART2 bus collision detection (Note 9) DMA0 DMA1 CAN0/1 error A-D, Key input (Note 7) UART2 transmission, NACK2 (Note 8) UART2 reception, ACK2 (Note 8) UART0 transmission, NACK0 (Note 8) UART0 reception, ACK0 (Note 8) UART1 transmission, NACK1 (Note 8) UART1 reception, ACK1 (Note 8) Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 ________ INT0 ________ INT1 ________ INT2 Software interrupt (Note 2) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Reference M16C/60, M16C/20 series software manual CAN module _______ INT interrupt Timer Timer, Serial I/O _______ CAN module, INT interrupt _______ Serial I/O, CAN module, INT interrupt Serial I/O DMAC CAN module A-D convertor, Key input interrupt Serial I/O Timer _______ INT interrupt M16C/60, M16C/20 series software manual Address relative to address in INTB. These interrupts cannot be disabled using the I flag. Use the IFSR0 register's IFSR07 bit to select. Use the IFSR0 register's IFSR06 bit to select. Use the IFSR1 register's IFSR17 bit to select. Use the IFSR1 register's IFSR16 bit to select. Furthermore, use the IFSR0 register's IFSR00 bit to select, when selecting SI/O3 or CAN1 successful transmission. Note 7: Use the IFSR0 register's IFSR01 bit to select. Note 8: During I2C mode, NACK and ACK interrupts comprise the interrupt source. Note 9: Bus collision detection: During IE mode, this bus collision detection constitutes the cause of an interrupt. During I2C mode, a start condition or a stop condition detection constitutes the cause of an interrupt. Rev.1.00 2003.05.30 page 76 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to non-maskable interrupts. Use the FLG register's I flag, IPL, and each interrupt control register's ILVL2 to ILVL0 bits to enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figures 1.10.3 and 1.10.4 show the interrupt control registers. Interrupt control register (Note 1) Address Symbol b7 b6 b5 b4 b3 b2 b1 b0 C01WKIC C0RECIC C0TRMIC TB5IC TB4IC/U1BCNIC (Note 2) TB3IC/U0BCNIC (Note 3) U2BCNIC DM0IC, DM1IC C01ERRIC ADIC/KUPIC S0TIC to S2TIC S0RIC to S2RIC TA0IC to TA4IC TB0IC to TB2IC Bit symbol After reset 004116 004216 004316 004516 004616 004716 004A16 004B16, 004C16 004D16 004E16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005916 005A16 to 005C16 Bit name XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 Function RW b2 b1 b0 ILVL0 ILVL1 Interrupt priority level select bit ILVL2 000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 0 : Interrupt not requested 1 : Interrupt requested IR Interrupt request bit - Noting is assigned. When write, set to "0". When read, their contents are indeterminate. (b7-b4) RW RW RW RW (Note 4) - Note 1: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that register. For details, refer to "Precautions for Interrupts" of the Usage Notes Reference Book. Note 2: Use the IFSR07 bit of IFSR0 register to select. Note 3: Use the IFSR06 bit of IFSR0 register to select. Note 4: This bit can only be reset by writing "0" (Do not write "1"). Figure 1.10.3 Interrupt Control Registers (1) Rev.1.00 2003.05.30 page 77 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Interrupt control register (Note 1) Symbol b7 b6 b5 b4 b3 b2 b1 b0 0 INT3IC (Note 2) C1RECIC/INT5IC C1TRMIC/S3IC/INT4IC INT0IC to INT2IC Bit symbol Address After reset 004416 004816 004916 005D16 to 005F16 XX00X0002 XX00X0002 XX00X0002 XX00X0002 Bit name Function RW b2 b1 b0 ILVL0 ILVL1 Interrupt priority level select bit ILVL2 IR POL (b5) (b7-b6) 000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 RW RW RW Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested Polarity select bit 0 : Selects falling edge (Notes 4, 5) 1 : Selects rising edge RW Reserved bit Set to "0" RW Nothing is assigned. When write, set to "0". When read, their contents are indeterminate. RW (Note 3) - Note 1: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that register. For details, refer to "Precautions for Interrupts" of the Usage Notes Reference Book. Note 2: When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the ILVL2 to ILVL0 bits in the INT5IC to INT3IC registers to "0002" (interrupt disabled). Note 3: This bit can only be reset by writing "0" (Do not write "1"). Note 4: If the IFSR1 register's IFSR1i bit (i = 0 to 5) is "1" (both edges), set the INTiIC register's POL bit to "0" (falling edge). Note 5: Set the S3IC register's POL bit to "0" (falling edge) when the IFSR0 register's IFSR00 bit = 1 and the IFSR1 register's IFSR16 bit = 0 (SI/O3 selected). Figure 1.10.4 Interrupt Control Registers (2) Rev.1.00 2003.05.30 page 78 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to "1" (enabled) enables the maskable interrupt. Setting the I flag to "0" (disabled) disables all maskable interrupts. IR Bit The IR bit is set to "1" (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is set to "0" (interrupt not requested). The IR bit can be set to "0" in a program. Note that do not write "1" to this bit. ILVL2 to ILVL0 Bits and IPL Interrupt priority levels can be set using the ILVL2 to ILVL0 bits. Table 1.10.3 shows the settings of interrupt priority levels and Table 1.10.4 shows the interrupt priority levels enabled by the IPL. The following are conditions under which an interrupt is accepted: * I flag = 1 * IR bit = 1 * interrupt priority level > IPL The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one another. Table 1.10.3 Settings of Interrupt Priority Levels ILVL2 to ILVL0 bits 0002 0012 0102 0112 1002 1012 1102 1112 Rev.1.00 Interrupt priority level Priority order Level 0 (Interrupt disabled) Level 1 Low Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High 2003.05.30 page 79 Table 1.10.4 Interrupt Priority Levels Enabled by IPL IPL 0002 0012 0102 0112 1002 1012 1102 1112 Enabled interrupt priority levels Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Interrupt Sequence An interrupt sequence -- what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed -- is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. The CPU behavior during the interrupt sequence is described below. Figure 1.10.5 shows time required for executing the interrupt sequence. (1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the address 0000016. Then it set the IR bit for the corresponding interrupt to "0" (interrupt not requested). (2) The FLG register immediately before entering the interrupt sequence is saved to the CPU's internal temporary register (Note). (3) The I, D and U flags in the FLG register become as follows: * The I flag = 0 (interrupts disabled). * The D flag = 0 (single-step interrupt disabled). * The U flag = 0 (ISP selected). However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is executed. (4) The CPU's internal temporary register (Note) is saved to the stack. (5) The PC is saved to the stack. (6) The interrupt priority level of the accepted interrupt is set in the IPL. (7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, the processor resumes executing instructions from the start address of the interrupt routine. Note: This register cannot be used by user. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CPU clock Address bus Data bus Address 000016 Interrupt information RD Indeterminate (Note 1) Indeterminate (Note 1) SP-2 SP-2 contents SP-4 SP-4 contents vec vec contents vec+2 vec+2 contents Indeterminate (Note 1) WR (Note 2) Note 1: The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to accept instructions. Note 2: The WR signal timing shown here is for the case where the stack is located in the internal RAM. Figure 1.10.5 Time Required for Executing Interrupt Sequence Rev.1.00 2003.05.30 page 80 PC 18 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Interrupt Response Time Figure 1.10.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction then executing is completed ((a) in Figure 1.10.6) and a time during which the interrupt sequence is executed ((b) in Figure 1.10.6). Interrupt request generated Interrupt request acknowledged Time Instruction Instruction in interrupt routine Interrupt sequence (a) (b) Interrupt response time (a) A time from when an interrupt request is generated till when the instruction then executing is completed. The length of this time varies with the instruction being executed. The DIVX instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) A time during which the interrupt sequence is executed. For details, see the table below. Note, however, that the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and single-step interrupts. Interrupt vector address SP value 16-bit bus, without wait 8-bit bus, without wait Even Even 18 cycles 20 cycles Odd 19 cycles Even 19 cycles Odd 20 cycles Odd Figure 1.10.6 Interrupt response time Variation of IPL when Interrupt Request is Accepted When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in Table 1.10.5 is set in the IPL. Table 1.10.5 shows the IPL values of software and special interrupts when they are accepted. Table 1.10.5 IPL Level that is Set to IPL When A Software or Special Interrupt is Accepted Interrupt sources Value set in the IPL _______ Oscillation stop and re-oscillation detection, Watchdog timer, NMI 7 _________ Software, address match, DBC, single-step Rev.1.00 2003.05.30 page 81 Not changed Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 1.10.7 shows the stack status before and after an interrupt request is accepted. The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the PUSHM instruction, and all registers except SP can be saved with a single instruction. Stack Stack MSB LSB MSB LSB Address Address m-4 m-4 PCL m-3 m-3 PCM m-2 m-2 m-1 m-1 m Content of previous stack m+1 Content of previous stack [SP] SP value before interrupt request is accepted. Stack status before interrupt request is acknowledged [SP] New SP value FLGL FLGH PCH m Content of previous stack m+1 Content of previous stack Stack status after interrupt request is acknowledged Figure 1.10.7 Stack Status Before and After Acceptance of Interrupt Request The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP (Note), at the time of acceptance of an interrupt request, is even or odd. If the SP (Note) is even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 1.10.8 shows the operation of the saving registers. Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the U flag. Otherwise, it is the ISP. (1)SP contains even number Address (2)SP contains odd number Stack Sequence in which order registers are saved [SP] - 5 (Odd) PCL [SP] - 3 (Odd) PCM [SP] - 2 (Even) FLGL [SP] FLGH (Even) PCH (3) [SP] - 3 (Even) PCM (4) [SP] - 2 (Odd) FLGL (1) (1) Saved simultaneously, all 16 bits Finished saving registers in two operations. Figure 1.10.8 Operation of Saving Registers 2003.05.30 Sequence in which order registers are saved PCL (2) Saved simultaneously, all 16 bits [SP] - 4 (Odd) [SP] - 1 (Even) [SP] Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Rev.1.00 Stack [SP] - 5 (Even) [SP] - 4 (Even) [SP] - 1 (Odd) Address page 82 (Odd) FLGH PCH Saved,8 bits at a time (2) Finished saving registers in four operations. Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request. Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction before executing the REIT instruction. Interrupt Priority If two or more interrupt requests are generated while executing one instruction, the interrupt request that has the highest priority is accepted. For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 1.10.9 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine. Reset High NMI DBC Oscillation stop and re-oscillation detection Watchdog timer Peripheral function Single step Address match Low Figure 1.10.9 Hardware Interrupt Priority Interrupt Priority Resolution Circuit The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. Figure 1.10.10 shows the circuit that judges the interrupt priority level. Rev.1.00 2003.05.30 page 83 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Priority level of each interrupt Level 0 (initial value) Highest INT1 Timer B2 Timer B0 Timer A3 Timer A1 UART1 reception, ACK1 UART0 reception, ACK0 UART2 reception, ACK2 INT2 INT0 Timer B1 Timer A4 Timer A2 Timer A0 UART1 transmission, NACK1 UART0 transmission, NACK0 A-D conversion, Key input DMA1 Priority of peripheral function interrupts (if priority levels are same) UART2 bus collision detection CAN1 successful reception, INT5 Timer B4, UART1 bus collision detection INT3 CAN0 successful reception UART2 transmission, NACK2 CAN0/1 error DMA0 SI/O3, CAN1 successful transmission, INT4 Timer B3, UART0 bus collision detection Timer B5 CAN0 successful transmission CAN0/1 wake-up IPL I flag Address match Oscillation stop and re-oscillation detection Watchdog timer DBC NMI Figure 1.10.10 Interrupts Priority Select Circuit Rev.1.00 2003.05.30 page 84 Lowest Interrupt request level resolution output to clock generation circuit (Figure 1.8.1) Interrupt request accepted Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts ______ INT Interrupt ________ INTi interrupt (i = 0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSR1 register's IFSR1i bit. ________ INT4 share the interrupt vector and interrupt control register with SI/O3 and CAN1 successful transmission. ________ INT5 share the interrupt vector and interrupt control register with CAN1 successful reception. To use the ________ ________ ________ INT4 interrupt, set the IFSR1 register's IFSR16 bit to "1" (INT4). To use the INT5 interrupt, set the IFSR1 ________ register's IFSR17 bit to "1" (INT5). After modifying the IFSR16 or IFSR17 bit, set the corresponding IR bit to "0" (interrupt not requested) before enabling the interrupt. Figure 1.10.11 shows the IFSR0 register and IFSR1 register. Rev.1.00 2003.05.30 page 85 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Interrupt request cause select register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR0 Address 01DE16 After reset 00XXX0002 Bit symbol Bit name Function RW IFSR00 Interrupt request cause select bit 0 : CAN1 successful transmission 1 : SI/O3 RW IFSR01 Interrupt request cause select bit 0 : A-D conversion 1 : Key input RW IFSR02 Interrupt request cause select bit 0 : CAN0/1 wake-up error 1 : CAN0 wake-up error/ CAN1 wake-up error RW (b5-b3) Nothing is assigned. When write, set to "0". When read, their contents are indeterminate. - IFSR06 Interrupt request cause select bit 0 : Timer B3 (Note 1) 1 : UART0 bus collision detection RW IFSR07 Interrupt request cause select bit 0 : Timer B4 (Note 2) 1 : UART1 bus collision detection RW Note 1: Timer B3 and UART0 bus collision detection share the vector and interrupt control register. When using the timer B3 interrupt, set the IFSR06 bit in the IFSR0 register to "0" (timer B3). When using UART0 bus collision detection, set the IFSR06 bit to "1" (UART0 bus collision detection). Note 2: Timer B4 and UART1 bus collision detection share the vector and interrupt control register. When using the timer B4 interrupt, set the IFSR07 bit in the IFSR0 register to "0" (timer B4). When using UART1 bus collision detection, set the IFSR07 bit to "1" (UART1 bus collision detection). Interrupt request cause select register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR1 Bit symbol Address 01DF16 Bit name After reset 0016 Function RW IFSR10 INT0 interrupt polarity switching bit 0 : One edge 1 : Both edges (Note 1) RW IFSR11 INT1 interrupt polarity switching bit 0 : One edge 1 : Both edges (Note 1) RW IFSR12 INT2 interrupt polarity switching bit 0 : One edge 1 : Both edges (Note 1) RW IFSR13 INT3 interrupt polarity switching bit 0 : One edge 1 : Both edges (Note 1) RW IFSR14 INT4 interrupt polarity switching bit 0 : One edge 1 : Both edges (Note 1) RW IFSR15 INT5 interrupt polarity switching bit 0 : One edge 1 : Both edges (Note 1) RW IFSR16 Interrupt request cause select bit (Note 2) 0 : SI/O3/CAN1 successful transmission (Note 3) 1 : INT4 RW IFSR17 Interrupt request cause select bit 0 : CAN1 successful reception 1 : INT5 RW Note 1: When setting this bit to "1" (both edges), make sure the INT0IC to INT5IC register's POL bit is set to "0" (falling edge). Note 2: During memory expansion and microprocessor modes, set this bit to "0" (SI/O3, CAN1 successful transmission). Note 3: When setting this bit to "0" (SI/O3, CAN1 successful transmission), make sure the IFSR0 register's IFSR00 bit is set to "0" (CAN1 successful transmission) or "1" (SI/O3). And, make sure the C1TRMIC register's POL bit is set to "0" (falling edge). Figure 1.10.11 IFSR0 Register and IFSR1 Register Rev.1.00 2003.05.30 page 86 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts ______ NMI Interrupt _______ _______ ______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. _______ The input level of this NMI interrupt input pin can be read by accessing the P8 register's P8_5 bit. This pin cannot be used as an input port. Key Input Interrupt Of P104 to P107, a key input interrupt is generated when input on any of the P104 to P107 pins which has had the PD10 register's PD10_4 to PD10_7 bits set to "0" (input) goes low. Key input interrupts can be used as a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode. However, if you intend to use the key input interrupt, do not use P104 to P107 as analog input ports. Figure 1.10.12 shows the block diagram of the key input interrupt. Note, however, that while input on any pin which has had the PD10_4 to PD10_7 bits set to "0" (input mode) is pulled low, inputs on all other pins of the port are not detected as interrupts. PUR2 register's PU25 bit Pull-up transistor KUPIC register PD10 register's PD10_7 bit PD10 register's PD10_7 bit KI3 PD10 register's PD10_6 bit Pull-up transistor Interrupt control circuit KI2 Pull-up transistor Key input interrupt request PD10 register's PD10_5 bit KI1 Pull-up transistor PD10 register's PD10_4 bit KI0 Figure 1.10.12 Key Input Interrupt Block Diagram CAN0/1 Wake-up Interrupt CAN0/1 wake-up interrupt is occurs when a falling edge is input to CRx0 or CRx1. Use the interrupt in stop/wait mode or CAN sleep mode. The CAN0/1 wake-up interrupt is enabled only when the port is defined as the CAN port. One interrupt is allocated to CAN0/1. Figure 1.10.13 shows the block diagram of the CAN0/1 wake-up interrupt. Please note that the wake-up message will be lost. C0CTLR register's PortEn bit C01WKIC register CRX0 C1CTLR register's PortEn bit Interrupt control circuit CRX1 Figure 1.10.13 CAN0/1 Wake-up Interrupt Block Diagram Rev.1.00 2003.05.30 page 87 CAN0/1 wake-up interrupt request Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi register. Use the AIER register's AIER0 and AIER1 bits and the AIER2 register's AIER20 and AIER21 bits to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the PC that is saved to the stack area varies depending on the instruction being executed (refer to "Saving Registers"). (The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one of the methods described below to return from the address match interrupt. * Rewrite the content of the stack and then use the REIT instruction to return. * Restore the stack to its previous state before the interrupt request was accepted by using the POP or similar other instruction and then use a jump instruction to return. Table 1.10.6 shows the value of the PC that is saved to the stack area when an address match interrupt request is accepted. Note that when using the external bus in 8-bit width, no address match interrupts can be used for external areas. Table 1.10.7 shows the relationship between address match interrupt sources and associated registers. Figure 1.10.14 shows the AIER, AIER2, and RMAD0 to RMAD3 registers. Table 1.10.6 Value of PC That is Saved to Stack Area When Address Match Interrupt Request is Accepted Instruction at address indicated by RMADi register Value at PC that is saved to stack area * 16-bit operation code * Address indicated by RMADi register + 2 * Instruction shown below among 8-bit operation code instructions ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (However, dest = A0 or A1) POPM dest * Instructions other than the above * Address indicated by RMADi register + 1 Value of PC that is saved to stack area: Refer to "Saving Registers". Table 1.10.7 Relationship Between Address Match Interrupt Sources and Associated Registers Address match interrupt sources Address match interrupt enable bit Address match interrupt register Address match interrupt 0 AIER0 RMAD0 Address match interrupt 1 AIER1 RMAD1 Address match interrupt 2 AIER20 RMAD2 Address match interrupt 3 AIER21 RMAD3 Rev.1.00 2003.05.30 page 88 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Interrupts Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Address 000916 Bit symbol Bit name AIER0 AIER1 - After reset XXXXXX002 Function RW Address match interrupt 0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW Address match interrupt 1 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW Nothing is assigned. When write, set to "0". When read, their contents are indeterminate. (b7-b2) - Address match interrupt enable register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER2 Address 01BB16 After reset XXXXXX002 Bit symbol Bit name Function RW AIER20 Address match interrupt 2 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW AIER21 Address match interrupt 3 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW - Nothing is assigned. When write, set to "0". When read, their contents are indeterminate. (b7-b2) Address match interrupt register i (i = 0 to 3) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 Bit symbol (b19-b0) (b23-b20) b0 Symbol RMAD0 RMAD1 RMAD2 RMAD3 Address 001216 to 001016 001616 to 001416 01BA16 to 01B816 01BE16 to 01BC16 Function Address setting register for address match interrupt - Setting range RW 0000016 to FFFFF16 RW Nothing is assigned. When write, set to "0". When read, their contents are indeterminate. Figure 1.10.14 AIER Register, AIER2 Register and RMAD0 to RMAD3 Registers Rev.1.00 2003.05.30 page 89 After reset X0000016 X0000016 X0000016 X0000016 - Under development This document is under development and its contents are subject to change. M16C/6N4 Group Watchdog Timer Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after reaching the terminal count can be selected using the PM12 bit of PM1 register. The PM12 bit can only be set to "1" (watchdog timer reset). Once this bit is set to "1", it cannot be set to "0" (watchdog timer interrupt) in a program. Refer to "Watchdog Timer Reset" for details about watchdog timer reset. When the main clock is selected for CPU clock, ring oscillator clock, PLL clock, the divide-by-n value for the prescaler can be selected to be 16 or 128. If a sub clock is selected for CPU clock, the divide-by-n value for the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calculated as given below. The period of watchdog timer is, however, subject to an error due to the prescaler. With main clock selected for CPU clock, ring oscillator clock, PLL clock Watchdog timer period = Prescaler dividing (16 or 128) Watchdog timer count (32768) CPU clock With sub clock selected for CPU clock Watchdog timer period = Prescaler dividing (2) Watchdog timer count (32768) CPU clock For example, when CPU clock = 16 MHz and the divide-by-n value for the prescaler = 16, the watchdog timer period is approx. 32.8 ms. The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting by writing to the WDTS register. In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released. Figure 1.11.1 shows the block diagram of the watchdog timer. Figure 1.11.2 shows the watchdog timerrelated registers. * Count source protective mode In this mode, a ring oscillator clock is used for the watchdog timer count source. The watchdog timer can be kept being clocked even when CPU clock stops as a result of runaway. Before this mode can be used, the following register settings are required: (1) Set the PRC1 bit of the PRCR register to "1" (enable writes to the PM1 and PM2 registers). (2) Set the PM12 bit of the PM1 register to "1" (reset when the watchdog timer underflows). (3) Set the PM22 bit of the PM2 register to "1" (ring oscillator clock used for the watchdog timer count source). (4) Set the PRC1 bit of the PRCR register to "0" (disable writes to the PM1 and PM2 registers). (5) Write to the WDTS register (watchdog timer starts counting). Rev.1.00 2003.05.30 page 90 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Watchdog Timer Setting the PM22 bit to "1" results in the following conditions: * The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source. Watchdog timer period = Watchdog timer count (32768) ring oscillator clock * The CM10 bit of the CM1 register is disabled against write. (Writing a "1" has no effect, nor is stop mode entered.) * The watchdog timer does not stop when in wait mode or hold state. Prescaler CM07 = 0 WDC7 = 0 1/16 PM12 = 0 CPU clock 1/128 CM07 = 0 WDC7 = 1 PM22 = 0 CM07 = 1 PM22 = 1 Watchdog timer interrupt request HOLD Watchdog timer 1/2 PM12 = 1 Watchdog timer Reset Ring oscillator clock Set to "7FFF16" Write to WDTS register RESET Figure 1.11.1 Watchdog Timer Block Diagram Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol WDC Address 000F16 Bit symbol After reset 00XXXXXX2 Function Bit name RW (b4-b0) High-order bit of watchdog timer RO (b6-b5) Reserved bit Set to "0" RW WDC7 Prescaler select bit 0 : Divided by 16 1 : Divided by 128 RW Watchdog timer start register (Note) b7 b0 Symbol WDTS Address 000E16 After reset Indeterminate Function RW The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to "7FFF16" regardless WO of whatever value is written. Note: Write to the WDTS register after the watchdog timer interrupt occurs. Figure 1.11.2 WDC Register and WDTS Register Rev.1.00 2003.05.30 page 91 Under development This document is under development and its contents are subject to change. M16C/6N4 Group DMAC DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit) data from the source address to the destination address. The DMAC uses the same data bus as used by the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after a DMA request is generated. Figure 1.12.1 shows the block diagram of the DMAC. Table 1.12.1 shows the DMAC specifications. Figures 1.12.2 to 1.12.4 show the DMAC related-registers. Address bus DMA0 source pointer SAR0(20) (addresses 002216 to 002016) DMA0 destination pointer DAR0 (20) (addresses 002616 to 002416) DMA0 forward address pointer (20) (Note) DMA0 transfer counter reload register TCR0 (16) (addresses 002916, 002816) DMA1 source pointer SAR1 (20) (addresses 003216 to 003016) DMA0 transfer counter TCR0 (16) DMA1 destination pointer DAR1 (20) DMA1 transfer counter reload register TCR1 (16) DMA1 forward address pointer (20) (Note) (addresses 003616 to 003416) (addresses 003916, 003816) DMA1 transfer counter TCR1 (16) DMA latch high-order bits DMA latch low-order bits Data bus low-order bits Data bus high-order bits Note: Pointer is incremented by a DMA request. Figure 1.12.1 DMAC Block Diagram A DMA request is generated by a write to the DSR bit of the DMiSL register (i = 0, 1), as well as by an interrupt request which is generated by any function specified by the DMS and DSEL3 to DSEL0 bits of the DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect interrupts, the IR bit of the interrupt control register does not change state due to a DMA transfer. A data transfer is initiated each time a DMA request is generated when the DMAE bit = 1 (DMA enabled) of the DMiCON register. However, if the cycle in which a DMA request is generated is faster than the DMA transfer cycle, the number of transfer requests generated and the number of times data is transferred may not match. For details, refer to "DMA Requests". Rev.1.00 2003.05.30 page 92 Under development This document is under development and its contents are subject to change. M16C/6N4 Group DMAC Table 1.12.1 DMAC Specifications Item Specification No. of channels 2 (cycle steal method) Transfer memory space * From any address in the 1 Mbyte space to a fixed address * From a fixed address to any address in the 1 Mbyte space * From a fixed address to a fixed address Maximum No. of bytes transferred 128 Kbytes (with 16-bit transfer) or 64 Kbytes (with 8-bit transfer) ________ DMA request factors (Notes 1, 2) ________ Falling edge of INT0 or INT1 ________ ________ Both edge of INT0 or INT1 Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 transfer, UART0 reception interrupt requests UART1 transfer, UART1 reception interrupt requests UART2 transfer, UART2 reception interrupt requests SI/O3 interrupt request A-D conversion interrupt requests Software triggers Channel priority DMA0 > DMA1 (DMA0 takes precedence) Transfer unit 8 bits or 16 bits Transfer address direction forward or fixed (The source and destination addresses cannot both be in the forward direction.) Transfer mode Single transfer Transfer is completed when the DMAi transfer counter underflows after reaching the terminal count. Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value of the DMAi transfer counter reload register and a DMA transfer is continued with it. DMA interrupt request generation timing When the DMAi transfer counter underflowed DMA start-up Data transfer is initiated each time a DMA request is generated when the DMAiCON register's DMAE bit = 1 (enabled). DMA shutdown Single transfer * When the DMAE bit is set to "0" (disabled) * After the DMAi transfer counter underflows Repeat transfer When the DMAE bit is set to "0" (disabled) When a data transfer is started after setting the DMAE bit to "1" (enabled), Reload timing for forward the forward address pointer is reloaded with the value of the SARi or the address pointer and transfer DARi pointer whichever is specified to be in the forward direction and the counter DMAi transfer counter is reloaded with the value of the DMAi transfer counter reload register. i = 0, 1 Note 1: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the interrupt control register. Note 2: The selectable causes of DMA requests differ with each channel. Note 3: Make sure that no DMAC-related registers (addresses 002016 to 003F16) are accessed by the DMAC. Rev.1.00 2003.05.30 page 93 Under development This document is under development and its contents are subject to change. M16C/6N4 Group DMAC DMA0 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0SL Bit symbol Address 03B816 After reset 0016 Function Bit name DSEL0 DSEL1 DSEL2 RW DMA request cause select bit Refer to note - RW RW DSEL3 (b5-b4) RW RW Nothing is assigned. When write, set to "0". When read, its content is "0". - DMS DMA request cause expansion select bit 0 : Basic cause of request 1 : Extended cause of request RW DSR Software DMA request bit A DMA request is generated by setting this bit to "1" when the DMS bit is "0" (basic cause) and the DSEL3 to DSEL0 bits are "00012" (software trigger). The value of this bit when read is "0". RW Note: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described below. DSEL3 to DSEL0 00002 00012 00102 00112 01002 01012 01102 01112 10002 10012 10102 10112 11002 11012 11102 11112 DMS = 0 (basic cause of request) Falling edge of INT0 pin Software trigger Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 UART0 transmit UART0 receive UART2 transmit UART2 receive A-D conversion UART1 transmit Figure 1.12.2 DM0SL Register Rev.1.00 2003.05.30 page 94 DMS = 1 (extended cause of request) -- -- -- -- -- -- Two edges of INT0 pin Timer B3 Timer B4 Timer B5 -- -- -- -- -- -- Under development This document is under development and its contents are subject to change. M16C/6N4 Group DMAC DMA1 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM1SL Bit symbol Address 03BA16 After reset 0016 Function Bit name DSEL0 DSEL1 DSEL2 RW DMA request cause select bit RW Refer to note RW DSEL3 (b5-b4) DMS DSR RW RW Nothing is assigned. When write, set to "0". When read, its content is "0". - DMA request cause expansion select bit 0 : Basic cause of request 1 : Extended cause of request RW Software DMA request bit A DMA request is generated by setting this bit to "1" when the DMS bit is "0" (basic cause) and the DSEL3 to DSEL0 bits are "00012" (software trigger). The value of this bit when read is "0". RW Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described below. DSEL3 to DSEL0 00002 00012 00102 00112 01002 01012 01102 01112 10002 10012 10102 10112 11002 11012 11102 11112 DMS = 0 (basic cause of request) Falling edge of INT1 pin Software trigger Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 UART0 transmit UART0 receive/ACK0 UART2 transmit UART2 receive/ACK2 A-D conversion UART1 transmit/ACK1 DMS = 1 (extended cause of request) -- -- -- -- -- SI/O3 -- Two edges of INT1 pin -- -- -- -- -- -- -- -- DMAi control register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0CON DM1CON Bit symbol Address 002C16 003C16 After reset 00000X002 00000X002 Function Bit name RW DMBIT Transfer unit bit select bit 0 : 16 bits 1 : 8 bits RW DMASL Repeat transfer mode select bit 0 : Single transfer 1 : Repeat transfer RW DMAS DMA request bit 0 : DMA not requested 1 : DMA requested DMAE DMA enable bit 0 : Disabled 1 : Enabled RW DSD Source address direction select bit (Note 2) 0 : Fixed 1 : Forward RW DAD Destination address direction select bit (Note 2) 0 : Fixed 1 : Forward RW (b7-b6) Nothing is assigned. When write, set to "0". When read, its content is "0". RW (Note 1) - Note 1: The DMAS bit can be set to "0" by writing "0" in a program. (This bit remains unchanged even if "1" is written.) Note 2: At least one of the DAD and DSD bits must be "0" (address direction fixed). Figure 1.12.3 DM1SL Register, DM0CON Register and DM1CON Register Rev.1.00 2003.05.30 page 95 Under development This document is under development and its contents are subject to change. M16C/6N4 Group DMAC DMAi source pointer (i = 0, 1) (Note) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address After reset 002216 to 002016 Indeterminate 003216 to 003016 Indeterminate Function Set the source address of transfer Setting range RW 0000016 to FFFFF16 RW Nothing is assigned. When write, set to "0". When read, these contents are "0". - Note: If the DSD bit of the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit of the DMiCON register is "0" (DMA disabled). If the DSD bit is "1" (forward direction), this register can be written to at any time. If the DSD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from this register. Otherwise, the value written to it can be read. DMAi destination pointer (i = 0, 1) (Note) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol DAR0 DAR1 Address After reset 002616 to 002416 Indeterminate 003616 to 003416 Indeterminate Function Set the destination address of transfer Setting range RW 0000016 to FFFFF16 RW Nothing is assigned. When write, set to "0". When read, these contents are "0". - Note: If the DAD bit of the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit of the DMiCON register is "0" (DMA disabled). If the DAD bit is "1" (forward direction), this register can be written to at any time. If the DAD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from this register. Otherwise, the value written to it can be read. DMAi transfer counter (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol TCR0 TCR1 2003.05.30 page 96 After reset Indeterminate Indeterminate Function Setting range RW Set the transfer count minus 1. The written value is stored in the DMAi transfer counter reload register, and when the DMAE bit of the DMiCON register is set to "1" (DMA enabled) or the DMAi transfer counter underflows when the DMASL bit of the DMiCON register is "1" (repeat transfer), the value of the DMAi transfer counter reload register is transferred to the DMAi transfer counter. When read, the DMAi transfer counter is read. 0000016 to FFFFF16 RW Figure 1.12.4 SAR0, SAR1, DAR0, DAR1, TCR0 and TCR1 Registers Rev.1.00 Address 002916, 002816 003916, 003816 Under development This document is under development and its contents are subject to change. M16C/6N4 Group DMAC 1. Transfer Cycle The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer. During memory expansion and microprocessor modes, it is also affected by the ________ BYTE pin level. Furthermore, the bus cycle itself is extended by a software wait or RDY signal. (a) Effect of Source and Destination Addresses If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd address, the source read cycle consists of one more bus cycle than when the source address of transfer begins with an even address. Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer begins with an odd address, the destination write cycle consists of one more bus cycle than when the destination address of transfer begins with an even address. (b) Effect of BYTE Pin Level During memory expansion and microprocessor modes, if 16 bits of data are to be transferred on an 8bit data bus (input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data twice. Therefore, this operation requires two bus cycles to read data and two bus cycles to write data. Furthermore, if the DMAC is to access the internal area (internal ROM, internal RAM, or SFR), unlike in the case of the CPU, the DMAC does it through the data bus width selected by the BYTE pin. (c) Effect of Software Wait For memory or SFR accesses in which one or more software wait states are inserted, the number of bus cycles required for that access increases by an amount equal to software wait states. _______ (d) Effect of RDY Signal During memory expansion and microprocessor modes, DMA transfers to and from an external area ________ ________ are affected by the RDY signal. Refer to "RDY Signal". Figure 1.12.5 shows the example of the cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for the source read and the destination write cycle, respectively. For example, when data is transferred in 16bit unit using an 8-bit bus ((2) in Figure 1.12.5), two source read bus cycles and two destination write bus cycles are required. Rev.1.00 2003.05.30 page 97 Under development This document is under development and its contents are subject to change. M16C/6N4 Group DMAC (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address BCLK Address bus CPU use Source Dummy cycle Destination CPU use RD signal WR signal Data bus CPU use Source Dummy cycle Destination CPU use (2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the transfer unit is 16 bits and an 8-bit bus is used BCLK Address bus CPU use Source Source + 1 Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use (3) When the source read cycle under condition (1) has one wait state inserted BCLK Address bus CPU use Source Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use (4) When the source read cycle under condition (2) has one wait state inserted BCLK Address bus CPU use Source Source + 1 Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use Note: The same timing changes occur with the respective conditions at the destination as at the source. Figure 1.12.5 Transfer Cycles for Source Read Rev.1.00 2003.05.30 page 98 Under development This document is under development and its contents are subject to change. M16C/6N4 Group DMAC 2. DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.12.2 shows the number of DMA transfer cycles. Table 1.12.3 shows the coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles j + No. of write cycles k Table 1.12.2 DMA Transfer Cycles Memory expansion mode Microprocessor mode Single-chip mode Transfer unit Bus width Access address No. of read No. of write No. of read No. of write cycles cycles cycles cycles 1 1 1 1 16 bits Even 8-bit transfer (BYTE = L) Odd 1 1 1 1 (DMBIT =1) 8 bits (BYTE= H) Even Odd - - 1 1 1 1 16 bits (BYTE =L) Even Odd 1 2 1 2 1 2 1 2 8 bits Even - - 2 2 (BYTE = H) Odd - - 2 2 16-bit transfer (DMBIT = 0) Table 1.12.3 Coefficient j, k Internal area Internal ROM, RAM External area SFR No wait With wait 1 wait 2 waits No wait (Note 1) (Note 1) j k 1 1 2 2 2 2 3 3 1 2 Separate bus With wait (Note 2) 1 wait 2 waits 3 waits 2 3 4 2 3 4 Note 1: Depends on the set value of the PM20 bit of the PM2 register. Note 2: Depends on the set value of the CSE register. Rev.1.00 2003.05.30 page 99 Multiplexed bus With wait (Note 2) 1 wait 3 3 2 waits 3 waits 3 4 3 4 Under development This document is under development and its contents are subject to change. M16C/6N4 Group DMAC 3. DMA Enable When a data transfer starts after setting the DMAE bit of the DMiCON register (i = 0, 1) to "1" (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit of the DMiCON register is "1" (forward) or the DARi register value when the DAD bit of the DMiCON register is "1" (forward). (2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value. If the DMAE bit is set to "1" again while it remains set, the DMAC performs the above operation. However, if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below. Step 1: Write "1" to the DMAE bit and DMAS bit of the DMiCON register simultaneously. Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program. If the DMAi is not in an initial state, the above steps should be repeated. 4. DMA Request The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS and DSEL3 to DSEL0 bits of the DMiSL register (i = 0, 1) on either channel. Table 1.12.4 shows the timing at which the DMAS bit changes state. Whenever a DMA request is generated, the DMAS bit is set to "1" (DMA requested) regardless of whether or not the DMAE bit is set. If the DMAE bit was set to "1" (enabled) when this occurred, the DMAS bit is set to "0" (DMA not requested) immediately before a data transfer starts. This bit cannot be set to "1" in a program (it can only be set to "0"). The DMAS bit may be set to "1" when the DMS or the DSEL3 to DSEL0 bits change state. Therefore, always be sure to set the DMAS bit to "0" after changing the DMS or the DSEL3 to DSEL0 bits. Because if the DMAE bit is "1", a data transfer starts immediately after a DMA request is generated, the DMAS bit in almost all cases is "0" when read in a program. Read the DMAE bit to determine whether the DMAC is enabled. Table 1.12.4 Timing at Which DMAS bit Changes State DMAS bit of DMiCON register DMA factor Timing at which the bit is set to "1" Timing at which the bit is set to "0" Software trigger Peripheral function When the DSR bit of the DMiSL register * Immediately before a data transfer starts is set to "1" * When set by writing "0" in a program When the interrupt control register for the peripheral function that is selected by the DSEL3 to DSEL0 and DMS bits of the DMiSL register has its IR bit set to "1". i = 0, 1 Rev.1.00 2003.05.30 page 100 Under development This document is under development and its contents are subject to change. M16C/6N4 Group DMAC 5. Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel is set to "1" (DMA requested) at the same time. In this case, the DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period. Figure 1.12.6 shows an example of DMA transfer effected by external factors. In Figure 1.12.6, DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, a bus arbitration is returned to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is completed, the bus arbitration is again returned to the CPU. In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when DMA requests, as DMA1 in Figure 1.12.6, occurs more than one time, the DMAS bit is set to "0" as soon as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed. __________ Refer to "(7) HOLD Signal in Bus Control" for details about bus arbitration between the CPU and DMA. An example where DMA requests for external causes are detected active at the same time, a DMA transfer is executed in the shortest cycle. BCLK DMA0 DMA1 Bus arbitration CPU INT0 DMA0 request bit INT1 DMA1 request bit Figure 1.12.6 DMA Transfer by External Factors Rev.1.00 2003.05.30 page 101 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timers Timers Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. Figures 1.13.1 and 1.13.2 show block diagrams of timer A and timer B configuration, respectively. Main clock f1 PLL clock Ring oscillator clock 1/2 f2 PCLK0 bit = 0 Clock prescaler f1 or f2 PCLK0 bit = 1 1/8 1/4 f1 or f2 f8 f32 fC32 1/32 XCIN f8 f32 Set the CPSR bit of CPSRF register to "1" (= prescaler reset) fC32 Reset Timer mode One-shot timer mod e Pulse Width Measuring (PWM) mode Timer A0 interrupt Noise filter TA0IN Timer A0 Event counter mod e Timer mode One-shot timer mod e PWM mode Noise filter TA1IN Timer A1 interrupt Timer A1 Event counter mod e Timer mode One-shot timer mod e PWM mode Timer A2 interrupt Noise filter TA2IN Timer A2 Event counter mod e Timer mod e One-shot timer mod e PWM mode Timer A3 interrupt Noise filter TA3IN Timer A3 Event counter mod e Timer mode One-shot timer mod e PWM mode Timer A4 interrupt Noise filter TA4IN Timer A4 Event counter mod e Timer B2 overflow or underflow Note: Be aware that TA0IN shares the pin with RxD2, SCL2 and TB5IN. Figure 1.13.1 Timer A Configuration Rev.1.00 2003.05.30 page 102 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timers Main clock f1 PLL clock Ring oscillator clock 1/2 f2 PCLK0 bit = 0 Clock prescaler f1 or f2 f8 1/8 1/4 f32 fC32 1/32 XCIN PCLK0 bit = 1 Set the CPSR bit of CPSRF register to "1" (= prescaler reset) Reset f1 or f2 f8 f32 fC32 Timer B2 overflow or underflow (to Timer A count source) Timer mode Pulse width measuring mode, pulse period measuring mode Noise filter TB0IN Timer B0 interrupt Timer B0 Event counter mode Timer mode Pulse width measuring mode, pulse period measuring mode Noise filter TB1IN Timer B1 interrupt Timer B1 Event counter mode Timer mode Pulse width measuring mode, pulse period measuring mode Noise filter TB2IN Timer B2 interrupt Timer B2 Event counter mode Timer mode Pulse width measuring mode, pulse period measuring mode Noise filter TB3IN Timer B3 interrupt Timer B3 Event counter mode Timer mode Pulse width measuring mode, pulse period measuring mode Noise filter TB4IN Timer B4 interrupt Timer B4 Event counter mode Timer mode Pulse width measuring mode, pulse period measuring mode Noise filter TB5IN Timer B5 Event counter mode Note: Be aware that TB5IN shares the pin with RxD2, SCL2 and TA0IN. Figure 1.13.2 Timer B Configuration Rev.1.00 2003.05.30 page 103 Timer B5 interrupt Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A Timer A Figure 1.13.3 shows a block diagram of the timer A. Figures 1.13.4 to 1.13.6 show the timer A-related registers. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode. * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external device or overflows and underflows of other timers. * One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count "000016." * Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively. Data bus high-order bits Clock source selection Data bus low-order bits Timer mode One shot mode PWM mode f1 or f2 f8 f32 fC32 Low-order 8 bits Timer mode (gate function) Reload register Event counter mode TAiIN Clock selection Counter Polarity selection Up-count/down-count TABSR register Clock selection (Note) TB2 overflow To external trigger circuit (Note) TAj overflow Down count UDF register TAk overflow Pulse output Toggle flip-flop TAiOUT i = 0 to 4 j = i -- 1. Note, however, that j = 4 when i = 0 k = i + 1. Note, however, that k = 0 when i = 4 Note: Overflow or underflow Figure 1.13.3 Timer A Block Diagram Rev.1.00 2003.05.30 High-order 8 bits page 104 Always counts down except in event counter mode TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 038716 - 038616 038916 - 038816 038B16 - 038A16 038D16 - 038C16 038F16 - 038E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A Timer Ai mode register (i = 0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0MR to TA4MR Bit symbol Address 039616 to 039A16 After reset 0016 Bit name Function RW b1 b0 TMOD0 Operation mode select bit TMOD1 MR0 MR1 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode RW Function varies with each operation mode RW MR3 TCK1 RW RW MR2 TCK0 RW RW Count source select bit Function varies with each operation mode RW RW Timer Ai register (i = 0 to 4) (Note 1) (b15) b7 (b8) b0 b7 b0 Symbol TA0 TA1 TA2 TA3 TA4 Address 038716, 038616 038916, 038816 038B16, 038A16 038D16, 038C16 038F16, 038E16 After reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Function Setting range RW Divide the count source by n + 1 where n = set value 000016 to FFFF16 RW Divide the count source by FFFF16 -- n + 1 where n = set value when counting up or by n + 1 when counting down (Note 2) 000016 to FFFF16 Divide the count source by n where n = set One-shot timer mode value and cause the timer to sto p 000016 to FFFF16 (Notes 3, 4) Pulse width Modify the pulse width as follows: modulation PWM period: (216 -- 1) / fj High level PWM pulse width: n / fj mode (16-bit PWM) where n = set value, fj = count source frequency 000016 to FFFE16 (Note 4, 5) Pulse width Modify the pulse width as follows: modulation PWM period: (28 -- 1) (m + 1)/ fj mode High level PWM pulse width: (m + 1)n / fj (8-bit PWM) where n = high-order address set value, m = low-order address set value, fj = count source frequency 0016 to FE16 (High-order address) 0016 to FF16 (Low-order address) WO (Note 4, 5) Mode Timer mode Event counter mode RW WO WO Note 1: The register must be accessed in 16-bit unit. Note 2: The timer counts pulses from an external device or overflows or underflows in other timers. Note 3: If the TAi register is set to "000016", the counter does not work and timer Ai interrupt requests are not generated either. Furthermore, if "pulse output" is selected, no pulses are output from the TAiOUT pin. Note 4: Use the MOV instruction to write to the TAi register. Note 5: If the TAi register is set to "000016", the pulse width modulator does not work, the output level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated either. The same applies when the 8 high-order bits of the timer TAi register are set to "0016" while operating as an 8-bit pulse width modulator. Figure 1.13.4 TA0MR to TA4MR Registers and TA0 to TA4 Registers Rev.1.00 2003.05.30 page 105 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Bit symbol Address 038016 After reset 0016 Bit name Function RW RW TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S Timer A2 count start flag RW TA3S Timer A3 count start flag RW TA4S Timer A4 count start flag RW TB0S Timer B0 count start flag RW TB1S Timer B1 count start flag RW TB2S Timer B2 count start flag RW 0 : Stops counting 1 : Starts counting RW Up/down flag (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Bit symbol Address 038416 Bit name TA0UD Timer A0 up/down flag TA1UD Timer A1 up/down flag TA2UD Timer A2 up/down flag TA3UD Timer A3 up/down flag TA4UD Timer A4 up/down flag TA2P TA3P TA4P After reset 0016 Function 0 : Down count 1 : Up count RW RW RW Enabled by setting the TAiMR RW register's MR2 bit to "0" (switching source in UDF register) RW during event counter mode. RW Timer A2 two-phase pulse 0 : two-phase pulse signal WO processing disabled signal processing select bit 1 : two-phase pulse signal processing enabled Timer A3 two-phase pulse WO (Notes 2, 3) signal processing select bit Timer A4 two-phase pulse signal processing select bit WO Note 1: Use MOV instruction to write to this register. Note 2: Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set to "0" (input mode). Note 3: When not using the two-phase pulse signal processing function, set the corresponding bit to timer A2 to timer A4 to "0". Figure 1.13.5 TABSR Register and UFD Register Rev.1.00 2003.05.30 page 106 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A One-shot start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol ONSF Address 038216 After reset 0016 Bit symbol Bit name Function RW TA0OS Timer A0 one-shot start flag RW TA1OS Timer A1 one-shot start flag TA2OS Timer A2 one-shot start flag TA3OS Timer A3 one-shot start flag TA4OS Timer A4 one-shot start flag The timer starts counting by setting this bit to "1" while the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) is "102" (one-shot timer mode) and the MR2 bit of TAiMR register is "0" (TAiOS bit enabled). When read, its content is "0". TAZIE Z-phase input enable bit 0 : Z-phase input disabled 1 : Z-phase input enabled RW RW RW RW RW b7 b6 TA0TGL Timer A0 event/trigger select bit TA0TGH 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 is selected 1 0 : TA4 is selected 1 1 : TA1 is selected RW RW Note: Make sure the PD7_1 bit of PD7 register is set to "0" (input mode). Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Bit symbol Address 038316 After reset 0016 Bit name Function RW b1 b0 TA1TGL TA1TGH Timer A1 event/trigger select bit 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 is selected 1 0 : TA0 is selected 1 1 : TA2 is selected RW RW b3 b2 TA2TGL TA2TGH Timer A2 event/trigger select bit 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 is selected 1 0 : TA1 is selected 1 1 : TA3 is selected RW RW b5 b4 TA3TGL TA3TGH Timer A3 event/trigger select bit 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 is selected 1 0 : TA2 is selected 1 1 : TA4 is selected RW RW b7 b6 TA4TGL TA4TGH Timer A4 event/trigger select bit 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 is selected 1 0 : TA3 is selected 1 1 : TA0 is selected RW RW Note: Make sure the port direction bits for the TA1IN to TA4IN pins are set to "0" (input mode). Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Bit symbol Address 038116 After reset 0XXXXXXX2 Bit name Function (b6-b0) Nothing is assigned. When write, set to "0". When read, their contents are indeterminate. CPSR Clock prescaler reset flag Setting this bit to "1" initializes the prescaler for the timekeeping clock. (When read, its content is "0".) Figure 1.13.6 ONSF Register, TRGSR Register and CPSRF Register Rev.1.00 2003.05.30 page 107 RW RW Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A 1. Timer Mode In timer mode, the timer counts a count source generated internally. Table 1.13.1 lists specifications in timer mode. Figure 1.13.7 shows TAiMR register in timer mode. Table 1.13.1. Specifications in Timer Mode Item Specification Count source f1, f2, f8, f32, fC32 Count operation * Down-count * When the timer underflows, it reloads the reload register contents and continues counting Divide ratio 1/(n+1) n: set value of TAiMR register 000016 to FFFF16 Count start condition Set TAiS bit of TABSR register to "1" (start counting) Count stop condition Set TAiS bit to "0" (stop counting) Interrupt request generation timing Timer underflow TAiIN pin function I/O port or gate input TAiOUT pin function I/O port or pulse output Read from timer Count value can be read by reading TAi register Write to timer * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) Select function * Gate function Counting can be started and stopped by an input signal to TAiIN pin * Pulse output function Whenever the timer underflows, the output polarity of TAiOUT pin is inverted. When not counting, the pin outputs a low. i = 0 to 4 Timer Ai mode register (i = 0 to 4) b7 b6 b5 b4 0 b3 b2 b1 b0 0 0 Symbol TA0MR to TA4MR Bit symbol TMOD0 TMOD1 MR0 Address 039616 to 039A16 After reset 0016 Bit name Function b1 b0 Operation mode select bit 0 0 : Timer mode Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (TAiOUT pin is a pulse output pin) RW RW RW RW b4 b3 MR1 Gate function select bit MR2 MR3 0 0 : Gate function not available } (TAiIN pin functions as I/O port) 01: 1 0 : Counts while input on the TAiIN pin is low (Note) 1 1 : Counts while input on the TAiIN pin is high (Note) Set to "0" in timer mode RW RW RW b7 b6 TCK0 Count source select bit TCK1 0 0 : f1 or f2 0 1 : f8 1 0 : f32 1 1 : fC32 Note: The port direction bit for the TAiIN pin must be set to "0" (input mode). Figure 1.13.7 Timer Ai Mode Register in Timer Mode Rev.1.00 2003.05.30 page 108 RW RW Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A 2. Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 1.13.2 lists specifications in event counter mode (when not processing two-phase pulse signal). Figure 1.13.8 shows TAiMR register in event counter mode (when not processing two-phase pulse signal). Table 1.13.3 lists specifications in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4). Figure 1.13.9 shows TA2MR to TA4MR registers in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4). Table 1.13.2 Specifications in Event Counter Mode (when not processing two-phase pulse signal) Item Specification Count source * External signals input to TAiIN pin (effective edge can be selected in program) * Timer B2 overflows or underflows, timer Aj (j = i - 1, except j = 4 if i = 0) overflows or underflows, timer Ak (k = i + 1, except k = 0 if i = 4) overflows or underflows Count operation * Up-count or down-count can be selected by external signal or program * When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading. Divided ratio 1/ (FFFF16 - n + 1) for up-count 1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16 Count start condition Set TAiS bit of TABSR register to "1" (start counting) Count stop condition Set TAiS bit to "0" (stop counting) Interrupt request generation timing Timer overflow or underflow TAiIN pin function I/O port or count source input TAiOUT pin function I/O port, pulse output, or up/down-count select input Read from timer Count value can be read by reading TAi register Write to timer * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) Select function * Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it * Pulse output function Whenever the timer underflows or underflows, the output polarity of TAiOUT pin is inverted. When not counting, the pin outputs a low. i = 0 to 4 Rev.1.00 2003.05.30 page 109 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A Timer Ai mode register (i = 0 to 4) (When not using two-phase pulse signal processing) b7 b6 b5 b4 b3 0 b2 b1 b0 Symbol TA0MR to TA4MR 0 1 Bit symbol TMOD0 Address 039616 to 039A16 Bit name Operation mode select bit TMOD1 MR0 Pulse output function select bit After reset 0016 Function b1 b0 RW R W RW 0 1 : Event counter mode (Note 1) RW 0 : Pulse is not output (TAiOUT pin functions as I/O port) 1 : Pulse is output RW (TAiOUT pin functions as pulse output pin) MR1 Count polarity select bit (Note 2) 0 : Counts external signal's falling edge RW 1 : Counts external signal's rising edge MR2 Up/down switching cause select bit 0 : UDF register 1 : Input signal to TAiOUT pin (Note 3) MR3 Set to "0" in event counter mode RW TCK0 Count operation type select bit RW TCK1 Can be "0" or "1" when not using two-phase pulse signal processing. RW 0 : Reload type 1 : Free-run type RW Note 1: During event counter mode, the count source can be selected using the ONSF and TRGSR registers. Note 2: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are"002" (TAiIN pin input). Note 3: Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port direction bit for TAiOUT pin must be set to "0" (input mode). Figure 1.13.8 TAiMR Register in Event Counter Mode (when not using two-phase pulse signal processing) Rev.1.00 2003.05.30 page 110 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A Table 1.13.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4) Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Select function (Note) Specification * Two-phase pulse signals input to TAiIN or TAiOUT pins * Up-count or down-count can be selected by two-phase pulse signal * When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading. 1/ (FFFF16 - n + 1) for up-count 1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16 Set TAiS bit of TABSR register to "1" (start counting) Set TAiS bit to "0" (stop counting) Timer overflow or underflow Two-phase pulse input Two-phase pulse input Count value can be read by reading timer A2, A3 or A4 register * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to reload register (Transferred to counter when reloaded next) * Normal processing operation (timer A2 and timer A3) The timer counts up rising edges or counts down falling edges on TAjIN pin when input signals on TAjOUT pin is "H". TAjOUT TAjIN Upcount Upcount Upcount Downcount Downcount Downcount * Multiply-by-4 processing operation (timer A3 and timer A4) If the phase relationship is such that TAkIN pin goes "H" when the input signal on TAkOUT pin is "H", the timer counts up rising and falling edges on TAkOUT and TAkIN pins. If the phase relationship is such that TAkIN pin goes "L" when the input signal on TAkOUT pin is "H", the timer counts down rising and falling edges on TAkOUT and TAkIN pins. TAkOUT Count up all edges Count down all edges TAkIN Count up all edges Count down all edges * Counter initialization by Z-phase input (timer A3) The timer count value is initialized to "0" by Z-phase input. i = 2 to 4 j = 2, 3 k = 3, 4 Note : Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to multiply-by-4 processing operation. Rev.1.00 2003.05.30 page 111 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A Timer Ai mode register (i = 2 to 4) (When using two-phase pulse signal processing) b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 1 Symbol TA2MR to TA4MR Address 039816 to 039A16 Function RW 0 1 : Event counter mode RW RW Bit name TMOD0 TMOD1 After reset 0016 b1 b0 Operation mode select bit RW MR0 To use two-phase pulse signal processing, set this bit to "0". MR1 RW MR2 To use two-phase pulse signal processing, set this bit to "1" . RW MR3 To use two-phase pulse signal processing, set this bit to "0". RW TCK0 Count operation type select bit 0 : Reload type 1 : Free-run type RW TCK1 Two-phase pulse signal processing operation select bit (Notes 1, 2) 0 : Normal processing operation 1 : Multiply-by-4 processing operation RW Note 1: TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in normal processing mode and x4 processing mode, respectively. Note 2: If two-phase pulse signal processing is desired, following register settings are required: Set the UDF register's TAiP bit to "1" (two-phase pulse signal processing function enabled). Set the TRGSR register's TAiTGH and TAiTGL bits to "002" (TAiIN pin input). Set the port direction bits for TAiIN and TAiOUT to "0" (input mode). Figure 1.13.9 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse signal processing with timer A2, A3 or A4) Rev.1.00 2003.05.30 page 112 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A * Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to "0" by Z-phase (counter initialization) input during twophase pulse signal processing. This function can only be used in timer A3 event counter mode during two-phase pulse signal process________ ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin. Counter initialization by Z-phase input is enabled by writing "000016" to the TA3 register and setting the TAZIE bit in ONSF register to "1" (Z-phase input enabled). Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be selected to be the rising or falling edge by using the POL bit of INT2IC register. The Z-phase pulse ________ width applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source. The counter is initialized at the next count timing after recognizing Z-phase input. Figure 1.13.10 shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase. If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3 interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this function. TA3OUT (A phase) TA3IN (B phase) Count source INT2 (Note) (Z phase) Input equal to or greater than one clock cycle of count source m Timer A3 m+1 1 2 3 4 5 Note: This timing diagram is for the case where the POL bit of INT2IC register = 1 (rising edge). Figure 1.13.10 Two-phase Pulse (A phase and B phase) and Z Phase Rev.1.00 2003.05.30 page 113 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A 3. One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. When the trigger occurs, the timer starts up and continues operating for a given period. Table 1.13.4 lists specifications in one-shot timer mode. Figure 1.13.11 shows the TAiMR register in one-shot timer mode. Table 1.13.4 Specifications in One-shot Timer Mode Item Specification Count source f1, f2, f8, f32, fC32 Count operation * Down-count * When the counter reaches 000016, it stops counting after reloading a new value * If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : set value of TAi register 000016 to FFFF16 However, the counter does not work if the divide-by-n value is set to 000016. Count start condition TAiS bit of TABSR register = 1 (start counting) and one of the following triggers occurs. * External trigger input from the TAiIN pin * Timer B2 overflow or underflow, timer Aj (j = i - 1, except j = 4 if i = 0) overflow or underflow, timer Ak (k = i + 1, except k = 0 if i = 4) overflow or underflow * The TAiOS bit of ONSF register is set to "1" (timer starts) Count stop condition * When the counter is reloaded after reaching "000016" * TAiS bit is set to "0" (stop counting) Interrupt request generation timing When the counter reaches "000016" TAiIN pin function I/O port or trigger input TAiOUT pin function I/O port or pulse output Read from timer An indeterminate value is read by reading TAi register Write to timer * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) Select function * Pulse output function The timer outputs a low when not counting and a high when counting. i = 0 to 4 Rev.1.00 2003.05.30 page 114 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A Timer Ai mode register (i = 0 to 4) b7 b6 b5 b4 b3 0 b2 b1 b0 1 0 Symbol TA0MR to TA4MR Bit symbol Address After reset 0016 039616 to 039A16 Bit name TMOD0 TMOD1 Function b1 b0 Operation mode select bit 1 0 : One-shot timer mode RW RW RW MR0 Pulse output function select bit 0 : Pulse is not output (TAiOUT pin functions as I/O port) RW 1 : Pulse is output (TAiOUT pin functions as a pulse output pin) MR1 External trigger select bit (Note 1) 0 : Falling edge of input signal to TAiIN pin (Note 2) 1 : Rising edge of input signal to TAiIN pin (Note 2) RW MR2 Trigger select bit 0 : TAiOS bit is enabled 1 : Selected by TAiTGH to TAiTGL bits MR3 Set to "0" in one-shot timer mode b7 b6 TCK0 Count source select bit TCK1 0 0 : f1 or f2 0 1 : f8 1 0 : f32 1 1 : fC32 RW RW RW RW Note 1: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are "002" (TAiIN pin input). Note 2: The port direction bit for the TAiIN pin must be set to "0" (input mode). Figure 1.13.11 TAiMR Register in One-shot Timer Mode Rev.1.00 2003.05.30 page 115 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A 4. Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession. The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Table 1.13.5 lists specifications in PWM mode. Figure 1.13.12 shows TAiMR register in PWM mode. Figures 1.13.13 and 1.13.14 show examples of how a 16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates, respectively. Table 1.13.5 Specifications in PWM Mode Item Specification Count source f1, f2, f8, f32, fC32 Count operation * Down-count (operating as an 8-bit or a 16-bit pulse width modulator) * The timer reloads a new value at a rising edge of PWM pulse and continues counting * The timer is not affected by a trigger that occurs during counting 16-bit PWM * High level width n / fj n : set value of TAi register 16 * Cycle time (2 -1) / fj fixed fj: count source frequency (f1, f2, f8, f32, fC32) 8-bit PWM * High level width n (m+1) / fj n : set value of TAiMR register high-order address 8 * Cycle time (2 -1) (m+1) / fj m : set value of TAiMR register low-order address Count start condition * TAiS bit of TABSR register is set to "1" (start counting) * TAiS bit = 1 and external trigger input from the TAiIN pin * TAiS bit = 1 and one of the following external triggers occurs Timer B2 overflow or underflow, timer Aj (j = i - 1, except j = 4 if i = 0) overflow or underflow, timer Ak (k = i + 1, except k = 0 if i = 4) overflow or underflow Count stop condition TAiS bit is set to "0" (stop counting) Interrupt request generation timing PWM pulse goes "L" TAiIN pin function I/O port or trigger input TAiOUT pin function Pulse output Read from timer An indeterminate value is read by reading TAi register Write to timer * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) i = 0 to 4 Rev.1.00 2003.05.30 page 116 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A Timer Ai mode register (i = 0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 Symbol TA0MR to TA4MR Bit symbol TMOD0 TMOD1 Address 039616 to 039A16 After reset 0016 Bit name Operation mode select bit Function b1 b0 1 1 : PWM mode RW RW RW RW MR0 Set to "1" in PWM mode MR1 0: Falling edge of input signal to TAiIN pin (Note 2) External trigger select RW bit (Note 1) 1: Rising edge of input signal to TAiIN pin (Note 2) MR2 Trigger select bit 0 : Write "1" to TAiS bit in the TABSR register RW 1 : Selected by TAiTGH to TAiTGL bits MR3 16/8-bit PWM mode select bit 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator Count source select bit 0 0 : f1 or f2 0 1 : f8 1 0 : f32 1 1 : fC32 RW b7 b6 TCK0 TCK1 RW RW Note 1: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are "002" (TAiIN pin input). Note 2: The port direction bit for the TAiIN pin must be set to "0" (input mode). Figure 1.13.12 TAiMR Register in PWM Mode Rev.1.00 2003.05.30 page 117 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer A 1 / fi (2 16 -- 1) Count source Input signal to TAiIN pin "H" "L" Trigger is not generated by this signal 1 / fj n PWM pulse output from TAiOUT pin "H" IR bit of TAiIC register "1" "L" "0" Set to "0" upon accepting an interrupt request or by writing in program i = 0 to 4 fj: Frequency of count source (f1, f2, f8, f32, fC32) Note 1: n = 000016 to FFFE16. Note 2: This timing diagram is the following case. TAi register = 000316 The TAiTGH and TAiTGL bits of ONSF or TRGSR register = 002 (TAiIN pin input) The MR1 bit of TAiMR register = 1 (rising edge) The MR2 bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits) Figure 1.13.13 Example of 16-bit Pulse Width Modulator Operation 1 / fj (m + 1) (2 8 -- 1) Count source (Note1) Input signal to TAiIN pin "H" "L" 1 / fj (m + 1) "H" Underflow signal of 8-bit prescaler (Note2) "L" 1 / fj (m + 1) n PWM pulse output from TAiOUT pin IR bit of TAiIC register "H" "L" "1" "0" Set to "0" upon accepting an interrupt request or by writing in program i = 0 to 4 fj: Frequency of count source (f1, f2, f8, f32, fC32) Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FE16. Note 4: This timing diagram is the following case. TAi register = 020216 The TAiTGH and TAiTGL bits of ONSF or TRGSR register = 002 (TAiIN pin input) The MR1 bit of TAiMR register = 0 (falling edge) The MR2 bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits) Figure 1.13.14 Example of 8-bit Pulse Width Modulator Operation Rev.1.00 2003.05.30 page 118 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer B Timer B Figure 1.13.15 shows a block diagram of the timer B. Figures 1.13.16 and 1.13.17 show the timer B-related registers. Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to 5) to select the desired mode. * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external device or overflows or underflows of other timers. * Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width. Data bus high-order bits Data bus low-order bits Clock source selection Low-order 8 bits Timer mode Pulse period measurement mode, pulse width measurement mode f1 or f2 f8 f32 fC32 High-order 8 bits Reload register Clock selection Counter Event counter mode TBiIN Polarity switching and edge pulse TABSR register TBSR register Counter reset circuit Can be selected in only event counter mode TBj overflow (Note) i = 0 to 5 j = i -- 1. Note, however, j = 2 when i = 0, j = 5 when i = 3 Note: Overflow or underflow Figure 1.13.15 Timer B Block Diagram Rev.1.00 2003.05.30 page 119 TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5 Addresses 039116 -039016 039316 -039216 039516 -039416 01D116 -01D016 01D316 -01D216 01D516 -01D416 TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer B Timer Bi mode register (i = 0 to 5) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TB0MR to TB2MR TB3MR to TB5MR Bit symbol Address After reset 039B16 to 039D16 00XX00002 01DB16 to 01DD16 00XX00002 Function Bit name RW b1 b0 TMOD0 Operation mode select bit TMOD1 MR0 MR1 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period measurement mode, pulse width measurement mode 1 1 : Must not be set RW Function varies with each operation mode RW RW RW RW (Note 1) MR2 (Note 2) RO MR3 TCK0 Count source select bit TCK1 Function varies with each operation mode RW RW Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Timer Bi register (i = 0 to 5) (Note 1) (b15) b7 (b8) b0 b7 b0 Mode Symbol TB0 TB1 TB2 TB3 TB4 TB5 Address 039116, 039016 039316, 039216 039516, 039416 01D116, 01D016 01D316, 01D216 01D516, 01D416 Function After reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Setting range RW Timer mode Divide the count source by n + 1 where n = set value 000016 to FFFF16 RW Event counter mode Divide the count source by n + 1 where n = set value (Note 2) 000016 to FFFF16 RW Pulse period Measures a pulse period or width modulation mode, Pulse width modulation mode RO Note 1: The register must be accessed in 16-bit unit. Note 2: The timer counts pulses from an external device or overflows or underflows of other timers. Figure 1.13.16 TB0MR to TB5MR Registers and TB0 to TB5 Registers Rev.1.00 2003.05.30 page 120 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer B Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 038016 After reset 0016 Bit name Bit symbol Function RW TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S Timer A2 count start flag RW TA3S Timer A3 count start flag RW TA4S Timer A4 count start flag RW TB0S Timer B0 count start flag RW TB1S Timer B1 count start flag RW TB2S Timer B2 count start flag RW 0 : Stops counting 1 : Starts counting RW RW Timer B3, B4, B5 count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBSR Bit symbol (b4-b0) Address 01C0 16 After reset 000XXXXX2 Bit name Function RW Nothing is assigned. When write, set to "0". When read, their contents are indeterminate. TB3S Timer B3 count start flag TB4S Timer B4 count start flag TB5S Timer B5 count start flag 0 : Stops counting 1 : Starts counting RW RW RW Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Bit symbol Address 038116 After reset 0XXXXXXX2 Bit name 2003.05.30 page 121 RW (b6-b0) Nothing is assigned. When write, set to "0". When read, their contents are indeterminate. CPSR Setting this bit to "1" initializes the Clock prescaler reset flag prescaler for the timekeeping clock. RW (When read, the value of this bit is "0".) Figure 1.13.17 TABSR Register, TBSR Register and CPSRF Register Rev.1.00 Function Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer B 1. Timer Mode In timer mode, the timer counts a count source generated internally. Table 1.13.6 lists specifications in timer mode. Figure 1.13.18 shows TBiMR register in timer mode. Table 1.13.6 Specifications in Timer Mode Item Specification Count source f1, f2, f8, f32, fC32 Count operation * Down-count * When the timer underflows, it reloads the reload register contents and continues counting Divide ratio 1/(n+1) n: set value of TBiMR register 000016 to FFFF16 Count start condition Set TBiS bit (Note) to "1" (start counting) Count stop condition Set TBiS bit to "0" (stop counting) Interrupt request generation timing Timer underflow TBiIN pin function I/O port Read from timer Count value can be read by reading TBi register Write to timer * When not counting and until the 1st count source is input after counting start Value written to TBi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TBi register is written to only reload register (Transferred to counter when reloaded next) i = 0 to 5 Note : The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits are assigned to the TBSR register bit 5 to bit 7. Timer Bi mode register (i = 0 to 5) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol TB0MR to TB2MR TB3MR to TB5MR Bit symbol TMOD0 Address 039B16 to 039D16 01DB16 to 01DD16 Bit name MR1 Function b1 b0 Operation mode select bit TMOD1 MR0 After reset 00XX00002 00XX00002 0 0 : Timer mode MR3 RW RW Has no effect in timer mode Can be set to "0" or "1" RW TB0MR, TB3MR registers Set to "0" in timer mode MR2 RW RW RW TB1MR, TB2MR, TB4MR, TB5MR registers Nothing is assigned. When write, set to "0". When read, its content is indeterminate. When write in timer mode, set to "0". When read in timer mode, its content is indeterminate. RO b7 b6 TCK0 Count source select bit TCK1 Figure 1.13.18 TBiMR Register in Timer Mode Rev.1.00 2003.05.30 page 122 0 0 : f1 or f2 0 1 : f8 1 0 : f32 1 1 : fC32 RW RW Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer B 2. Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Table 1.13.7 lists specifications in event counter mode. Figure 1.13.19 shows TBiMR register in event counter mode. Table 1.13.7 Specifications in Event Counter Mode Item Count source Specification * External signals input to TBiIN pin (effective edge can be selected in program) * Timer Bj overflow or underflow (j = i - 1, except j = 2 if i = 0, j = 5 if i = 3) Count operation * Down-count * When the timer underflows, it reloads the reload register contents and continues counting Divide ratio 1/(n+1) n: set value of TBi register 000016 to FFFF16 Count start condition Set TBiS bit (Note) to "1" (start counting) Count stop condition Set TBiS bit to "0" (stop counting) Interrupt request generation timing Timer underflow TBiIN pin function Count source input Read from timer Count value can be read by reading TBi register Write to timer * When not counting and until the 1st count source is input after counting start Value written to TBi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TBi register is written to only reload register (Transferred to counter when reloaded next) i = 0 to 5 Note: The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits are assigned to the TBSR register bit 5 to bit 7. Timer Bi mode register ( i= 0 to 5) b7 b6 b5 b4 b3 b2 b1 b0 0 1 Symbol TB0MR to TB2MR TB3MR to TB5MR Bit symbol TMOD0 Address 039B16 to 039D16 01DB16 to 01DD16 After reset 00XX00002 00XX00002 Bit name Function b1 b0 Operation mode select bit TMOD1 0 1 : Event counter mode RW RW RW b3 b2 MR0 Count polarity select bit (Note 1) MR1 0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Must not be set TB0MR, TB3MR registers Set to "0" in event counter mode RW RW RW MR2 TB1MR, TB2MR, TB4MR, TB5MR registers Nothing is assigned. When write, set to "0". When read, its content is indeterminate. MR3 When write in event counter mode, set to "0". When read in event counter mode, its content is indeterminate. RO TCK0 Has no effect in event counter mode. Can be set to "0" or "1". RW TCK1 Event clock select bit 0 : Input from TBiIN pin (Note 2) 1 : TBj overflow or underflow (j = i -- 1, except j = 2 if i = 0, j = 5 if i = 3) RW Note 1: Effective when the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow), these bits can be set to "0" or "1" . Note 2: The port direction bit for the TBiIN pin must be set to "0" (input mode). Figure 1.13.19 TBiMR Register in Event Counter Mode Rev.1.00 2003.05.30 page 123 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer B 3. Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal. Table 1.13.8 lists specifications in pulse period and pulse width measurement mode. Figure 1.13.20 shows TBiMR register in pulse period and pulse width measurement mode. Figure 1.13.21 shows the operation timing when measuring a pulse period. Figure 1.13.22 shows the operation timing when measuring a pulse width. Table 1.13.8 Specifications in Pulse Period and Pulse Width Measurement Mode Item Count source Count operation Specification f1, f2, f8, f32, fC32 * Up-count * Counter value is transferred to reload register at an effective edge of measurement pulse. The counter value is set to "000016" to continue counting. Count start condition Set TBiS bit (Note 1) to "1" (start counting) Count stop condition Set TBiS bit to "0" (stop counting) Interrupt request generation timing * When an effective edge of measurement pulse is input (Note 2) * Timer overflow. When an overflow occurs, the MR3 bit of TBiMR register is set to "1" (overflow) simultaneously. The MR3 bit is set to "0" (no overflow) by writing to TBiMR register at the next count timing or later after the MR3 bit was set to "1". At this time, make sure TBiS bit is set to "1" (start counting). TBiIN pin function Measurement pulse input Read from timer Contents of the reload register (measurement result) can be read by reading TBi register (Note 3) Write to timer Value written to TBi register is written to neither reload register nor counter i = 0 to 5 Note 1: The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits are assigned to the TBSR register bit 5 to bit 7. Note 2: Interrupt request is not generated when the first effective edge is input after the timer started counting. Note 3: Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting. Rev.1.00 2003.05.30 page 124 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer B Timer Bi mode register (i = 0 to 5) b7 b6 b5 b4 b3 b2 b1 Symbol TB0MR to TB2MR TB3MR to TB5MR b0 1 0 Bit symbol TMOD0 TMOD1 Address 039B16 to 039D16 01DB16 to 01DD16 Bit name After reset 00XX00002 00XX00002 Function b1 b0 Operation mode select bit 1 0 : Pulse period / pulse width measurement mode RW RW RW b3 b2 MR0 Measurement mode select bit MR1 MR2 MR3 0 0 : Pulse period measurement (Measurement between a falling edge and the next falling edge of measured pulse) 0 1 : Pulse period measurement (Measurement between a rising edge and the next rising edge of measured pulse) 1 0 : Pulse width measurement (Measurement between a falling edge and the next rising edge of measured pulse and between a rising edge and the next falling edge) 1 1 : Must not be set. TB0MR and TB3MR registers Set to "0" in pulse period and pulse width measurement mode TB1MR, TB2MR, TB4MR, TB5MR registers Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Timer Bi overflow 0 : Timer did not overflow flag ( Note) 1 : Timer has overflown RW RW RW RO b7 b6 TCK0 TCK1 Count source select bit 0 0 : f1 or f2 0 1 : f8 1 0 : f32 1 1 : fC32 RW RW Note: This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is set to "0" (no overflow) by writing to the TBiMR register at the next count timing or later after the MR3 bit was set to "1" (overflow). The MR3 bit cannot be set to "1" in a program. The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits are assigned to the TBSR register's bit 5 to bit 7. Figure 1.13.20 TBiMR Register in Pulse Period and Pulse Width Measurement Mode Rev.1.00 2003.05.30 page 125 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Timer B Count source Measurement pulse Reload register transfer timing "H" "L" Transfer (indeterminate value) Transfer (measured value) counter (Note 1) (Note 1) (Note 2) Timing at which counter reaches "000016" "1" TBiS bit "0" TBiIC register's IR bit "1" TBiMR register's MR3 bit "1" "0" Set to "0" upon accepting an interrupt request or by writing in program "0" The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits are assigned to the TBSR register's bit 5 to bit 7. i = 0 to 5 Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflown. Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are "002" (measure the interval from falling edge to falling edge of the measurement pulse). Figure 1.13.21 Operation Timing When Measuring Pulse Period Count source Measurement pulse Reload register transfer timing "H" "L" counter Transfer (indeterminate value) (Note 1) Transfer (measured value) (Note 1) Transfer (measured value) (Note 1) Transfer (measured value) (Note 1) (Note 2) Timing at which counter reaches "000016" "1" TBiS bit "0" "1" TBiIC register's IR bit "0" "1" TBiMR register's MR3 bit Set to "0" upon accepting an interrupt request or by writing in program "0" The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits are assigned to the TBSR register's bit 5 to bit 7. i = 0 to 5 Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflown. Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are "102" (measure the interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the measurement pulse). Figure 1.13.22 Operation Timing When Measuring Pulse Width Rev.1.00 2003.05.30 page 126 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Three-phase Motor Control Timer Function Three-phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 1.14.1 lists the specifications of the three-phase motor control timer function. Figure 1.14.1 shows the block diagram for three-phase motor control timer function. Also, the related registers are shown on Figures 1.14.2 to 1.14.8. Table 1.14.1 Three-phase Motor Control Timer Function Specifications Item Specification ___ ___ ___ Three-phase waveform output pin Six pins (U, U, V, V, W, W) _______ Forced cutoff input (Note) Input "L" to NMI pin Used Timers Timer A4, A1, A2 (used in the one-shot timer mode) ___ * Timer A4: U- and ___ U-phase waveform control * Timer A1: V- and V-phase waveform control ___ * Timer A2: W- and W-phase waveform control Timer B2 (used in the timer mode) * Carrier wave cycle control Dead time timer (3 eight-bit timer and shared reload register) * Dead time control Output waveform Triangular wave modulation, Sawtooth wave modification * Enable to output "H" or "L" for one cycle * Enable to set positive-phase level and negative-phase level respectively Carrier wave cycle Triangular wave modulation: count source (m+1) 2 Sawtooth wave modulation: count source (m+1) m: Setting value of TB2 register, 0 to 65535 Count source: f1, f2, f8, f32, fC32 Three-phase PWM output width Triangular wave modulation: count source n 2 Sawtooth wave modulation: count source n n: Setting value of TA4, TA1 and TA2 registers (of TA4, TA41, TA1, TA11, TA2 and TA21 registers when setting the INV11 bit to "1"), 1 to 65535 Count source: f1, f2, f8, f32, fC32 Dead time Count source p, or no dead time p: Setting value of DTT register, 1 to 255 Count source: f1, f2, f1 divided by 2, f2 divided by 2 Active level Enable to select "H" or "L" Positive and negative-phase concurrent Positive and negative-phases concurrent active disable function active disable function Positive and negative-phases concurrent active detect function Interrupt frequency For Timer B2 interrupt, select a carrier wave cycle-to-cycle basis through 15 times carrier wave cycle-to-cycle basis _______ Note: Forced cutoff with NMI input is_______ effective when the IVPCR1 bit of TB2SC register is_______ set to "1" (threephase output forcible cutoff by NMI input enabled). If an "L" signal is applied to the NMI pin when the IVPCR1 bit is "1", the related pins go to a high-impedance state regardless of which functions of those pins are being used. Related pins: * P72/CLK2/TA1OUT/V _________ _________ ___ * P73/CTS2/RTS2/TA1IN/V * P74/TA2OUT/W ____ * P75/TA2IN/W * P80/TA4OUT___/U * P81/TA4IN/U Rev.1.00 2003.05.30 page 127 Rev.1.00 2003.05.30 page 128 T Q INV11 (One-shot timer mode) Timer A4 counter Reload Figure 1.14.1 Three-phase Motor Control Timer Function Block Diagram T Q INV11 (One-shot timer mode) Timer A 1 counter T Q INV11 (One-shot timer mode) Timer A 2 counter Reload TA21 register TA11 register 1 INV06 INV06 Timer A4 one-shot pulse Trigger Trigger D Q T Trigger W phase output control circuit Trigger U phase output signal Three-phase output shift register (U phase) W phase output signal W phase output signal Dead time timer n = 1 to 255 V phase output signal V phase output signal INV04 INV05 RESET NMI Reverse control Reverse control Reverse control Reverse control Reverse control Reverse control INV14 R INV03 D Q W W V V U U Diagram for switching to P80, P81 and P72 to P75 is not shown. D Q T D Q T T D Q T D Q T D Q D Q T Timer B2 interrupt request bit U phase output signal Dead time timer n = 1 to 255 DUB0 bit D Q T DU0 bit V phase output control circuit Trigger Trigger D Q T DUB1 bit D Q T DU1 bit Dead time timer n = 1 to 255 Reload register n = 1 to 255 ICTB2 counter n = 1 to 15 Interrupt occurrence set circuit U phase output control circuit INV12 0 1 Note : If the INV06 bit = 0 (triangular wave modulation mode), a transfer trigger is generated at only the first occurrence of a timer B2 underflow after writing to the IDB0 and IDB1 registers. Set to "0" when TA2S bit = 0 Trigger TA2 register Set to "0" when TA1S bit = 0 Trigger Reload TA41 register INV06 1/2 Transfer trigger (Note) f1 0 INV01 INV11 ICTB2 register n = 1 to 15 M16C/6N4 Group TA1 register Set to "0" when TA4S bit = 0 Trigger TA4 register INV07 Timer A4 reload control signal Timer Ai (i = 1, 2, 4) start trigger signal (Timer mode) Timer B2 Signal to be written to timer B2 INV10 Timer B2 underflow INV00 INV13 Under development This document is under development and its contents are subject to change. Three-phase Motor Control Timer Function Under development This document is under development and its contents are subject to change. M16C/6N4 Group Three-phase Motor Control Timer Function Three-phase PWM control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset INVC0 01C816 0016 Bit symbol INV00 Bit name Effective interrupt output polarity select bit (Note 2) Description RW 0: ICTB2 counter incremented by 1 at odd-numbered occurrences of a timer B2 underflow 1: ICTB2 counter incremented by 1 at even-numbered occurrences of a timer B2 underflow RW INV01 Effective interrupt output specification bit (Notes 2, 3) 0: ICTB2 counter incremented by 1 at a timer B2 underflow 1: Selected by INV00 bit RW INV02 Mode select bit (Note 4) 0: Three-phase motor control timer function unused (Note 5) 1: Three-phase motor control timer function RW INV03 Output control bit (Note 6) 0: Three-phase motor control timer output disabled (Note 5) 1: Three-phase motor control timer output enabled RW INV04 Positive and negative phases concurrent output disable bit 0: Simultaneous active output enabled 1: Simultaneous active output disabled RW INV05 Positive and negative phases concurrent output detect flag 0: Not detected yet 1: Already detected (Note 7) RW INV06 0: Triangular wave modulation mode Modulation mode select (Note 8) 1: Sawtooth wave modulation mode (Note 9) bit RW INV07 Software trigger select bit Setting this bit to "1" generates a transfer trigger. If the INV06 bit is "1", a trigger for the dead time timer is also generated. The value of this bit when read is "0". RW Note 1: Write to this register after setting the PRC1 bit of PRCR register to "1" (write enable). Note also that INV00 to INV02, INV04 and INV06 bits can only be rewritten when timers A1, A2, A4 and B2 are idle. Note 2: Effective when the INV11 bit is "1" (three-phase mode 1). If INV11 is "0" (three-phase mode 0), the ICTB2 counter is incremented by "1" each time the timer B2 underflows, regardless of whether the INV00 and INV01 bits are set. Note 3: If this bit needs to be set to "1", set any value in the ICTB2 register before writing to it. Note 4: Setting the INV02 bit to "1" activates the dead time timer, U/V/W-phase output control circuits and ICTB2 counter. Note 5: All of the U, U, V, V, W and W pins are placed in the high-impedance state by setting the INV02 bit to 1 (three-phase motor control timer function) and setting the INV03 bit to "0" (three-phase motor control timer output disable). Note 6: The INV03 bit is set to "0" in the following cases: When reset When positive and negative go active simultaneously while INV04 bit is "1" When set to "0" in a program When input on the NMI pin changes state from "H" to "L" (The INV03 bit cannot be set to "1" when NMI input is "L".) Note 7: Can only be set by writing "0" in a program, and cannot be set to "1". Note 8: The effects of the INV06 bit are described in the table below. Item Mode INV06 = 0 INV06 = 1 Sawtooth wave modulation mode Timing at which transferred from IDB0 to IDB1 registers to three-phase output shift register Triangular wave modulation mode Transferred only once synchronously with the transfer trigger after writing to the IDB0 to IDB1 registers Timing at which dead time timer trigger is generated when INV16 bit is "0" Synchronous with the falling edge of timer A1, A2, or A4 one-shot pulse Synchronous with the transfer trigger and the falling edge of timer A1, A2, or A4 one-shot pulse INV13 bit Effective when INV11 is "1" and INV06 is "0" Has no effect Transferred every transfer trigger Transfer trigger: Timer B2 underflow, write to the INV07 bit or write to the TB2 register when INV10 is "1" Note 9: If the INV06 bit is "1", set the INV11 bit to "0" (three-phase mode 0) and set the PWCON bit to "0" (timer B2 reloaded by a timer B2 underflow). Figure 1.14.2 INVC0 Register Rev.1.00 2003.05.30 page 129 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Three-phase Motor Control Timer Function Three-phase PWM control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset INVC1 01C916 0016 Bit symbol Bit name 0 Description RW 0: Timer B2 underflow 1: Timer B2 underflow and write to the TB2 register INV10 Timer A1, A2, A4 start trigger signal select bit INV11 Timer A1-1, A2-1, A4-1 control bit (Note 2) INV12 Dead time timer count source select bit 0 : f1 or f2 1 : f1 divided by 2 or f2 divided by 2 RW INV13 Carrier wave detect flag (Note 4) 0: Timer A output at even-numbered occurrences (TA11, TA21, TA41 register value counted) 1: Timer A output at odd-numbered occurrences (TA1, TA2, TA4 register value counted) RO INV14 Output polarity control bit 0 : Output waveform "L" active 1 : Output waveform "H" active RW INV15 Dead time invalid bit 0: Dead time timer enabled 1: Dead time timer disabled RW INV16 Dead time timer trigger select bit 0: Falling edge of timer A4, A1 or A2 one-shot pulse (Note 5) 1: Rising edge of three-phase output shift register (U, V or W phase) output RW Reserved bit Set to "0" RW (b7) 0: Three-phase mode 0 1: Three-phase mode 1 (Note 3) RW RW Note 1: Write to this register after setting the PRC1 bit of PRCR register to "1" (write enable). Note also that this register can only be rewritten when timers A1, A2, A4 and B2 are idle. Note 2: The effects of the INV11 bit are described in the table below. Item INV11 = 1 INV11 = 0 Mode Three-phase mode 0 Three-phase mode 1 TA11, TA21, TA41 registers Not used Used INV00 bit, INV01 bit Has no effect. ICTB2 counted every time Effect timer B2 underflows regardless of whether the INV00 to INV01 bits are set. Effective when INV11 bit is "1" and Has no effect INV06 bit is "0" INV13 bit Note 3: If the INV06 bit is "1" (sawtooth wave modulation mode), set this bit to "0" (three-phase mode 0). Also, if the INV11 bit is "0", set the PWCON bit to "0" (timer B2 reloaded by a timer B2 underflow). Note 4: The INV13 bit is effective only when the INV06 bit is "0" (triangular wave modulation mode) and the INV11 bit is "1" (three-phase mode 1). Note 5: If all of the following conditions hold true, set the INV16 bit to "1" (dead time timer triggered by the rising edge of three-phase output shift register output). The INV15 bit is "0" (dead time timer enabled) When the INV03 bit is set to "1" (three-phase motor control timer output enabled), the Dij bit and DiBj bit (i: U, V, or W, j: 0, 1) have always different values (the positive-phase and negative-phase always output different levels during the period other than dead time). Conversely, if either one of the above conditions holds false, set the INV16 bit to "0" (dead time timer triggered by the falling edge of one-shot timer pulse). Figure 1.14.3 INVC1 Register Rev.1.00 2003.05.30 page 130 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Three-phase Motor Control Timer Function Three-phase output buffer register i (i = 0, 1) (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol IDB0 IDB1 Bit Symbol Address 01CA16 01CB16 After reset 0016 0016 Bit name Function RW DUi U phase output buffer i DUBi U phase output buffer i DVi V phase output buffer i DVBi V phase output buffer i DWi W phase output buffer i RW DWBi W phase output buffer i RW (b7-b6) Nothing is assigned. When write, set to "0". When read, its content is "0". Write the output level 0: Active level 1: Inactive level When read, these bits show the three-phase output shift register value. RW RW RW RW Note: The IDB0 and IDB1 register values are transferred to the three-phase output shift register by a transfer trigger. The value written to the IDB0 register after a transfer trigger generates the output signal of each phase, and the next value written to the IDB1 register at the falling edge of the timer A1, A2 or A4 one-shot pulse represents the output signal of each phase. Dead time timer (Notes 1, 2) b7 b0 Symbol DTT Address 01CC16 After reset Indeterminate Function Assuming the set value = n, upon a start trigger the timer starts counting the count source selected by the INV12 bit and stops after counting it n times. The positive or negative phase whichever is going from an inactive to an active level changes at the same time the dead time timer stops. Setting range RW 1 to 255 WO Note 1: Use MOV instruction to write to this register. Note 2: Effective when the INV15 bit is "0" (dead time timer enabled). If the INV15 bit is "1", the dead time timer is disabled and has no effect. Figure 1.14.4 IDB0 Register, IDB1 Register and DTT Register Rev.1.00 2003.05.30 page 131 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Three-phase Motor Control Timer Function Timer Ai, Ai-1 register (i = 1, 2, 4) (Notes 1 to 6) (b15) b7 (b8) b0 b7 b0 Symbol TA1 TA2 TA4 TA11 (Note 7) TA21 (Note 7) TA41 (Note 7) Address 038916-038816 038B16-038A16 038F16-038E16 01C316-01C216 01C516-01C416 01C716-01C616 After reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Function Setting range Assuming the set value = n, upon a start trigger the timer starts counting the count source and stops after counting it n times. The positive and negative phases change at the same time timer A1, A2 or A4 stops. 000016 to FFFF16 RW WO Note 1: The register must be accessed in 16-bit unit. Note 2: When these registers are set to "000016", the counter does not operate and a timer Ai interrupt does not occur. Note 3: Use MOV instruction to write to these registers. Note 4: If the INV15 bit is "0" (dead time timer enabled), the positive or negative phase whichever is going from an inactive to an active level changes at the same time the dead time timer stops. Note 5: If the INV11 bit is "0" (three-phase mode 0), the TAi register value is transferred to the reload register by a timer Ai (i = 1, 2 or 4) start trigger. If the INV11 bit is "1" (three-phase mode 1), the TAi1 register value is transferred to the reload register by a timer Ai start trigger first and then the TAi register value is transferred to the reload register by the next timer Ai start trigger. Thereafter, the TAi1 register and TAi register values are transferred to the reload register alternately. Note 6: Do not write to these registers synchronously with a timer B2 underflow. Note 7: Write to TAi1 register as follows: (1) Write a value to the TAi1 register. (2) Wait for one cycle of timer Ai count source. (3) Write the same value to the TAi1 register again. Timer B2 register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TB2 Address 039516 -039416 Function Divide the count source by n + 1 where n = set value. Timer A1, A2 and A4 are started at every occurrence of underflow. After reset Indeterminate Setting range 000016 to FFFF16 Note: The register must be accessed in 16-bit unit. Figure 1.14.5 TA1, TA2, TA4, TA11, TA21 and TA41 Registers, and TB2 Register Rev.1.00 2003.05.30 page 132 RW RW Under development This document is under development and its contents are subject to change. M16C/6N4 Group Three-phase Motor Control Timer Function Timer B2 interrupt occurrences frequency set counter b7 b0 Symbol ICTB2 Address 01CD16 After reset Indeterminate Setting range Function If the INV01 bit is "0" (ICTB2 counter counted every time timer B2 underflows), assuming the set value = n, a timer B2 interrupt is generated at every n'th occurrence of a timer B2 underflow. If the INV01 bit is "1" (ICTB2 counter count timing selected by the INV00 bit), assuming the set value = n, a timer B2 interrupt is generated at every n'th occurrence of a timer B2 underflow that meets the condition selected by the INV00 bit. (Note) RW 1 to 15 WO Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Note: Use MOV instruction to write to this register. If the INV01 bit = 1, make sure the TB2S bit also = 0 (timer B2 count stopped) when writing to this register. If the INV01 bit = 0, although this register can be written even when the TB2S bit = 1 (timer B2 count start), do not write synchronously with a timer B2 underflow Timer B2 special mode register (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TB2SC Bit symbol Address 039E16 After reset XXXXXX002 Bit name Function RW Timer B2 reload timing switching bit 0 : Timer B2 underflow RW 1 : Timer A output at odd-numbered (Note 2) occurrences IVPCR1 Three-phase output port NMI control bit 1 (Note 3) 0 : Three-phase output forcible cutoff by NMI input (high-impedance) disabled 1 : Three-phase output forcible cutoff by NMI input (high-impedance) enabled (b7-b2) Nothing is assigned. When write, set to "0". When read, its content is "0". PWCOM RW Note 1: Write to this register after setting the PRC1 bit of PRCR register to "1" (write enabled). Note 2: If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (sawtooh wave modulation mode), set this bit to "0" (timer B2 underflow). Note 3: Related pins are U(P80/TA4OUT), U(P81/TA4IN), V(P72/CLK2/TA1OUT), V(P73/CTS2/RTS2/TA1IN), W(P74/TA2OUT), W(P75/TA2IN). If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1, the target pins go to a high-impedance state regardless of which functions of those pins are being used. After forced interrupt (cutoff), input "H" to the NMI pin and set IVPCR1 bit to "0": this forced cutoff will be reset. Figure 1.14.6 ICTB2 Register and TB2SC Register Rev.1.00 2003.05.30 page 133 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Three-phase Motor Control Timer Function Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Bit symbol TA1TGL Address 038316 After reset 0016 Bit name Timer A1 event/trigger select bit Function To use the V-phase output control circuit, set these bits to "012" (TB2 underflow). RW RW RW TA1TGH TA2TGL Timer A2 event/trigger select bit To use the W-phase output control circuit, set these bits to "012" (TB2 underflow). TA2TGH RW RW b5 b4 TA3TGL Timer A3 event/trigger select bit TA3TGH TA4TGL Timer A4 event/trigger select bit 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 is selected 1 0 : TA2 is selected 1 1 : TA4 is selected To use the U-phase output control circuit, set these bits to "012" (TB2 underflow). TA4TGH RW RW RW RW Note: Set the corresponding port direction bit to "0" (input mode). Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Bit symbol Address 038016 Bit name 2003.05.30 page 134 Function RW TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S Timer A2 count start flag RW TA3S Timer A3 count start flag RW TA4S Timer A4 count start flag RW TB0S Timer B0 count start flag RW TB1S Timer B1 count start flag RW TB2S Timer B2 count start flag RW Figure 1.14.7 TRGSR Register and TRBSR Register Rev.1.00 After reset 0016 0 : Stops counting 1 : Starts counting RW RW Under development This document is under development and its contents are subject to change. M16C/6N4 Group Three-phase Motor Control Timer Function Timer Ai mode register (i = 1, 2, 4) Symbol TA1MR TA2MR TA4MR b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 0 Address 039716 039816 039A16 Bit symbol After reset 0016 0016 0016 Bit name TMOD0 Function RW Operation mode select bit RW Set to "102" (one-shot timer mode) for the three-phase motor control timer function RW MR0 Pulse output function select bit Set to "0" for the three-phase motor control timer function RW MR1 External trigger select bit Has no effect for the three-phase motor control timer function RW MR2 Trigger select bit Set to "1" (selected by TRGSR register) for the three-phase motor control timer function RW MR3 Set to "0" for the three-phase motor control timer function TMOD1 b7 b6 TCK0 Count source select bit TCK1 RW RW 0 0 : f1 or f2 0 1 : f8 1 0 : f32 1 1 : fC32 RW Timer B2 mode register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol TB2MR Bit symbol TMOD0 TMOD1 Address 039D16 After reset 00XX00002 Bit name Function RW Operation mode select bit Set to "002" (timer mode) for the three-phase motor control timer function RW Has no effect for the three-phase motor control timer function . When write, set to "0". When read, its content is indeterminate . RW MR1 MR2 Set to "0" for the three-phase motor control timer function RW MR3 When write in the three-phase motor control timer function, write "0". When read, its content is indeterminate. RO MR0 b7 b6 TCK0 Count source select bit TCK1 0 0 : f1 or f2 0 1 : f8 1 0 : f32 1 1 : fC32 Figure 1.14.8 TA1MR, TA2MR and TA4MR Registers, and TB2MR Register Rev.1.00 2003.05.30 page 135 RW RW RW RW Under development This document is under development and its contents are subject to change. M16C/6N4 Group Three-phase Motor Control Timer Function The three-phase motor control timer function is enabled by setting the INV02 bit of INVC0 register to "1". When this function is selected, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are __ ___ ___ used to control three-phase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a dedicated dead-time timer. Figure 1.14.9 shows the example of triangular modulation waveform and Figure 1.14.10 shows the example of sawtooth modulation waveform. Carrier wave: triangular waveform Carrier wave Signal wave TB2S bit of the TABSR register Timer B2 Start trigger signal for timer A4* m Timer A4 one-shot pulse* m n p n p Rewriting IDB0, IDB1 registers U phase output signal * Transfer to three-phase output shift register U phase output signal * INV14 = 0 ("L" active) U phase U phase Dead time INV14 = 1 ("H" active) U phase Dead time U phase INV13 (INV11 = 1 (three-phase mode 1)) * Internal signals. See the block diagram of the three-phase motor control timer function. Shown here is a typical waveform for the case where INVC0 = 00XX11XX2 (X = set as suitable for the system) and INVC1 = 010XXXX02. An example for changing PWM outputs is shown below. (1)When INV11 = 1 (three-phase mode 1) (2)When INV11 = 0 (three-phase mode 0) INV01 = 0, ICTB2 = 216 (timer B2 interrupt is generated at every INV01 = 0, ICTB2 = 116 (timer B2 interrupt is generated at every occurrence 2'th occurrence of a timer B2 underflow), or INV01 = 1, INV00 = 1, of a timer B2 underflow) ICTB2=116(timer B2 interrupt is generated at even-numbered Initial timer value: TA4 = m. The TA4 register is modified each time occurrences of a timer B2 underflow). a timer B2 interrupt occurs. First time, TA4 = m. Second time, TA4 = n. Initial timer value: TA41 = m, TA4 = m. The TA4 and TA41 registers Third time, TA4 = n. Fourth time, TA4 = p. Fifth time, TA4 = p. are modified every time a timer B2 interrupt occurs. First time, Initial values of IDB0 and IDB1 registers: DU0 = 1, DUB0 = 0, DU1 = 0, TA41 = n, TA4 = n. Second time, TA41 = p, TA4 = p. DUB1 = 1. The register values are changed to DU0 = 1, DUB0 = 0, DU1= 1 Initial values of IDB0 and IDB1 registers: DU0 = 1, DUB0 = 0, and DUB1 = 0 the sixth time a timer B2 interrupt occurs. DU1 = 0, DUB1 = 1.The register values are changed to DU0 = 1, DUB0 = 0, DU1= 1 and DUB1 = 0 the third time a timer B2 interrupt occurs. The value written to the TA4 register and TA41 register are inverted at odd-numbered timer A outputs. Figure 1.14.9 Triangular Wave Modulation Operation Rev.1.00 2003.05.30 page 136 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Three-phase Motor Control Timer Function Carrier wave: sawtooth waveform Carrier wave Signal wave Timer B2 Start trigger signal for timer A4* Timer A4 one-shot pulse* Rewriting IDB0, IDB1 registers Transfer to three-phase output shift register U phase output signal * U phase output signal * INV14 = 0 ("L" active) U phase Dead time U phase INV14 = 1 ("H" active) U phase Dead time U phase * Internal signals. See the block diagram of the three-phase motor control timer function. Shown here is a typical waveform for the case where INVC0 = 01XX110X2 (X = set as suitable for the system) and INVC1 = 010XXX002. An example for changing PWM outputs is shown below. Initial values of IDB0 and IDB1 registers: DU0 = 0, DUB0 = 1, DU1 = 1, DUB1 = 1. The register values are changed to DU0 = 1, DUB0 = 0, DU1 = 1, DUB1 = 1 a timer B2 interrupt occurs. Figure 1.14.10 Sawtooth Wave Modulation Operation Rev.1.00 2003.05.30 page 137 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O Serial I/O Serial I/O is configured with four channels: UART0 to UART2 and SI/O3. UARTi (i = 0 to 2) Each UARTi has an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.15.1 shows the block diagram of UARTi. Figures 1.15.2 shows the block diagram of the UARTi transmit/receive. UARTi has the following modes: * Clock synchronous serial I/O mode * Clock asynchronous serial I/O mode (UART mode). 2 * Special mode 1 (I C mode) * Special mode 2 * Special mode 3 (Bus collision detection function, IE mode) : UART0, UART1 * Special mode 4 (SIM mode) : UART2 Figures 1.15.3 to 1.15.8 show the UARTi-related registers. Refer to tables listing each mode for register setting. Rev.1.00 2003.05.30 page 138 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O 1/2 f2SIO PCLK1=0 f1SIO or f2SIO f1SIO Main clock, PLL clock, or ring oscillator clock PCLK1=1 1/8 f8SIO 1/4 (UART0) f32SIO TxD polarity reversing circuit RxD polarity reversing circuit RxD0 Clock source selection f1SIO or f2SIO f8SIO f32SIO UART reception 1/16 CLK1 to CLK0 002 Internal CKDIR=0 012 102 Reception control circuit Clock synchronous type U0BRG register 1 / (n0+1) 1/16 UART transmission Transmission control Clock synchronous circuit type Clock synchronous type (when internal clock is selected) 1/2 CKDIR=0 Clock synchronous type (when external clock is selected) CKDIR=1 Clock synchronous type (when internal clock is selected) External TxD0 Receive clock Transmit clock Transmit/ receive unit CKDIR=1 CKPOL CLK polarity reversing circuit CLK0 CTS/RTS selected CRS=1 CTS0 / RTS0 CTS/RTS disabled RTS0 "H" CRS=0 CTS/RTS disabled CRD=1 RCSP=0 CTS0 CRD=0 CTS0 from UART1 RCSP=1 (UART1) Clock source selection CLK1 to CLK0 002 f1SIO or f2SIO Internal CKDIR=0 012 f8SIO 102 f32SIO External UART reception 1/16 1 / (n1+1) 1/16 Transmission control circuit Clock synchronous type CLKMD0=0 Clock output pin select CLKMD1=1 CTS1 / RTS1/ CTS0/ CLKS1 UART transmission CKDIR=1 CLK polarity reversing circuit CLK1 Reception control circuit Clock synchronous type U1BRG register CKPOL TxD1 Receive clock Transmit/ receive unit Transmit clock Clock synchronous type 1/2 (when internal clock is selected) CKDIR=0 Clock synchronous type (when external clock is selected) CKDIR=1 Clock synchronous type (when internal clock is selected) CLKMD0=1 CTS/RTS selected CRS=1 CLKMD1=0 CRS=0 CTS/RTS disabled RTS1 "H" CTS/RTS disabled RCSP=0 CRD=1 CTS1 CRD=0 CTS0 from UART0 RCSP=1 (UART2) Clock source selection CLK1 to CLK0 002 f1SIO or f2SIO 012 Internal CKDIR=0 f8SIO 102 f32SIO External CKPOL CLK2 CLK polarity reversing circuit CTS/RTS selected CRS=1 CTS2 / RTS2 CRS=0 1/16 1 / (n2+1) 1/16 CKDIR=1 Clock synchronous type 1/2 (when internal clock is selected) CKDIR=0 Clock synchronous type (when external clock is selected) CKDIR=1 Clock synchronous type (when internal clock is selected) CTS/RTS disabled RTS2 "H" i = 0 to 2 ni: Values set to the UiBRG register SMD2 to SMD0, CKDIR: UiMR register's bits CLK1 to CLK0, CKPOL, CRD, CRS: UiC0 register's bits CLKMD0, CLKMD1, RCSP: UCON register's bits Figure 1.15.1 UARTi Block Diagram Reception control circuit UART transmission Clock synchronous type CRD=0 page 139 UART reception Clock synchronous type U2BRG register CTS/RTS disabled CRD=1 2003.05.30 TxD polarity reversing circuit RxD polarity reversing circuit RxD2 Rev.1.00 TxD polarity reversing circuit RxD polarity reversing circuit RxD1 CTS2 Transmission control circuit Receive clock Transmit clock Transmit/ receive unit TxD2 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O No reverse IOPOL=0 RxD data reverse circuit RxDi Reverse IOPOL=1 Clock synchronous type 1SP PAR disabled STPS= 0 PRYE=0 SP 2SP SP UARTi receive register UART(7 bits) PAR PRYE=1 PAR enabled STPS= 1 0 UART (7 bits) UART (8 bits) Clock synchronous type 0 0 0 UART 0 Clock synchronous type UART (9 bits) 0 0 UART (8 bits) UART (9 bits) D8 D7 D6 D5 D4 D3 D2 D1 D0 UiRB register Logic reverse circuit + MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits Logic reverse circuit + MSB/LSB conversion circuit D7 D8 UART (9 bits) D6 D5 D4 D3 D2 D1 D0 UiTB register UART (8 bits) UART (9 bits) Clock synchronous type PAR 2SP STPS= 1 enabled PRYE=1 UART SP SP PAR STPS =0 1SP PRYE=0 PAR disabled "0" Clock synchronous type UART (7 bits) UART (8 bits) UARTi transmit register UART(7 bits) Clock synchronous type Error signal output disable i=0 to 2 SP: Stop bit PAR: Parity bit SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: UiMR register's bits UiERE: UiC1 register's bit Figure 1.15.2 UARTi Transmit/Receive Unit Rev.1.00 2003.05.30 page 140 UiERE=1 No reverse IOPOL=0 UiERE=0 Error signal output circuit Error signal output enable IOPOL=1 TxD data reverse circuit Reverse TxDi Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O UARTi transmit buffer register (i = 0 to 2)(Note) (b8) b0 b7 (b15) b7 b0 Symbol U0TB U1TB U2TB Address 03A316-03A216 03AB16-03AA16 01FB16-01FA16 After reset Indeterminate Indeterminate Indeterminate Function RW WO Transmit data Nothing is assigned. When write, set to "0". When read, their contents are indeterminate. . Note: Use MOV instruction to write to this register. UARTi receive buffer register (i = 0 to 2) (b15) b7 (b8) b0 b7 Symbol U0RB U1RB U2RB b0 Bit symbol Address 03A716-03A616 03AF16-03AE16 01FF16-01FE16 After reset Indeterminate Indeterminate Indeterminate Function Bit name (b7-b0) (b8) RW Receive data (D7 to D0) RO Receive data (D8) RO Nothing is assigned When write, set to "0". (b10-b9) When read, their contents are indeterminate. . ABT Arbitration lost detecting flag (Note 1) OER 0 : No overrun error Overrun error flag (Note 2) 1 : Overrun error found FER Framing error flag (Note 2) 0 : No framing error 1 : Framing error found RO PER Parity error flag (Note 2) 0 : No parity error 1 : Parity error found RO SUM Error sum flag (Note 2) 0 : No error 1 : Error found RO 0 : Not detected 1 : Detected RW RO Note 1: The ABT bit is set to "0" by writing "0" in a program. (Writing "1" has no effect.) Note 2: When the UiMR register's SMD2 to SMD0 bits = 0002 (serial I/O disabled) or the UiC1 register's RE bit = 0 (reception disabled), all of the SUM, PER, FER and OER bits are set to "0" (no error). The SUM bit is set to "0" (no error) when all of the PER, FER and OER bits are = 0 (no error). Also, the PER and FER bits are set to "0" by reading the lower byte of the UiRB register. UARTi bit rate generator (i = 0 to 2)(Notes 1, 2) b7 b0 Symbol U0BRG U1BRG U2BRG Address 03A116 03A916 01F916 After reset Indeterminate Indeterminate Indeterminate Function Setting range RW Assuming that set value = n, UiBRG divides the count source by n + 1 0016 to FF16 WO Note 1: Write to this register while serial I/O is neither transmitting nor receiving. Note 2: Use MOV instruction to write to this register. Figure 1.15.3 U0TB to U2TB Registers, U0RB to U2RB Registers, and U0BRG to U2BRG Registers Rev.1.00 2003.05.30 page 141 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O UARTi transmit/receive mode register (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0MR to U2MR Bit symbol SMD0 Address 03A016, 03A816, 01F816 After reset 0016 Function Bit name Serial I/O mode select bit (Note 1) SMD1 SMD2 RW b2 b1 b0 RW 0 0 0 : Serial I/O disabled 0 0 1 : Clock synchronous serial I/O mode (Note 2) 0 1 0 : I2C mode 1 0 0 : UART mode transfer data 7-bit long 1 0 1 : UART mode transfer data 8-bit long 1 1 0 : UART mode transfer data 9-bit long Must not be set except above RW RW CKDIR Internal/external clock select bit 0 : Internal clock 1 : External clock (Note 3) RW STPS Stop bit length select bit 0 : One stop bit 1 : Two stop bits RW PRY Odd/even parity select bit 0 : Odd parity 1 : Even parity PRYE Parity enable bit 0 : Parity disabled 1 : Parity enabled RW IOPOL TxD, RxD I/O polarity reverse bit 0 : No reverse 1 : Reverse RW Effective when PRYE = 1 RW Note 1: To receive data, set the corresponding port direction bit for each RxDi pin to "0" (input mode). Note 2: Set the corresponding port direction bit for SCL and SDA pins to "0" (input mode). Note 3: Set the corresponding port direction bit for each CLKi pin to "0" (input mode). UARTi transmit/receive control register 0 (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0C0 to U2C0 Bit symbol Address After reset 03A416, 03AC16, 01FC16 000010002 Bit name Function RW b1 b0 CLK0 BRG count source select bit 0 0 : f1SIO or f2SIO is selected 0 1 : f8SIO is selected 1 0 : f32SIO is selected 1 1 : Must not be set CTS/RTS function select bit (Note 1) Effective when CRD = 0 0 : CTS function is selected (Note 2) 1 : RTS function is selected CLK1 CRS TXEPT 0 : Data present in transmit register (during transmission) Transmit register empty 1 : No data present in transmit register flag (transmission completed) RW RW RW RO CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60, P64 and P73 can be used as I/O ports) RW NCH Data output select bit (Note 3) 0 : TxDi/SDAi and SCLi pins are CMOS output 1 : TxDi/SDAi and SCLi pins are N channel open-drain output RW CKPOL CLK polarity select bit 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge RW UFORM Transfer format select bit 0 : LSB first (Note 4) 1 : MSB first RW Note 1: CTS1/RTS1 can be used when the UCON register's CLKMD1 bit = 0 (only CLK1 output) and the UCON register's RCSP bit = 0 (CTS0/RTS0 not separated). Note 2: Set the corresponding port direction bit for each CTSi pin to "0" (input mode). Note 3: SCL2/P71 is N channel open-drain output. Cannot be set to the CMOS output. Set the NCH bit of the U2C0 register to "0". Note 4: Effective for clock synchronous serial I/O mode and UART mode transfer data 8-bit long. Figure 1.15.4 U0MR to U2MR Registers and U0C0 to U2C0 Registers Rev.1.00 2003.05.30 page 142 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O UARTj transmit/receive control register 1 (j = 0, 1) b7 b6 b5 b4 b3 b2 b1 Symbol U0C1, U1C1 b0 Bit symbol Address 03A516,03AD16 After reset 000000102 Function Bit name RW TE Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled RW TI Transmit buffer empty flag 0 : Data present in UjTB register 1 : No data present in UjTB register RO RE Receive enable bit 0 : Reception disabled 1 : Reception enabled RW RI Receive complete flag 0 : No data present in UjRB register 1 : Data present in UjRB register RO (b5-b4) Nothing is assigned. When write, set to "0". When read, these contents are "0". UjLCH Data logic select bit 0 : No reverse 1 : Reverse RW UjERE Error signal output enable bit 0 : Output disabled 1 : Output enabled RW UART2 transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C1 Bit symbol Address 01FD16 RW Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled RW TI Transmit buffer empty flag 0 : Data present in U2TB register 1 : No data present in U2TB register RO RE Receive enable bit 0 : Reception disabled 1 : Reception enabled RW RI Receive complete flag 0 : No data present in U2RB register 1 : Data present in U2RB register RO UART2 transmit interrupt 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) cause select bit RW UART2 continuous U2RRM receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled RW U2LCH Data logic select bit 0 : No reverse 1 : Reverse RW 0 : Output disabled 1 : Output enabled RW U2ERE Error signal output enable bit Figure 1.15.5 U0C1 to U2C1 Registers 2003.05.30 Function Bit name TE U2IRS Rev.1.00 After reset 000000102 page 143 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O UART transmit/receive control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UCON Address 03B016 After reset X00000002 Bit symbol Bit name U0IRS UART0 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) RW U1IRS UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) RW U0RRM UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled RW U1RRM UART1 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled RW CLKMD0 UART1 CLK/CLKS select bit 0 Effective when CLKMD1 = 1 0 : Clock output from CLK1 1 : Clock output from CLKS1 RW CLKMD1 UART1 CLK/CLKS select bit 1 (Note) 0 : CLK output is only CLK1 1 : Transfer clock output from multiple pins function selected RW Separate UART0 CTS/RTS bit 0 : CTS/RTS shared pin 1 : CTS/RTS separated (CTS0 supplied from the P64 pin) RW RCSP Function RW Nothing is assigned. When write, set to "0". When read, its content is indeterminate. (b7) Note: When using multiple transfer clock output pins, make sure the following conditions are met: U1MR register's CKDIR bit = 0 (internal clock) UARTi special mode register (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address U0SMR to U2SMR 01EF16, 01F316, 01F716 0 Bit symbol After reset X00000002 Function Bit name RW IICM I2C mode select bit 0 : Other than I2C mode 1 : I2C mode RW ABC Arbitration lost detecting flag control bit 0 : Update per bit 1 : Update per byte RW BBS Bus busy flag 0 : STOP condition detected 1 : START condition detected (busy) (b3) Reserved bit Set to "0" RW Bus collision detect sampling clock select bit 0 : Rising edge of transfer clock 1 : Underflow signal of timer Aj (Note 2) RW Auto clear function select bit of transmit enable bit 0 : No auto clear function 1 : Auto clear at occurrence of bus collision RW Transmit start condition select bit 0 : Not synchronized to RxDi 1 : Synchronized to RxDi (Note 3) RW ABSCS ACSE SSS (b7) RW (Note1) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Note 1: The BBS bit is set to "0" by writing "0" in a program. (Writing "1" has no effect.). Note 2: Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer A0 in UART2. Note 3: When a transfer begins, the SSS bit is set to "0" (Not synchronized to RxDi). Figure 1.15.6 UCON Register and U0SMR to U2SMR Registers Rev.1.00 2003.05.30 page 144 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O UARTi special mode register 2 (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address U0SMR2 to U2SMR2 01EE16, 01F216, 01F616 Bit symbol Bit name After reset X00000002 Function RW IICM2 I 2C mode select bit 2 Refer to "Table 1.15.11 I2C Mode FUnctions" RW CSC Clock-synchronous bit 0 : Disabled 1 : Enabled RW SWC SCL wait output bit 0 : Disabled 1 : Enabled RW ALS SDA output stop bit 0 : Disabled 1 : Enabled RW STAC UARTi initialization bit 0 : Disabled 1 : Enabled RW SWC2 SCL wait output bit 2 0: Transfer clock 1: "L" output RW SDHI SDA output disable bit 0: Enabled 1: Disabled (high-impedance) RW Nothing is assigned. When write, set to "0". When read, its content is indeterminate. (b7) UARTi special mode register 3 (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR3 to U2SMR3 Bit symbol (b0) CKPH (b2) NODC (b4) Address 01ED16, 01F116, 01F516 Bit name After reset 000X0X0X2 Function RW Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Clock phase set bit 0 : Without clock delay 1 : With clock delay RW Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Clock output select bit 0 : CLKi is CMOS output 1 : CLKi is N channel open-drain output RW Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 DL0 DL1 DL2 SDAi digital delay setup bit (Notes 1, 2) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Without delay 1 : 1 to 2 cycle(s) of UiBRG count source 0 : 2 to 3 cycles of UiBRG count source 1 : 3 to 4 cycles of UiBRG count source 0 : 4 to 5 cycles of UiBRG count source 1 : 5 to 6 cycles of UiBRG count source 0 : 6 to 7 cycles of UiBRG count source 1 : 7 to 8 cycles of UiBRG count source RW RW RW Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I2C mode. In other than I2C mode, set these bits to "0002" (no delay). Note 2 : The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock, the amount of delay increases by about 100 ns. Figure 1.15.7 U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers Rev.1.00 2003.05.30 page 145 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O UARTi special mode register 4 (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR4 to U2SMR4 Bit symbol Bit name Function RW 0 : Clear 1 : Start RW Restart condition RSTAREQ generate bit (Note) 0 : Clear 1 : Start RW STPREQ Stop condition generate bit (Note) 0 : Clear 1 : Start RW STSPSEL SCL,SDA output select bit 0 : Start and stop conditions not output 1 : Start and stop conditions output RW ACKD ACK data bit 0 : ACK 1 : NACK RW ACKC ACK data output enable bit 0 : Serial I/O data output 1 : ACK data output RW SCLHI SCL output stop enable bit 0 : Disabled 1 : Enabled RW SWC9 SCL wait bit 3 0 : SCL "L" hold disabled 1 : SCL "L" hold enabled RW Note: Set to "0" when each condition is generated. Figure 1.15.8 U0SMR4 to U2SMR4 Registers 2003.05.30 After reset 0016 Start condition generate bit (Note) STAREQ Rev.1.00 Address 01EC16, 01F016, 01F416 page 146 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode) Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.15.1 lists the specifications of the clock synchronous serial I/O mode. Table 1.15.2 lists the registers used in clock synchronous serial I/O mode and the register values set. Table 1.15.1 Clock Synchronous Serial I/O Mode Specifications Item Transfer data format Transfer clock Transmission, reception control Transmission start condition Reception start condition Interrupt request generation timing Error detection Select function Specification * Transfer data length: 8 bits * UiMR register's CKDIR bit = 0 (internal clock) : fj/ 2(n+1) fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16 * CKDIR bit = 1 (external clock ) : Input from CLKi pin _______ _______ _______ _______ * Selectable from CTS function, RTS function or CTS/RTS function disabled * Before transmission can start, the following requirements must be met (Note 1) _ The TE bit of UiC1 register = 1 (transmission enabled) _ The TI bit of UiC1 register = 0 (data present in UiTB register) _______ _______ _ If CTS function is selected, input on the CTSi pin = L * Before reception can start, the following requirements must be met (Note 1) _ The RE bit of UiC1 register = 1 (reception enabled) _ The TE bit of UiC1 register = 1 (transmission enabled) _ The TI bit of UiC1 register = 0 (data present in the UiTB register) * For transmission, one of the following conditions can be selected _ The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission) _ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from the UARTi transmit register * For reception When transferring data from the UARTi receive register to the UiRB register (at completion of reception) * Overrun error (Note 3) This error occurs if the serial I/O started receiving the next data before reading the UiRB register and received the 7th bit of the next data * CLK polarity selection Transfer data input/output can be selected to occur synchronously with the rising or the falling edge of the transfer clock * LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected * Continuous receive mode selection Reception is enabled immediately by reading the UiRB register * Switching serial data logic This function reverses the logic value of the transmit/receive data * Transfer clock output from multiple pins selection (UART1) The output pin can be selected in a program from two UART1 transfer clock pins that have been set _______ _______ * Separate CTS/RTS pins (UART0) _________ _________ CTS0 and RTS0 are input/output from separate pins i = 0 to 2 Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register's CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the UiC0 register's CKPOL bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4. Note 3: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change. Rev.1.00 2003.05.30 page 147 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode) Table 1.15.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Bit Function UiTB (Note 1) 0 to 7 Set transmission data UiRB (Note 1) 0 to 7 Reception data can be read UiBRG OER Overrun error flag 0 to 7 Set a transfer rate UiMR (Note 1) SMD2 to SMD0 UiC0 Set to "0012" CKDIR Select the internal clock or external clock IOPOL Set to "0" CLK1 to CLK0 Select the count source for the UiBRG register CRS Select CTS or RTS to use TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS function NCH Select TxDi pin output mode CKPOL Select the transfer clock polarity UFORM Select the LSB first or MSB first TE Set this bit to "1" to enable transmission/reception TI Transmit buffer empty flag RE Set this bit to "1" to enable reception _______ _______ _______ UiC1 _______ RI Reception complete flag U2IRS (Note 2) Select the source of UART2 transmit interrupt U2RRM (Note 2) Set this bit to "1" to use continuous receive mode UiLCH Set this bit to "1" to use inverted data logic UiERE Set to "0" UiSMR 0 to 7 Set to "0" UiSMR2 0 to 7 Set to "0" UiSMR3 0 to 2 Set to "0" NODC Select clock output mode 4 to 7 Set to "0" UiSMR4 0 to 7 Set to "0" UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt U0RRM, U1RRM Set this bit to "1" to use continuous receive mode CLKMD0 Select the transfer clock output pin when CLKMD1 = 1 CLKMD1 Set this bit to "1" to output UART1 transfer clock from two pins RCSP Set this bit to "1" to accept as input the UART0 CTS0 signal from the P64 pin 7 Set to "0" _________ i = 0 to 2 Note 1: Not all register bits are described above. Set those bits to "0" when writing to the registers in clock synchronous serial I/O mode. Note 2: Set the U0C1 and U1C1 register bit 4 and bit 5 to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register. Rev.1.00 2003.05.30 page 148 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode) Table 1.15.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 1.15.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 1.15.4 lists the P64 pin functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an "H". (If the N channel open-drain output is selected, this pin is in a high-impedance state.) Figure 1.15.9 shows the transmit/receive timings during clock synchronous serial I/O mode. Table 1.15.3 Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function) Pin name Function Method of selection (Outputs dummy data when performing reception only) TxDi Serial data output (P63, P67, P70) RxDi Serial data input PD6 register's PD6_2 bit = 0, PD6_6 bit = 0 PD7 register's PD7_1 bit = 0 (P62, P66, P71) (Can be used as an input port when performing transmission only) CLKi (P61, P65, P72) Transfer clock output UiMR register's CKDIR bit = 0 Transfer clock input UiMR register's CKDIR bit = 1 PD6 register's PD6_1 bit = 0, PD6_5 bit = 0 PD7 register's PD7_2 bit = 0 _________________ ________ CTSi/RTS i CTS input UiC0 register's CRD bit = 0 UiC0 register's CRS bit = 0 (P60, P64, P73) PD6 register's PD6_0 bit = 0, PD6_4 bit = 0 PD7 register's PD7_3 bit = 0 ________ RTS output UiC0 register's CRD bit = 0 UiC0 register's CRS bit = 1 I/O port UiC0 register's CRD bit = 1 Table 1.15.4 P64 Pin Functions Bit set value Pin function U1C0 register UCON register PD6 register CRD CRS RCSP CLKMD1 CLKMD0 PD6_4 P64 1 0 0 Input: 0, Output: 1 _________ CTS 1 0 0 0 0 0 _________ RTS 1 0 1 0 0 _________ CTS 0 (Note 1) 0 0 1 0 0 CLKS1 1 (Note 2) _________ 1 _________ Note 1: In addition to this, set the U0C0 register's CRD bit to "0" (CTS0/RTS0 enabled) and the U0C0 _________ register's CRS bit to "1" (RTS0 selected). Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output: * High if the U1C0 register's CLKPOL bit = 0 * Low if the U1C0 register's CLKPOL bit = 1 Rev.1.00 2003.05.30 page 149 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode) (1) Example of transmit timing (when internal clock is selected) Tc Transfer clock UiC1 register TE bit UiC1 register TI bit "1" "0" Write data to the UiTB register "1" "0" Transferred from UiTB register to UARTi transmit register "H" CTSi TCLK "L" Stopped pulsing because CTSi = H Stopped pulsing because the TE bit = 0 CLKi TxDi D0 D 1 D2 D3 D4 D5 D6 D 7 UiC0 register TXEPT bit "1" SiTIC register IR bit "1" D 0 D 1 D2 D3 D4 D 5 D 6 D7 D 0 D1 D 2 D 3 D 4 D5 D6 D 7 "0" "0" Set to "0" when interrupt request is accepted, or set to "0" in a program Tc = TCLK = 2(n + 1) / fj fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) n: value set to UiBRG register i = 0 to 2 The above timing diagram applies to the case where the register bits are set as follows: UiMR register CKDIR bit = 0 (internal clock) UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected) UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) UiRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4 (2) Example of receive timing (when external clock is selected) "1" UiC1 register RE bit "0" UiC1 register TE bit "0" UiC1 register TI bit "1" Write dummy data to UiTB register "1" "0" Transferred from UiTB register to UARTi transmit register "H" RTSi "L" Even if the reception is completed, the RTS does not change. The RTS becomes "L" when the RI bit changes to "0" from "1". 1 / fEXT CLKi Receive data is taken in D 0 D1 D 2 D3 D 4 D5 D6 D 7 RxDi UiC1 register RI bit "1" SiRIC register IR bit "1" Transferred from UARTi receive register to UiRB register D0 D 1 D 2 D3 D 4 D 5 Read out from UiRB register "0" "0" Set to "0" when interrupt request is accepted, or set to "0" in a program The above timing diagram applies to the case where the register bits are set Make sure the following conditions are met when input as follows: to the CLKi pin before receiving data is high: UiMR register CKDIR bit = 1 (external clock) UiC1 register TE bit = 1 (transmission enabled) UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected) UiC1 register RE bit = 1 (reception enabled) UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive Write dummy data to the UiTB registe r data taken in at the rising edge of the transfer clock) fEXT: frequency of external clock Figure 1.15.9 Transmit and Receive Operation Rev.1.00 2003.05.30 page 150 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode) (a) CLK Polarity Select Function Use the UiC0 register (i = 0 to 2)'s CKPOL bit to select the transfer clock polarity. Figure 1.15.10 shows the polarity of the transfer clock. (1) When the UiC0 register's CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) CLKi (Note 1) TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 (2) When the UiC0 register's CKPOL bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock) (Note 2) CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 R XD i D0 D1 D2 D3 D4 D5 D6 D7 i = 0 to 2 * This applies to the case where the UiC0 register's UFORM bit = 0 (LSB first) and UiC1 register's UiLCH bit = 0 (no reverse). Note 1: When not transferring, the CLKi pin outputs a high signal. Note 2: When not transferring, the CLKi pin outputs a low signal. Figure 1.15.10 Transfer Clock Polarity (b) LSB First/MSB First Select Function Use the UiC0 register (i = 0 to 2)'s UFORM bit to select the transfer format. Figure 1.15.11 shows the transfer format. (1) When UiC0 register's UFORM bit = 0 (LSB first) CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 R XD i D0 D1 D2 D3 D4 D5 D6 D7 (2) When UiC0 register's UFORM bit = 1 (MSB first) CLKi TXDi D7 D6 D5 D4 D3 D2 D1 D0 RXDi D7 D6 D5 D4 D3 D2 D1 D0 i = 0 to 2 * This applies to the case where the UiC0 register's CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the UiC1 register's UiLCH bit = 0 (no reverse). Figure 1.15.11 Transfer Format Rev.1.00 2003.05.30 page 151 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode) (c) Continuous Receive Mode When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register's TI bit is set to "0" (data present in UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON register bit 2 and bit 3, respectively, and the U2RRM bit is the U2C1 register bit 5. (d) Serial Data Logic Switching Function When the UiC1 register (i = 0 to 2)'s UiLCH bit = 1 (reverse), the data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 1.15.12 shows serial data logic. (1) When the UiC1 register's UiLCH bit = 0 (no reverse) Transfer clock "H" "L" TxDi "H" (no reverse) "L" D0 D1 D2 D3 D4 D5 D6 D7 D6 D7 (2) When the UiC1 register's UiLCH bit = 1 (reverse) Transfer clock "H" "L" TxDi "H" (reverse) "L" D0 D1 D2 D3 D4 D5 i = 0 to 2 * This applies to the case where the UiC0 register's CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the UFORM bit = 0 (LSB first). Figure 1.15.12 Serial Data Logic Switching (e) Transfer Clock Output From Multiple Pins (UART1) Use the UCON register's CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins. Figure 1.15.13 shows the transfer clock output from the multiple pins function usage. This function can be used when the selected transfer clock for UART1 is an internal clock. Microcomputer TXD1 (P67) CLKS1 (P64) CLK1 (P65) IN IN CLK CLK Transfer enabled when the UCON register's CLKMD0 bit = 0 Transfer enabled when the UCON register's CLKMD0 bit = 1 * This applies to the case where the U1MR register's CKDIR bit = 0 (internal clock) and the UCON register's CLKMD1 bit = 1 (transfer clock output from multiple pins). Figure 1.15.13 Transfer Clock Output From Multiple Pins Rev.1.00 2003.05.30 page 152 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode) _______ _______ (f) CTS/RTS Separate Function (UART0) _______ _______ _______ _______ This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0 from the P64 pin. To use this function, set the register bits as shown below. _______ _______ * U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS) _______ * U0C0 register's CRS bit = 1 (outputs UART0 RTS) _______ _______ * U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS) _______ * U1C0 register's CRS bit = 0 (inputs UART1 CTS) _______ * UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin) * UCON register's CLKMD1 bit = 0 (CLKS1 not used) _______ _______ _______ _______ Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be used. _______ _______ Figure 1.15.14 shows CTS/RTS separate function usage. IC Microcomputer TXD0 (P63) RXD0 (P62) IN OUT CLK0 (P61) CLK RTS0 (P60) CTS CTS0 (P64) RTS _______ _______ Figure 1.15.14 CTS/RTS Separate Function Rev.1.00 2003.05.30 page 153 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (UART Mode) Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 1.15.5 lists the specifications of the UART mode. Table 1.15.6 lists the registers used in UART mode and the register values set. Table 1.15.5 UART Mode Specifications Item Transfer data format Transfer clock Transmission, reception control Transmission start condition Reception start condition Interrupt request generation timing Error detection Select function Specification * Character bit (transfer data): Selectable from 7, 8 or 9 bits * Start bit: 1 bit * Parity bit: Selectable from odd, even, or none * Stop bit: Selectable from 1 or 2 bits * UiMR register's CKDIR bit = 0 (internal clock) : fj/ 16(n+1) 0016 to FF16 fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register * CKDIR bit = 1 (external clock) : fEXT/16(n+1) fEXT: Input from CLKi pin. n :Setting value of UiBRG register 0016 to FF16 _______ _______ _______ _______ * Selectable from CTS function, RTS function or CTS/RTS function disabled * Before transmission can start, the following requirements must be met _ The TE bit of UiC1 register = 1 (transmission enabled) _ The TI bit of UiC1 register = 0 (data present in UiTB register) _______ _______ _ If CTS function is selected, input on the CTSi pin = L * Before reception can start, the following requirements must be met _ The RE bit of UiC1 register = 1 (reception enabled) _ Start bit detection * For transmission, one of the following conditions can be selected _ The UiIRS bit (Note 1) = 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission) _ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from the UARTi transmit register * For reception When transferring data from the UARTi receive register to the UiRB register (at completion of reception) * Overrun error (Note 2) This error occurs if the serial I/O started receiving the next data before reading the UiRB register and received the bit one before the last stop bit of the next data * Framing error This error occurs when the number of stop bits set is not detected * Parity error This error occurs when if parity is enabled, the number of 1's in parity and character bits does not match the number of 1's set * Error sum flag This flag is set to "1" when any of the overrun, framing, and parity errors is encountered * LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected * Serial data logic switch This function reverses the logic of the transmit/receive data. The start and stop bits are not reversed. * TXD, RXD I/O polarity switch This function reverses the polarities of the TXD pin output and RXD pin input. The logic levels of all I/O data is reversed. _______ _______ * Separate CTS/RTS pins (UART0) _________ _________ CTS0 and RTS0 are input/output from separate pins i = 0 to 2 Note 1: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4. Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change. Rev.1.00 2003.05.30 page 154 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (UART Mode) Table 1.15.6 Registers to Be Used and Settings in UART Mode Register Bit Function UiTB 0 to 8 Set transmission data (Note 1) UiRB 0 to 8 Reception data can be read (Note 1) UiBRG 0 to 7 Set a transfer rate UiMR SMD2 to SMD0 Set these bits to "1002" when transfer data is 7-bit long OER,FER,PER,SUM Error flag Set these bits to "1012" when transfer data is 8-bit long Set these bits to "1102" when transfer data is 9-bit long CKDIR UiC0 Select the internal clock or external clock STPS Select the stop bit PRY, PRYE Select whether parity is included and whether odd or even IOPOL Select the TxD/RxD input/output polarity CLK0, CLK1 Select the count source for the UiBRG register CRS Select CTS or RTS to use TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS function NCH Select TxDi pin output mode CKPOL Set to "0" UFORM LSB first or MSB first can be selected when transfer data is 8-bit long. Set this _______ _______ _______ _______ bit to "0" when transfer data is 7- or 9-bit long. UiC1 TE Set this bit to "1" to enable transmission TI Transmit buffer empty flag RE Set this bit to "1" to enable reception RI Reception complete flag U2IRS (Note 2) Select the source of UART2 transmit interrupt U2RRM (Note 2) Set to "0" UiLCH Set this bit to "1" to use inverted data logic UiERE Set to "0" UiSMR 0 to 7 Set to "0" UiSMR2 0 to 7 Set to "0" UiSMR3 0 to 7 Set to "0" UiSMR4 0 to 7 Set to "0" UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt U0RRM, U1RRM Set to "0" CLKMD0 Invalid because CLKMD1 = 0 CLKMD1 Set to "0" RCSP Set this bit to "1" to accept as input the UART0 CTS0 signal from the P64 pin 7 Set to "0" _________ i = 0 to 2 Note 1: The bits used for transmit/receive data are as follows: * Bit 0 to bit 6 when transfer data is 7-bit long * Bit 0 to bit 7 when transfer data is 8-bit long * Bit 0 to bit 8 when transfer data is 9-bit long. Note 2: Set the U0C1 and U1C1 registers bit 4 to bit 5 to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are included in the UCON register. Rev.1.00 2003.05.30 page 155 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (UART Mode) Table 1.15.7 lists the functions of the input/output pins during UART mode. Table 1.15.8 lists the P64 pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an "H". (If the N channel open-drain output is selected, this pin is in a high-impedance state.) Figure 1.15.15 shows the typical transmit timings in UART mode. Figure 1.15.16 shows the typical receive timing in UART mode. Table 1.15.7 I/O Pin Functions Pin name Function TxDi Serial data output Method of selection (Outputs dummy data when performing reception only) (P63, P67, P70) RxDi Serial data input (P62, P66, P71) PD6 register's PD6_2 bit = 0, PD6_6 bit = 0 PD7 register's PD7_1 bit = 0 (Can be used as an input port when performing transmission only) CLKi I/O port UiMR register's CKDIR bit = 0 (P61, P65, P72) Transfer clock input UiMR register's CKDIR bit = 1 PD6 register's PD6_1 bit = 0, PD6_5 bit = 0 ________ ________ _______ CTSi/RTS i CTS input PD7 register's PD7_2 bit = 0 UiC0 register's CRD bit = 0 UiC0 register's CRS bit = 0 (P60, P64, P73) PD6 register's PD6_0 bit = 0, PD6_4 bit = 0 PD7 register's PD7_3 bit = 0 ________ RTS output UiC0 register's CRD bit = 0 I/O port UiC0 register's CRS bit = 1 UiC0 register's CRD bit = 1 i = 0 to 2 Table 1.15.8 P64 Pin Functions Bit set value Pin function U1C0 register UCON register PD6 register CRD CRS RCSP CLKMD1 PD6_4 P64 1 0 0 Input: 0, Output: 1 _________ CTS1 0 0 0 0 0 _________ RTS1 0 1 0 0 _________ CTS 0 (Note) 0 0 1 0 0 _________ _________ Note : In addition to this, set the U0C0 register's CRD bit to "0" (CTS 0 /RTS 0 enabled) and the U0C0 _________ register's CRS bit to "1" (RTS0 selected). Rev.1.00 2003.05.30 page 156 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (UART Mode) (1) Example of transmit timing when transfer data is 8-bit long (parity enabled, one stop bit) The transfer clock stops momentarily as CTSi is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to "L". Tc Transfer clock UiC1 register TE bit "1" "0" UiC1 register TI bit Write data to the UiTB register "1" "0" Transferred from UiTB register to UARTi transmit register "H" CTSi "L" Start bit TxDi ST D0 D1 D2 D3 D4 D5 D6 D7 UiC0 register TXEPT bit Stopped pulsing because the TE bit =0 Parity Stop bit bit P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 "1" "0" SiTIC register IR bit "1" "0" Set to "0" when interrupt request is accepted, or set to "0" in a program The above timing diagram applies to the case where the register bits are set as follows: UiMR register PRYE bit = 1 (parity enabled) UiMR register STPS bit = 0 (1 stop bit) UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected) UilRS bit = 1 (an interrupt request occurs when transmit completed): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4 Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of UiBRG count source (external clock) n : value set to UiBRG i = 0 to 2 (2) Example of transmit timing when transfer data is 9-bit long (parity disabled, two stop bits) Tc Transfer clock UiC1 register TE bit UiC1 register TI bit "1" Write data to the UiTB register "0" "1" "0" Start bit TxDi Stop Stop bit bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP UiC0 register TXEPT bit "1" SiTIC register IR bit "1" Transferred from UiTB register to UARTi transmit register ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1 "0" "0" Set to "0" when interrupt request is accepted, or set to "0" in a program The above timing diagram applies to the case where the register bits are set as follows: UiMR register PRYE bit = 0 (parity disabled) UiMR register STPS bit = 1 (2 stop bits) UiC0 register CRD bit = 1 (CTS/RTS disabled) UilRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4 Figure 1.15.15 Transmit Operation Rev.1.00 2003.05.30 page 157 Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of UiBRG count source (external clock) n : value set to UiBRG i = 0 to 2 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (UART Mode) * Example of receive timing when transfer data is 8-bit long (parity disabled, one stop bit) UiBRG count source "1" "0" UiC1 register RE bit Stop bit Start bit RxDi D7 D1 D0 Sampled "L" Receive data taken in Transfer clock Reception triggered when transfer clock "1" is generated by falling edge of start bit UiC1 register RI bit Transferred from UARTi receive register to UiRB register "0" "H" "L" RTSi "1" "0" SiRIC register IR bit i = 0 to 2 Set to "0" when interrupt request is accepted, or set to "0" in a program. The above timing diagram applies to the case where the register bits are set as follows: UiMR register PRYE bit = 0 (parity disabled) UiMR register STPS bit = 0 (1 stop bit) UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected) Figure 1.15.16 Receive Operation (a) LSB First/MSB First Select Function As shown in Figure 1.15.17, use the UiC0 register's UFORM bit to select the transfer format. This function is valid when transfer data is 8-bit long. (1) When UiC0 register's UFORM bit = 0 (LSB first) CLKi TXDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RXDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP (2) When UiC0 register's UFORM bit = 1 (MSB first) CLKi TXDi ST D7 D6 D5 D4 D3 D2 D1 D0 P SP RXDi ST D7 D6 D5 D4 D3 D2 D1 D0 P SP i = 0 to 2 ST: Start bit P: Parity bit SP: Stop bit Note: This applies to the case where the UiC0 register's CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the UiC1 register's UiLCH bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit) and UiMR register's PRYE bit = 1 (parity enabled). Figure 1.15.17 Transfer Format Rev.1.00 2003.05.30 page 158 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (UART Mode) (b) Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 1.15.18 shows serial data logic. (1) When the UiC1 register's UiLCH bit = 0 (no reverse) Transfer clock "H" "L" TxDi "H" (no reverse) "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP D5 D6 D7 P SP (2) When the UiC1 register's UiLCH bit = 1 (reverse) Transfer clock "H" "L" TxDi "H" (reverse) "L" ST D0 D1 D2 D3 D4 i = 0 to 2 ST: Start bit P: Parity bit SP: Stop bit Note: This applies to the case where the UiC0 register s CKPOL bit = 0 (transmit data output at the falling edge of the transfer clock), the UiC0 register's UFORM bit = 0 (LSB first), the UiMR register's STPS bit = 0 (1 stop bit) and UiMR register's PRYE bit = 1 (parity enabled). Figure 1.15.18 Serial Data Logic Switching (c) TxD and RxD I/O Polarity Inverse Function This function inverses the polarities of the TxDi pin output and RxDi pin input. The logic levels of all input/output data (including the start, stop and parity bits) are inversed. Figure 1.15.19 shows the TxD and RxD input/output polarity inverse. (1) When the UiMR register's IOPOL bit = 0 (no reverse) Transfer clock "H" "L" TxDi "H" (no reverse) "L" RxDi "H" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP (no reverse) "L" (2) When the UiMR register's IOPOL bit = 1 (reverse) Transfer clock "H" "L" TxDi "H" (reverse) "L" "H" RxDi "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP (reverse) i = 0 to 2 ST: Start bit P: Parity bit SP: Stop bit Note: This applies to the case where the UiC0 register's UFORM bit = 0 (LSB first), the UiMR register's STPS bit = 0 (1 stop bit) and the UiMR register's PRYE bit = 1 (parity enabled). Figure 1.15.19 TXD and RXD I/O Polarity Inverse Rev.1.00 2003.05.30 page 159 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (UART Mode) _______ _______ (d) CTS/RTS Separate Function (UART0) ________ ________ ________ ________ This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0 from the P64 pin. To use this function, set the register bits as shown below. _______ _______ * U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS) _______ * U0C0 register's CRS bit = 1 (outputs UART0 RTS) _______ _______ * U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS) _______ * U1C0 register's CRS bit = 0 (inputs UART1 CTS) _______ * UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin) * UCON register's CLKMD1 bit = 0 (CLKS1 not used) _______ _______ _______ _______ Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be used. _______ _______ Figure 1.15.20 shows CTS/RTS separate function usage. IC Microcomputer TXD0 (P63) RXD0 (P62) IN OUT RTS0 (P60) CTS CTS0 (P64) RTS _______ _______ Figure 1.15.20 CTS/RTS Separate Function Rev.1.00 2003.05.30 page 160 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) Special Mode 1 (I2C Mode) 2 2 I C mode is provided for use as a simplified I C interface compatible mode. Table 1.15.9 lists the 2 2 specifications of the I C mode. Figure 1.15.21 shows the block diagram for I C mode. Table 1.15.10 lists 2 2 the registers used in the I C mode and the register values set. Table 1.15.11 lists the features in I C mode. Figure 1.15.22 shows SCLi timing. 2 As shown in Table 1.15.11, the microcomputer is placed in I C mode by setting the SMD2 to SMD0 bits to "0102" and the IICM bit to "1". Because SDAi transmit output has a delay circuit attached, SDAi output does not change state until SCLi goes low and remains stably low. 2 Table 1.15.9 I C Mode Specifications Item Specification Transfer data format Transfer clock * Transfer data length: 8 bits * During master UiMR register's CKDIR bit = 0 (internal clock) : fj/ 2(n+1) fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16 * During slave CKDIR bit = 1 (external clock ) : Input from SCLi pin Transmission start condition * Before transmission can start, the following requirements must be met (Note 1) _ The TE bit of UiC1 register = 1 (transmission enabled) _ Reception start condition The TI bit of UiC1 register = 0 (data present in UiTB register) * Before reception can start, the following requirements must be met (Note 1) _ _ The RE bit of UiC1 register = 1 (reception enabled) The TE bit of UiC1 register = 1 (transmission enabled) _ The TI bit of UiC1 register = 0 (data present in the UiTB register) When start or stop condition is detected, acknowledge undetected, and acknowledge Interrupt request generation timing detected * Overrun error (Note 2) Error detection This error occurs if the serial I/O started receiving the next data before reading the UiRB register and received the 8th bit of the next data Select function * Arbitration lost Timing at which the UiRB register's ABT bit is updated can be selected * SDAi digital delay No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable * Clock phase setting With or without clock delay selectable i = 0 to 2 Note 1: When an external clock is selected, the conditions must be met while the external clock is in the high state. Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change. Rev.1.00 2003.05.30 page 161 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) Start and stop condition generation block SDAi STSPSEL=1 Delay circuit ACKC=1 SDASTSP SCLSTSP STSPSEL=0 IICM2=1 Transmission register ACKC=0 IICM=1 and IICM2=0 UARTi SDHI ACKD bit D DMA0 (UART0, UART2) Arbitration Q IICM2=1 Reception register UARTi IICM=1 and IICM2=0 Start condition detection S R Q NACK D IICM=0 R Q STSPSEL=0 IICM=1 UARTi Noise Filter Q T Falling edge detection I/O port UARTi receive, ACK interrupt request, DMA1 request Bus busy Stop condition detection SCLi UARTi transmit, NACK interrupt request ALS T Noise Filter DMA0, DMA1 request (UART1: DMA0 only) D Q T Port register (Note) Internal clock SWC2 STSPSEL=1 External clock ACK 9th bit Start/stop condition detection interrupt request CLK control UARTi R S 9th bit falling edge SWC This diagram applies to the case where the UiMR register's SMD2 to SMD0 bits = 0102 and the UiSMR register's IICM bit = 1. i = 0 to 2 IICM: UiSMR register's bit IICM2, SWC, ALS, SWC2, SDHI: UiSMR2 register's bits STSPSEL, ACKD, ACKC: UiSMR4 register's bits Note: If the IICM bit =1, the pins can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode). 2 Figure 1.15.21 I C Mode Block Diagram Rev.1.00 2003.05.30 page 162 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) Table 1.15.10 Registers to Be Used and Settings in I2C Mode Register Bit UiTB (Note 1) 0 to 7 UiRB (Note 1) 0 to 7 8 ABT OER UiBRG 0 to 7 UiMR (Note 1) SMD2 to SMD0 CKDIR IOPOL UiC0 CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI U2IRS (Note 2) U2RRM (Note 2), UiLCH, UiERE UiSMR IICM ABC UiSMR2 BBS 3 to 7 IICM2 CSC SWC ALS STAC UiSMR3 UiSMR4 SWC2 SDHI 7 0, 2, 4 and NODC CKPH DL2 to DL0 STAREQ RSTAREQ STPREQ STSPSEL ACKD ACKC SCLHI SWC9 IFSR0 UCON IFSR06, ISFR07 U0IRS, U1IRS 2 to 7 Function Master Set transmission data Reception data can be read ACK or NACK is set in this bit Arbitration lost detection flag Overrun error flag Set a transfer rate Set to "0102" Set to "0" Set to "0" Select the count source for the UiBRG register Invalid because CRD = 1 Transmit register empty flag Set to "1" Set to "1" Set to "0" Set to "1" Set this bit to "1" to enable transmission Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Invalid Set to "0" Slave Invalid Invalid Set to "1" Invalid Set to "1" Select the timing at which arbitration-lost Invalid is detected Bus busy flag Set to "0" Refer to "Table 1.15.11 I2C Mode Functions" Set this bit to "1" to enable clock synchronization Set to "0" Set this bit to "1" to have SCLi output fixed to "L" at the falling edge of the 9th bit of clock Set this bit to "1" to have SDAi output Set to "0" stopped when arbitration-lost is detected Set to "0" Set this bit to "1" to initialize UARTi at start condition detection Set this bit to "1" to have SCLi output forcibly pulled low Set this bit to "1" to disable SDAi output Set to "0" Set to "0" Refer to Table 1.15.11 I2C Mode Functions" Set the amount of SDAi digital delay Set this bit to "1" to generate start condition Set to "0" Set this bit to "1" to generate restart condition Set to "0" Set this bit to "1" to generate stop condition Set to "0" Set this bit to "1" to output each condition Set to "0" Select ACK or NACK Set this bit to "1" to output ACK data Set this bit to "1" to have SCLi output Set to "0" stopped when stop condition is detected Set this bit to "1" to set the SCLi to "L" hold Set to "0" at the falling edge of the 9th bit of clock Set to "1" Invalid Set to "0" i = 0 to 2 Note 1: Not all register bits are described above. Set those bits to "0" when writing to the registers in I2C mode. Note 2: Set the U0C1 and U1C1 register bit 4 and bit 5 to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register. Rev.1.00 2003.05.30 page 163 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) 2 Table 1.15.11 I C Mode Functions Function Factor of interrupt number 6, 7 and 10 (Notes 1, 5, 7) Factor of interrupt number 15, 17 and 19 (Notes 1, 6) I2C mode (SMD2 to SMD0 = 0102, IICM = 1) Clock IICM2 = 0 IICM2 = 1 synchronous (UART transmit/UART receive interrupt) (NACK/ACK interrupt) serial I/O mode (SMD2 to SMD0 = CKPH = 1 CKPH = 0 CKPH = 0 CKPH = 1 0012, IICM = 0) (No clock delay) (Clock delay) (No clock delay) (Clock delay) - UARTi transmission Transmission started or completed (selected by UiIRS) Factor of interrupt UARTi reception number 16, 18 and 20 When 8th bit received (Notes 1, 6) CKPOL = 0 (rising edge) CKPOL = 1 (falling edge) Timing for transferring CKPOL = 0 (rising edge) data from the UART CKPOL = 1 (falling edge) reception shift register to the UiRB register UARTi transmission Not delayed output delay Functions of P63, TxDi output P67 and P70 pins Functions of P62, RxDi input P66 and P71 pins Functions of P61, CLKi input or P65 and P72 pins output selected Noise filter width 15 ns Read RxDi and Possible when the SCLi pins levels corresponding port direction bit = 0 Initial value of TxDi CKPOL = 0 (H) and SDAi outputs CKPOL = 1 (L) Initial and end value of SCLi DMA1 factor UARTi reception (Note 6) Store received 1st to 8th bits are data Read received data Start condition detection or stop condition detection (Refer to "Table 1.15.12 STSPSEL Bit Functions") UARTi transmission Falling edge of SCLi next to the 9th bit No acknowledgment detection (NACK) Rising edge of SCLi 9th bit UARTi transmission Rising edge of SCLi 9th bit Acknowledgment detection (ACK) Rising edge of SCLi 9th bit UARTi reception Falling edge of SCLi 9th bit Rising edge of SCLi 9th bit Falling edge of SCLi 9th bit Falling and rising edges of SCLi 9th bit Delayed SDAi input/output SCLi input/output 2 - (Cannot be used in I C mode) 200 ns Always possible no matter how the corresponding port direction bit is set 2 The value set in the port register before setting I C mode (Note 2) H L Acknowledgment detection (ACK) H L UARTi reception Falling edge of SCLi 9th bit stored in UiRB register bit 7 to bit 0 1st to 7th bits are stored in UiRB register bit 6 to bit 0, with 1st to 8th bits are 8th bit stored in UiRB stored in UiRB register register bit 8 bit 7 to bit 0 (Note 3) Read UiRB register UiRB register status is read directly as is bit 6 to bit 0 as bit 7 to bit 1, and bit 8 as bit 0 (Note 4) i = 0 to 2 Note 1: If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to "1" (interrupt requested). (Refer to "Precautions for Interrupts" of the Usage Notes Reference Book.) If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to set the IR bit to "0" (interrupt not requested) after changing those bits. * SMD2 to SMD0 bits in the UiMR register * IICM bit in the UiSMR register * IICM2 bit in the UiSMR2 register * CKPH bit in the UiSMR3 register Note 2: Set the initial value of SDAi output while the UiMR register 's SMD2 to SMD0 bits = 0002 (serial I/O disabled). Note 3: Second data transfer to UiRB register (rising edge of SCLi 9th bit) Note 4: First data transfer to UiRB register (falling edge of SCLi 9th bit) Note 5: Refer to "Figure 1.15.24 STSPSEL Bit Functions". Note 6: Refer to "Figure 1.15.22 Transfer to UiRB Register and Interrupt Timing". Note 7: When using UART0, be sure to set the IFSR06 bit in the IFSR0 register to "1" (cause of interrupt: UART0 bus collision). When using UART1, be sure to set the IFSR07 bit in the IFSR0 register to "1" (cause of interrupt: UART1 bus collision). Rev.1.00 2003.05.30 page 164 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) (1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK) ACK interrupt (DMA1 request), NACK interrupt Transfer to UiRB register b15 b9 b8 b7 D8 D7 b0 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 D3 D2 D1 UiRB register (2) IICM2 = 0, CKPH = 1 (clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D8 (ACK, NACK) D0 ACK interrupt (DMA1 request), NACK interrupt Transfer to UiRB register b15 b9 b8 b7 D8 D7 b0 D6 D5 D4 D3 UiRB register (3) IICM2 = 1 (UART transmit/receive interrupt), CKPH = 0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK) Receive interrupt (DMA1 request) Transmit interrupt Transfer to UiRB register b15 b9 b8 b7 b0 D0 (4) IICM2 = 1, CKPH = 1 1st bit 2nd bit D7 D6 D5 D4 UiRB register 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK) Receive interrupt (DMA1 request) Transfer to UiRB register b15 b9 b8 D0 b7 b0 D7 D6 D5 D4 D3 D2 Transmit interrupt Transfer to UiRB register b15 b9 D1 UiRB register i = 0 to 2 This diagram applies to the case where the following condition is met. UiMR register CKDIR bit = 0 (slave selected) Figure 1.15.22 Transfer to UiRB Register and Interrupt Timing Rev.1.00 2003.05.30 page 165 b8 b7 D8 D7 b0 D6 D5 D4 D3 D2 UiRB register D1 D0 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) * Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated when the SDAi pin changes state from low to high while the SCLi pin is in the high state. Figure 1.15.23 shows the detection of start and stop condition. Because the start and stop condition-detected interrupts share the interrupt control register and vector, check the UiSMR register's BBS bit to determine which interrupt source is requesting the interrupt. 3 to 6 cycles < duration for setting-up (Note) 3 to 6 cycles < duration for holding (Note) Duration for setting-up Duration for holding SCLi SDAi (Start condition) SDA i (Stop condition) i = 0 to 2 Note: When the PCLKR register's PCLK1 bit = 1, this is the cycle number of f1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO. Figure 1.15.23 Detection of Start and Stop Condition * Output of Start and Stop Condition A start condition is generated by setting the UiSMR4 register (i = 0 to 2)'s STAREQ bit to "1" (start). A restart condition is generated by setting the UiSMR4 register's RSTAREQ bit to "1" (start). A stop condition is generated by setting the UiSMR4 register's STPREQ bit to "1" (start). The output procedure is described below. (1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to "1" (start). (2) Set the STSPSEL bit in the UiSMR4 register to "1" (output). Table 1.15.12 and Figure 1.15.24 show the functions of the STSPSEL bit. Rev.1.00 2003.05.30 page 166 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) Table 1.15.12 STSPSEL Bit Functions Function Output of SCLi and SDAi pins Start/stop condition interrupt request generation timing STSPSEL = 0 Output of transfer clock and data Output of start/stop condition is accomplished by a program using ports (not automatically generated in hardware) Start/stop condition detection STSPSEL = 1 Output of a start/stop condition according to the STAREQ, RSTAREQ and STPREQ bit Finish generating start/stop condition (1) When slave CKDIR = 1 (external clock) STSPSEL bit 0 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit SCLi SDAi Start condition detection interrupt Stop condition detection interrupt (2) When master CKDIR = 0 (internal clock), CKPH = 1 (clock delayed) STSPSEL bit Set to "1" in a program Set to "0" in a program 1st 2nd 3rd 4th SCLi Set to "1" in a program 5th 6th 7th 8th Set to "0" in a program 9th bit SDAi Set STAREQ= 1 (start) Start condition detection interrupt Set STPREQ= 1 (start) Stop condition detection interrupt Figure 1.15.24 STSPSEL Bit Functions * Arbitration Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge of SCLi. Use the UiSMR register's ABC bit to select the timing at which the UiRB register's ABT bit is updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to "1" at the same time unmatching is detected during check, and is set to "0" when not detected. In cases when the ABC bit is set to "1", if unmatching is detected even once during check, the ABT bit is set to "1" (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated bytewise, set the ABT bit to "0" (undetected) after detecting acknowledge in the first byte, before transferring the next byte. Setting the UiSMR2 register's ALS bit to "1" (SDA output stop enabled) causes arbitration-lost to occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit is set to "1" (unmatching detected). Rev.1.00 2003.05.30 page 167 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) * Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 1.15.24. The UiSMR2 register's CSC bit is used to synchronize the internally generated clock (internal SCLi) and an external clock supplied to the SCLi pin. In cases when the CSC bit is set to "1" (clock synchronization enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the internal SCLi goes low, at which time the UiBRG register value is reloaded with and starts counting in the low-level interval. If the internal SCLi changes state from low to high while the SCLi pin is low, counting stops, and when the SCLi pin goes high, counting restarts. In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi pin signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock. The UiSMR2 register's SWC bit allows to select whether the SCLi pin should be fixed to or freed from low-level output at the falling edge of the 9th clock pulse. If the UiSMR4 register's SCLHI bit is set to "1" (enabled), SCLi output is turned off (placed in the highimpedance state) when a stop condition is detected. Setting the UiSMR2 register's SWC2 bit = 1 (0 output) makes it possible to forcibly output a low-level signal from the SCLi pin even while sending or receiving data. Setting the SWC2 bit to "0" (transfer clock) allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a low-level signal. If the UiSMR4 register's SWC9 bit is set to "1" (SCL hold low enabled) when the UiSMR3 register's CKPH bit = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the ninth. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output. * SDA Output The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7. The ninth bit (D8) is ACK or NACK. 2 The initial value of SDAi transmit output can only be set when IICM = 1 (I C mode) and the UiMR register's SMD2 to SMD0 bits = 0002 (serial I/O disabled). The UiSMR3 register's DL2 to DL0 bits allow to add no delays or a delay of 2 to 8 UiBRG count source clock cycles to SDAi output. Setting the UiSMR2 register's SDHI bit = 1 (SDA output disabled) forcibly places the SDAi pin in the high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi transfer clock. This is because the ABT bit may inadvertently be set to "1" (detected). * SDA Input When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit 7 to bit 0. The 9th bit (D8) is ACK or NACK. When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit 6 to bit 0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the UiRB register after the rising edge of the corresponding clock pulse of 9th bit. Rev.1.00 2003.05.30 page 168 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) * ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to "0" (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register is set to "1" (ACK data output), the value of the ACKD bit in the UiSMR4 register is output from the SDAi pin. If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low at the rising edge of the 9th bit of transmit clock pulse. If ACKi is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an acknowledge. * Initialization of Transmission/Reception If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial I/O operates as described below. - The transmit shift register is initialized, and the content of the UiTB register is transferred to the transmit shift register. In this way, the serial I/O starts sending data synchronously with the next clock pulse applied. However, the UARTi output value does not change state and remains the same as when a start condition was detected until the first bit of data is output synchronously with the input clock. - The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the next clock pulse applied. - The SWC bit is set to "1" (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the falling edge of the ninth clock pulse. Note that when UARTi transmission/reception is started using this function, the TI bit does not change state. Note also that when using this function, the selected transfer clock should be an external clock. Rev.1.00 2003.05.30 page 169 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) Special Mode 2 Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 1.15.13 lists the specifications of Special Mode 2. Figure 1.15.25 shows communication control example for Special Mode 2. Table 1.15.14 lists the registers used in Special Mode 2 and the register values set. Table 1.15.13 Special Mode 2 Specifications Item Specification Transfer data format Transfer clock * Transfer data length: 8 bits * Master mode UiMR register's CKDIR bit = 0 (internal clock) : fj/ 2(n+1) fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16 * Slave mode CKDIR bit = 1 (external clock selected) : Input from CLKi pin Transmit/receive control Transmission start condition Controlled by input/output ports * Before transmission can start, the following requirements must be met (Note 1) _ _ Reception start condition * Before reception can start, the following requirements must be met (Note 1) _ The RE bit of UiC1 register = 1 (reception enabled) _ _ Interrupt request generation timing The TE bit of UiC1 register = 1 (transmission enabled) The TI bit of UiC1 register = 0 (data present in UiTB register) The TE bit of UiC1 register = 1 (transmission enabled) The TI bit of UiC1 register = 0 (data present in the UiTB register) * For transmission, one of the following conditions can be selected The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission) _ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from the UARTi transmit register * For reception When transferring data from the UARTi receive register to the UiRB register (at completion of reception) _ Error detection * Overrun error (Note 3) This error occurs if the serial I/O started receiving the next data before reading the UiRB register and received the 7th bit of the next data * Clock phase setting Select function Selectable from four combinations of transfer clock polarities and phases i = 0 to 2 Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register's CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the UiC0 register's CKPOL bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4. Note 3: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change. Rev.1.00 2003.05.30 page 170 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) P13 P12 P93 P72(CLK2) P72(CLK2) P71(RxD2) P71(RxD2) P70(TxD2) P70(TxD2) Microcomputer (Master) Microcomputer (Slave) P93 P72(CLK2) P71(RxD2) P70(TxD2) Microcomputer (Slave) Figure 1.15.25 Serial Bus Communication Control Example (UART2) Rev.1.00 2003.05.30 page 171 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) Table 1.15.14 Registers to Be Used and Settings in Special Mode 2 Register Bit UiTB (Note 1) 0 to 7 UiRB (Note 1) 0 to 7 OER UiBRG 0 to 7 UiMR (Note 1) SMD2 to SMD0 CKDIR IOPOL UiC0 CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI U2IRS (Note 2) U2RRM (Note 2), U2LCH, UiERE UiSMR 0 to 7 UiSMR2 0 to 7 UiSMR3 CKPH NODC 0, 2, 4 to 7 UiSMR4 0 to 7 UCON U0IRS, U1IRS U0RRM, U1RRM CLKMD0 CLKMD1, RCSP, 7 Function Set transmission data Reception data can be read Overrun error flag Set a transfer rate Set to "0012" Set this bit to "0" for master mode or "1" for slave mode Set to "0" Select the count source for the UiBRG register Invalid because CRD = 1 Transmit register empty flag Set to "1" Select TxDi pin output format Clock phases can be set in combination with the UiSMR3 register's CKPH bit Set to "0" Set this bit to "1" to enable transmission Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Select UART2 transmit interrupt cause Set to "0" Set to "0" Set to "0" Clock phases can be set in combination with the UiC0 register's CKPOL bit Set to "0" Set to "0" Set to "0" Select UART0 and UART1 transmit interrupt cause Set to "0" Invalid because CLKMD1 = 0 Set to "0" i = 0 to 2 Note 1: Not all register bits are described above. Set those bits to "0" when writing to the registers in Special Mode 2. Note 2: Set the U0C1 and U1C1 register bit 4 and bit 5 to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register. Rev.1.00 2003.05.30 page 172 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) * Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3 register's CKPH bit and the UiC0 register's CKPOL bit. Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated. (a) Master (Internal Clock) Figure 1.15.26 shows the transmission and reception timing in master (internal clock). "H" Clock output (CKPOL=0, CKPH=0) "L" "H" Clock output (CKPOL=1, CKPH=0) "L" Clock output "H" (CKPOL=0, CKPH=1) "L" "H" Clock output (CKPOL=1, CKPH=1) "L" Data output timing "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 Data input timing Figure 1.15.26 Transmission and Reception Timing in Master Mode (Internal Clock) (b) Slave (External Clock) Figure 1.15.27 shows the transmission and reception timing (CKPH = 0) in slave (external clock). Figure 1.15.28 shows the transmission and reception timing (CKPH = 1) in slave (external clock). Rev.1.00 2003.05.30 page 173 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) "H" Slave control input "L" "H" Clock input (CKPOL=0, CKPH=0) "L" "H" Clock input (CKPOL=1, CKPH=0) "L" Data output timing "H" D0 "L" Data input timing D1 D2 D3 D4 D5 D6 D7 Indeterminate Figure 1.15.27 Transmission and Reception Timing (CKPH = 0) in Slave Mode (External Clock) "H" Slave control input "L" "H" Clock input (CKPOL=0, CKPH=1) "L" "H" Clock input (CKPOL=1, CKPH=1) "L" Data output timing "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 Data input timing Figure 1.15.28 Transmission and Reception Timing (CKPH = 1) in Slave Mode (External Clock) Rev.1.00 2003.05.30 page 174 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) Special Mode 3 (IE Mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 1.15.15 lists the registers used in IE mode and the register values set. Figure 1.15.29 shows the functions of bus collision detect function related bits. If the TxDi pin (i = 0 to 2) output level and RxDi pin input level do not match, a UARTi bus collision detect interrupt request is generated. Use the IFSR0 register's IFSR06 and IFSR07 bits to enable the UART0/UART1 bus collision detect function. Table 1. 15.15 Registers to Be Used and Settings in IE Mode Register UiTB UiRB (Note 1) UiBRG UiMR UiC0 UiC1 UiSMR UiSMR2 UiSMR3 UiSMR4 IFSR0 UCON Bit 0 to 8 0 to 8 OER,FER,PER,SUM 0 to 7 SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI U2IRS (Note 2) UiRRM (Note 2), UiLCH, UiERE 0 to 3, 7 ABSCS ACSE SSS 0 to 7 0 to 7 0 to 7 IFSR06, IFSR07 U0IRS, U1IRS U0RRM, U1RRM CLKMD0 CLKMD1, RCSP, 7 Function Set transmission data Reception data can be read Error flag Set a transfer rate Set to "1102" Select the internal clock or external clock Set to "0" Invalid because PRYE = 0 Set to "0" Select the TxD/RxD input/output polarity Select the count source for the UiBRG register Invalid because CRD = 1 Transmit register empty flag Set to "1" Select TxDi pin output mode Set to "0" Set to "0" Set this bit to "1" to enable transmission Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Select the source of UART2 transmit interrupt Set to "0" Set to "0" Select the sampling timing at which to detect a bus collision Set this bit to "1" to use the auto clear function of transmit enable bit Select the transmit start condition Set to "0" Set to "0" Set to "0" Set to "1" Select the source of UART0/UART1 transmit interrupt Set to "0" Invalid because CLKMD1 = 0 Set to "0" i= 0 to 2 Note 1: Not all register bits are described above. Set those bits to "0" when writing to the registers in IE mode. Note 2: Set the U0C1 and U1C1 registers bit 4 and bit 5 to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register. Rev.1.00 2003.05.30 page 175 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) (1) UiSMR register ABSCS bit (bus collision detect sampling clock select) If ABSCS = 0, bus collision is determined at the rising edge of the transfer clock Transfer clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxDi RxDi Input to TAjIN Timer Aj If ABSCS = 1, bus collision is determined when timer Aj (one-shot timer mode) underflows. Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2 (2) UiSMR register ACSE bit (auto clear of transmit enable bit) Transfer clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxDi RxDi UiBCNIC register IR bit If ACSE bit = 1 (automatically clear when bus collision occurs), the TE bit is set to "0" (transmission disabled) when the UiBCNIC register's IR bit = 1 (unmatching detected). UiC1 register TE bit (3) UiSMR register SSS bit (transmit start condition select) If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met. Transfer clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP D6 D7 D8 SP TxDi Transmission enable condition is met If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxDi CLKi ST TxDi D0 D1 D2 D3 D4 D5 (Note 2) RxDi Note 1: The falling edge of RxDi when IOPOL = 0; the rising edge of RxDi when IOPOL = 1. Note 2: The transmit condition must be met before the falling edge (Note 1) of RxDi. i = 0 to 2 This diagram applies to the case where IOPOL =1 (reversed) Figure 1.15.29 Bus Collision Detect Function-Related Bits Rev.1.00 2003.05.30 page 176 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows to output a low from the TxD2 pin when a parity error is detected. Tables 1.15.16 lists the specifications of SIM mode. Table 1.15.17 lists the registers used in the SIM mode and the register values set. Figure 1.15.30 shows the typical transmit/receive timing in SIM mode. Table 1.15.16 SIM Mode Specifications Item Transfer data format Transfer clock Transmission start condition Reception start condition Interrupt request generation timing (Note 2) Error detection Specification * Direct format * Inverse format * U2MR register's CKDIR bit = 0 (internal clock) : fi/ 16(n+1) fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register 0016 to FF16 * CKDIR bit = 1 (external clock) : fEXT/16(n+1) fEXT: Input from CLK2 pin. n: Setting value of U2BRG register 0016 to FF16 * Before transmission can start, the following requirements must be met _ The TE bit of U2C1 register = 1 (transmission enabled) _ The TI bit of U2C1 register = 0 (data present in U2TB register) * Before reception can start, the following requirements must be met _ The RE bit of U2C1 register = 1 (reception enabled) _ Start bit detection * For transmission When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit = 1) * For reception When transferring data from the UART2 receive register to the U2RB register (at completion of reception) * Overrun error (Note 1) This error occurs if the serial I/O started receiving the next data before reading the U2RB register and received the bit one before the last stop bit of the next data * Framing error This error occurs when the number of stop bits set is not detected * Parity error During reception, if a parity error is detected, parity error signal is output from the TxD2 pin. During transmission, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs * Error sum flag This flag is set to "1" when any of the overrun, framing, and parity errors is encountered Note 1: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC register does not change. Note 2: A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to "1" (transmit is completed) and U2ERE bit to "1" (error signal output) after reset. Therefore, when using SIM mode, be sure to set the IR bit to "0" (interrupt not requested) after setting these bits. Rev.1.00 2003.05.30 page 177 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) Table 1.15.17 Registers to Be Used and Settings in SIM Mode Register Bit U2TB (Note) 0 to 7 U2RB (Note) 0 to 7 OER,FER,PER,SUM U2BRG 0 to 7 U2MR SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL Set transmission data Reception data can be read Error flag Set a transfer rate Set to "1012" Select the internal clock or external clock Set to "0" Set this bit to "1" for direct format or "0" for inverse format Set to "1" Set to "0" U2C0 CLK1, CLK0 Select the count source for the U2BRG register CRS Invalid because CRD = 1 U2C1 Function TXEPT Transmit register empty flag CRD Set to "1" NCH Set to "0" CKPOL Set to "0" UFORM Set this bit to "0" for direct format or "1" for inverse format TE Set this bit to "1" to enable transmission TI Transmit buffer empty flag RE Set this bit to "1" to enable reception RI Reception complete flag U2IRS Set to "1" U2RRM Set to "0" U2LCH Set this bit to "0" for direct format or "1" for inverse format U2ERE Set to "1" U2SMR (Note) 0 to 3 Set to "0" U2SMR2 0 to 7 Set to "0" U2SMR3 0 to 7 Set to "0" U2SMR4 0 to 7 Set to "0" Note: Not all register bits are described above. Set those bits to "0" when writing to the registers in SIM mode. Rev.1.00 2003.05.30 page 178 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) Tc (1) Transmission Transfer clock U2C1 register TE bit "1" U2C1 register TI bit "1" Write data to U2TB register "0" "0" Transferred from U2TB register to UART2 transmit register Parity Stop bit bit Start bit TxD2 ST D0 D1 D2 D3 D4 D5 D6 D7 P ST D0 D1 D2 D3 D4 D5 D6 D7 SP Parity error signal sent back from receiver P SP An "L" level returns due to the occurrence of a parity error. RxD2 pin level (Note) ST D0 D1 D2 D3 D4 D5 D6 D7 P ST D0 D1 D2 D3 D4 D5 D6 D7 SP P SP The level is detected by the interrupt routine. U2C0 register TXEPT bit "1" S2TIC register IR bit "1" The level is detected by the interrupt routine. "0" The IR bit is set to "1" at the falling edge of transfer clock "0" The above timing diagram applies to the case where data is transferred in the direct format. U2MR register STPS bit = 0 (1 stop bit) U2MR register PRY bit = 1 (even parity) U2C0 register UFORM bit = 0 (LSB first) U2C1 register U2LCH bit = 0 (no reverse) U2C1 register U2IRS bit = 1 (transmit is completed) Set to "0" when interrupt request is accepted, or set to "0" in a program Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of U2BRG count source (external clock) n : value set to U2BRG Note: Because TxD2 and RxD2 are connected, this is composite waveform consisting of the TxD2 output and the parity error signal sent back from receiver. (2) Reception Tc Transfer clock U2C1 register RE bit "1" "0" Start bit Transmitter's transmit waveform Parity Stop bit bit ST D0 D1 D2 D3 D4 D5 D6 D7 P ST D0 D1 D2 D3 D4 D5 D6 D7 SP P SP TxD2 An "L" level is output from TxD2 due to the occurrence of a parity error RxD2 pin level (Note) ST D0 D1 D2 D3 D4 D5 D6 D7 P ST D0 D1 D2 D3 D4 D5 D6 D7 SP P SP U2C0 register "1" RI bit "0" S2RIC register "1" IR bit Read the U2RB register Read the U2RB register "0" The above timing diagram applies to the case where data is received in the direct format. U2MR register STPS bit = 0 (1 stop bit) U2MR register PRY bit = 1 (even parity) U2C0 register UFORM bit = 0 (LSB first) U2C1 register U2LCH bit = 0 (no reverse) U2C1 register U2IRS bit = 1 (transmit is completed) Set to "0" when interrupt request is accepted, or set to "0" in a program Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of U2BRG count source (external clock) n : value set to U2BRG Note: Because TxD2 and RxD2 are connected, this is composite waveform consisting of the transmitter's transmit waveform and the parity error signal received. Figure 1.15.30 Transmit and Receive Timing in SIM Mode Rev.1.00 2003.05.30 page 179 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) Figure 1.15.31 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up. Microcomputer SIM card TxD2 RxD2 Figure 1.15.31 SIM Interface Connection (a) Parity Error Signal Output The parity error signal is enabled by setting the U2C1 register's U2ERE bit to "1". * When receiving The parity error signal is output when a parity error is detected while receiving data. This is achieved by pulling the TxD2 output low with the timing shown in Figure 1.15.32. If the R2RB register is read while outputting a parity error signal, the PER bit is set to "0" and at the same time the TxD2 output is returned high. * When transmitting A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service routine. Figure 1.15.32 shows the output timing of the parity error signal Transfer clock "H" RxD2 "H" TxD2 "H" U2C1 register RI bit "1" "L" ST D0 D1 D2 D3 D4 D5 D6 "L" SP "0" Note: The output of microcomputer is in the high-impedance state (pulled up externally). Figure 1.15.32 Parity Error Signal Output Timing 2003.05.30 P (Note) This timing diagram applies to the case where the direct format is implemented. Rev.1.00 D7 "L" page 180 ST: Start bit P: Even Parity SP: Stop bit Under development This document is under development and its contents are subject to change. M16C/6N4 Group Serial I/O (Special Modes) (b) Format * Direct Format Set the U2MR register's PRY bit to "1", U2C0 register's UFORM bit to "0" and U2C1 register's U2LCH bit to "0". * Inverse Format Set the PRY bit to "0", UFORM bit to "1" and U2LCH bit to "1". Figure 1.15.33 shows the SIM interface format. (1) Direct format Transfer clock "H" TxD2 "H" "L" "L" D0 D1 D2 D3 D4 D5 D6 D7 P P : Even parity (2) Inverse format Transfer clock TxD2 "H" "L" "H" "L" D7 D6 D5 D4 D3 D2 D1 D0 P P : Odd parity Figure 1.15.33 SIM Interface Format Rev.1.00 2003.05.30 page 181 Under development This document is under development and its contents are subject to change. M16C/6N4 Group SI/O3 SI/O3 SI/O3 is exclusive clock-synchronous serial I/O. Figure 1.15.34 shows the block diagram of SI/O3, and Figure 1.15.35 shows the SI/O3-related registers. Table 1.15.18 lists the specifications of SI/O3. Main clock, PLL clock, or ring oscillator clock 1/2 f2SIO PCLK1=0 f1SIO 1/8 PCLK1=1 1/4 Clock source select SM31 to SM30 002 f8SIO 012 f32SIO 102 Synchronous circuit SM34 CLK3 SM33 SM36 Data bus 1/(n+1) 1/2 S3BRG register SM36 CLK polarity reversing circuit SI/O counter 3 SM32 SM33 SOUT3 SIN3 SM35 LSB MSB S3TRR register 8 n = A value set in the S3BRG register. Figure 1.15.34 SI/O3 Block Diagram Rev.1.00 2003.05.30 page 182 SI/O3 interrupt request Under development This document is under development and its contents are subject to change. M16C/6N4 Group SI/O3 SI/O3 control register (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol S3C Bit symbol SM30 Address 01E216 After reset 010000016 Description Bit name b1 b0 RW RW Internal synchronous clock select bit 0 0 : Selecting f1SIO or f2SIO 0 1 : Selecting f8SIO 1 0 : Selecting f32SIO 1 1 : Must not be set SM32 SOUT3 output disable bit (Note 2) 0 : SOUT3 output 1 : SOUT3 output disabled (high-impedance) RW SM33 S I/O3 port select bit 0 : Input/output port 1 : SOUT3 output, CLK3 function RW SM34 CLK polarity select bit 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge RW SM35 Transfer direction select bit 0 : LSB first 1 : MSB first RW SM36 Synchronous clock select bit 0 : External clock (Note 3) 1 : Internal clock (Note 4) RW SM37 SOUT3 initial value set bit Effective when SM33 = 0 0 : "L" output 1 : "H" output RW SM31 RW Note 1: Make sure this register is written to by the next instruction after setting the PRCR register's PRC2 bit to "1" (write enabled). Note 2: When the SM32 bit is set to "1", the target pin goes to a high-impedance state regardless of which function of the pin is being used. Note 3: Set the SM33 bit to "1" and the corresponding port direction bit to "0" (input mode). Note 4: Set the SM33 bit to "1" (SOUT3 output, CLK3 function). SI/O3 bit rate generator (Notes 1, 2) b7 b0 Symbol S3BRG Address 01E316 After reset Indeterminate Description Setting range RW Assuming that set value = n, S3BRG divides the count source by n + 1 0016 to FF16 WO Note 1: Write to this register while serial I/O is neither transmitting nor receiving. Note 2: Use MOV instruction to write to this register. SI/O3 transmit/receive register (Notes 1, 2) b7 b0 Symbol S3TRR Address 01E016 After reset Indeterminate Description RW Transmission/reception starts by writing transmit data to this register. After transmission/reception finishes, reception data can be read by reading this register. RW Note 1: Write to this register while serial I/O is neither transmitting nor receiving. Note 2: To receive data, set the corresponding port direction bit for SIN3 to "0" (input mode). Figure 1.15.35 S3C Register, S3BRG Register and S3TRR Register Rev.1.00 2003.05.30 page 183 Under development This document is under development and its contents are subject to change. M16C/6N4 Group SI/O3 Table 1.15.18 SI/O3 Specifications Item Specification Transfer data format Transfer clock * Transfer data length: 8 bits * S3C register's SM36 bit = 1 (internal clock) : fj/ 2(n+1) fj = f1SIO, f8SIO, f32SIO. n = Setting value of S3BRG register 0016 to FF16. * SM36 bit = 0 (external clock) : Input from CLK3 pin (Note 1) Transmission/reception start condition * Before transmission/reception can start, the following requirements must be met Write transmit data to the S3TRR register (Notes 2, 3) Interrupt request generation timing * When S3C register's SM34 bit = 0 The rising edge of the last transfer clock pulse (Note 4) * When SM34 = 1 The falling edge of the last transfer clock pulse (Note 4) CLK3 pin function I/O port, transfer clock input, transfer clock output SOUT3 pin function SIN3 pin function I/O port, transmit data output, high-impedance I/O port, receive data input Select function * LSB first or MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected * Function for setting an SOUT3 initial value set function When the S3C register's SM36 bit = 0 (external clock), the SOUT3 pin output level while not transmitting can be selected. * CLK polarity selection Whether transmit data is output/input timing at the rising edge or falling edge of transfer clock can be selected. Note 1: To set the S3C register's SM36 bit to "0" (external clock), follow the procedure described below. * If the S3C register's SM34 bit = 0, write transmit data to the S3TRR register while input on the CLK3 pin is high. The same applies when rewriting the S3C register's SM37 bit. * If the SM34 bit = 1, write transmit data to the S3TRR register while input on the CLK3 pin is low. The same applies when rewriting the SM37 bit. * Because shift operation continues as long as the transfer clock is supplied to the SI/O3 circuit, stop the transfer clock after supplying eight pulses. If the SM36 bit = 1 (internal clock), the transfer clock automatically stops. Note 2: Unlike UART0 to UART2, SI/O3 is not separated between the transfer register and buffer. Therefore, do not write the next transmit data to the S3TRR register during transmission. Note 3: When the S3C register's SM36 bit = 1 (internal clock), SOUT3 retains the last data for a 1/2 transfer clock period after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is written to the S3TRR register during this period, SOUT3 immediately goes to a high-impedance state, with the data hold time thereby reduced. Note 4: When the S3C register's SM36 bit = 1 (internal clock), the transfer clock stops in the high state if the SM34 bit = 0, or stops in the low state if the SM34 bit = 1. Rev.1.00 2003.05.30 page 184 Under development This document is under development and its contents are subject to change. M16C/6N4 Group SI/O3 (a) SI/O3 Operation Timing Figure 1.15.36 shows the SI/O3 operation timing. 1.5 cycle (max.) (Note 1) SI/O3 internal clock "H" "L" CLK3 output "H" "L" Signal written to the S3TRR register "H" "L" SOUT3 output "H" "L" SIN3 input "H" "L" S3IC register IR bit "1" "0" (Note 2) D0 D1 D2 D3 D4 D5 D6 D7 * This diagram applies to the case where the S3C register bits are set as follows: SM32 = 0 (SOUT3 output) SM33 = 1 (SOUT3 output, CLK3 function) SM34 = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) SM35 = 0 (LSB first) SM36 = 1 (internal clock) Note 1: If the SM36 bit = 1 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the S3TRR register. Note 2: When the SM36 bit = 1 (internal clock), the SOUT3 pin is placed in the high-impedance state after the transfer finishes. Figure 1.15.36 SI/O3 Operation Timing (b) CLK Polarity Selection The S3C register's SM34 bit allows selection of the polarity of the transfer clock. Figure 1.15.37 shows the polarity of the transfer clock. (1) When S3C register's SM34 bit = 0 (Note 1) CLK3 SIN3 D0 D1 D2 D3 D4 D5 D6 D7 SOUT3 D0 D1 D2 D3 D4 D5 D6 D7 (2) When S3C register's SM34 bit = 1 (Note 2) CLK3 SIN3 D0 D1 D2 D3 D4 D5 D6 D7 SOUT3 D0 D1 D2 D3 D4 D5 D6 D7 *This diagram applies to the case where the S3C register bits are set as follows: SM35 = 0 (LSB first) SM36 = 1 (internal clock) Note 1: When the SM36 bit = 1 (internal clock), a high level is output from the CLK3 pin if not transferring data. Note 2: When the SM36 bit = 1 (internal clock), a low level is output from the CLK3 pin if not transferring data. Figure 1.15.37 Polarity of Transfer Clock Rev.1.00 2003.05.30 page 185 Under development This document is under development and its contents are subject to change. M16C/6N4 Group SI/O3 (c) Functions for Setting an SOUT3 Initial Value If the S3C register's SM36 bit = 0 (external clock), the SOUT3 pin output can be fixed high or low when not transferring. Figure 1.15.38 shows the timing chart for setting an SOUT3 initial value and how to set it. (Example) When "H" selected for SOUT3 initial value Setting of the initial value of SOUT3 output and starting of transmission/reception Signal written to S3TRR register SM37 bit Set the SM33 bit to "0" (SOUT3 pin functions as an I/O port) SM33 bit D0 SOUT3 (internal) SOUT3 output D0 Port output Set the SM37 bit to "1" (SOUT3 initial value = H) Set the SM33 bit to "1" (SOUT3 pin functions as SOUT3 output) Initial value = H (Note 1) Setting the SOUT3 initial value to "H" (Note 2) Port selection switching (I/O port SOUT3) * This diagram applies to the case where the S3C register bits are set as follows: SM32 = 0 (SOUT3 output) SM35 = 0 (LSB first) SM36 = 0 (external clock) Note 1: If the SM36 bit = 1 (internal clock) or if the SM32 bit = 1 (SOUT3 output disabled), this output goes to the high-impedance state. Note 2: SOUT3 can only be initialized when input on the CLK3 pin is in the high state if the S3C register's SM34 bit = 0 (transmit data output at the falling edge of the transfer clock) or in the low state if the SM34 bit = 1 (transmit data output at the rising edge of the transfer clock). Figure 1.15.38 SOUT3's Initial Value Setting Rev.1.00 2003.05.30 page 186 "H" level is output from the SOUT3 pin Write to the S3TRR register Serial transmit/reception starts Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter A-D Converter The microcomputer contains one A-D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107, P95, _________ P96, P00 to P07, and P20 to P27. Similarly, ADTRG input shares the pin with P97. Therefore, when using these inputs, make sure the corresponding port direction bits are set to "0" (input mode). When not using the A-D converter, set the VCUT bit to "0" (VREF unconnected), so that no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip. The A-D conversion result is stored in the ADi register bits for ANi, AN0i, and AN2i pins (i = 0 to 7). Table 1.16.1 shows the performance of the A-D converter. Figure 1.16.1 shows the block diagram of the A-D converter, and Figures 1.16.2 and 1.16.3 show the A-D converter-related registers. Table 1.16.1 A-D Converter Performance Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1) 0V to AVCC (VCC) Operating clock AD (Note 2) fAD, divide-by-2 of fAD, divide-by-3 of fAD, divide-by-4 of fAD, divide-by-6 of fAD, divide-by-12 of fAD Resolution 8 bits or 10 bits (selectable) Integral nonlinearity error * With 8-bit resolution: 2LSB * With 10-bit resolution : 3LSB When external operation amp connection mode is selected : 7LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN00 to AN07) + 8 pins (AN20 to AN27) A-D conversion start condition * Software trigger The ADCON0 register's ADST bit is set to "1" (A-D conversion starts) * External trigger (retriggerable) __________ Input on the ADTRG pin changes state from high to low after the ADST bit is set to "1" (A-D conversion starts) Conversion speed per pin * Without sample and hold function 8-bit resolution: 49 AD cycles, 10-bit resolution: 59 AD cycles * With sample and hold function 8-bit resolution: 28 AD cycles, 10-bit resolution: 33 AD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Operation clock frequency (AD frequency) must be 10 MHz or less. A case without sample-and-hold function, turn (AD frequency) into 250 kHz or more. A case with the sample and hold function, turn (AD frequency) into 1 MHz or more. Rev.1.00 2003.05.30 page 187 Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter A-D conversion rate selection CKS1=1 CKS2=0 1/2 fAD 1/2 1/3 CKS0=1 AD CKS1=0 CKS0=0 CKS2=1 TRG=0 Software trigger A-D trigger ADTRG TRG=1 VREF Resistor ladder VCUT=0 AVSS VCUT=1 Successive conversion register ADCON1 register ADCON0 register AD register 0 (16) AD register 1 (16) AD register 2 (16) AD register 3 (16) AD register 4 (16) AD register 5 (16) AD register 6 (16) AD register 7 (16) Decoder for A-D register Data bus high-order ADCON2 register Data bus low-order PM00 PM01 (Note) VREF Decoder for channel selection VIN Port P0 group CH2 to CH0 =0002 =0012 =0102 =0112 =1002 =1012 =1102 =1112 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 CH2 to CH0 =0002 =0012 =0102 =0112 =1002 =1012 =1102 =1112 Port P2 group AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 Port P10 group AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ANEX1 ADGSEL1 to ADGSEL0=002 OPA1 to OPA0=002 PM01 to PM00=002 (Note) ADGSEL1 to ADGSEL0=102 OPA1 to OPA0=002 PM01 to PM00=002 ADGSEL1 to ADGSEL0=112 OPA1 to OPA0=002 ADGSEL1 to ADGSEL0=002 OPA1 to OPA0=112 (Note) PM01 to PM00=002 ADGSEL1 to ADGSEL0=102 OPA1 to OPA0=112 PM01 to PM00=002 ADGSEL1 to ADGSEL0=112 OPA1 to OPA0=112 ANEX0 CH2 to CH0 =0002 =0012 =0102 =0112 =1002 =1012 =1102 =1112 OPA0=1 OPA1 to OPA0 =012 OPA1=1 OPA1=1 Note: Port P0 group (AN00 to AN07) can be used as analog input pins even when the PM01 to PM00 bits are set to "012" (memory expansion mode) and the PM05 to PM04 bits are . set to "112" (multiplexed bus allocated to the entire CS space) Figure 1.16.1 A-D Converter Block Diagram Rev.1.00 2003.05.30 page 188 Comparator Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset ADCON0 03D616 00000XXX2 Bit symbol Bit name Function CH0 CH1 RW RW Analog input pin select bit Function varies with each operation mode RW RW CH2 b4 b3 MD0 A-D operation mode select bit 0 MD1 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 or Repeat sweep mode 1 RW RW TRG Trigger select bit 0 : Software trigger 1 : ADTRG trigger RW ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started RW CKS0 Frequency select bit 0 See Note 2 for the ADCON2 register RW Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address ADCON1 03D716 Bit symbol Bit name SCAN0 A-D sweep pin select bit SCAN1 After reset 0016 Function Function varies with each operation mode RW RW RW MD2 A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 RW BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode RW CKS1 Frequency select bit 1 See Note 2 for the ADCON2 register RW VCUT VREF connect bit (Note 2) 0 : VREF not connected 1 : VREF connected RW OPA0 External op-amp connection mode bit Function varies with each operation mode OPA1 RW RW Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate. Note 2: If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 s or more before starting A-D conversion. Figure 1.16.2 ADCON0 Register and ADCON1 Register Rev.1.00 2003.05.30 page 189 Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter A-D control register 2 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol Address After reset ADCON2 03D416 0016 Bit symbol Bit name Function A-D conversion method select bit SMP RW 0 : Without sample and hold 1 : With sample and hold RW b2 b1 0 0 : Port P10 group is selected 0 1 : Must not be set 1 0 : Port P0 group is selected 1 1 : Port P2 group is selected RW Reserved bit Set to "0" RW Frequency select bit 2 (Note 2) 0 : Selects fAD, divide-by-2 of fAD, or divide-by-4 of fAD. RW 1 : Selects divide-by-3 of fAD, divide-by-6 of fAD, or divide-by-12 of fAD. ADGSEL0 A-D input group select bit ADGSEL1 (b3) CKS2 - RW Nothing is assigned. When write, set to "0". When read, their contents are "0". (b7-b5) - Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate. Note 2: The AD frequency must be 10 MHz or less. The selected AD frequency is determined by a combination of the ADCON0 register's CKS0 bit, ADCON1 register's CKS1 bit, and ADCON2 register's CKS2 bit. AD CKS0 CKS1 CKS2 0 0 0 Divide-by-4 of fAD 0 0 1 Divide-by-2 of fAD 0 1 0 0 1 1 1 0 0 Divide-by-12 of fAD 1 0 1 Divide-by-6 of fAD 1 1 0 1 1 1 fAD Divide-by-3 of fAD Symbol A-D register i (i = 0 to 7) (b15) b7 (b8) b0 b7 b0 Address 03C116 03C316 03C516 03C716 03C916 03CB16 03CD16 03CF16 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 to to to to to to to to 03C016 03C216 03C416 03C616 03C816 03CA16 03CC16 03CE16 After reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Function When the ADCON1 register's BITS bit is "1" (10-bit mode) When the ADCON1 register's BITS bit is "0" (8-bit mode) RW Low-order 8 bits of A-D conversion result A-D conversion result RO High-order 2 bits of A-D conversion result When read, the content is indeterminate. RO Nothing is assigned. When write, set to "0". When read, their contents are "0". Figure 1.16.3 ADCON2 Register, and AD0 to AD7 Registers Rev.1.00 2003.05.30 page 190 - Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter (1) One-shot Mode In this mode, the input voltage on one selected pin is A-D converted once. Table 1.16.2 lists the specifications of one-shot mode. Figure 1.16.4 shows the ADCON0 and ADCON1 registers in one-shot mode. Table 1.16.2 One-shot Mode Specifications Item Specification Function The input voltage on one pin selected by the ADCON0 register's CH2 to CH0 bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits or the ADCON1 register's OPA1 to OPA0 bits is A-D converted once. A-D conversion start condition * When the ADCON0 register's TRG bit is "0" (software trigger) The ADCON0 register's ADST bit is set to "1" (A-D conversion starts) _________ * When the TRG bit is "1" (ADTRG trigger) _________ Input on the ADTRG pin changes state from high to low after the ADST bit is set to "1" (A-D conversion starts) A-D conversion stop condition * Completion of A-D conversion (If a software trigger is selected, the ADST bit is set to "0" (A-D conversion halted).) * Set the ADST bit to "0" Interrupt request generation timing Completion of A-D conversion Analog input pin Select one pin from AN0 to AN7, AN00 to AN07, AN20 to AN27, ANEX0 to ANEX1 Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin Rev.1.00 2003.05.30 page 191 Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol Address After reset ADCON0 03D616 00000XXX2 Bit symbol Bit name Function RW b2 b1 b0 CH0 CH1 Analog input pin select bit CH2 MD0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected (Note 2) 1 1 1 : AN7 is selected (Note 3) RW RW RW RW A-D operation mode select bit 0 0 0 : One-shot mode TRG Trigger select bit 0 : Software trigger 1 : ADTRG trigger RW ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started RW CKS0 Frequency select bit 0 See Note 2 for the ADCON2 register RW MD1 b4 b3 (Note 3) RW Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate. Note 2: AN00 to AN07, and AN20 to AN27 can be used in same way as AN0 to AN7. Use the ADCON2 register's ADGSEL1 to ADGSEL0 bits to select the desired pin. Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 1 b2 b1 b0 0 Symbol Address ADCON1 03D716 Bit symbol After reset 0016 Bit name Function RW RW SCAN0 A-D sweep pin select bit Invalid in one-shot mode SCAN1 RW MD2 A-D operation mode select bit 1 Set to "0" when one-shot mode is selected RW BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode RW CKS1 Frequency select bit 1 See Note 2 for the ADCON2 register RW VCUT VREF connect bit (Note 2) 1 : VREF connected RW External op-amp connection mode bit 0 0 : ANEX0 and ANEX1 are not used RW 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted RW 1 1 : External op-amp connection mode b7 b6 OPA0 OPA1 Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate. Note 2: If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 s or more before starting A-D conversion. Figure 1.16.4 ADCON0 Register and ADCON1 Register in One-shot Mode Rev.1.00 2003.05.30 page 192 Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter (2) Repeat Mode In this mode, the input voltage on one selected pin is A-D converted repeatedly. Table 1.16.3 lists the specifications of repeat mode. Figure 1.16.5 shows the ADCON0 and ADCON1 registers in repeat mode. Table 1.16.3 Repeat Mode Specifications Item Specification Function The input voltage on one pin selected by the ADCON0 register's CH2 to CH0 bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits or the ADCON1 register's OPA1 to OPA0 bits is A-D converted repeatedly. A-D conversion start condition * When the ADCON0 register's TRG bit is "0" (software trigger) The ADCON0 register's ADST bit is set to "1" (A-D conversion starts) ___________ * When the TRG bit is "1" (ADTRG trigger) ___________ Input on the ADTRG pin changes state from high to low after the ADST bit is set to "1" (A-D conversion starts) A-D conversion stop condition Set the ADST bit to "0" (A-D conversion halted) Interrupt request generation timing None generated Analog input pin Select one pin from AN0 to AN7, AN00 to AN07, AN20 to AN27, ANEX0 to ANEX1 Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin Rev.1.00 2003.05.30 page 193 Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 1 Symbol Address After reset ADCON0 03D616 00000XXX2 Bit symbol Bit name Function RW b2 b1 b0 CH0 CH1 Analog input pin select bit CH2 MD0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected (Note 2) 1 1 1 : AN7 is selected (Note 3) RW RW RW RW MD1 A-D operation mode select bit 0 0 1 : Repeat mode TRG Trigger select bit 0 : Software trigger 1 : ADTRG trigger RW ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started RW CKS0 Frequency select bit 0 See Note 2 for the ADCON2 register RW b4 b3 (Note 3) RW Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate. Note 2: AN00 to AN07, and AN20 to AN27 can be used in same way as AN0 to AN7. Use the ADCON2 register's ADGSEL1 to ADGSEL0 bits to select the desired pin. Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction. A-D control register 1 (Note 1) b7 b6 b5 b4 1 b3 b2 b1 b0 0 Symbol Address ADCON1 03D716 Bit symbol After reset 0016 Bit name Function RW RW SCAN0 A-D sweep pin select bit Invalid in repeat mode SCAN1 RW MD2 A-D operation mode select bit 1 Set to "0" when repeat mode is selected RW BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode RW CKS1 Frequency select bit 1 See Note 2 for the ADCON2 register RW VCUT VREF connect bit (Note 2) 1 : VREF connected RW External op-amp connection mode bit 0 0 : ANEX0 and ANEX1 are not used RW 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted RW 1 1 : External op-amp connection mode b7 b6 OPA0 OPA1 Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate. Note 2: If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 s or more before starting A-D conversion. Figure 1.16.5 ADCON0 Register and ADCON1 Register in Repeat Mode Rev.1.00 2003.05.30 page 194 Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter (3) Single Sweep Mode In this mode, the input voltages on selected pins are A-D converted, one pin at a time. Table 1.16.4 lists the specifications of single sweep mode. Figure 1.16.6 shows the ADCON0 and ADCON1 registers in single sweep mode. Table 1.16.4 Single Sweep Mode Specifications Item Specification Function The input voltages on pins selected by the ADCON1 register's SCAN1 to SCAN0 bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits are A-D converted, one pin at a time. A-D conversion start condition * When the ADCON0 register's TRG bit is "0" (software trigger) The ADCON0 register's ADST bit is set to "1" (A-D conversion starts) ___________ * When the TRG bit is "1" (ADTRG trigger) ___________ Input on the ADTRG pin changes state from high to low after the ADST bit is set to "1" (A-D conversion starts) A-D conversion stop condition * Completion of A-D conversion (If a software trigger is selected, the ADST bit is set to "0" (A-D conversion halted).) * Set the ADST bit to "0" Interrupt request generation timing Completion of A-D conversion Analog input pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0 to AN7 (8 pins) (Note) Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin Note: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. Rev.1.00 2003.05.30 page 195 Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol Address After reset ADCON0 03D616 00000XXX2 Bit symbol Bit name Function RW CH0 CH1 Analog input pin select bit Invalid in single sweep mode RW RW CH2 MD0 RW RW MD1 A-D operation mode select bit 0 1 0 : Single sweep mode TRG Trigger select bit 0 : Software trigger 1 : ADTRG trigger RW ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started RW CKS0 Frequency select bit 0 See Note 2 for the ADCON2 register RW b4 b3 RW Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 1 b3 b2 b1 b0 0 Symbol Address ADCON1 03D716 Bit symbol After reset 0016 Bit name Function RW When single sweep mode is selected SCAN0 A-D sweep pin select bit SCAN1 b1 b0 RW 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) RW 1 1 : AN0 to AN7 (8 pins) (Note 2) MD2 A-D operation mode select bit 1 Set to "0" when single sweep mode RW is selected BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode RW CKS1 Frequency select bit 1 See Note 2 for the ADCON2 register RW VCUT VREF connect bit (Note 3) 1 : VREF connected RW External op-amp connection mode bit 0 0 : ANEX0 and ANEX1 are not used RW 0 1 : Must not be set 1 0 : Must not be set RW 1 1 : External op-amp connection mode b7 b6 OPA0 OPA1 Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate. Note 2: AN00 to AN07, and AN20 to AN27 can be used in same way as AN0 to AN7. Use the ADCON2 register's ADGSEL1 to ADGSEL0 bits to select the desired pin. Note 3: If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 s or more before starting A-D conversion. Figure 1.16.6 ADCON0 Register and ADCON1 Register in Single Sweep Mode Rev.1.00 2003.05.30 page 196 Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter (4) Repeat Sweep Mode 0 In this mode, the input voltages on selected pins are A-D converted repeatedly. Table 1.16.5 lists the specifications of repeat sweep mode 0. Figure 1.16.7 shows the ADCON0 and ADCON1 registers in repeat sweep mode 0. Table 1.16.5 Repeat Sweep Mode 0 Specifications Item Specification Function The input voltages on pins selected by the ADCON1 register's SCAN1 to SCAN0 bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits are A-D converted repeatedly. A-D conversion start condition * When the ADCON0 register's TRG bit is "0" (software trigger) The ADCON0 register's ADST bit is set to "1" (A-D conversion starts) ___________ * When the TRG bit is "1" (ADTRG trigger) ___________ Input on the ADTRG pin changes state from high to low after the ADST bit is set to "1" (A-D conversion starts) A-D conversion stop condition Set the ADST bit to "0" (A-D conversion halted) Interrupt request generation timing None generated Analog input pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0 to AN7 (8 pins) (Note) Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin Note: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. Rev.1.00 2003.05.30 page 197 Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol Address After reset ADCON0 03D616 00000XXX2 Bit symbol Bit name Function RW CH0 CH1 Analog input pin select bit Invalid in repeat sweep mode 0 RW RW CH2 MD0 RW b4 b3 RW A-D operation mode select bit 0 1 1 : Repeat sweep mode 0 or Repeat sweep mode 1 TRG Trigger select bit 0 : Software trigger 1 : ADTRG trigger RW ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started RW CKS0 Frequency select bit 0 See Note 2 for the ADCON2 register RW MD1 RW Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 1 b3 b2 b1 b0 0 Symbol Address ADCON1 03D716 Bit symbol After reset 0016 Bit name Function RW When repeat sweep mode 0 is selected SCAN0 A-D sweep pin select bit SCAN1 b1 b0 RW 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) RW 1 1 : AN0 to AN7 (8 pins) (Note 2) MD2 A-D operation mode select bit 1 Set to "0" when repeat sweep mode 0 is selected RW BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode RW CKS1 Frequency select bit 1 See Note 2 for the ADCON2 register RW VCUT VREF connect bit (Note 3) 1 : VREF connected RW External op-amp connection mode bit 0 0 : ANEX0 and ANEX1 are not used RW 0 1 : Must not be set 1 0 : Must not be set RW 1 1 : External op-amp connection mode b7 b6 OPA0 OPA1 Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate. Note 2: AN00 to AN07, and AN20 to AN27 can be used in same way as AN0 to AN7. Use the ADCON2 register's ADGSEL1 to ADGSEL0 bits to select the desired pin. Note 3: If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 s or more before starting A-D conversion. Figure 1.16.7 ADCON0 Register and ADCON1 Register in Repeat Sweep Mode 0 Rev.1.00 2003.05.30 page 198 Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter (5) Repeat Sweep Mode 1 In this mode, the input voltages on all pins are A-D converted repeatedly, with priority given to the selected pins. Table 1.16.6 lists the specifications of repeat sweep mode 1. Figure 1.16.8 shows the ADCON0 and ADCON1 registers in repeat sweep mode 1. Table 1.16.6 Repeat Sweep Mode 1 Specifications Item Specification Function The input voltages on all pins selected by the ADCON2 register's ADGSEL1 to ADGSEL0 bits are A-D converted repeatedly, with priority given to pins selected by the ADCON1 register's SCAN1 to SCAN0 bits and ADGSEL1 to ADGSEL0 bits. Example : If AN0 selected, input voltages are A-D converted in order of AN0 AN1 AN0 AN2 AN0 AN3, and so on. A-D conversion start condition * When the ADCON0 register's TRG bit is "0" (software trigger) The ADCON0 register's ADST bit is set to "1" (A-D conversion starts) _________ * When the TRG bit is "1" (ADTRG trigger) _________ Input on the ADTRG pin changes state from high to low after the ADST bit is set to "1" (A-D conversion starts) A-D conversion stop condition Set the ADST bit to "0" (A-D conversion halted) Interrupt request generation timing None generated Analog input pins to be given Select from AN0 (1 pin), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 priority when A-D converted pins) (Note) Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin Note: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. Rev.1.00 2003.05.30 page 199 Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol Address After reset ADCON0 03D616 00000XXX2 Bit symbol Bit name Function RW CH0 CH1 Analog input pin select bit Invalid in repeat sweep mode 1 RW RW CH2 MD0 RW b4 b3 RW A-D operation mode select bit 0 1 1 : Repeat sweep mode 0 or Repeat sweep mode 1 TRG Trigger select bit 0 : Software trigger 1 : ADTRG trigger RW ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started RW CKS0 Frequency select bit 0 See Note 2 for the ADCON2 register RW MD1 RW Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 1 b3 b2 b1 b0 1 Symbol Address ADCON1 03D716 Bit symbol After reset 0016 Bit name Function RW When repeat sweep mode 1 is selected SCAN0 A-D sweep pin select bit SCAN1 b1 b0 RW 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) RW 1 1 : AN0 to AN3 (4 pins) (Note 2) MD2 A-D operation mode select bit 1 Set to "1" when repeat sweep mode 1 is selected RW BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode RW CKS1 Frequency select bit 1 See Note 2 for the ADCON2 register RW VCUT VREF connect bit (Note 3) 1 : VREF connected RW External op-amp connection mode bit 0 0 : ANEX0 and ANEX1 are not used RW 0 1 : Must not be set 1 0 : Must not be set RW 1 1 : External op-amp connection mode b7 b6 OPA0 OPA1 Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate. Note 2: AN00 to AN07, and AN20 to AN27 can be used in same way as AN0 to AN7. Use the ADCON2 register's ADGSEL1 to ADGSEL0 bits to select the desired pin. Note 3: If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 s or more before starting A-D conversion. Figure 1.16.8 ADCON0 Register and ADCON1 Register in Repeat Sweep Mode 1 Rev.1.00 2003.05.30 page 200 Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter (a) Resolution Select Function The desired resolution can be selected using the ADCON1 register's BITS bit. If the BITS bit is set to "1" (10-bit conversion accuracy), the A-D conversion result is stored in the ADi register (i = 0 to 7)'s bit 0 to bit 9. If the BITS bit is set to "0" (8-bit conversion accuracy), the A-D conversion result is stored in the ADi register's bit 0 to bit 7. (b) Sample and Hold If the ADCON2 register's SMP bit is set to "1" (with sample-and-hold), the conversion speed per pin is increased to 28 AD cycles for 8-bit resolution or 33 AD cycles for 10-bit resolution. Sample-and-hold is effective in all operation modes. Select whether or not to use the sample-and-hold function before starting A-D conversion. (c) Extended Analog Input Pins In one-shot and repeat modes, the ANEX0 and ANEX1 pins can be used as analog input pins. Use the ADCON1 register's OPA1 to OPA0 bits to select whether or not use ANEX0 and ANEX1. The A-D conversion results of ANEX0 and ANEX1 inputs are stored in the AD0 and AD1 registers, respectively. (d) External Operation Amp Connection Mode Multiple analog inputs can be amplified using a single external op-amp via the ANXE0 and ANEX1 pins. Set the ADCON1 register's OPA1 to OPA0 bits to "112" (external op-amp connection mode). The inputs from ANi (i = 0 to 7) (Note) are output from the ANEX0 pin. Amplify this output with an external op-amp before sending it back to the ANEX1 pin. The A-D conversion result is stored in the corresponding ADi register. The A-D conversion speed depends on the response characteristics of the external op-amp. Note that the ANXE0 and ANEX1 pins cannot be directly connected to each other. Figure 1.16.9 shows an example of how to connect the pins in external operation amp. Note: AN0i and AN2i can be used the same as ANi. Microcomputer ADCON2 register's ADGSEL1 to ADGSEL0 bits=002 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Resistor ladder Successive conversion register ADGSEL1 to ADGSEL0 bits=102 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 ADGSEL1 to ADGSEL0 bits=112 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 ANEX0 ANEX1 External op-amp Figure 1.16.9 External Op-amp Connection Rev.1.00 2003.05.30 page 201 Comparator Under development This document is under development and its contents are subject to change. M16C/6N4 Group A-D Converter (e) Current Consumption Reducing Function When not using the A-D converter, its resistor ladder and reference voltage input pin (VREF) can be separated using the ADCON1 register's VCUT bit. When separated, no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip. To use the A-D converter, set the VCUT bit to "1" (VREF connected) and then set the ADCON0 register's ADST bit to "1" (A-D conversion start). The VCUT and ADST bits cannot be set to "1" at the same time. Nor can the VCUT bit be set to "0" (VREF unconnected) during A-D conversion. Note that this does not affect VREF for the D-A converter (irrelevant). (f) Analog Input Pin and External Sensor Equivalent Circuit Example Figure 1.16.10 shows analog input pin and external sensor equivalent circuit example. Microcomputer Sensor equivalent circuit R0 VIN R Sampling time C VC Sample-and-hold function enabled: 3 fAD Sample-and-hold function disabled: 2 fAD Figure 1.16.10 Analog Input Pin and External Sensor Equivalent Circuit Rev.1.00 2003.05.30 page 202 Under development This document is under development and its contents are subject to change. M16C/6N4 Group D-A Converter D-A Converter This is an 8-bit, R-2R type D-A converter. These are two independent D-A converters. D-A conversion is performed by writing to the DAi register (i = 0, 1). To output the result of conversion, set the DACON register's DAiE bit to "1" (output enabled). Before D-A conversion can be used, the corresponding port direction bit must be set to "0" (input mode). Setting the DAiE bit to "1" removes a pull-up from the corresponding port. Output analog voltage (V) is determined by a set value (n : decimal) in the DAi register. V = VREF n/ 256 (n = 0 to 255) VREF : reference voltage Table 1.17.1 lists the performance of the D-A converter. Figure 1.17.1 shows the block diagram of the D-A converter. Figure 1.17.2 shows the D-A converter-related registers. Figure 1.17.3 shows the D-A converter equivalent circuit. Table 1.17.1 D-A Converter Performance Item D-A conversion method R-2R method Resolution 8 bits Analog output pin 2 (DA0 and DA1) Performance Data bus low-order DA0 register DA0 R-2R ladder resistor DA0E bit DA1 register DA1 R-2R ladder resistor DA1E bit Figure 1.17.1 D-A Converter Block Diagram Rev.1.00 2003.05.30 page 203 Under development This document is under development and its contents are subject to change. M16C/6N4 Group D-A Converter D-A control register (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset DACON 03DC16 0016 Bit symbol Bit name Function DA0E D-A0 output enable bit 0 : Output disabled 1 : Output enabled DA1E D-A1 output enable bit 0 : Output disabled 1 : Output enabled (b7-b2) RW RW RW Nothing is assigned. When write, set to "0". When read, their contents are "0". - Note: When not using the D-A converter, set the DAiE bit (i = 0, 1) to "0" (output disabled) to reduce the unnecessary current consumption in the chip and set the DAi register to "0016" to prevent current from flowing into the R-2R resistor ladder. D-Ai register (Note) (i = 0, 1) b7 b0 Symbol Address DA0 DA1 03D816 03DA16 After reset Indeterminate Indeterminate Function RW RW Output value of D-A conversion Note: When not using the D-A converter, set the DAiE bit (i = 0, 1) to "0" (output disabled) to reduce the unnecessary current consumption in the chip and set the DAi register to "0016" to prevent current from flowing into the R-2R resistor ladder. Figure 1.17.2 DACON Register, DA0 Register and DA1 Register DAiE bit R "0" R R R R R R R 2R DAi "1" 2R 2R 2R 2R MSB "1" AVSS VREF i = 0, 1 Note: The above diagram shows an instance in which the DAi register is assigned "2A16". Figure 1.17.3 D-A Converter Equivalent Circuit Rev.1.00 2003.05.30 2R 2R 2R LSB DAi register "0" 2R page 204 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CRC Calculation CRC Calculation The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a 16 12 5 generator polynomial of CRC-CCITT (X + X + X + 1) to generate CRC code. The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8-bit unit. After the initial value is set in the CRCD register, the CRC code is set in that register each time one byte of data is written to the CRCIN register. CRC code generation for one-byte data is finished in two cycles. Figure 1.18.1 shows the block diagram of the CRC circuit. Figure 1.18.2 shows the CRC-related registers. Figure 1.18.3 shows the calculation example using the CRC operation. Data bus high-order Data bus low-order Low-order 8 bits High-order 8 bits CRCD register CRC code generating circuit x16 +x12 +x5 +1 CRCIN register Figure 1.18.1 CRC Circuit Block Diagram CRC data register (b15) b7 (b8) b0 b7 b0 Symbol Address CRCD 03BD16-03BC16 Function After reset Indeterminate Setting range When data is written to the CRCIN register after setting the initial value in the CRCD register, the CRC code can be read out from the CRCD register. RW 000016 to FFFF16 RW CRC input register b7 b0 Symbol Address CRCIN 03BE16 Function Data input Figure 1.18.2 CRCD Register and CRCIN Register Rev.1.00 2003.05.30 page 205 After reset Indeterminate Setting range RW 0016 to FF16 RW Under development This document is under development and its contents are subject to change. M16C/6N4 Group CRC Calculation Setup procedure and CRC operation when generating CRC code "80C416" (a) CRC operation performed by the M16C CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is divided by the generator polynomial Generator polynomial: X16 + X12 + X5 + 1 (1 0001 0000 0010 00012) (b) Setting procedure (1) Reverse the bit positions of the value "80C416" bytewise in a program. "8016" "0116", "C416" "2316" b15 b0 (2) Write 000016 (initial value) CRCD register b7 b0 (3) Write 0116 CRCIN register Two cycles later, the CRC code for "8016," i.e., 918816, has its bit positions reversed to become "118916" which is stored in the CRCD register. b0 b15 CRCD register 118916 b7 b0 (4) Write 2316 CRCIN register Two cycles later, the CRC code for "80C416," i.e., 825016, has its bit positions reversed to become "0A4116" which is stored in the CRCD register. b15 b0 CRCD register 0A4116 (c) Details of CRC operation In the case of (3) above, the value written to the CRCIN register "0116 (000000012)" has its bit positions reversed to become "100000002". The value "1000 0000 0000 0000 0000 00002" derived from that by adding 16 digits and the CRCD register s initial value "000016" are added, the result of which is divided by the generator polynomial using modulo-2 arithmetic. Modulo-2 operation is operation that complies with the law given below. 1000 1000 1 0001 0000 0010 0001 1000 0000 0000 0000 1000 1000 0001 0000 Generator polynomial 1000 0001 0000 1000 1000 0001 1001 0001 0000 1 1000 0000 1000 0000 0 1 1000 Data 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1 CRC code The value "0001 0001 1000 10012 (118916)" derived from the remainder "1001 0001 1000 10002 (918816)" by reversing its bit positions may be read from the CRCD register. If operation (4) above is performed subsequently, the value written to the CRCIN register "2316 (001000112)" has its bit positions reversed to become "110001002". The value "1100 0100 0000 0000 0000 00002" derived from that by adding 16 digits and the remainder in (3) "1001 0001 1000 10002" which is left in the CRCD register are added, the result of which is divided by the generator polynomial using modulo-2 arithmetic. The value "0000 1010 0100 00012 (0A4116)" derived from the remainder by reversing its bit positions may be read from the CRCD register. Figure 1.18.3 CRC Calculation Rev.1.00 2003.05.30 page 206 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CAN Module The CAN (Controller Area Network) module for the M16C/6N4 group of microcomputers is a communication controller implementing the CAN 2.0B protocol as defined in the BOSCH specification. The M16C/6N4 group contains two CAN modules which can transmit and receive messages in both standard (11-bit) ID and extended (29-bit) ID formats. Figure 1.19.1 shows a block diagram of the CAN module. External CAN bus driver and receiver are required. Data Bus CiCONR Register CiCTLR Register CiGMR Register CiIDR Register CiLMAR Register CiMCTLj Register CiLMBR Register CTX Message Box slots 0 to 15 Protocol Controller Acceptance Filter slots 0 to 15 16 Bit Timer CRX CiTSR Register Message ID DLC Message Data Time Stamp Wake Up Function Interrupt Generation Function CiRECR Register CiTECR Register CiSTR Register CiSSTR Register CiICR Register CANi Successful Reception Int CANi Successful Transmission Int CANi Error Int Data Bus CANi Wake Up Int i = 0, 1 j = 0 to 15 Figure 1.19.1 Block Diagram of CAN Module CTx/CRx: Protocol controller: CAN I/O pins. This controller handles the bus arbitration and the CAN protocol services, i.e. bit timing, stuffing, error status etc. Message box: This memory block consists of 16 slots that can be configured either as transmitter or receiver. Each slot contains an individual ID, data length code, a data field (8 bytes) and a time stamp. Acceptance filter: This block performs filtering operation for received messages. For the filtering operation, the CiGMR register (i = 0, 1), the CiLMAR register, or the CiLMBR register is used. 16 bit timer: Used for the time stamp function. When the received message is stored in the message memory, the timer value is stored as a time stamp. Wake up function: CAN0/1 wake up interrupt is generated by a message from the CAN bus. Interrupt generation function: The interrupt events are provided by the CAN module. CANi successful reception interrupt, CANi successful transmission interrupt, CAN0/1 error interrupt, and CAN0/1 wake up interrupt. Rev.1.00 2003.05.30 page 207 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CAN Module-Related Registers The CANi (i = 0, 1) modules have the following registers. (1) CAN Message Box A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as Basic CAN. * Priority of the slots: The smaller the number of the slot, the higher the priority, in both transmission and reception. * A program can define whether a slot is defined as transmitter or receiver. (2) Acceptance Mask Registers A CAN module is equipped with 3 masks for the acceptance filter. * CANi global mask register (CiGMR register: 6 bytes) Configuration of the masking condition for acceptance filtering processing to slots 0 to 13 * CANi local mask A register (CiLMAR register: 6 bytes) Configuration of the masking condition for acceptance filtering processing to slot 14 * CANi local mask B register (CiLMBR register: 6 bytes) Configuration of the masking condition for acceptance filtering processing to slot 15 (3) CAN SFR Registers * CANi message control register j (CiMCTLj register: 8 bits 16) (j = 0 to 15) Control of transmission and reception of a corresponding slot * CANi control register (CiCTLR register: 16 bits) Control of the CAN protocol * CANi status register (CiSTR register: 16 bits) Indication of the protocol status * CANi slot status register (CiSSTR register: 16 bits) Indication of the status of contents of each slot * CANi interrupt control register (CiICR register: 16 bits) Selection of "interrupt enabled or disabled" for each slot * CANi extended ID register (CiIDR register: 16 bits) Selection of ID format (standard or extended) for each slot * CANi configuration register (CiCONR register: 16 bits) Configuration of the bus timing * CANi receive error count register (CiRECR register: 8 bits) Indication of the error status of the CAN module in reception: the counter value is incremented or decremented according to the error occurrence. * CANi transmit error count register (CiTECR register: 8 bits) Indication of the error status of the CAN module in transmission: the counter value is incremented or decremented according to the error occurrence. * CANi time stamp register (CiTSR register: 16 bits) Indication of the value of the time stamp counter * CANi acceptance filter support register (CiAFS register: 16 bits) Decoding the received ID for use by the acceptance filter support unit Explanation of each register is given below. Rev.1.00 2003.05.30 page 208 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CANi Message Box (i = 0, 1) Table 1.19.1 shows the memory mapping of the CANi message box. It is possible to access to the message box in byte or word. Mapping of the message contents differs from byte access to word access. Byte access or word access can be selected by the MsgOrder bit of the CiCTLR register. Table 1.19.1 Memory Mapping of CANi Message Box (n = 0 to 15: the number of the slot) Address Message content (Memory mapping) CAN0 CAN1 Byte access (8 bits) Word access (16 bits) 006016 + n *16 + 0 026016 + n *16 + 0 SID10 to SID6 SID5 to SID0 006016 + n *16 + 1 026016 + n *16 + 1 SID5 to SID0 SID10 to SID6 006016 + n *16 + 2 026016 + n *16 + 2 EID17 to EID14 EID13 to EID6 006016 + n *16 + 3 026016 + n *16 + 3 EID13 to EID6 EID17 to EID14 006016 + n *16 + 4 026016 + n *16 + 4 EID5 to EID0 Data Length Code (DLC) Data Length Code (DLC) 006016 + n *16 + 5 026016 + n *16 + 5 006016 + n *16 + 6 026016 + n *16 + 6 Data byte 0 Data byte 1 006016 + n *16 + 7 026016 + n *16 + 7 Data byte 1 Data byte 0 006016 + n *16 + 13 006016 + n *16 + 14 026016 + n *16 + 13 026016 + n *16 + 14 Data byte 7 Time stamp high-order byte Data byte 6 Time stamp low-order byte 006016 + n *16 + 15 026016 + n *16 + 15 Time stamp low-order byte Time stamp high-order byte i = 0, 1 Rev.1.00 2003.05.30 page 209 EID5 to EID0 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module Figures 1.19.2 and 1.19.3 show the bit mapping in each slot in byte access and word access. The content of each slot remains unchanged unless transmission or reception of a new message is performed. Bit 7 Bit 0 SID 5 EID13 EID12 SID10 SID 9 SID 8 SID 7 SID 6 SID 4 SID 3 SID 2 SID 1 SID 0 EID17 EID16 EID15 EID14 EID11 EID10 EID 9 EID 8 EID 7 EID 6 EID 5 EID 4 EID 3 EID 2 EID 1 EID 0 DLC3 DLC2 DLC1 DLC0 Data Byte 0 Data Byte 1 Data Byte 7 Time Stamp high-order byte Time Stamp low-order byte CAN Data Frame: SID10 to 6 SID5 to 0 EID17 to 14 EID13 to 6 EID5 to 0 DLC3 to 0 Data Byte 0 Data Byte 1 Data Byte 7 is read, the value is the one written upon the transmission slot configuration. Note: When The value is "0" when read on the reception slot configuration. Figure 1.19.2 Bit Mapping in Byte Access Bit 15 Bit 8 Bit 7 Bit 0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID 1 SID0 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID 7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 DLC3 DLC 2 DLC1 DLC0 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Time Stamp high-order byte Time Stamp low-order byte CAN Data Frame: SID10 to 6 SID5 to 0 Note: When EID17 to 14 EID13 to 6 EID5 to 0 DLC3 to 0 Data Byte 0 is read, the value is the one written upon the transmission slot configuration. The value is "0" when read on the reception slot configuration. Figure 1.19.3 Bit Mapping in Word Access Rev.1.00 2003.05.30 Data Byte 1 page 210 Data Byte 7 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module Acceptance Mask Registers Figures 1.19.4 and 1.19.5 show the CiGMR register (i = 0, 1), the CiLMAR register, and the CiLMBR register, in which bit mapping in byte access and word access are shown. Bit 7 Bit 0 SID5 EID13 EID12 EID12 EID12 SID9 SID8 SID7 SID6 016016 036016 SID4 SID3 SID2 SID1 SID0 016116 036116 EID17 EID16 EID15 EID14 016216 036216 EID10 EID9 EID8 EID7 EID6 016316 036316 EID5 EID4 EID3 EID2 EID1 EID0 016416 036416 SID10 SID9 SID8 SID7 SID6 016616 036616 SID4 SID3 SID2 SID1 SID0 016716 036716 EID17 EID16 EID15 EID14 016816 036816 EID11 EID10 EID9 EID8 EID7 EID6 016916 036916 EID5 EID4 EID3 EID2 EID1 EID0 016A16 036A16 SID10 SID9 SID8 SID7 SID6 016C16 036C16 SID4 SID3 SID2 SID1 SID0 016D16 036D16 EID17 EID16 EID15 EID14 016E16 036E16 SID5 EID13 SID10 EID11 SID5 EID13 Addresses CAN0 CAN1 EID11 EID10 EID9 EID8 EID7 EID6 016F16 036F16 EID5 EID4 EID3 EID2 EID1 EID0 017016 037016 CiGMR register CiLMAR register CiLMBR register i = 0, 1 Figure 1.19.4 Bit Mapping of Mask Registers in Byte Access Bit 15 Bit 8 Bit 7 Bit 0 SID5 SID4 SID3 SID2 SID1 SID0 016016 036016 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 016216 036216 016416 036416 SID5 SID4 SID3 SID2 SID1 SID0 016616 036616 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 016816 036816 016A16 036A16 SID5 SID4 SID3 SID2 SID1 SID0 016C16 036C16 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 016E16 036E16 017016 037016 SID10 SID9 SID8 SID7 SID6 EID5 EID4 EID3 EID2 EID1 EID0 SID10 SID9 SID8 SID7 SID6 EID5 EID4 EID3 EID2 EID1 EID0 SID10 SID9 SID8 SID7 SID6 EID5 EID4 EID3 EID2 EID1 EID0 i = 0, 1 Figure 1.19.5 Bit Mapping of Mask Registers in Word Access Rev.1.00 2003.05.30 Addresses CAN0 CAN1 page 211 CiGMR register CiLMAR register CiLMBR register Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CAN SFR Registers CiMCTLj Register (i = 0, 1, j = 0 to 15) Figure 1.19.6 shows the CiMCTLj register. CANi message control register j (i = 0, 1, j = 0 to 15) (Note 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0MCTL0 to C0MCTL15 C1MCTL0 to C1MCTL15 Bit symbol Address After reset 0016 0016 020016 to 020F16 022016 to 022F16 Bit name Function (Note 4) RW NewData Successful reception flag When set to reception slot 0: The content of the slot is read or still under RO processing by the CPU. (Note 1) 1 The CAN module has stored new data in the slot. SentData Successful transmission flag When set to transmission slot 0: Transmission is not started or completed yet. 1: Transmission is successfully completed. InvalData "Under reception" When set to reception slot flag 0: The message is valid. 1: The message is invalid. (The message is being updated.) RO "Under When set to transmission slot transmission" flag 0: Waiting for bus idle or completion of arbitration. 1: Transmitting RO TrmActive RO (Note 1) MsgLost Overwrite flag When set to reception slot 0: No message has been overwritten in this slot. RO 1: This slot already contained a message, but it has (Note 1) been overwritten by a new one. RemActive Remote frame transmission/ reception status flag (Note 2) 0: Data frame transmission/reception status 1: Remote frame automatic transfer status Transmission/ reception auto response lock mode select bit When set to reception remote frame slot 0: After a remote frame is received, it will be answered automatically. 1: After a remote frame is received, no transmission will be started as long as this bit is set to "1". (Not responding) Remote frame corresponding slot select bit 0: Slot not corresponding to remote frame 1: Slot corresponding to remote frame RW Reception slot request bit (Note 3) 0: Not reception slot 1: Reception slot RW Transmission slot request bit (Note 3) 0: Not transmission slot 1: Transmission slot RW RspLock Remote RecReq TrmReq RW RW Note 1: As for write, only writing "0" is possible. The value of each bit is written when the CAN module enters the respective state. Note 2: In Basic CAN mode, they serve as data format identification flag. Refer to "Basic CAN Mode" for more details. Note 3: One slot cannot be defined as reception slot and transmission slot at the same time. Note 4: This register can not be set in CAN reset/initialization mode of the CAN module. Figure 1.19.6 CiMCTLj Register Rev.1.00 2003.05.30 page 212 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CiCTLR Register (i = 0, 1) Figure 1.19.7 shows the CiCTLR register. CANi control register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0CTLR C1CTLR Bit symbol Address 021016 After reset X00000012 X00000012 023016 Bit name Function RW Reset CAN module reset bit 0: Operation mode 1: Reset/initialization mode RW LoopBack Loop back mode select bit 0: Normal operation mode 1: Loop back mode RW MsgOrder Message order select bit 0: Word access 1: Byte access RW BasicCAN Basic CAN mode select bit 0: Normal operation mode 1: Basic CAN mode RW BusErrEn Bus error interrupt enable bit 0: Bus error interrupt disabled 1: Bus error interrupt enabled RW Sleep Sleep mode select bit 0: Sleep mode disabled 1: Sleep mode enabled; clock supply stopped RW PortEn CAN port enable bit 0: I/O port function 1: CTx/CRx function (Note) RW - Nothing is assigned. When write, set to "0". When read, its content is indeterminate. (b7) - Note: CTx/CRx function regardless of configuration of PD7 and PD9 registers. (b15) b7 b6 b5 b4 b3 b2 b1 (b8) b0 Symbol C0CTLR C1CTLR Bit symbol TSPreScale Bit1, Bit0 Address 021116 023116 After reset XX0X00002 XX0X00002 Bit name Function RW b1 b0 Time stamp prescaler 0 0: Period of 1 bit time 0 1: Period of 1/2 bit time 1 0: Period of 1/4 bit time 1 1: Period of 1/8 bit time RW TSReset Time stamp counter 0: Normal operation mode reset bit (Note 1) 1: Force reset of the time stamp counter RW RetBusOff Return from bus off 0: Normal operation mode command bit 1: Force return from bus off RW (Note 2) (b4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RXOnly Listen-only mode select bit - Nothing is assigned. When write, set to "0". When read, its content is indeterminate. (b7-b6) 0: Normal operation mode 1: Listen-only mode RW - Note 1: When the TSReset bit = 1, the CiTSR register is set to "000016". After this, the bit is automatically set to "0". Note 2: When the RetBusOff bit = 1, the CiRECR register and the CiTECR register are set to "0016". After this, the bit is automatically set to "0". Figure 1.19.7 CiCTLR Register Rev.1.00 2003.05.30 page 213 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CiSTR Register (i = 0, 1) Figure 1.19.8 shows the CiSTR register. CANi status register (i = 0, 1) (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0STR C1STR Bit symbol MBOX Address 021216 023216 After reset 0016 0016 Bit name Active slot bits Function RW b3 b2 b1 b0 0 0 0 0 : Slot 0 0 0 0 1 : Slot 1 0 0. 1 0 : Slot 2 .. 1 1 1 0 : Slot 14 1 1 1 1 : Slot 15 RO Successful transmission flag 0: No [successful] transmission 1: The CAN module has transmitted a message successfully. RO RecSucc Successful reception flag 0: No [successful] reception 1: CAN module received a message successfully. RO TrmState Transmission flag (Transmitter) 0: CAN module is idle or receiver. 1: CAN module is transmitter. RO RecState Reception flag (Receiver) 0: CAN module is idle or transmitter. 1: CAN module is receiver. RO TrmSucc Note: This register can not be set in CAN reset/initialization mode of the CAN module. (b15) b7 b6 b5 b4 b3 b2 b1 (b8) b0 Symbol C0STR C1STR Rev.1.00 2003.05.30 page 214 After reset X00000012 X00000012 Bit symbol Bit name State_Reset Reset state flag 0: Operation mode 1: Reset mode RO State_ LoopBack Loop back state flag 0: Normal operation mode 1: Loop back mode RO State_ MsgOrder Message order state flag 0:Word access 1: Byte access RO State_ BasicCAN Basic CAN mode state flag 0: Normal operation mode 1: Basic CAN mode RO State_ BusError Bus error state flag 0: No error has occurred. 1: A CAN bus error has occurred. RO State_ ErrPass Error passive state flag 0: The CAN module is not in error passive state. 1: The CAN module is in error passive state. RO State_ BusOff Error bus off state flag 0: The CAN module is not in error bus off state. 1: The CAN module is in error bus off state. RO - Nothing is assigned. When write, set to "0". When read, its content is indeterminate. (b7) Figure 1.19.8 CiSTR Register Address 021316 023316 Function RW - Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CiSSTR Register (i = 0, 1) Figure 1.19.9 shows the CiSSTR register. CANi slot status register (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol C0SSTR C1SSTR Address 021516, 021416 023516, 023416 Function Slot status bits Each bit corresponds to the slot with the same number. After reset 000016 000016 Setting values 0: Reception slot The message has been read. Transmission slot Transmission is not completed. 1: Reception slot The message has not been read. Transmission slot Transmission is completed. Figure 1.19.9 CiSSTR Register Rev.1.00 2003.05.30 page 215 RW RO Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CiICR Register (i = 0, 1) Figure 1.19.10 shows the CiICR register. CANi interrupt control register (i = 0, 1) (Note) (b15) b7 (b8) b0 b7 b0 Symbol C0ICR C1ICR Address 021716, 021616 023716, 023616 After reset 000016 000016 Function Setting values 0: Interrupt disabled Interrupt enable bits: 1: Interrupt enabled Each bit corresponds with a slot with the same number. Enabled/disabled of successful transmission interrupt or successful reception interrupt can be selected. RW RW Note: This register can not be set in CAN reset/initialization mode of the CAN module. Figure 1.19.10 CiICR Register CiIDR Register Figure 1.19.11 shows the CiIDR register. CANi extended ID register (i = 0, 1) (Note) (b15) b7 (b8) b0 b7 b0 Symbol C0IDR C1IDR Address 021916, 021816 023916, 023816 After reset 000016 000016 Function Extended ID bits: Each bit corresponds with a slot with the same number. Selection of the ID format that each slot handles. Note: This bit can not be set in CAN reset/initialization mode of the CAN module. Figure 1.19.11 CiIDR Register Rev.1.00 2003.05.30 page 216 Setting values 0: Standard ID 1: Extended ID RW RW Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CiCONR Register (i = 0, 1) Figure 1.19.12 shows the CiCONR register. CANi configuration register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0CONR C1CONR Bit symbol BRP Address 021A16 023A16 After reset Indeterminate Indeterminate Bit name Prescaler division ratio select bits Function RW b3 b2 b1 b0 0 0 0 0 : Divide-by-1 of fCAN 0 0 0 1 : Divide-by-2 of fCAN 0 0 1 0 : Divide-by-3 of fCAN ..... RW 1 1 1 0 : Divide-by-15 of fCAN 1 1 1 1 : Divide-by-16 of fCAN SAM Sampling control bit 0 : One time sampling 1 : Three times sampling PTS Propagation time segment control bits b7 b6 b5 (Note) RW 0 0 0 : 1Tq 0 0 1 : 2Tq 0 1 0 : 2Tq ..... RW 1 1 0 : 7Tq 1 1 1 : 8Tq Note: fCAN serves for the CAN clock. The period is decided by configuration of the CCLKi bits (i = 0 to 2 and 4 to 6) of CCLKR register. (b15) b7 b6 b5 b4 b3 b2 b1 (b8) b0 Symbol C0CONR C1CONR Bit symbol PBS1 Address 021B16 023B16 After reset Indeterminate Indeterminate Bit name Phase buffer segment 1 control bits Function RW b2 b1b0 0 0 0 : Inhibited 0 0 1 : 2Tq 0 1 0 : 3Tq RW ..... 1 1 0 : 7Tq 1 1 1 : 8Tq PBS2 Phase buffer segment 2 control bits b5 b4 b3 ..... 0 0 0 : Inhibited 0 0 1 : 2Tq 0 1 0 : 3Tq RW 1 1 0 : 7Tq 1 1 1 : 8Tq SJW Figure 1.19.12 CiCONR Register Rev.1.00 2003.05.30 page 217 Resynchronization jump width control bits b7 b6 0 0 1 1 0 : 1Tq 1 : 2Tq 0 : 3Tq 1 : 4Tq RW Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CiRECR Register (i = 0, 1) Figure 1.19.13 shows the CiRECR register. CANi receive error count register (i = 0, 1) (Note 2) b7 b0 Symbol C0RECR C1RECR Address 021C16 023C16 After reset 0016 0016 Counter value Function Reception error counting function The value is incremented or decremented according to the CAN module's error status. 0016 to FF16 (Note 1) RW RO Note 1: The value is indeterminate in bus off state. Note 2: This register can not be set in CAN reset/initialization mode of the CAN module. Figure 1.19.13 CiRECR Register CiTECR Register (i = 0, 1) Figure 1.19.14 shows the CiTECR register. CANi transmit error count register (i = 0, 1) (Note) b7 b0 Symbol C0TECR C1TECR Address 021D16 023D16 After reset 0016 0016 Function Transmission error counting function The value is incremented or decremented according to the CAN module's error status. Note: This register can not be set in CAN reset/initialization mode of the CAN module. Figure 1.19.14 CiTECR Register Rev.1.00 2003.05.30 page 218 Counter value 0016 to FF16 RW RO Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CiTSR Register (i = 0, 1) Figure 1.19.15 shows the CiTSR register. CANi time stamp register (i = 0, 1) (Note) (b15) b7 (b8) b0 b7 b0 Symbol C0TSR C1TSR Address 021F16, 021E16 023F16, 023E16 After reset 000016 000016 Function Setting range Time stamp function 000016 to FFFF16 RW RO Note: This register can not be set in CAN reset/initialization mode of the CAN module. Figure 1.19.15 CiTSR Register CiAFS Register (i = 0, 1) Figure 1.19.16 shows the CiAFS register. CANi acceptance filter support register (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol C0AFS C1AFS Address 024316 , 024216 024516 , 024416 Function Write the content equivalent to the standard frame ID of the received message. The value is "converted standard frame ID" when read. Figure 1.19.16 CiAFS Register Rev.1.00 2003.05.30 page 219 After reset Indeterminate Indeterminate Setting values RW Standard frame ID RW Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module Operational Modes The CAN module has the following three operational modes. * CAN Reset/Initialization Mode * CAN Sleep Mode * CAN Operation Mode Figure 1.19.17 shows transition between operational modes. MCU Reset Reset = 0 Sleep mode Reset = 1 Reset = 1 TEC > 255 Operation mode (State_Reset = 0) RetBusOff = 1 Sleep = 1 Sleep = 0 Reset/initialization mode (State_Reset = 1) Bus off state (State_BusOff = 1) Figure 1.19.17 Transition Between Operational Modes CAN Reset/Initialization Mode The CAN reset/initialization mode is activated upon MCU reset or by setting the Reset bit of the CiCTLR register (i = 0, 1). It can be observed by reading the State_Reset bit of the CiSTR register. Entering the CAN reset/initialization mode initiates the following functions by the module: * Suspend all communication functions. When the CAN reset/initialization mode is activated during an ongoing transmission in operation mode, the module suspends the mode transition until completion of the transmission (successful, arbitration loss, or error detection) and then sets the State_Reset bit. * Initialization of CiMCTLj (j = 0 to 15), CiSTR, CiICR, CiIDR,CiRECR, CiTECR and CiTSR registers to their reset values. All these registers are locked to prevent CPU modification. * The CiCTLR and CiCONR registers and the message box retain their contents and are available for CPU access. Rev.1.00 2003.05.30 page 220 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CAN Operation Mode The CAN operation mode is activated by clearing the Reset bit of the CiCTLR register. Entering the operation mode initiates the following functions by the module: * The module's communication functions are released and it becomes an active node on the network and may transmit and receive CAN messages. * Release the internal fault confinement logic including receive and transmit error counters. The module may leave the CAN operation mode depending on the error counts. Within the CAN operation mode the module may be in three different sub modes, depending on which type of communication functions are performed: * Module idle: The modules receive and transmit sections are inactive. * Module receives: The module receives a CAN message sent by another node. * Module transmits: The module transmits a CAN message. The module may receive its own message simultaneously when the loopback function is enabled. Figure 1.19.18 shows sub modes of the CAN operation mode. Module idle TrmState = 0 RecState = 0 Start transmission Finish transmission Detect an SOF Finish reception Module transmits Module receives TrmState = 1 RecState = 0 TrmState = 0 RecState = 1 Lost in arbitration Figure 1.19.18 Sub Modes of CAN Operation Mode CAN Sleep Mode The CAN sleep mode is activated by setting the Sleep bit of the CiCTLR register. It should never be activated from the CAN operation mode but only via the CAN reset/initialization mode. Entering the CAN sleep mode instantly stops the modules clock supply and thereby reduces power dissipation. Bus off State The bus off state is entered according to the fault confinement rules of the CAN specification. It can be quit instantly to error active state by setting the RetBusOff bit of the CiCTLR register to "1" (force return from buss off) and CAN communication becomes possible again. This does not alter any CAN registers, except CiRECR and CiTECR registers. Rev.1.00 2003.05.30 page 221 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module Configuration of the CAN Module System Clock The M16C/6N4 group has a CAN module system clock select circuit dedicated to each channel. Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the BRP bits of the CiCONR registers (i = 0, 1). For the CCLKR register, refer to "Clock Generation Circuit". Figure 1.19.19 shows a block diagram of the clock generation circuit of the CAN module system. XIN Divider Value: 1, 2, 4, 8, 16 Divide-by-1 of XIN (undivided) Divide-by-2 of XIN Divide-by-4 of XIN Divide-by-8 of XIN Divide-by-16 of XIN Prescaler fCAN 1/2 Prescaler for baud rate fCANCLK Division by (P + 1) CCLKR register CAN module i = 0, 1 CAN module system clock fCAN: P: The value written in the BRP bit of the CiCONR register. P = 0 to 15 fCANCLK: CAN communication clock fCANCLK = fCAN/2(P + 1) Figure 1.19.19 Block Diagram of CAN Module System Clock Generation Circuit CAN Bus Timing Control Bit Timing Configuration The bit time consists of the following four segments: * Synchronization segment (SS) This serves for monitoring a falling edge for synchronization. * Propagation time segment (PTS) This segment absorbs physical delay on the CAN network which amounts to double the total sum of delay on the CAN bus, the input comparator delay, and the output driver delay. * Phase buffer segment 1 (PBS1) This serves for compensating the phase error. When the falling edge of the bit falls later than expected, the segment can become longer by the maximum of the value defined in SJW. * Phase buffer segment 2 (PBS2) This segment has the same function as the phase buffer segment 1. When the falling edge of the bit falls earlier than expected, the segment can become shorter by the maximum of the value defined in SJW. Figure 1.19.20 shows the bit timing. Bit time SS PTS PBS2 PBS1 SJW SJW Sampling point The range of each segment: Bit time = 8 to 25Tq SS = 1Tq PTS = 1Tq to 8Tq PBS1 = 2Tq to 8Tq PBS2 = 2Tq to 8Tq SJW = 1Tq to 4Tq Figure 1.19.20. Bit Timing Rev.1.00 2003.05.30 page 222 Configuration of PBS1 and PBS2: PBS1 PBS2 PBS1 SJW PBS2 2 when SJW = 1 PBS2 SJW when 2 SJW 4 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module Baud Rate Baud rate depends on XIN, the division value of the CAN module system clock, the division value of the prescaler for baud rate, and the number of Tq of one bit. Table 1.19.2 shows the examples of baud rate. Table 1.19.2 Examples of Baud Rate Baud rate 20 MHz 16 MHz 10 MHz 8 MHz 1 Mbps 10Tq (1) 8Tq (1) 500 kbps 10Tq (2) 8Tq (2) 10Tq (1) 8Tq (1) 20Tq (1) 16Tq (1) 125 kbps 10Tq (8) 8Tq (8) 10Tq (4) 8Tq (4) 20Tq (4) 16Tq (4) 20Tq (2) 16Tq (2) 83.3 kbps 10Tq (12) 8Tq (12) 10Tq (6) 8Tq (6) 20Tq (6) 16Tq (6) 20Tq (3) 16Tq (3) 33.3 kbps 10Tq (30) 8Tq (30) 10Tq (15) 8Tq (15) 20Tq (15) 16Tq (15) Note: The number in ( ) indicates a value of "fCAN division value" multiplied by "division value of the prescaler for baud rate". Calculation of Baud Rate XIN 2 "fCAN division value (Note 1)" "division value of prescaler for baud rate (Note 2)" "number of Tq of one bit" Note 1: fCAN division value = 1, 2, 4, 8, 16 fCAN division value: a value selected in the CCLKR register Note 2: Division value of prescaler for baud rate = P + 1 (P: 0 to 15) P: a value selected in the BRP bit of the CiCONR register (i = 0, 1) Rev.1.00 2003.05.30 page 223 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module Acceptance Filtering Function and Masking Function These functions serve the users to select and receive a facultative message. The CiGMR register (i =0, 1), the CiLMAR register, and the CiLMBR register can perform masking to the standard ID and the extended ID of 29 bits. The CiGMR register corresponds to slots 0 to 13, the CiLMAR register corresponds to slot 14, and the CiLMBR register corresponds to slot 15. The masking function becomes valid to 11 bits or 29 bits of a received ID according to the value in the corresponding slot of the CiIDR register upon acceptance filtering operation. When the masking function is employed, it is possible to receive a certain range of IDs. Figure 1.19.21 shows correspondence of the mask registers and slots, Figure 1.19.22 shows the acceptance function. CiGMR register Slot #0 Slot #1 Slot #2 Slot #3 Slot #4 Slot #5 Slot #6 Slot #7 Slot #8 Slot #9 Slot #10 Slot #11 Slot #12 Slot #13 CiLMAR register CiLMBR register Slot #14 Slot #15 i = 0, 1 Figure 1.19.21 Correspondence of Mask Registers to Slots ID stored in ID of the the slot received message The value of the mask register Mask Bit Values 0: ID (to which the received message corresponds) match is handled as "Don't care". 1: ID (to which the received message corresponds) match is checked. Acceptance Signal Acceptance judge signal 0: The CAN module ignores the current incoming message. (Not stored in any slot) 1: The CAN module stores the current incoming message in a slot of which ID matches. Figure 1.19.22 Acceptance Function When using the acceptance function, note the following points. (1) When one ID is defined in two slots, the one with a smaller number alone is valid. (2) When it is configured that slots 14 and 15 receive all IDs with Basic CAN mode, slots 14 and 15 receive all IDs which are not stored into slots 0 to 13. Rev.1.00 2003.05.30 page 224 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module Acceptance Filter Support Unit (ASU) The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search. The IDs to receive are registered in the data table; a received ID is stored in the CiAFS register (i = 0, 1), and table search is performed with a decoded received ID. The acceptance filter support unit can be used for the IDs of the standard frame only. The acceptance filter support unit is valid in the following cases. * When the ID to receive cannot be masked by the acceptance filter. (Example) IDs to receive: 07816, 08716, 11116 * When there are too many IDs to receive; it would take too much time to filter them by software. Figure 1.19.23 shows the write and read of CiAFS register in word access. Bit 15 Addresses CAN0 CAN1 Bit 8 Bit 7 When write SID10 SID9 SID 8 SID7 SID 6 Bit 0 SID5 SID 4 SID3 SID 2 SID1 SID 0 24216 24416 3/8 Decoder Bit 15 Bit 8 When read Bit 7 Figure 1.19.23 Write/read of CiAFS Register in Word Access Rev.1.00 2003.05.30 Bit 0 SID10 SID9 SID8 SID 7 SID6 SID 5 SID4 SID 3 page 225 24216 24416 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module Basic CAN Mode When the BasicCAN bit of the CiCTLR register (i = 0, 1) is set to "1", slots 14 and 15 correspond to Basic CAN mode. When slots 14 and 15 are defined as reception slots in Basic CAN mode, received messages are stored in slots 14 and 15 alternately. Figure 1.19.24 shows the operation of slots 14 and 15 in Basic CAN mode. Slot 14 Slot 15 Empty Locked (empty) Msg n Msg n Locked (empty) Locked (Msg n) Msg n + 1 Msg n+1 Msg n+2 (Msg n lost) Locked (Msg n+1) Msg n+2 Figure 1.19.24 Operation of Slots 14 and 15 in Basic CAN Mode When configuring Basic CAN mode, note the following points. (1) Selection of Basic CAN mode has to be done in reset/initialization mode. (2) Select the same ID for slots 14 and 15. Also, configuration of the CiLMAR register and that of the CiLMBR register has to be the same. (3) Define slots 14 and 15 as reception slot only. (4) There is no protection available against message overwrite. A message can be overwritten by a new message. (5) Slots 0 to 13 can be used in the same way as in normal CAN operation mode. Rev.1.00 2003.05.30 page 226 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module Return from Bus off Function When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by the return from bus off function of the CiCTLR register (i = 0, 1). At this time, the error state changes from bus off state to error active state. Implementation of this function initializes the protocol controller. However, registers of the CAN module such as CiCONR register and the content of each slot are not initialized. Time Stamp Counter and Time Stamp Function When the CiTSR register is read, the value of the time stamp counter at the moment is read. The period of the time stamp counter reference clock is the same as that of 1 bit time that is configured by the CiCONR register. The time stamp counter functions as a free run counter. The 1 bit time period can be divided by 1 (undivided), 2, 4 or 8 to produce the time stamp counter reference clock. Use the TSPreScale bits 1 and 0 of the CiCTLR register to select the divide-by-n value. The time stamp counter is equipped with a register that captures the counter value when the protocol controller regards it as a successful reception. The captured value is stored when a time stamp value is stored in a reception slot. Listen-Only Mode When the RXOnly bit of the CiCTLR register is set to "1", the module enters listen-only mode. In listen-only mode, no transmission -- data frames, error frames, and ACK response -- is performed to bus. Rev.1.00 2003.05.30 page 227 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module Reception and Transmission Configuration of CAN Reception and Transmission Mode Table 1.19.3 shows configuration of CAN reception and transmission mode. Table 1.19.3 Configuration of CAN Reception and Transmission Mode TrmReq RecReq 0 0 0 1 0 0 Configured as a reception slot for a data frame. 1 0 1 0 Configured as a transmission slot for a remote frame. (At this time the RemActive bit is "1".) After completion of transmission, this functions as a reception slot for a data frame. (At this time the RemActive bit is "0".) However, when an ID that matches on the CAN bus is detected before remote frame transmission, this immediately functions as a reception slot for a data frame. 1 0 0 0 Configured as a transmission slot for a data frame. 0 1 1 1/0 Remote RspLock Communication mode of the slot Communication environment configuration mode: configure the communication mode of the slot. Configured as a reception slot for a remote frame. (At this time the RemActive bit is "1".) After completion of reception, this functions as a transmission slot for a data frame. (At this time the RemActive bit is "0".) However, transmission does not start as long as RspLock bit remains "1"; thus no automatic remote frame response. Response (transmission) starts when RspLock bit is set to "0". RemActive bit, RspLock bit: CiMCTLj register's bits (i = 0, 1, j = 0 to 15) When configuring a slot as a reception slot, note the following points. (1) Before configuring a slot as a reception slot, be sure to set the CiMCTLj registers (i = 0, 1, j = 0 to 15) to "0016". (2) A received message is stored in a slot that matches the condition first according to the result of reception mode configuration and acceptance filtering operation. Upon deciding in which slot to store, the smaller the number of the slot is, the higher priority it has. (3) In normal CAN operation mode, when a CAN module transmits a message of which ID matches, the CAN module never receives the transmitted data. In loop back mode, however, the CAN module receives back the transmitted data. In this case, the module does not return ACK. When configuring a slot as a transmission slot, note the following points. (1) Before configuring a slot as a transmission slot, be sure to set the CiMCTLj registers to "0016". (2) Set the TrmReq bit in the CiMCTLj register to "0" (not transmission slot) before rewriting a transmission slot. (3) A transmission slot should not be rewritten when the TrmActive bit in the CiMCTLj register is "1" (transmitting). If it is rewritten, an indeterminate data will be transmitted. Rev.1.00 2003.05.30 page 228 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module Reception Figure 1.19.25 shows the behavior of the module when receiving two consecutive CAN messages, that fit into the slot of the shown CiMCTLj register (i =0, 1, j = 0 to 15) and leads to losing/overwriting of the first message. SOF ACK EOF IF SOF ACK EOF IF CANbus InvalData bit (2) NewData bit (2) (5) (4) (5) MsgLost bit CANi Successful Reception Interrupt (5) (3) (1) RecSucc bit MBOX bit Receive slot No. CiSTR register RecState bit CiMCTLj register RecReq bit i = 0, 1 j = 0 to 15 Figure 1.19.25 Timing of Receive Data Frame Sequence 1) On monitoring a SOF on the CAN bus the RecState bit in the CiSTR register (i = 0, 1) becomes "1" (CAN module is receiver) immediately, given the module has no transmission pending (refer to "Transmission"). 2) After successful reception of the message the NewData bit in the CiMCTLj register (j = 0 to 15) of the receiving slot becomes "1" (stored new data in slot). The InvalData bit in the CiMCTLj register becomes "1" (message is being updated) at the same time and the InvalData bit becomes "0" (message is valid) again after the complete message was transferred to the slot. 3) When the interrupt enable bit in the CiICR register of the receiving slot = 1 (interrupt enabled), the successful reception interrupt request is occurred and the MBOX bit in the CiSTR register changes. It shows the slot number where the message was stored and the RecSucc bit in the CiSTR register is active. 4) After reading out the message out of the slot, the CPU should set the New Data bit to "0" (the content of the slot is read or still under processing by the CPU). 5) If the NewData bit is not set to "0" by the CPU and the Receive request for the slot is not disabled before the next successful reception of a CAN message that is fitting in this slot the MsgLost bit in the CiMCTLj register becomes "1" (message has been overwritten). The new received message is transferred to the slot. The interrupt request and change of the CiSTR register is same as in 3). Rev.1.00 2003.05.30 page 229 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module Transmission Figure 1.19.26 shows the timing of the transmit sequence. SOF ACK EOF IF SOF (1) (4) B TrmActive bit (2) (2)A (3b) SentData bit (3b) CANi Successful Transmission Interrupt (3b) TrmState bit (2) (2)A TrmSucc bit MBOX bit (3b) Transmission slot No. CiSTR register TrmReq bit CiMCTLj register CTx i = 0, 1 j = 0 to 15 Figure 1.19.26 Timing of Transmit Sequence 1) If one or more of the slots of a module has a request for transmission, the module attempts to start the transmission at the next possible time (depending on the bus condition). 2) The TrmActive bit in the CiMCTLj register (i = 0, 1, j = 0 to 15) of the lowest slot with transmit request is set to "1" (transmitting). Also the TrmState bit in the CiSTR register is set to "1" (transmitter). If the arbitration is lost against another CAN node both bits are set to "0" (idle) again (A). 3a) When the arbitration was won, but the transmission was not successful; The module will attempt to re-transmit. 3b) When the arbitration was won and the transmission has been successful; The SentData bit in the CiMCTLj register is set to "1" (transmission is successfully completed) and TrmSucc bit in the CiSTR register is set to "1" (transmitted a message successfully). If the according interrupt enable bit in the CiICR register is "1", the successful transmission interrupt request is occurred. The number of the slot that was transmitted can be found in MBOX bit in the CiSTR register. 4) After a successful transmission, the module will not attempt to send the slot again until it is reactivated. To reactivate a slot for transmission, first the TrmReq bit in the CiMCTLj register has to be set to "0" (not transmission slot). Then the Sent Data bit in the CiMCTLj register can be set to "0" (transmission is not started or completed yet) and the TrmReq bit is can be set to "1" (transmission slot) again (B). Note that the SentData bit is locked and cannot be set to "0" as long as TrmReq bit =1. Rev.1.00 2003.05.30 page 230 Under development This document is under development and its contents are subject to change. M16C/6N4 Group CAN Module CAN Interrupts The CAN module provides the following CAN interrupts. * CAN0 Successful Reception Interrupt * CAN0 Successful Transmission Interrupt * CAN1 Successful Reception Interrupt * CAN1 Successful Transmission Interrupt * CAN0/1 Error Interrupt Error Passive State Error BusOff State Bus Error (this feature can be disabled separately) * CAN0/1 Wake Up Interrupt When the CPU detects a successful reception/transmission interrupt request, the MBOX bit in the CiSTR register (i = 0, 1) must be read to determine which slot has generated the interrupt request. Rev.1.00 2003.05.30 page 231 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Programmable I/O Ports Programmable I/O Ports The programmable input/output ports (hereafter referred to simply as "I/O ports") consist of 87 lines P0 to P10 (except P85). Each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high every 4 lines. P85 is an input-only port and does not have a pull_______ ______ up resistor. Port P85 shares the pin with NMI, so that the NMI input level can be read from the P8 register P8_5 bit. Figures 1.20.1 to 1.20.5 show the I/O ports. Figure 1.20.6 shows the I/O pins. Each pin functions as an I/O port, a peripheral function input/output, or a bus control pin. For details on how to set peripheral functions, refer to each functional description in this manual. If any pin is used as a peripheral function input or D-A converter output pin, set the direction bit for that pin to "0" (input mode). Any pin used as an output pin for peripheral functions other than the D-A converter is directed for output no matter how the corresponding direction bit is set. When using any pin as a bus control pin, refer to "Bus Control." (1) Port Pi Direction Register (PDi Register, i = 0 to 10) Figure 1.20.7 shows the PDi register. This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one for one to each port. During memory expansion and microprocessor modes, the PDi registers for the pins functioning as bus _______ _________ ______ __________________ _________ _________ _________ control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK) cannot be modified. No direction register bit for P85 is available. (2) Port Pi Register (Pi Register, i = 0 to 10) Figure 1.20.8 shows the Pi register. Data input/output to and from external devices are accomplished by reading and writing to the Pi register. The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. The data written to the port latch is output from the pin. The bits in the Pi register correspond one for one to each port. During memory expansion and microprocessor modes, the PDi registers for the pins functioning as bus _______ _________ ______ __________________ _________ _________ _________ control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK) cannot be modified. (3) Pull-up Control Register j (PURj Register, j = 0 to 2) Figure 1.20.9 shows the PURj register. The PURj register bits can be used to select whether or not to pull the corresponding port high in 4 bit units. The port selected to be pulled high has a pull-up resistor connected to it when the direction bit is set for input mode. However, the pull-up control register has no effect on P0 to P3, P40 to P43, and P5 during memory expansion and microprocessor modes. Although the register contents can be modified, no pull-up resistors are connected. (4) Port Control Register (PCR Register) Figure 1.20.10 shows the PCR register. When the P1 register is read after setting the PCR register's PCR0 bit to "1", the corresponding port latch can be read no matter how the PD1 register is set. Tables 1.20.1 and 1.20.2 list an example connection of unused pins. Figure 1.20.11 shows an example connection of unused pins. Rev.1.00 2003.05.30 page 232 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Programmable I/O Ports Pull-up selection Direction register P00 to P07, P20 to P27 (inside dotted-line included) Port latch Data bus (Note) P30 to P37, P40 to P47, P50 to P54, P56 (inside dotted-line not included) Analog input Pull-up selection Direction register P10 to P14 Port P1 control register Port latch Data bus (Note) Pull-up selection Direction register P15 to P17 Port P1 control register Data bus Port latch (Note) Input to respective peripheral functions Pull-up selection Direction register P57, P60, P64, P70 , P73 to P76, P80, P81, P90, P92 "1" Output Data bus Port latch (Note) Input to respective peripheral functions Note: Figure 1.20.1 I/O Ports (1) Rev.1.00 2003.05.30 page 233 symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Under development This document is under development and its contents are subject to change. M16C/6N4 Group Programmable I/O Ports Pull-up selection Direction register P61, P65, P72 "1" Output Data bus Port latch Switching between CMOS and Nch (Note) Input to respective peripheral functions Pull-up selection Direction register P82 to P84 Port latch Data bus (Note) Input to respective peripheral functions Pull-up selection Direction register P55, P77, P97 Port latch Data bus (Note) Input to respective peripheral functions Note: Figure 1.20.2 I/O Ports (2) Rev.1.00 2003.05.30 page 234 symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Under development This document is under development and its contents are subject to change. M16C/6N4 Group Programmable I/O Ports Pull-up selection Direction register P62, P66 Port latch Data bus (Note 1) Switching between CMOS and Nch Input to respective peripheral functions Pull-up selection Direction register P63, P67 "1" Port latch Data bus Output (Note 1) Switching between CMOS and Nch P85 Data bus NMI interrupt input (Note 1) Direction register P71, P91 "1" Output Data bus Port latch (Note 2) Input to respective peripheral functions Note 1: symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Note 2: symbolizes a parasitic diode. Figure 1.20.3 I/O Ports (3) Rev.1.00 2003.05.30 page 235 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Programmable I/O Ports Pull-up selection P100 to P103 (inside dotted-line not included) P104 to P107 (inside dotted-line included) Direction register Port latch Data bus (Note) Analog input Input to respective peripheral functions Pull-up selection D-A output enabled Direction register P93, P94 Data bus Port latch (Note) Input to respective peripheral functions Analog output D-A output enabled Pull-up selection Direction register P96 "1" Port latch Data bus Output (Note) Analog input Pull-up selection Direction register P95 "1" Output Data bus Port latch (Note) Input to respective peripheral functions Analog input Note: Figure 1.20.4 I/O Ports (4) Rev.1.00 2003.05.30 page 236 symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Under development This document is under development and its contents are subject to change. M16C/6N4 Group Programmable I/O Ports Pull-up selection Direction register P87 Data bus Port latch (Note) fc Rf Pull-up selection Rd Direction register P86 "1" Data bus Port latch Output (Note) Note: symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 1.20.5 I/O Ports (5) (Note 1) BYTE BYTE signal input (Note 2) (Note 1) CNVSS CNVSS signal input (Note 2) RESET RESET signal input (Note 2) Note 1: A parasitic diode on the VCC side is added to the mask ROM version. Make sure the input voltage on each port will not exceed Vcc. Note 2: symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 1.20.6 I/O Pins Rev.1.00 2003.05.30 page 237 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Programmable I/O Ports Port Pi direction register (i = 0 to 7, 9, 10) (Notes 1, 2) b7 b6 b5 b4 b3 b2 b1 Symbol PD0 to PD3 PD4 to PD7 PD9, PD10 b0 Bit symbol Address 03E216, 03E316, 03E616, 03E716 03EA16, 03EB16, 03EE16, 03EF16 03F316, 03F616 After reset 0016 0016 0016 Function RW RW 0 : Input mode (Functions as an input port) PDi_1 Port Pi1 direction bit RW 1 : Output mode Port Pi2 direction bit PDi_2 RW (Functions as an output port) Port Pi3 direction bit PDi_3 RW (i = 0 to 7, 9, 10) Port Pi4 direction bit PDi_4 RW Port Pi5 direction bit PDi_5 RW Port Pi6 direction bit PDi_6 RW Port Pi7 direction bit PDi_7 RW Note 1: Make sure the PD7 and PD9 registers are written to by the next instruction after setting the PRCR register's PRC2 bit to "1" (write enabled). Note 2: During memory expansion and microprocessor modes, the PD register for the pins functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK) cannot be modified. PDi_0 Bit name Port Pi0 direction bit Port P8 direction register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD8 Bit symbol Port P80 direction bit PD8_1 Port P81 direction bit PD8_2 Port P82 direction bit PD8_3 Port P83 direction bit PD8_4 Port P84 direction bit page 238 After reset 00X000002 Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. PD8_6 Port P86 direction bit PD8_7 Port P87 direction bit Figure 1.20.7 PD0 to PD10 Registers 2003.05.30 Bit name PD8_0 (b5) Rev.1.00 Address 03F216 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) RW RW RW RW RW RW RW RW Under development This document is under development and its contents are subject to change. M16C/6N4 Group Programmable I/O Ports Port Pi register (i = 0 to 7, 9, 10) (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol P0 to P3 P4 to P7 P9, P10 Bit symbol Address 03E016, 03E116, 03E416, 03E516 03E816, 03E916, 03EC16, 03ED16 03F116, 03F416 After reset Indeterminate Indeterminate Indeterminate Function RW RW Pi_1 Port Pi1 bit RW Port Pi2 bit Pi_2 RW Port Pi3 bit Pi_3 RW Port Pi4 bit Pi_4 RW Port Pi5 bit Pi_5 RW Port Pi6 bit Pi_6 RW (i = 0 to 7, 9, 10) Port Pi7 bit Pi_7 RW Note 1: During memory expansion and microprocessor modes, the Pi register for the pins functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK) cannot be modified. Note 2: Since P71 and P91 are N channel open-drain ports, the data is high-impedance. Pi_0 Bit name Port Pi0 bit The pin level on any I/O port which is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port which is set for output mode can be controlled by writing to the corresponding bit in this register. 0 : "L" level 1 : "H" level (Note 2) Port P8 register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P8 Bit symbol 2003.05.30 page 239 Bit name P8_0 Port P80 bit P8_1 Port P81 bit Pi8_2 Port P82 bit P8_3 Port P83 bit P8_4 Port P84 bit P8_5 Port P85 bit P8_6 Port P86 bit P8_7 Port P87 bit Figure 1.20.8 P0 to P10 Registers Rev.1.00 Address 03F016 After reset Indeterminate Function The pin level on any I/O port which is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port which is set for output mode can be controlled by writing to the corresponding bit in this register. (Except for P85.) 0 : "L" level 1 : "H" level RW RW RW RW RW RW RO RW RW Under development This document is under development and its contents are subject to change. M16C/6N4 Group Programmable I/O Ports Pull-up control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Bit symbol Address 03FC16 After reset 0016 Function RW RW PU01 P04 to P07 pull-up RW P10 to P13 pull-up PU02 RW P14 to P17 pull-up PU03 RW P20 to P23 pull-up PU04 RW P24 to P27 pull-up PU05 RW P30 to P33 pull-up PU06 RW P34 to P37 pull-up PU07 RW Note 1: During memory expansion and microprocessor modes, the pins are not pulled high although their corresponding register contents can be modified. Note 2: The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high. PU00 Bit name P00 to P03 pull-up 0 : Not pulled high 1 : Pulled high (Note 2) Pull-up control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR1 Address 03FD16 After reset (Note 1) 000000002 000000102 Bit symbol Bit name RW Function PU10 P40 to P43 pull-up (Note 2) RW 0 : Not pulled high 1 : Pulled high (Note 5) PU11 P44 to P47 pull-up (Note 3) RW P50 to P53 pull-up (Note 2) PU12 RW P54 to P57 pull-up (Note 2) PU13 RW P60 to P63 pull-up PU14 RW P64 to P67 pull-up PU15 RW P70, P72 and P73 pull-up (Note 4) PU16 RW P74 to P77 pull-up PU17 RW Note 1: The values after hardware reset is as follows: 000000002 when input on CNVss pin is "L". 000000102 when input on CNVss pin is "H". The values after software reset, watchdog timer reset and oscillation stop detection reset are as follows: 000000002 when PM 01 to PM00 bits of PM0 register are "002" (single-chip mode). 000000102 when PM 01 to PM00 bits of PM0 register are "012" (memory expansion mode) or "112" (microprocessor mode). Note 2: During memory expansion and microprocessor modes, the pins are not pulled high although their corresponding register contents can be modified. Note 3: If the PM01 to PM00 bits are set to "012" (memory expansion mode) or "112" (microprocessor mode) in a program during single-chip mode, the PU11 bit becomes "1". Note 4: The P71 pin does not have pull-up. Note 5: The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high. Symbol PUR2 Address 03FE16 Pull-up control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Bit symbol Bit name PU20 P80 to P83 pull-up PU21 P84 to P87 pull-up (Note 1) PU22 P90, P92 and P93 pull-up (Note 2) PU23 P94 to P97 pull-up PU24 P100 to P103 pull-up PU25 - P104 to P107 pull-up (b7-b6) After reset 0016 Function 0 : Not pulled high 1 : Pulled high (Note 3) Nothing is assigned. When write, set to "0". When read, its content is "0". RW RW RW RW RW RW RW - Note 1: The P85 pin does not have pull-up. Note 2: The P91 pin does not have pull-up. Note 3: The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high. Figure 1.20.9 PUR0 to PUR2 Registers Rev.1.00 2003.05.30 page 240 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Programmable I/O Ports Port control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PCR Bit symbol PCR0 (b7-b1) Figure 1.20.10 PCR Register Rev.1.00 2003.05.30 page 241 Address 03FF16 Bit name Port P1 control bit After reset 0016 Function RW Operation performed when the P1 register is read 0 : When the port is set for input, the input levels of P10 to P17 pins are read. When set for output, the port RW latch is read. 1 : The port latch is read regardless of whether the port is set for input or output. Nothing is assigned. When write, set to "0". When read, its content is "0". - Under development This document is under development and its contents are subject to change. M16C/6N4 Group Programmable I/O Ports Table 1.20.1 Unassigned Pin Handling in Single-chip Mode Pin name Ports P0 to P7, P80 to P84, Connection P86, P87, P9, P10 After setting for input mode, connect every pin to VSS via a resistor (pull-down); or after setting for output mode, leave these pins open. (Notes 1, 2, 3) XOUT (Note 4) Open _______ NMI(P85) Connect via resistor to VCC (pull-up) AVCC Connect to VCC AVSS, VREF, BYTE Connect to VSS Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input mode until it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes indeterminate, causing the power supply current to increase while the port remains in input mode. Furthermore, by considering a possibility that the contents of the direction registers could be changed by noise or noise-induced runaway, it is recommended that the contents of the direction registers be periodically reset in software, for the increased reliability of the program. Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins (within 2 cm). Note 3: When the ports P71 and P91 are set for output mode, make sure a low-level signal is output from the pins. The ports P71 and P91 are N-channel open-drain outputs. Note 4: With external clock input to XIN pin. Table 1.20.2 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode Pin name Ports P0 to P7, P80 to P84, P86, P87, P9, P10 ______ Connection After setting for input mode, connect every pin to VSS via a resistor (pull-down); or after setting for output mode, leave these pins open. (Notes 1, 2, 3, 4) ______ P45/CS1 to P47/CS3 Connect to VCC via a resistor (pulled high) by setting the PD4 register's _____ corresponding direction bit for CS i (i = 1 to 3) to "0" (input mode) and _____ the CSR register's CS i bit to "0" (chip select disabled). ________ __________ Open BHE, ALE, HLDA, XOUT (Note 5), BCLK (Note 6) ___________ ________ _______ HOLD, RDY, NMI(P85) AVCC Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS AVSS, V REF Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input mode until it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes indeterminate, causing the power supply current to increase while the port remains in input mode. Furthermore, by considering a possibility that the contents of the direction registers could be changed by noise or noise-induced runaway, it is recommended that the contents of the direction registers be periodically reset in software, for the increased reliability of the program. Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins (within 2 cm). Note 3: If the CNVSS pin has the VSS level applied to it, these pins are set for input ports until the processor mode is switched over in a program after reset. For this reason, the voltage levels on these pins become indeterminate, causing the power supply current to increase while they remain set for input ports. Note 4: When the ports P71 and P91 are set for output mode, make sure a low-level signal is output from the pins. The ports P71 and P91 are N-channel open-drain outputs. Note 5: With external clock input to XIN pin. Note 6: If the PM0 register's PM07 bit is set to "1" (BCLK not output), connect this pin to VCC via a resistor. (pulled high). Rev.1.00 2003.05.30 page 242 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Programmable I/O Ports Microcomputer Microcomputer Port P0 to P10 (Input mode) (except for P85) Port P6 to P10 (Input mode) (Input mode) (Input mode) (Output mode) (except for P85) Open VCC Port P45/CS1 to P47/CS3 NMI XOUT (Output mode) VCC Open VCC AVCC NMI BHE HLDA ALE XOUT BCLK (Note) VCC Open Open VCC HOLD BYTE RDY BYTE AVSS AVCC VREF AVSS VREF VSS In single-chip mode VSS In memory expansion mode or in microprocessor mode Note: If the PM0 register's PM07 bit is set to "1" (BCLK not output), connect this pin to VCC via a resistor (pulled high). Figure 1.20.11 Unassigned Pins Handling Rev.1.00 2003.05.30 page 243 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Electrical Characteristics Table 1.21.1 Absolute Maximum Ratings Symbol VCC1 VCC2 AVCC VI VO Pd Topr Tstg Parameter Supply voltage Supply voltage Analog supply voltage ____________ Input RESET, CNVSS, BYTE, voltage P60~P67, P70, P72~P77, P80~P87, Output voltage Power dissipation Operating ambient temperature Storage temperature 2003.05.30 Rated value Unit -0.3 to 6.5 -0.3<VCC2=VCC1 -0.3 to 6.5 -0.3 to VCC1+0.3 V V V V -0.3 to VCC2+0.3 V -0.3 to 6.5 -0.3 to VCC1+0.3 V V -0.3 to VCC2+0.3 V -0.3 to 6.5 700 -40 to 85/-40 to 125 (option) -65 to 150 V mW C C P90, P92~P97, P100~P107, VREF, XIN P00~P07, P10~P17, P20~P27, P30~P37, P40~P47, P50~P57 P71, P91 P60~P67, P70, P72~P77, P80~P84, P86, P87, P90, P92~P97, P100~P107, XOUT P00~P07, P10~P17, P20~P27, P30~P37, P40~P47, P50~P57 P71, P91 option: If you desire this option, please so specify. Rev.1.00 Condition VCC1=AVCC VCC2 VCC1=AVCC page 244 Topr=25C Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Table 1.21.2 Recommended Operating Conditions (Note 1) Symbol Parameter Min. 4.2 Standard Max. Typ. 5.0 5.5 VCC 0 0 VCC Supply voltage (VCC1=VCC2) Analog supply voltage Supply voltage Analog supply voltage 0.8VCC HIGH input P31~P37, P40~P47, P50~P57, P60~P67, voltage P70, P72~P77, P80~P87, P90, P92~P97, P100~P107, ____________ XIN, RESET, CNVSS, BYTE 0.8VCC 6.5 P71, P91 VCC P00~P07, P10~P17, P20~P27, P30 (During single-chip mode) 0.8VCC 0.5VCC VCC P00~P07, P10~P17, P20~P27, P30 (Data input during memory expansion and microprocessor modes) VIL 0 0.2VCC LOW input P31~P37, P40~P47, P50~P57, P60~P67, P70~P77, P80~P87, P90~P97, P100~P107, voltage ____________ XIN, RESET, CNVSS, BYTE 0 0.2VCC P00~P07, P10~P17, P20~P27, P30 (During single-chip mode) P00~P07, P10~P17, P20~P27, P30 0 0.16VCC (Data input during memory expansion and microprocessor modes) IOH (peak) -10.0 HIGH peak output P00~P07, P10~P17, P20~P27, P30~P37, P40~P47, P50~P57, P60~P67, P70, P72~P77, current P80~P84, P86, P87, P90, P92~P97, P100~P107 IOH (avg) -5.0 P00~P07, P10~P17, P20~P27, P30~P37, HIGH average 0 ~P4 7 , P5 0 ~P5 7 , P6 0 ~P6 7 , P7 0 , P7 2 ~P7 7 , P4 output current P80~P84, P86, P87, P90, P92~P97, P100~P107 IOL (peak) 10.0 LOW peak output P00~P07, P10~P17, P20~P27, P30~P37, P40~P47, P50~P57, P60~P67, P70~P77, current P80~P84, P86, P87, P90~P97, P100~P107 IOL (avg) P00~P07, P10~P17, P20~P27, P30~P37, 5.0 LOW average P40~P47, P50~P57, P60~P67, P70~P77, output current P80~P84, P86, P87, P90~P97, P100~P107 f(XIN) Main clock input No wait Mask ROM version VCC=4.2 to 5.5V 0 16 oscillation frequency Flash memory version (Notes 4, 5 and 6) f(XCIN) Sub clock oscillation frequency 50 32.768 f(Ring) Ring oscillation frequency 1 PLL clock oscillation frequency f(PLL) 20 0 CPU operation clock VCC=4.2 to 5.5V f(BCLK) 20 PLL frequency synthesizer stabilization wait time tsu(PLL) 20 Note 1: Referenced to VCC = 4.2 to 5.5 V at Topr = -40 to 85 C unless otherwise specified. Note 2: The mean output current is the mean value within 100 ms. Note 3: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9 and P10 must be 80mA max. The total I OL Main clock input oscillation frequency (Mask ROM, flash memory version: no wait) (peak) for ports P3, P4, P5, P6, P7 and P80 to P84 must be 80mA max. The total IOH (peak) for ports 16.0 P0, P1, and P2 must be -40mA max. The total IOH (peak) for ports P3, P4 and P5 must be -40mA max. The total IOH (peak) for ports P6, P7 and P80 to P84 must be -40mA max. The total IOH (peak) for ports P86, P87, P9 and P10 must be -40mA max. Note 4: Relationship between main clock oscillation frequency and supply voltage is shown right. 0.0 4.2 5.5 Note 5: Execute program /erase of flash memory by VCC [V] (main clock: no division) VCC = 5.0 0.5 V. Note 6: When using 16 MHz or more, use PLL clock. f(XIN) operating maximum frequency [MHz] VCC1, VCC2 AVCC VSS AVSS VIH Rev.1.00 2003.05.30 page 245 Unit V V V V V V V V V V V mA mA mA mA MHz kHz MHz MHz MHz ms Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Table 1.21.3 Electrical Characteristics (Note 1) Symbol VOH Parameter P00~P07, P10~P17, P20~P27, P30~P37, P40~P47, P50~P57, P60~P67, P70, P72~P77, P80~P84, P86, P87, P90, P92~P97, P100~P107 P00~P07, P10~P17, P20~P27, P30~P37, VOH HIGH output voltage P40~P47, P50~P57, P60~P67, P70, P72~P77, P80~P84, P86, P87, P90, P92~P97, P100~P107 XOUT HIGHPOWER VOH HIGH output voltage LOWPOWER XCOUT HIGHPOWER HIGH output voltage LOWPOWER P00~P07, P10~P17, P20~P27, P30~P37, VOL LOW output voltage P40~P47, P50~P57, P60~P67, P70~P77, P80~P84, P86, P87, P90~P97, P100~P107 P00~P07, P10~P17, P20~P27, P30~P37, VOL LOW output voltage P40~P47, P50~P57, P60~P67, P70~P77, P80~P84, P86, P87, P90~P97, P100~P107 XOUT HIGHPOWER VOL LOW output voltage LOWPOWER XCOUT HIGHPOWER LOW output voltage LOWPOWER __________ ________ HOLD, RDY, TA0 IN~TA4IN, VT+-VT- Hysteresis _______ _______ ______ __________ TB0IN~TB5IN, INT0~INT5, NMI, ADTRG, ________ ________ CTS0~CTS2, SCL, SDA, CLK0~CLK4, _____ _____ TA2 OUT~TA4OUT, KI0~KI3, RxD0~RxD2, SIN3 ____________ RESET VT+-VT- Hysteresis HIGH input P00~P07, P10~P17, P20~P27, P30~P33, IIH P40~P47, P50~P57, P60~P67, P70~P77, current P80~P8 7, P90~P97, P100~P107, ____________ XIN, RESET, CNVSS, BYTE LOW input P00~P07, P10~P17, P20~P27, P30~P33, IIL current P40~P47, P50~P57, P60~P67, P70~P77, P80~P8 7, P90~P97, P100~P107, ____________ XIN, RESET, CNVSS, BYTE P00~P07, P10~P17, P20~P27, P30~P37, RPULLUP Pull-up resistance P40~P47, P50~P57, P60~P67, P70, P72~P77, P80~P84, P86, P87, P90, P92~P97, P100~P107 Feedback resistance XIN RfXIN XCIN RfXCIN Feedback resistance RAM retention voltage VRAM In single-chip mode, Power supply current ICC the output pins are (VCC = 4.2 to 5.5V) open and other pins are VSS. HIGH output voltage Measuring condition Min. Standard Typ. Max. Unit IOH=-5mA VCC-2.0 VCC V IOH=-200A VCC-0.3 VCC V 3.0 3.0 VCC VCC V IOH=-1mA IOH=-0.5mA With no load applied With no load applied IOL=5mA 2.5 1.6 V 2.0 V IOL=200A 0.45 V IOL=1mA IOL=0.5mA With no load applied With no load applied 2.0 2.0 V 0 0 V 0.2 1.0 V 0.2 VI=5V 2.2 5.0 V A VI=0V -5.0 A 170 k 18 32 M M V mA 1 20 34 mA mA VI=0V 30 50 1.5 15 At stop mode Mask ROM f(BCLK)=20MHz, No division, PLL operation No division, Ring oscillation Flash memory f(BCLK)=20MHz, No division, PLL operation No division, Ring oscillation Flash memory f(BCLK)=10MHz, Program VCC=5V Flash memory f(BCLK)=10MHz, Erase VCC=5V Mask ROM f(XCIN)=32kHz, Low power dissipation mode, ROM (Note 2) Flash memory f(BCLK)=32kHz, Low power dissipation mode, RAM (Note 2) f(BCLK)=32kHz, Low power dissipation mode, Flash memory (Note 2) Mask ROM Ring oscillation, Wait mode Flash memory f(BCLK)=32kHz, Wait mode (Note 3), Oscillation capacity High f(BCLK)=32kHz, Wait mode (Note 3), Oscillation capacity Low Stop mode, Topr = 25 C 2.0 1.8 15 mA mA 25 mA 25 A 25 A 420 A 50 8.5 A A 3.0 A 0.8 3.0 A Note 1: Referenced to VCC = 4.2 to 5.5 V, Vss = 0 V at Topr = -40 to 85 C, f(BCLK) = 20 MHz unless otherwise specified. Note 2: This indicates the memory in which the program to be executed exists. Note 3: With one timer operated using fC32. Rev.1.00 2003.05.30 page 246 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Table 1.21.4 A-D Conversion Characteristics (Note 1) Symbol - INL Parameter Resolution Integral non-linearity error - Min. VREF=VCC VREF=VCC ANEX0, ANEX1 input, =5V AN0 to AN 7 input, AN00 to AN07 input, AN20 to AN27 input External operation amp connection mode VREF=AVCC=VCC=5V VREF=VCC ANEX0, ANEX1 input, =5V AN0 to AN7 input, AN00 to AN07 input, AN20 to AN27 input External operation amp connection mode VREF=AVCC=VCC=5V 10 bits 8 bits 10 bits Absolute accuracy Measuring condition Standard Typ. Max. 10 3 Unit Bits LSB 7 LSB 2 3 LSB LSB 7 LSB 8 bits 2 LSB Differential non-linearity error LSB 1 Offset error LSB 3 Gain error 3 LSB VREF=VCC 10 Ladder resistance k 40 3.3 Conversion time (10 bits), Sample & hold function available VREF=VCC=5V, AD=10MHz s 2.8 Conversion time (8 bits), Sample & hold function available VREF=VCC=5V, AD=10MHz s 0.3 tSAMP Sampling time s 2.0 VREF VCC Reference voltage V VIA 0 VREF Analog input voltage V Note 1: Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, -40 to 85 C unless otherwise specified. Note 2: AD operation clock frequency (AD frequency) must be 10 MHz or less. Note 3: A case without sample & hold function turn AD frequency into 250 kHz or more in addition to a limit of Note 2. A case with sample & hold function turn AD frequency into 1 MHz or more in addition to a limit of Note 2. DNL - - RLADDER tCONV Table 1.21.5 D-A conversion Characteristics (Note 1) Standard Unit Typ. Max. 8 Resolution - Bits 1.0 - Absolute accuracy % 3 tsu Setup time s 10 20 RO Output resistance 4 k IVREF 1.5 Reference power supply input current mA (Note 2) Note 1: Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, -40 to 85 C unless otherwise specified. Note 2: This applies when using one D-A converter, with the DAi register (i = 0, 1) for the unused D-A converter set to "0016". The A-D converter's ladder resistance is not included. Also, the current IVREF always flows even though VREF may have been set to be unconnected by the ADCON1 register. Symbol Measuring condition Parameter Min. Table 1.21.6 Power Supply Circuit Timing Characteristics Symbol td(P-R) td(R-S) td(W-S) td(M-L) Measuring condition Parameter Time for internal power supply stabilization during VCC = 4.2 to 5.5 V powering-on STOP release time Low power dissipation mode wait mode release time Time for internal power supply stabilization when main clock oscillation status Interrupt for stop mode releaser CPU clock td(R-S) Rev.1.00 2003.05.30 page 247 Min. Standard Typ. Max. 2 150 150 50 Unit ms s s s Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Timing Requirements (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) Table 1.21.7 External Clock Input (XIN Input) Symbol Parameter External External External External External tC tw(H) tw(L) tr tf clock clock clock clock clock input cycle time input HIGH pulse width input LOW pulse width rise time fall time Standard Min. Max. 62.5 25 25 15 15 Unit ns ns ns ns ns Table 1.21.8 Memory Expansion Mode and Microprocessor Mode Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK) tsu(HOLD-BCLK) th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) td(BCLK-HLDA) Parameter Data input access time (for setting with no wait) Data input access time (for setting with wait) Data input access time (when accessing multiplexed bus area) Data input setup time ________ RDY input setup time __________ HOLD input setup time Data input hold time ________ RDY input hold time __________ HOLD input hold time __________ HLDA output delay time Standard Unit Min. Max. (Note 1) ns (Note 2) ns (Note 3) ns ns 40 ns 30 ns 40 ns 0 ns 0 ns 0 40 ns Note 1: Calculated according to the BCLK frequency as follows: 0.5 10 - 45 [ns] f(BCLK) 9 Note 2: Calculated according to the BCLK frequency as follows: (n -0.5) 109 - 45 [ns] f(BCLK) n is "2" for 1-wait setting, "3" for 2-wait setting and "4" for 3-wait setting. Note 3: Calculated according to the BCLK frequency as follows: (n -0.5) 10 f(BCLK) 9 Rev.1.00 2003.05.30 - 45 [ns] page 248 n is "2" for 2-wait setting, "3" for 3-wait setting. Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Timing Requirements (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) Table 1.21.9 Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) tw(TAH) tw(TAL) Parameter TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Min. Max. 100 40 40 Unit ns ns ns Table 1.21.10 Timer A Input (Gating Input in Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) Parameter TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Min. Max. 400 200 200 Unit ns ns ns Table 1.21.11 Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) Parameter TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Min. Max. 200 100 100 Table 1.21.12 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Standard Symbol Parameter Min. Max. tw(TAH) TAiIN input HIGH pulse width 100 tw(TAL) TAiIN input LOW pulse width 100 Table 1.21.13 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Standard Symbol Parameter Min. Max. tc(UP) TAiOUT input cycle time 2000 tw(UPH) 1000 TAiOUT input HIGH pulse width tw(UPL) 1000 TAiOUT input LOW pulse width tsu(UP-TIN) 400 TAiOUT input setup time th(TIN-UP) 400 TAiOUT input hold time Unit ns ns ns Unit ns ns Unit ns ns ns ns ns Table 1.21.14 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN input cycle time tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time Rev.1.00 2003.05.30 page 249 Standard Min. Max. 800 200 200 Unit ns ns ns Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Timing Requirements (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) Table 1.21.15 Timer B Input (Counter Input in Event Counter Mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN TBiIN TBiIN TBiIN TBiIN TBiIN input input input input input input cycle time (counted on one edge) HIGH pulse width (counted on one edge) LOW pulse width (counted on one edge) cycle time (counted on both edges) HIGH pulse width (counted on both edges) LOW pulse width (counted on both edges) Standard Min. Max. 100 40 40 200 80 80 Unit ns ns ns ns ns ns Table 1.21.16 Timer B Input (Pulse Period Measurement Mode) Symbol tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Min. Max. 400 200 200 Unit ns ns ns Table 1.21.17 Timer B Input (Pulse Width Measurement Mode) Symbol tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Min. Max. 400 200 200 Unit ns ns ns Table 1.21.18 A-D Trigger Input Symbol Parameter __________ tC(AD) tw(ADL) AD TRG input cycle time (trigger able minimum) __________ ADTRG input LOW pulse width Standard Min. Max. 1000 125 Unit ns ns Table 1.21.19 Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Parameter CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time Standard Min. Max. 200 100 100 80 0 30 90 Unit ns ns ns ns ns ns ns _______ Table 1.21.20 External Interrupt INTi Input Symbol Parameter _______ tw(INH) tw(INL) Rev.1.00 INTi input HIGH pulse width _______ INTi input LOW pulse width 2003.05.30 page 250 Standard Min. Max. 250 250 Unit ns ns Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Switching Characteristics (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) Table 1.21.21 Memory Expansion Mode and Microprocessor Mode (for setting with no wait) Standard Measuring Symbol Parameter Unit condition Min. Max. td(BCLK-AD) Address output delay time 25 ns Figure 1.21.1 th(BCLK-AD) Address output hold time (refers to BCLK) ns 4 th(RD-AD) ns Address output hold time (refers to RD) 0 th(WR-AD) ns Address output hold time (refers to WR) (Note 1) td(BCLK-CS) Chip select output delay time ns 25 th(BCLK-CS) Chip select output hold time (refers to BCLK) ns 4 ns td(BCLK-ALE) ALE signal output delay time 25 ns th(BCLK-ALE) ALE signal output hold time -4 ns td(BCLK-RD) RD signal output delay time 25 ns th(BCLK-RD) RD signal output hold time 0 ns td(BCLK-WR) WR signal output delay time 25 ns th(BCLK-WR) WR signal output hold time 0 ns td(BCLK-DB) Data output delay time (refers to BCLK) 40 ns th(BCLK-DB) Data output hold time (refers to BCLK) (Note 3) 4 ns td(DB-WR) Data output delay time (refers to WR) (Note 2) th(WR-DB) ns Data output hold time (refers to WR) (Note 3) (Note 1) Note 1: Calculated according to the BCLK frequency as follows: 0.5 109 - 10 [ns] f(BCLK) Note 2: Calculated according to the BCLK frequency as follows: 0.5 10 - 40 [ns] f(BCLK) 9 f(BCLK) is 12.5 MHz or less. Note 3: This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = - CR ln (1 - VOL / VCC) by a circuit of the right figure. R For example, when VOL = 0.2 VCC, C = 30 pF, DBi R =1 k, hold time of output "L" level is C t = - 30 pF 1 k ln (1 - 0.2 VCC / VCC) = 6.7 ns. P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30pF Figure 1.21.1. Port P0 to P10 Measurement Circuit Rev.1.00 2003.05.30 page 251 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Switching Characteristics (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) Table 1.21.22 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access) Standard Measuring Symbol Unit Parameter condition Min. Max. td(BCLK-AD) Address output delay time 25 ns Figure 1.21.1 th(BCLK-AD) Address output hold time (refers to BCLK) ns 4 th(RD-AD) ns Address output hold time (refers to RD) 0 th(WR-AD) ns Address output hold time (refers to WR) (Note 1) td(BCLK-CS) Chip select output delay time ns 25 ns th(BCLK-CS) Chip select output hold time (refers to BCLK) 4 ns td(BCLK-ALE) ALE signal output delay time 25 ns th(BCLK-ALE) ALE signal output hold time -4 ns td(BCLK-RD) RD signal output delay time 25 ns th(BCLK-RD) RD signal output hold time 0 ns td(BCLK-WR) WR signal output delay time 25 ns th(BCLK-WR) WR signal output hold time 0 ns td(BCLK-DB) Data output delay time (refers to BCLK) 40 ns th(BCLK-DB) Data output hold time (refers to BCLK) (Note 3) 4 ns td(DB-WR) Data output delay time (refers to WR) (Note 2) ns th(WR-DB) Data output hold time (refers to WR) (Note 3) (Note 1) Note 1: Calculated according to the BCLK frequency as follows: 0.5 10 - 10 [ns] f(BCLK) 9 Note 2: Calculated according to the BCLK frequency as follows: (n - 0.5) 10 - 40 [ns] f(BCLK) 9 n is "1" for 1-wait setting, "2" for 2-wait setting and "3" for 3-wait setting. When n = 1, f(BCLK) is 12.5 MHz or less. Note 3: This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR ln (1 - VOL / VCC) by a circuit of the right figure. R For example, when VOL = 0.2 VCC, C = 30 pF, R =1 k, hold time of output "L" level is DBi C t = - 30 pF 1 k ln (1 - 0.2 VCC / VCC) = 6.7 ns. Rev.1.00 2003.05.30 page 252 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Switching Characteristics (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) Table 1.21.23 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) Standard Measuring Symbol Parameter condition Min. Max. td(BCLK-AD) Address output delay time 25 Figure 1.21.1 th(BCLK-AD) Address output hold time (refers to BCLK) 4 th(RD-AD) Address output hold time (refers to RD) (Note 1) th(WR-AD) Address output hold time (refers to WR) (Note 1) td(BCLK-CS) Chip select output delay time 25 th(BCLK-CS) Chip select output hold time (refers to BCLK) 4 th(RD-CS) Chip select output hold time (refers to RD) (Note 1) th(WR-CS) Chip select output hold time (refers to WR) (Note 1) td(BCLK-RD) RD signal output delay time 25 th(BCLK-RD) RD signal output hold time 0 td(BCLK-WR) WR signal output delay time 25 th(BCLK-WR) WR signal output hold time 0 td(BCLK-DB) Data output delay time (refers to BCLK) 40 th(BCLK-DB) Data output hold time (refers to BCLK) 4 td(DB-WR) Data output delay time (refers to WR) (Note 2) th(WR-DB) Data output hold time (refers to WR) (Note 1) td(BCLK-ALE) ALE signal output delay time (refers to BCLK) 25 th(BCLK-ALE) ALE signal output hold time (refers to BCLK) -4 td(AD-ALE) ALE signal output delay time (refers to Address) (Note 3) th(ALE-AD) ALE signal output hold time (refers to Address) (Note 4) td(AD-RD) RD signal output delay from the end of Address 0 td(AD-WR) WR signal output delay from the end of Address 0 tdZ(RD-AD) Address output floating start time 8 Note 1: Calculated according to the BCLK frequency as follows: 0.5 109 - 10 [ns] f(BCLK) Note 2: Calculated according to the BCLK frequency as follows: (n -0.5) 10 f(BCLK) 9 - 40 [ns] n is "2" for 2-wait setting, "3" for 3-wait setting. Note 3: Calculated according to the BCLK frequency as follows: 0.5 10 - 25 [ns] f(BCLK) 9 Note 4: Calculated according to the BCLK frequency as follows: 0.5 109 - 15 [ns] f(BCLK) Rev.1.00 2003.05.30 page 253 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN--UP) tsu(UP--TIN) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode tC(TA) TAiIN input tsu(TAIN--TAOUT) tsu(TAIN--TAOUT) tsu(TAOUT--TAIN) TAiOUT input tsu(TAOUT--TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C--Q) TxDi td(C--Q) tsu(D--C) RxDi tw(INL) INTi input tw(INH) Figure 1.21.2 Timing Diagram (1) Rev.1.00 2003.05.30 page 254 th(C--D) Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY--BCLK) th(BCLK--RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD--BCLK) th(BCLK--HOLD) HOLD input HLDA output td(BCLK--HLDA) td(BCLK--HLDA) Hi--Z P0, P1, P2, P3, P4, P50 to P52 Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit of PM0 register and PM11 bit of PM1 register. Measuring conditions : VCC = 5 V Input timing voltage : Determined with VIL = 1.0 V, VIH = 4.0 V Output timing voltage: Determined with VOL = 2.5 V, VOH = 2.5 V Figure 1.21.3 Timing Diagram (2) Rev.1.00 2003.05.30 page 255 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) -4ns.min 25ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 tcyc-45)ns.max Hi-Z DB tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) 25ns.max th(WR-AD) (0.5 tcyc-10)ns.min -4ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) th(BCLK-DB) 4ns.min 40ns.max Hi-Z DBi td(DB-WR) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 1.21.4 Timing Diagram (3) Rev.1.00 2003.05.30 th(WR-DB) (0.5 tcyc-40)ns.min (0.5 tcyc-10)ns.min 1 tcyc = f(BCLK) page 256 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) th(BCLK-ALE) 0ns.min -4ns.min 25ns.max ALE td(BCLK-RD) th(BCLK-RD) 0ns.min 25ns.max RD tac2(RD-DB) (1.5 tcyc-45)ns.max Hi-Z DB th(RD-DB) tSU(DB-RD) 0ns.min 40ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(WR-AD) (0.5 tcyc-10)ns.min -4ns.min 25ns.max ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) th(BCLK-DB) 4ns.min 40ns.max Hi-Z DBi td(DB-WR) 1 tcyc = f(BCLK) (0.5 tcyc-40)ns.min Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 1.21.5 Timing Diagram (4) Rev.1.00 2003.05.30 page 257 th(WR-DB) (0.5 tcyc-10)ns.min Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access ) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(RD-AD) th(BCLK-ALE) -4ns.min 0ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 25ns.max RD tac2(RD-DB) (2.5 tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min CSi 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(WR-AD) (0.5 tcyc-10)ns.min th(BCLK-ALE) -4ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max DB Hi-Z td(DB-WR) (1.5 tcyc-40)ns.min tcyc = 1 f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 1.21.6 Timing Diagram (5) Rev.1.00 th(BCLK-DB) 4ns.min 2003.05.30 page 258 th(WR-DB) (0.5 tcyc-10)ns.min Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-AD) td(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) 0ns.min th(BCLK-ALE) 25ns.max -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 25ns.max 0ns.min RD tac2(RD-DB) (3.5 tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) th(RD-DB) 40ns.min 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min td(BCLK-AD) th(BCLK-AD) 4ns.min CSi 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(WR-AD) (0.5 tcyc-10)ns.min th(BCLK-ALE) -4ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH DB td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min Hi-Z td(DB-WR) (2.5 tcyc-40)ns.min 1 tcyc = f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 1.21.7 Timing Diagram (6) Rev.1.00 2003.05.30 page 259 th(WR-DB) (0.5 tcyc-10)ns.min Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK td(BCLK-CS) th(RD-CS) (0.5 tcyc-10)ns.min tcyc 25ns.max th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 tcyc-25)ns.min ADi /DBi th(ALE-AD) (0.5 tcyc-15)ns.min Address 8ns.max Address Data input tdZ(RD-AD) tac3(RD-DB) (1.5 tcyc-45)ns.max tSU(DB-RD) th(RD-DB) 0ns.min 40ns.min td(AD-RD) 0ns.min td(BCLK-AD) th(BCLK-AD) 4ns.min 25ns.max ADi BHE td(BCLK-ALE) th(BCLK-ALE) 25ns.max th(RD-AD) (0.5 tcyc-10)ns.min -4ns.min ALE td(BCLK-RD) th(BCLK-RD) 0ns.min 25ns.max RD Write timing BCLK td(BCLK-CS) th(BCLK-CS) th(WR-CS) (0.5 tcyc-10)ns.min tcyc 25ns.max 4ns.min CSi th(BCLK-DB) td(BCLK-DB) 4ns.min 40ns.max ADi /DBi Address Data output td(DB-WR) td(AD-ALE) (1.5 tcyc-40)ns.min (0.5 tcyc-25)ns.min Address th(WR-DB) (0.5 tcyc-10)ns.min td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) td(AD-WR) -4ns.min 0ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max WR,WRL, WRH tcyc = 1 f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 1.21.8 Timing Diagram (7) Rev.1.00 2003.05.30 page 260 th(BCLK-WR) 0ns.min Under development This document is under development and its contents are subject to change. M16C/6N4 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK th(RD-CS) (0.5 tcyc-10)ns.min td(BCLK-CS) th(BCLK-CS) 4ns.min 25ns.max CSi td(AD-ALE) (0.5 tcyc-25)ns.min ADi /DB th(ALE-AD) (0.5 tcyc-15)ns.min Address td(BCLK-AD) td(AD-RD) 25ns.max ADi BHE Data input tdZ(RD-AD) 8ns.max th(RD-DB) tac3(RD-DB) (2.5 tcyc-45)ns.max 0ns.min tSU(DB-RD) 0ns.min th(BCLK-AD) 40ns.min 4ns.min (no multiplex) td(BCLK-ALE) 25ns.max th(RD-AD) th(BCLK-ALE) (0.5 tcyc-10)ns.min -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 0ns.min 25ns.max RD Write timing tcyc BCLK th(WR-CS) (0.5 tcyc-10)ns.min td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi th(BCLK-DB) td(BCLK-DB) 40ns.max ADi /DB Address 4ns.min Data output td(AD-ALE) td(DB-WR) (0.5 tcyc-25)ns.min (2.5 tcyc-40)ns.min th(WR-DB) (0.5 tcyc-10)ns.min td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE (no multiplex) td(BCLK-ALE) 25ns.max th(BCLK-ALE) th(WR-AD) -4ns.min td(AD-WR) ALE td(BCLK-WR) 25ns.max WR, WRL WRH tcyc = 1 f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 1.21.9 Timing Diagram (8) Rev.1.00 (0.5 tcyc-10)ns.min 0ns.min 2003.05.30 page 261 th(BCLK-WR) 0ns.min Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Flash Memory Flash Memory Performance The flash memory version is functionally the same as the mask ROM version except that it internally contains flash memory. The flash memory version has four modes -- CPU rewrite mode, standard serial I/O mode, parallel I/O mode and CAN I/O mode -- in which its internal flash memory can be operated on. Table 1.22.1 shows the outline performance of flash memory version (refer to "Table 1.1.1 Performance outline of M16C/6N4 Group" for the items not listed in Table 1.22.1). Table 1.22.2 shows the outline of flash memory rewrite mode. Table 1.22.1 Flash Memory Version Specifications Item Flash memory operating mode Specifications 4 modes (CPU rewrite, standard serial I/O, parallel I/O, CAN I/O) Erase block User ROM area Refer to "Figure 1.22.1 Flash Memory Block Diagram" division Boot ROM area 1 block (4 Kbytes) (Note 1) Method for program In units of word, in units of byte (Note 2) Method for erasure Collective erase, block erase Program, erase control method Program and erase controlled by software command Protect method Protected for each block by lock bit Number of commands 8 commands Number of program and erasure (Note 3) 100 times ROM code protect ion Parallel I/O , standard serial I/O and CAN I/O modes are supported. Note 1: The boot ROM area contains a standard serial I/O mode and CAN I/O mode rewrite control program which is stored in it when shipped from the factory. This area can only be rewritten in parallel I/O mode. Note 2: Can be programmed in byte units in only parallel I/O mode. Note 3: Definition of programming and erasure times The programming and erasure times are defined to be per-block erasure times. For example, assume a case where a 4K-byte block A is programmed in 2,048 operations by writing one word at a time and erased thereafter. In this case, the block is reckoned as having been programmed and erased once. If a product is guaranteed of 100 times of programming and erasure, each block in it can be erased up to 100 times. Table 1.22.2 Flash Memory Rewrite Modes Overview Flash memory CPU rewrite mode rewrite mode (Note 1) Function The user ROM area is rewritten by executing software commands from the CPU. EW0 mode: Standard serial I/O mode The user ROM area is rewritten by using a dedicated serial programmer. Standard serial I/O mode 1: Can be rewritten in any Clock synchronous area other than the flash serial I/O memory (Note 2) Standard serial I/O mode 2: EW1 mode: Can be rewritten in the UART (Note 3) Parallel I/O mode CAN I/O mode The boot ROM and user ROM areas are rewritten by using a dedicated parallel programmer. The user ROM area is rewritten by using a dedicated CAN programmer. User ROM area Boot ROM area Parallel I/O mode User ROM area Boot mode Parallel programmer CAN programmer flash memory Areas which User ROM area User ROM area can be rewritten Operation Single chip mode Boot mode mode Memory expansion mode (EW0 mode) Boot mode (EW0 mode) ROM None Serial programmer programmer Note 1: The PM13 bit remains set to "1" while the FMR01 bit in the FMR0 register = 1 (CPU rewrite mode enabled). The PM13 bit is reverted to its original value by setting the FMR01 bit to "0" (CPU rewrite mode disabled). However, if the PM13 bit is changed during CPU rewrite mode, its changed value is not reflected until after the FMR01 bit is set to "0". Note 2: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to "1". The rewrite control program can only be executed in the internal RAM or in an external area that is enabled for use when the PM13 bit = 1. Note 3: When using the standard serial I/O mode 2, make sure a main clock input oscillation frequency is set to 5 MHz, 10 MHz or 16 MHz . Rev.1.00 2003.05.30 page 262 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Memory Map The ROM in the flash memory version is separated between a user ROM area and a boot ROM area. Figure 1.22.1 shows the block diagram of flash memory. The user ROM area has a 4-Kbyte block A, in addition to the area that stores a program for microcomputer operation during singe-chip or memory expansion mode. The user ROM area is divided into several blocks, each of which can individually be protected (locked) against programming or erasure. The user ROM area can be rewritten in all of CPU rewrite, standard serial I/O mode, parallel I/O mode and CAN I/O mode. Block A is enabled for use by setting the PM1 ______ register's PM10 bit to "1" (block A enabled, CS2 area at addresses 1000016 to 26FFF16). The boot ROM area is located at addresses that overlap the user ROM area, and can only be rewritten in parallel I/O mode. After a hardware reset that is performed by applying a high-level signal to the CNVSS and P50 pins and a low-level signal to the P55 pin, the program in the boot ROM area is executed. After a hardware reset that is performed by applying a low-level signal to the CNVSS pin, the program in the user ROM area is executed (but the boot ROM area cannot be read). 00F000 16 Block A: 4 Kbytes (Note 1) 00FFFF16 Data ROM area Reserved area 0C000016 Block 8: 64 Kbytes 0CFFFF16 0D000016 0F000016 Block 5: 32 Kbytes Block 7: 64 Kbytes 0F7FFF16 0F8000 16 0DFFFF16 0E0000 16 Block 4: 8 Kbytes Block 6: 64 Kbytes 0F9FFF16 0FA00016 Block 3: 8 Kbytes 0FBFFF16 0FC00016 0EFFFF16 0F000016 Block 5 to 0 (32+8+8+8+4+4) Kbytes 0FFFFF16 Block 2: 8 Kbytes 0FDFFF16 0FE00016 0FEFFF16 0FF000 16 0FFFFF16 Block 1: 4 Kbytes Block 0: 4 Kbytes User ROM area 0FF000 16 0FFFFF16 4 Kbytes Boot ROM area (Note 2) * Shown here is a block diagram during single-chip mode. Note 1: Block A can be made usable by setting the PM1 register's PM10 bit to "1" (block A enabled, CS2 area allocated at addresses 1000016 to 26FFF16). Block A cannot be erased by the Erase All Unlocked Block command. Use the Block Erase command to erase it. Note 2: The boot ROM area can only be rewritten in parallel input/output mode. Note 3: To specify a block, use an even address in that block. Figure 1.22.1 Flash Memory Block Diagram Rev.1.00 2003.05.30 page 263 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Boot Mode After a hardware reset which is performed by applying a low-level signal to the P55 pin and a high-level signal to the CNVSS and P50 pins, the microcomputer is placed in boot mode, thereby executing the program in the boot ROM area. During boot mode, the boot ROM and user ROM areas are switched over by the FMR05 bit in the FMR0 register. The boot ROM area contains a standard serial I/O mode and CAN I/O mode based rewrite control program which was stored in it when shipped from the factory. The boot ROM area can be rewritten in parallel input/output mode. Prepare an EW0 mode based rewrite control program and write it in the boot ROM area, and the flash memory can be rewritten as suitable for the system. Functions to Prevent Flash Memory from Rewriting To prevent the flash memory from being read or rewritten easily, parallel I/O mode has a ROM code protect and standard serial I/O mode and CAN I/O mode have an ID code check function. * ROM Code Protect Function The ROM code protect function inhibits the flash memory from being read or rewritten during parallel I/O mode. Figure 1.22.2 shows the ROMCP register. The ROMCP register is located in the user ROM area. The ROMCP1 bit consists of two bits. The ROM code protect function is enabled by setting one or both of two ROMCP1 bits to "0" when the ROMCR bits are not "002", with the flash memory thereby protected against reading or rewriting. Conversely, when the ROMCR bits are "002" (ROM code protect removed), the flash memory can be read or rewritten. Once the ROM code protect function is enabled, the ROMCR bits cannot be changed during parallel I/O mode. Therefore, use standard serial I/O mode or other modes to rewrite the flash memory. * ID Code Check Function Use this function in standard serial I/O mode and CAN I/O mode. Unless the flash memory is blank, the ID codes sent from the programmer and the ID codes written in the flash memory are compared to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Prepare a program in which the ID codes are preset at these addresses and write it in the flash memory. Figure 1.22.3 shows the ID code store addresses. Rev.1.00 2003.05.30 page 264 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory ROM code protect control address b7 b6 b5 b4 b3 b2 b1 b0 Symbol ROMCP 1 1 1 1 Bit symbol (b3-b0) Address 0FFFFF16 Value when shipped FF16 (Note 1) Bit name Function Set to "1" Reserved bit RW RW b5 b4 ROMCR ROM code protect reset bit (Notes 1, 2) 0 0 : Removes protect 01: 1 0 : Enables ROOMCP1 bit 11: RW RW b7 b6 ROMCP1 ROM code protect level 1 set bit (Notes 1, 3, 4) 00: 0 1 : Protect enabled 10: 1 1 : Protect disabled RW RW Note 1: Once any of these bits is set to "0", it cannot be set back to "1". If a memory block that contains the ROMCP register is erased, the ROMCP register is set to "FF16". Note 2: If the ROMCR bits are set to "002", ROM code protect level 1 is removed. However, because the ROMCR bits cannot be modified during parallel I/O mode, they need to be modified in standard serial I/O or other modes. Note 3: If the ROMCR bits are set to other than "002" and the ROMCP1 bits are set to other than "112" (ROM code protect enabled), the flash memory is disabled against reading and rewriting in parallel input/output mode. Note 4: The ROMCP1 bits are effective when the ROMCR bits are "012", "102" or "112". Figure 1.22.2 ROMCP Register Address 0FFFDF16 to 0FFFDC16 ID1 Undefined instruction vector 0FFFE316 to 0FFFE016 ID2 Overflow vector BRK instruction vector 0FFFE716 to 0FFFE416 0FFFEB16 to 0FFFE816 ID3 Address match vector 0FFFEF16 to 0FFFEC16 ID4 Single step vector 0FFFF316 to 0FFFF016 ID5 Oscillation stop and re-oscillation detection/Watchdog timer vector 0FFFF716 to 0FFFF416 ID6 DBC vector 0FFFFB16 to 0FFFF816 ID7 NMI vector 0FFFFF16 to 0FFFFC16 ROMCP Reset vector 4 bytes Figure 1.22.3 Address for ID Code Stored Rev.1.00 2003.05.30 page 265 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board without having to use a ROM programmer, etc. In CPU rewrite mode, only the user ROM area shown in Figure 1.22.1 can be rewritten and the boot ROM area cannot be rewritten. Make sure the Program and the Block Erase commands are executed only on each block in the user ROM area. During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase Write 1 (EW1) mode. Table 1.22.3 lists the differences between EW0 and EW1 modes. Table 1.22.3 EW0 Mode and EW1 Mode Item EW0 mode Operation mode * Single chip mode * Memory expansion mode * Boot mode Areas in which a * User ROM area rewrite control * Boot ROM area program can be located Areas in which a Must be transferred to any area other rewrite control than the flash memory (e.g., RAM) program can be executed before being executed (Note 2) Areas which can be User ROM area rewritten Software command limitations None Modes after Program or Erase CPU status during Auto Write and Auto Erase Read Status Register mode Flash memory status detection EW1 mode Single chip mode User ROM area Can be executed directly in the user ROM area User ROM area However, this does not include the area in which a rewrite control program exists * Program, Block Erase command Cannot be executed on any block in which a rewrite control program exists * Erase All Unlocked Block command Cannot be executed when the lock bit for any block in which a rewrite control program exists is set to "1" (unlocked) or the FMR0 register's FMR02 bit is set to "1" (lock bit disabled) * Read Status Register command Cannot be executed Read Array mode Operating Hold state (I/O ports retain the state in which they were before the command was executed) (Note 1) *Read the FMR0 register's FMR00, Read the FMR0 register's FMR00, FMR06, and FMR07 bits in a program FMR06, and FMR07 bits in a program *Execute the Read Status Register command to read the status register's SR7, SR5, and SR4 flags. _______ Note 1: Make sure no interrupts (except NMI and watchdog timer interrupts) and DMA transfers will occur. Note 2: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to "1". The rewrite control program can only be executed in the internal RAM or in an external area that is enabled for use when the PM13 bit = 1. Rev.1.00 2003.05.30 page 266 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory * EW0 Mode The microcomputer is placed in CPU rewrite mode by setting the FMR0 register's FMR01 bit to "1" (CPU rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register's FMR11 bit = 0, EW0 mode is selected. The FMR01 bit can be set to "1" by writing "0" and then "1" in succession. Use software commands to control program and erase operations. Read the FMR0 register or status register to check the status of program or erase operation at completion. * EW1 Mode EW1 mode is selected by setting FMR11 bit to "1" (by writing "0" and then "1" in succession) after setting the FMR01 bit to "1" (by writing "0" and then "1" in succession). Read the FMR0 register to check the status of program or erase operation at completion. The status register cannot be read during EW1 mode. Rev.1.00 2003.05.30 page 267 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Figure 1.22.4 shows the FMR0 register and FMR1 register. FMR00 Bit This bit indicates the operating status of the flash memory. The bit is "0" when the Program, Erase, or Lock Bit program is running; otherwise, the bit is "1". FMR01 Bit The microcomputer is made ready to accept commands by setting the FMR01 bit to "1" (CPU rewrite mode). During boot mode, make sure the FMR05 bit also is "1" (user ROM area access). FMR02 Bit The lock bit set for each block can be disabled by setting the FMR02 bit to "1" (lock bit disabled). (Refer to "Data Protect Function".) The lock bits set are enabled by setting the FMR02 bit to "0". The FMR02 bit only disables the lock bit function and does not modify the lock bit data (lock bit status flag). However, if the Erase command is executed while the FMR02 bit is set to "1", the lock bit data changes state from "0" (locked) to "1" (unlocked) after Erase is completed. FMSTP Bit This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of current consumed in the flash memory. Setting the FMSTP bit to "1" makes the internal flash memory inaccessible. Therefore, make sure the FMSTP bit is modified in other than the flash memory area. In the following cases, set the FMSTP bit to "1": * When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit not reset to "1" (ready)) * When entering low power dissipation mode or ring oscillator low power dissipation mode Figure 1.22.7 shows a flow chart to be followed before and after entering low power dissipation mode. Note that when going to stop or wait mode, the FMR0 register does not need to be set because the power for the internal flash memory is automatically turned off and is turned back on again after returning from stop or wait mode. FMR05 Bit This bit switches between the boot ROM and user ROM areas during boot mode. Set this bit to "0" when accessing the boot ROM area (for read) or "1" (user ROM access) when accessing the user ROM area (for read, write, or erase). FMR06 Bit This is a read-only bit indicating the status of auto program operation. The bit is set to "1" when a program error occurs; otherwise, it is set to "0". For details, refer to "Full Status Check". FMR07 Bit This is a read-only bit indicating the status of auto erase operation. The bit is set to "1" when an erase error occurs; otherwise, it is set to "0". For details, refer to "Full Status Check". FMR11 Bit Setting this bit to "1" (EW1 mode) places the microcomputer in EW1 mode. FMR16 Bit This is a read-only bit indicating the execution result of the Read Lock Bit Status command. Figures 1.22.5 and 1.22.6 show the setting and resetting of EW0 mode and EW1 mode, respectively. Rev.1.00 2003.05.30 page 268 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Flash memory control register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol Address After reset FMR0 01B716 XX0000012 Bit name Bit symbol Function RW FMR00 RY/BY status flag 0 : Busy (being written or erased) (Note 1) 1 : Ready RO FMR01 CPU rewrite mode select bit (Note 2) 0 : Disables CPU rewrite mode 1 : Enables CPU rewrite mode RW FMR02 Lock bit disable select bit (Note 3) 0: Enables lock bit 1: Disables lock bit RW FMSTP Flash memory stop bit (Notes 4, 5) 0 Enables flash memory operation 1: Stops flash memory operation (placed in low power dissipation mode, flash memory initialized) RW Reserved bit Set to "0" RW - (b4) FMR05 User ROM area select bit 0 : Boot ROM area is accessed (Effective in only boot mode) 1 : User ROM area is accessed (Note 4) RW FMR06 Program status flag (Note 6) 0 : Terminated normally 1 : Terminated in error RO FMR07 Erase status flag (Note 6) 0 : Terminated normally 1 : Terminated in error RO Note 1: This status includes writing or reading with the Lock Bit Program or Read Lock Bit Status command. Note 2: To set this bit to "1", write "0" and then "1" in succession. Make sure no interrupts or no DMA transfers will occur before writing "1" after writing "0". Write to this bit when the NMI pin is in the high state. Also, while in EW0 mode, make sure this bit is modified in other than the flash memory area. To set this bit to "0", in a read array mode. Note 3: To set this bit to "1", write "0" and then "1" in succession when the FMR01 bit = 1. Make sure no interrupts or no DMA transfers will occur before writing "1" after writing "0". Note 4: Make sure this bit is modified in other than the flash memory area. Note 5: Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMSTP bit can be set to "1" by writing "1" in a program, the flash memory is neither placed in low power mode nor initialized. Note 6: This flag is set to "0" by executing the Clear Status command. Flash memory control register 1 b7 0 b6 b5 b4 0 0 b3 b2 b1 b0 Symbol Address After reset FMR1 01B516 0X00XX0X2 Bit symbol - Bit name Function RW Reserved bit The value in this bit when read is indeterminate. RO EW1 mode select bit (Note) 0 : EW0 mode 1 : EW1 mode RW Reserved bit The value in this bit when read is indeterminate. RO (b5-b4) Reserved bit Set to "0" RW FMR16 Lock bit status flag 0 : Lock 1 : Unlock RO Reserved bit Set to "0" RW (b0) FMR11 - (b3-b2) - - (b7) Note: To set this bit to "1", write "0" and then "1" in succession when the FMR01 bit = 1. Make sure no interrupts or no DMA transfers will occur before writing "1" after writing "0". Write to this bit when the NMI pin is in the high state. Note that the FMR01 and FMR11 bits both are set to "0" by setting the FMR01 bit to "0". Figure 1.22.4 FMR0 Register and FMR1 Register Rev.1.00 2003.05.30 page 269 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory EW0 mode operation procedure Rewrite control program Single-chip mode, memory expansion mode, or boot mode For only boot mode set the FMR05 bit to "1" (user ROM area access) Set CM0, CM1, and PM1 registers (Note 1) Set the FMR01 bit by writing "0" and then "1" (CPU rewrite mode enabled) (Note 2) Transfer the rewrite control program to any area other than the flash memory (Note 5) Execute software commands Jump to the rewrite control program which has been transferred to any area other than the flash memory (The subsequent processing is executed by the rewrite control program in any area other than the flash memory.) Note 1: Select 10 MHz or less for CPU clock using the CM0 register's CM06 bit and CM1 register's CM17 to CM16 bits. Also, set the PM1 register's PM17 bit to "1" (with wait state). Note 2: To set the FMR01 bit to "1", write "0" and then "1" in succession. Make sure no interrupts or no DMA transfers will occur before writing "1" after writing "0". Write to the FMR01 bit from a program in other than the flash memory. Also write only when the NMI pin is "H" level. Note 3: Disables the CPU rewrite mode after executing the Read Array command. Note 4: User ROM area is accessed when the FMR05 bit is set to "1". Note 5: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to "1". The rewrite control program can only be executed in the internal RAM or in an external area that is enabled for use when the PM13 bit = 1. Execute the Read Array command Write "0" to the FMR01 bit (CPU rewrite mode disabled) For only boot mode Write "0" to the FMR05 bit (Boot ROM area accessed) (Note 4) Jump to a specified address in the flash memory Figure 1.22.5 Setting and Resetting of EW0 Mode EW1 mode operation procedure Program in ROM Single-chip mode (Note 1) Set CM0, CM1, and PM1 registers (Note 2) Set the FMR01 bit by writing "0" and then "1" (CPU rewrite mode enabled) Set the FMR11 bit by writing "0" and then "1" (EW1 mode) (Note 3) Execute software commands Write "0" to the FMR01 bit (CPU rewrite mode disabled) Note 1: In EW1 mode, do not set the microcomputer in memory expansion or boot mode. Note 2: Select 10 MHz or less for CPU clock using the CM0 register's CM06 bit and CM1 register's CM17 to CM16 bits. Also, set the PM1 register's PM17 bit to "1" (with wait state). Note 3: To set the FMR01 bit to "1", write "0" and then "1" in succession. Make sure no interrupts or no DMA transfers will occur before writing "1" after writing "0". Also write only when the NMI pin is "H" level. Figure 1.22.6 Setting and Resetting of EW1 Mode Rev.1.00 2003.05.30 page 270 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Low power dissipation mode program Transfer a low power dissipation mode program to any area other the flash memory Set the FMR01 bit by writing "0" and then "1" (CPU rewrite mode enabled) Jump to the low power dissipation mode program which has been transferred to any area other than the flash memory (The subsequent processing is executed by a program in any area other than the flash memory.) Set FMSTP bit to "1" (flash memory stopped. Low power state) (Note 1) Switch the clock source for CPU clock. Turn main clock off. (Note 2) Process of low power dissipation mode or ring oscillator low power dissipation mode > wait until oscillation stabilizes > Turn main clock on switch the clock source for CPU clock (Note 2) Set the FMSTP bit to "0" (flash memory operation) Write "0" to the FMR01 bit (CPU rewrite mode disabled) Wait until the flash memory circuit stabilizes (tps) (Note 3) Jump to a specified address in the flash memory Note 1: Set the FMSTP bit to "1" after setting the FMR01 bit to "1" (CPU rewrite mode). Note 2: Before the clock source for CPU clock can be changed to main clock or sub clock, the clock to which to be changed must be stable. Note 3: Insert tps wait time in a program. The flash memory cannot be accessed during this wait time. Figure 1.22.7 Processing Before and After Low Power Dissipation Mode Rev.1.00 2003.05.30 page 271 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation Speed Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register. Also, set the PM17 bit in the PM1 register to "1" (with wait state). (2) Instructions to Prevent from Using The following instructions cannot be used in EW0 mode because the flash memory's internal data is referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts EW0 Mode * Any interrupt which has a vector in the variable vector table can be used providing that its vector is transferred into the RAM area. _______ * The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register are initialized when one of those interrupts occurs. The jump addresses for those interrupt service routines should be set in the fixed vector table. _______ Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. * The address match interrupt cannot be used because the flash memory's internal data is referenced. EW1 Mode * Make sure that any interrupt which has a vector in the variable vector table or address match interrupt will not be accepted during the auto program or auto erase period. * Avoid using watchdog timer interrupts. _______ * The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed vector table. _______ Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. (4) How to Access To set the FMR01, FMR02, or FMR11 bit to "1", write "0" and then "1" in succession. This is necessary to ensure that no interrupts or no DMA transfers will occur before writing "1" after writing "0". Also only _______ when NMI pin is "H" level. (5) Writing in User ROM Space EW0 Mode * If the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, consequently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial I/O, parallel I/O or CAN I/O mode should be used. EW1 Mode * Avoid rewriting any block in which the rewrite control program is stored. Rev.1.00 2003.05.30 page 272 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory (6) DMA Transfer In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register's FMR00 bit = 0 (during the auto program or auto erase period). (7) Writing Command and Data Write the command code and data at even addresses. (8) Wait Mode When shifting to wait mode, set the FMR01 bit to "0" (CPU rewrite mode disabled) before executing the WAIT instruction. (9) Stop Mode When shifting to stop mode, the following settings are required: * Set the FMR01 bit to "0" (CPU rewrite mode disabled) and disable DMA transfers before setting the CM10 bit to "1" (stop mode). * Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to "1" (stop mode) Example program BSET JMP.B 0, CM1 L1 ; Stop mode L1: Program after returning from stop mode (10) Low Power Dissipation Mode and Ring Oscillator Low Power Dissipation Mode If the CM05 bit is set to "1" (main clock stop), the following commands must not be executed. * Program * Block erase * Erase all unlocked blocks * Lock bit program Rev.1.00 2003.05.30 page 273 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Software Commands Software commands are described below. The command code and data must be read and written in 16-bit unit, to and from even addresses in the user ROM area. When writing command code, the high-order 8 bits (D15 to D8) are ignored. Table 1.22.4 lists the software commands. Table 1.22.4 Software Commands First bus cycle Software command Second bus cycle Mode Address Data (D15 to D0) Read array Write xxFF16 - - - Read status register Write xx70 16 Read SRD Clear status register Write xx50 16 - - - Program Write WA xx40 16 Write WA WD Block erase Write xx20 16 Write BA xxD016 Erase all unlocked block (Note 1) Write xxA716 Write xxD016 Lock bit program Write BA xx77 16 Write BA xxD016 Read lock bit status Write xx71 16 Write BA xxD0 16(Note 2) Mode Address Data (D15 to D0) Note 1: It is only blocks 0 to 8 that can be erased by the Erase All Unlocked Block command. Block A cannot be erased. Use the Block Erase command to erase block A. Note 2: Note that the commands in the second bus cycle are different from those of the existing M16C/6N0 group. The lock bit status is output to the FMR16 bit of the FMR1 register. Read this bit: "0" (locked), "1" (unlocked) SRD: Status register data (D7 to D0) WA: Write address (Make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle.) WD: Write data (16 bits) BA: Uppermost block address (even address, however) : Any even address in the user ROM area x: High-order 8 bits of command (ignored) Read Array Command (FF16) This command reads the flash memory. Writing "xxFF16" in the first bus cycle places the microcomputer in read array mode. Enter the read address in the next or subsequent bus cycles, and the content of the specified address can be read in 16-bit unit. Because the microcomputer remains in read array mode until another command is written, the contents of multiple addresses can be read in succession. Read Status Register Command (7016) This command reads the status register. Write "xx7016" in the first bus cycle, and the status register can be read in the second bus cycle. (Refer to "Status Register.") When reading the status register too, specify an even address in the user ROM area. Do not execute this command in EW1 mode. Rev.1.00 2003.05.30 page 274 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Clear Status Register Command (5016) This command clears the status register to "0". Write "xx5016" in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 in the status register will be set to "0". Program Command (4016) This command writes data to the flash memory in 1-word (2-byte) unit. Write "xx4016" in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle. Check the FMR00 bit in the FMR0 register to see if auto programming has finished. The FMR00 bit is "0" during auto programming and set to "1" when auto programming is completed. Check the FMR06 bit in the FMR0 register after auto programming has finished, and the result of auto programming can be known. (Refer to "Full Status Check".) Figure 1.22.8 shows an example of program flowchart. Note that each block can be disabled from being programmed by a lock bit. (Refer to "Data Protect Function".) Be careful not to write over already programmed addresses. In EW1 mode, do not execute this command on any address at which the rewrite control program is located. In EW0 mode, the microcomputer goes to read status register mode at the same time auto programming starts, making it possible to read the status register. The status register bit 7 (SR7) is set to "0" at the same time auto programming starts, and set back to "1" when auto programming finishes. In this case, the microcomputer remains in read status register mode until a read command is written next. The result of auto programming can be known by reading the status register after auto programming has finished. Start Write the command code "xx4016" to the write address Write data to the write address FMR00=1? NO YES Full status check Program completed Note: Write the command code and data at even number. Figure 1.22.8 Program Command Rev.1.00 2003.05.30 page 275 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Block Erase Write "xx2016" in the first bus cycle and write "xxD016" to the uppermost address of a block (even address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start. Check the FMR0 register's FMR00 bit to see if auto erasing has finished. The FMR00 bit is "0" during auto erasing and set to "1" when auto erasing is completed. Check the FMR0 register's FMR07 bit after auto erasing has finished, and the result of auto erasing can be known. (Refer to "Full Status Check".) Figure 1.22.9 shows an example of a block erase flowchart. Each block can be protected against erasing by a lock bit. (Refer to "Data Protect Function".) In EW1 mode, do not execute this command on any address at which the rewrite control program is located. In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing starts, making it possible to read the status register. The status register bit 7 (SR7) is set to "0" at the same time auto erasing starts, and set back to "1" when auto erasing finishes. In this case, the microcomputer remains in read status register mode until the Read Array or Read Lock Bit Status command is written next. Start Write the command code "xx2016" Write "xxD016" to the uppermost block address FMR00=1? NO YES Full status check Block erase completed Note: Write the command code and data at even number. Figure 1.22.9 Block Erase Command Rev.1.00 2003.05.30 page 276 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Erase All Unlocked Block Write "xxA716" in the first bus cycle and write "xxD016" in the second bus cycle, and all blocks except block A will be erased successively, one block at a time. Check the FMR0 register's FMR00 bit to see if auto erasing has finished. The result of the auto erase operation can be known by inspecting the FMR0 register's FMR07 bit. Each block can be protected against erasing by a lock bit. (Refer to "Data Protect Function".) In EW1 mode, do not execute this command when the lock bit for any block = 1 (unlocked) in which the rewrite control program is stored, or when the FMR0 register's FMR02 bit = 1 (lock bit disabled). In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing starts, making it possible to read the status register. The status register bit 7 (SR7) is set to "0" at the same time auto erasing starts, and set back to "1" when auto erasing finishes. In this case, the microcomputer remains in read status register mode until the Read Array or Read Lock Bit Status command is written next. Note that only blocks 0 to 8 can be erased by the Erase All Unlocked Block command. Block A cannot be erased. Use the Block Erase command to erase block A. Lock Bit Program Command (7716/D016) This command sets the lock bit for a specified block to "0" (locked). Write "xx7716" in the first bus cycle and write "xxD016" to the uppermost address of a block (even address, however) in the second bus cycle, and the lock bit for the specified block is set to "0". Make sure the address value specified in the first bus cycle is the same uppermost block address that is specified in the second bus cycle. Figure 1.22.10 shows an example of a lock bit program flowchart. The lock bit status (lock bit data) can be read using the Read Lock Bit Status command. Check the FMR0 register's FMR00 bit to see if writing has finished. For details about the lock bit function, and on how to set the lock bit to "1", refer to "Data Protect Function". Start Write command code "xx7716" to the uppermost block address Write "xxD016" to the uppermost block address FMR00=1? NO YES Full status check Lock bit program completed Note: Write the command code and data at even number. Figure 1.22.10 Lock Bit Program Command Rev.1.00 2003.05.30 page 277 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Read Lock Bit Status Command (7116) This command reads the lock bit status of a specified block. Write "xx7116" in the first bus cycle and write "xxD016" to the uppermost address of a block (even address, however) in the second bus cycle, and the lock bit status of the specified block is stored in the FMR1 register's FMR16 bit. Read the FMR16 bit after the FMR0 register's FMR00 bit is set to "1" (ready). Figure 1.22.11 shows an example of a read lock bit status flowchart. Start Write the command code "xx7116" Write "xxD016" to the uppermost block address FMR00=1? NO YES FMR16=0? NO YES Locked Not locked Note: Write the command code and data at even number . Figure 1.22.11 Read Lock Bit Status Command Rev.1.00 2003.05.30 page 278 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Data Protect Function Each block in the flash memory has a nonvolatile lock bit. The lock bit is effective when the FMR02 bit = 0 (lock bit enabled). The lock bit allows each block to be individually protected (locked) against programming and erasure. This helps to prevent data from inadvertently written to or erased from the flash memory. The following shows the relationship between the lock bit and the block status. * When the lock bit = 0, the block is locked (protected against programming and erasure). * When the lock bit = 1, the block is not locked (can be programmed or erased). The lock bit is set to "0" (locked) by executing the Lock Bit Program command, and is set to "1" (unlocked) by erasing the block. The lock bit cannot be set to "1" by a command. The lock bit status can be read using the Read Lock Bit Status command The lock bit function is disabled by setting the FMR02 bit to "1", with all blocks placed in an unlocked state. (The lock bit data itself does not change state.) Setting the FMR02 bit to "0" enables the lock bit function (lock bit data retained). If the Block Erase or Erase All Unlocked Block command is executed while the FMR02 bit = 1, the target block or all blocks are erased irrespective of how the lock bit is set. The lock bit for each block is set to "1" after completion of erasure. For details about the commands, refer to "Software Commands." Status Register The status register indicates the operating status of the flash memory and whether an erase or programming operation terminated normally or in error. The status of the status register can be known by reading the FMR0 register's FMR00, FMR06, and FMR07 bits. Table 1.22.5 shows the status register. In EW0 mode, the status register can be read in the following cases: (1) When a given even address in the user ROM area is read after writing the Read Status Register command (2) When a given even address in the user ROM area is read after executing the Program, Block Erase, Erase All Unlocked Block, or Lock Bit Program command but before executing the Read Array command. Sequencer Status (SR7 and FMR00 Bits) The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto programming, auto erase, and lock bit write, and is set to "1" (ready) at the same time the operation finishes. Erase Status (SR5 and FMR07 Bits) Refer to "Full Status Check". Program Status (SR4 and FMR06 Bits) Refer to "Full Status Check". Rev.1.00 2003.05.30 page 279 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Table 1.22.5 Status Register Contents Status register bit FMR0 register bit SR7 (D7) FMR00 Sequencer status SR6 (D6) - Reserved SR5 (D5) FMR07 Erase status Terminated normally Terminated in error 0 SR4 (D4) FMR06 Program status Terminated normally Terminated in error 0 SR3 (D3) - Reserved - - - SR2 (D2) - Reserved - - - SR1 (D1) - Reserved - - - SR0 (D0) - Reserved - - - Status name "0" "1" Busy Ready - - Value after reset 1 - Note: The FMR07 bit (SR5) and FMR06 bit (SR4) are set to "0" by executing the Clear Status Register command. When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program, Block Erase, Erase All Unlocked Block, and Lock Bit Program commands are not accepted. D7 to D0: Indicates the data bus which is read out when the Read Status Register command is executed. Rev.1.00 2003.05.30 page 280 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Full Status Check When an error occurs, the FMR0 register's FMR06 or FMR07 bits are set to "1", indicating occurrence of each specific error. Therefore, execution results can be verified by checking these status bits (full status check). Table 1.22.6 lists errors and FMR0 register status. Figure 1.22.12 shows a full status check flowchart and the action to be taken when each error occurs. Table 1.22.6 Errors and FMR0 Register Status FRM00 register (status register) status FMR07 FMR06 (SR5) (SR4) 1 1 1 0 0 1 Error Error occurrence condition Command *When any command is not written correctly sequence error *When invalid data was written other than those that can be written in the second bus cycle of the Lock Bit Program, Block Erase, or Erase All Unlocked Block command (i.e., other than "xxD016" or "xxFF16") (Note 1) Erase error *When the Block Erase command was executed on locked blocks (Note 2) *When the Block Erase or Erase All Unlocked Block command was executed on unlocked blocks but the blocks were not automatically erased correctly Program error *When the Block Erase command was executed on locked blocks (Note 2) *When the Program command was executed on unlocked blocks but the blocks were not automatically programmed correctly. *When the Lock Bit Program command was executed but not programmed correctly Note 1: Writing "xxFF16" in the second bus cycle of these commands places the microcomputer in read array mode, and the command code written in the first bus cycle is nullified. Note 2: When the FMR02 bit of FMR0 register = 1 (lock bit disabled), no error will occur under this condition. Rev.1.00 2003.05.30 page 281 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Full status check FMR06 = 1 and FMR07 = 1? YES Command sequence error (1) Execute the Clear Status Register command to set status flags to "0". (2) Reexecute the command after checking that it is entered correctly. NO FMR07 = 0? NO Erase error YES FMR06 = 0? NO YES Full status check completed Program error (1) Execute the Clear Status Register command to set the erase status flag to "0". (2) Execute the Read Lock Bit Status command to see if the lock bit for the block in error is "0". If so, set the FMR0 register s FMR02 bit to "1". (3) Reexecute the Block Erase Command or Erase All Unlocked Block command. Note 1: If the error still occurs, the block in error cannot be used. Furthermore, if the lock bit = 1 in (2) above, the block in error cannot be used either. [During programming] (1) Execute the Clear Status Register command to set the erase status flag to "0" . (2) Execute the Read Lock Bit Status command to see if the lock bit for the block in error is "0". If so, set the FMR0 register s FMR02 bit to "1". (3) Reexecute the Program command. Note 2: If the error still occurs, the block in error cannot be used. Furthermore, if the lock bit = 1 in (2) above, the block in error cannot be used either. [During lock bit programming] (1) Execute the Clear Status Register command to set the erase status flag to "0" . (2) Set the FMR0 register s FMR02 bit to "1". (3) Execute the Block Erase command to erase the block in error. (4) Reexecute the Lock Bit command. Note 3: If the error still occurs, the block in error cannot be used. Note 4: If FMR06 or FMR07 = 1, any of the Program, Block Erase, Erase All Unlocked Block, Lock Bit Program, or Read Lock Bit Status command is not accepted. Execute the Clear Status Register command before executing those commands. Figure 1.22.12 Full Status Check and Handling Procedure for Each Error Rev.1.00 2003.05.30 page 282 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Standard Serial I/O Mode In standard serial I/O mode, the user ROM area can be rewritten while the microcomputer is mounted onboard by using a serial programmer suitable for the M16C/6N4 group. For more information about serial programmers, contact the manufacturer of your serial programmer. For details on how to use, refer to the user's manual included with your serial programmer. Table 1.22.7 lists pin functions for standard serial I/O mode. Figures 1.22.13 shows pin connections for standard serial I/O mode. ID Code Check Function This function determines whether the ID codes sent from the serial programmer and those written in the flash memory match. (Refer to "Functions to Prevent Flash Memory from Rewriting".) Rev.1.00 2003.05.30 page 283 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Table 1.22.7 Pin Functions for Standard Serial I/O Mode Pin Name VCC, VSS Power input CNVSS Description I/O Apply the voltage guaranteed for Program and Erase to V CC pin and 0 V to VSS pin. CNVSS I Connect to VCC pin. RESET Reset input I Reset input pin. While RESET pin is "L" level, input 20 cycles or longer XIN Clock input I XOUT Clock output O BYTE BYTE I ____________ _____________ clock to XIN pin. Connect a ceramic resonator or crystal oscillator between X IN and XOUT pins. To input an externally generated clock, input it to X IN pin and open XOUT pin. AVCC, AVSS Connect this pin to VCC or V SS. Connect AV SS to VSS and AVCC to V CC, respectively. Analog power supply input VREF Reference voltage input I Enter the reference voltage for A-D and D-A converters from this pin. P00 to P07 Input port P0 I Input "H" or "L" level signal or open. P10 to P17 Input port P1 I Input "H" or "L" level signal or open. P20 to P27 Input port P2 I Input "H" or "L" level signal or open. P30 to P37 Input port P3 I Input "H" or "L" level signal or open. P40 to P47 Input port P4 I Input "H" or "L" level signal or open. P50 CE input I Input "H" level signal. P51 to P54, Input port P5 I Input "H" or "L" level signal or open. _____ P56, P57 ________ P55 EPM input I Input "L" level signal. P60 to P63 Input port P6 I Input "H" or "L" level signal or open. BUSY output O Standard serial I/O mode 1: BUSY signal output pin ________ P64/RTS1 Standard serial I/O mode 2: Monitors the boot program operation check signal output pin. Standard serial I/O mode 1: Serial clock input pin. P65/CLK1 SCLK input I P66/RxD1 RxD input I Serial data input pin P67/TxD1 TxD output O Serial data output pin (Note) P70 to P77 Input port P7 I Input "H" or "L" level signal or open. P80 to P84, Input port P8 I Input "H" or "L" level signal or open. I Connect this pin to VCC. I Input "H" or "L" level signal or open. I Input "H" or "L" level signal or connect to a CAN transceiver. Standard serial I/O mode 2: Input "L". P86, P87 _______ P85/NMI ________ NMI input P90 to P94, P97 Input port P9 CRx input P95/CRx0 P96/CTx0 CTx output O Input "H" level signal, open or connect to a CAN transceiver. P100 to P107 Input port P10 I Input "H" or "L" level signal or open. ___________ Note: When using standard serial input/output mode 1, the TxD pin must be held high while the RESET pin is pulled low. Therefore, connect this pin to VCC via a resistor. Because this pin is directed for data output after reset, adjust the pull-up resistance value in the system so that data transfers will not be affected. Rev.1.00 2003.05.30 page 284 Under development This document is under development and its contents are subject to change. Flash Memory 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VCC2 M16C/6N4 Group 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 M16C/6N4 Group CE EPM BUSY SCLK RXD TXD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (Flash memory version) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 VSS VCC1 CNVSS RESET Connect oscillator circuit Mode setup method Signal Value CNVss VCC1 EPM VSS RESET VSS to VCC1 CE VCC2 Package: 100P6S-A Figure 1.22.13 Pin Connections for Serial I/O Mode Rev.1.00 2003.05.30 page 285 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Example of Circuit Application in Standard Serial I/O Mode Figures 1.22.14 and 1.22.15 show example of circuit application in standard serial I/O mode 1 and mode 2, respectively. Refer to the user's manual for serial writer to handle pins controlled by a serial writer. Note that when using the standard serial I/O mode 2, make sure a main clock input oscillation frequency is set to 5 MHz, 10 MHz or 16 MHz . Microcomputer SCLK input P66/CLK1 TxD output P67/TxD1 BUSY output P64/RTS1 RxD input P66/RxD1 P50(CE) Reset input P55(EPM) CNVss RESET P85/NMI User reset signal Control pins and external circuitry will vary according to programmer. For more information, refer to the programmer manual. In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVss input with a switch. If in standard serial input/output mode 1 there is a possibility that the user reset signal will go low during serial input/output mode, break the connection between the user reset signal and RESET pin by using, for example, a jumper switch. Figure 1.22.14 Circuit Application in Standard Serial I/O Mode 1 Microcomputer P65/CLK1 P50(CE) TxD output P67/TxD1 P55(EPM) Monitor output P64/RTS1 RxD input P66/RxD1 CNVss P85/NMI In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVss input with a switch. Figure 1.22.15 Circuit Application in Standard Serial I/O Mode 2 Rev.1.00 2003.05.30 page 286 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Parallel I/O Mode In parallel I/O mode, the user ROM and boot ROM areas can be rewritten by using a parallel programmer suitable for the M16C/6N4 group. For more information about parallel programmers, contact the manufacturer of your parallel programmer. For details on how to use, refer to the user's manual included with your parallel programmer. User ROM and Boot ROM Areas In the boot ROM area, an erase block operation is applied to only one 4-Kbyte block. The boot ROM area contains a standard serial I/O and CAN I/O modes based rewrite control program which was written in it when shipped from the factory. Therefore, when using a serial programmer or a CAN programmer, be careful not to rewrite the boot ROM area. When in parallel I/O mode, the boot ROM area is located at addresses 0FF00016 to 0FFFFF16. When rewriting the boot ROM area, make sure that only this address range is rewritten. (Do not access other than the addresses 0FF00016 to 0FFFFF16.) ROM Code Protect Function The ROM code protect function inhibits the flash memory from being read or rewritten. (Refer to "Functions to Prevent Flash Memory from Rewriting".) Rev.1.00 2003.05.30 page 287 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory CAN I/O Mode In CAN I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a CAN programmer suitable for the M16C/6N4 group. For more information about CAN programmers, contact the manufacturer of your CAN programmer. For details on how to use, refer to the user's manual included with your CAN programmer. Table 1.22.8 lists pin functions for CAN I/O mode. Figures 1.22.16 shows pin connections for CAN I/O mode. ID code check function This function determines whether the ID codes sent from the CAN programmer and those written in the flash memory match. (Refer to "Functions to Prevent Flash Memory from Rewriting".) Table 1.22.8 Pin Functions for CAN I/O Mode Pin Name Description I/O VCC, VSS Power input CNVSS CNVSS I Connect to VCC pin. RESET Reset input I Reset input pin. While RESET pin is "L" level, input 20 cycles or longer XIN Clock input I XOUT Clock output O Apply the voltage guaranteed for Program and Erase to V CC pin and 0 V to VSS pin. ____________ _____________ clock to XIN pin. Connect a ceramic resonator or crystal oscillator between X IN and X OUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect this pin to VCC or VSS. BYTE BYTE AVCC, AVSS Analog power supply input VREF Reference voltage input I Enter the reference voltage for A-D and D-A converters from this pin. P0 0 to P0 7 Input port P0 I Input "H" or "L" level signal or open. P1 0 to P1 7 Input port P1 I Input "H" or "L" level signal or open. P2 0 to P2 7 Input port P2 I Input "H" or "L" level signal or open. P3 0 to P3 7 Input port P3 I Input "H" or "L" level signal or open. P4 0 to P4 7 Input port P4 I Input "H" or "L" level signal or open. P50 CE input I Input "H" level signal. P5 1 to P5 4, Input port P5 I Input "H" or "L" level signal or open. I Input "L" level signal. I Input "H" or "L" level signal or open. I Input "L" level signal. I Connect AVSS to V SS and AVCC to VCC, respectively. _____ P5 6, P5 7 ________ EPM input P55 P60 to P64, P66 Input port P6 SCLK input P6 5/CLK1 P6 7/TxD 1 TxD output O Input "H" level signal. P7 0 to P7 7 Input port P7 I Input "H" or "L" level signal or open. P8 0 to P8 4, Input port P8 I Input "H" or "L" level signal or open. I Connect this pin to VCC. I Input "H" or "L" level signal or open. I Connect to a CAN transceiver. P8 6, P8 7 _______ P8 5/NMI ________ NMI input P90 to P94, P97 Input port P9 CRx input P9 5/CRx0 P9 6/CTx 0 CTx output O Connect to a CAN transceiver. P100 to P107 Input port P10 I Input "H" or "L" level signal or open. Rev.1.00 2003.05.30 page 288 Under development This document is under development and its contents are subject to change. Flash Memory 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VCC2 M16C/6N4 Group 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 CE EPM SCLK TXD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 M16C/6N4 Group (Flash memory version) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 VSS VCC1 CNVSS CTx CRx RESET Connect oscillator circuit Mode setup method Signal Value CNVss VCC EPM VSS RESET VSS to VCC CE VCC SCLK VSS TxD VCC Package: 100P6S-A Figure 1.22.16 Pin Connections for CAN I/O Mode Rev.1.00 2003.05.30 page 289 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Example of Circuit Application in CAN I/O Mode Figure 1.22.17 shows example of circuit application in CAN I/O mode. Refer to the user's manual for CAN writer to handle pins controlled by a CAN writer. Microcomputer P67/TXD1 P50(CE) P65/CLK1 P55(EPM) CAN transceiver CAN_H CAN_L CAN_H CAN_L P95/CRx0 CNVss P96/CTx0 RESET P85/NMI Control pins and external circuitry will vary according to programmer. For more information, refer to the programmer manual. In this example, modes are switched between single-chip mode and CAN input/output mode by controlling the CNVss input with a switch. Figure 1.22.17 Circuit Application in CAN I/O Mode Rev.1.00 2003.05.30 page 290 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Flash Memory Electrical Characteristics Table 1.22.9 lists the flash memory electrical characteristics. Table 1.22.10 lists the flash memory version program/erase voltage and read operation voltage characteristics. Table 1.22.9 Flash Memory Electrical Characteristics (Note 1) Parameter Symbol - Word program time - Block erase time - Erase all unlocked blocks time - Lock bit program time tps Flash memory circuit stabilization wait time Min. Standard Typ. 30 Max. 200 Unit s 1 4 1 n (Note 2) 4n s s 30 200 s 15 s Note 1: Referenced to VCC = 4.5 to 5.5 V, Topr = 0 to 60 C unless otherwise specified. Note 2: n denotes the number of blocks to erase. Table 1.22.10 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics (at Topr = 0 to 60 C) Flash program, erase voltage VCC = 5.0 0.5 V Rev.1.00 2003.05.30 page 291 Flash read operation voltage VCC = 4.2 to 5.5 V Under development This document is under development and its contents are subject to change. M16C/6N4 Group Package Dimension Package Dimension 100P6S-A MMP EIAJ Package Code QFP100-P-1420-0.65 Plastic 100pin 1420mm body QFP Weight(g) 1.58 Lead Material Alloy 42 MD e JEDEC Code - 81 1 b2 100 ME HD D 80 I2 Recommended Mount Pad E 30 HE Symbol 51 50 A L1 c A2 31 A A1 A2 b c D E e HD HE L L1 x y b y Rev.1.00 2003.05.30 page 292 x M A1 F e L Detail F b2 I2 MD ME Dimension in Millimeters Min Nom Max - - 3.05 0.1 0.2 0 - - 2.8 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 - 0.65 - 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 - - - - 0.13 - - 0.1 - 0 10 - - 0.35 1.3 - - - - 14.6 - - 20.6 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Register Index Register Index A AD0 ............................................... 190 C0TECR ........................................ 218 C0TRMIC ........................................ 77 AD1 ............................................... 190 AD2 ............................................... 190 C0TSR .......................................... 219 C1AFS ........................................... 219 AD3 ............................................... 190 AD4 ............................................... 190 C1CONR ....................................... 217 C1CTLR ........................................ 213 AD5 ............................................... 190 AD6 ............................................... 190 C1GMR .......................................... 211 C1ICR ........................................... 216 AD7 ............................................... 190 ADCON0 .... 189,192,194,196,198,200 C1IDR ........................................... 216 C1LMAR ......................................... 211 ADCON1 .... 189,192,194,196,198,200 ADCON2 ....................................... 190 C1LMBR ......................................... 211 C1MCTL0 ...................................... 212 ADIC ................................................ 77 AIER ................................................ 89 C1MCTL1 ...................................... 212 C1MCTL2 ...................................... 212 AIER2 .............................................. 89 C1MCTL3 ...................................... 212 C1MCTL4 ...................................... 212 C C01ERRIC ...................................... 77 C1MCTL5 ...................................... 212 C1MCTL6 ...................................... 212 C01WKIC ........................................ 77 C0AFS ........................................... 219 C1MCTL7 ...................................... 212 C1MCTL8 ...................................... 212 C0CONR ....................................... 217 C0CTLR ........................................ 213 C1MCTL9 ...................................... 212 C1MCTL10 .................................... 212 C0GMR .......................................... 211 C0ICR ........................................... 216 C1MCTL11 .................................... 212 C1MCTL12 .................................... 212 C0IDR ........................................... 216 C0LMAR ......................................... 211 C1MCTL13 .................................... 212 C1MCTL14 .................................... 212 C0LMBR ......................................... 211 C0MCTL0 ...................................... 212 C1MCTL15 .................................... 212 C1RECIC ........................................ 78 C0MCTL1 ...................................... 212 C0MCTL2 ...................................... 212 C1RECR ....................................... 218 C1SSTR ........................................ 215 C0MCTL3 ...................................... 212 C0MCTL4 ...................................... 212 C1STR .......................................... 214 C1TECR ........................................ 218 C0MCTL5 ...................................... 212 C0MCTL6 ...................................... 212 C1TRMIC ........................................ 78 C1TSR .......................................... 219 C0MCTL7 ...................................... 212 C0MCTL8 ...................................... 212 CAN0/1 SLOT 0 to 15 : Time Stamp ....................... 209,210 C0MCTL9 ...................................... 212 C0MCTL10 .................................... 212 : Data Field .......................... 209,210 : Message Box .................... 209,210 C0MCTL11 .................................... 212 C0MCTL12 .................................... 212 CCLKR ............................................ 52 CM0 ................................................. 49 C0MCTL13 .................................... 212 C0MCTL14 .................................... 212 CM1 ................................................. 50 CM2 ................................................. 51 C0MCTL15 .................................... 212 C0RECIC ........................................ 77 CPSRF ................................... 107,121 CRCD ............................................ 205 C0RECR ....................................... 218 C0SSTR ........................................ 215 CRCIN ........................................... 205 CSE ................................................. 43 C0STR .......................................... 214 CSR ................................................. 37 Rev.1.00 2003.05.30 page 293 D DA0 ............................................... 204 DA1 ............................................... 204 DACON ......................................... 204 DAR0 ............................................... 96 DAR1 ............................................... 96 DM0CON ......................................... 95 DM0IC ............................................. 77 DM0SL ............................................ 94 DM1CON ......................................... 95 CM1IC ............................................. 77 DM1SL ............................................ 95 DTT ............................................... 131 F FMR0 ............................................ 269 FMR1 ............................................ 269 I ICTB2 ............................................ 133 IDB0 .............................................. 131 IDB1 .............................................. 131 IFSR0 .............................................. 86 IFSR1 .............................................. 86 INT0IC ............................................. 78 INT1IC ............................................. 78 INT2IC ............................................. 78 INT3IC ............................................. 78 INT4IC ............................................. 78 INT5IC ............................................. 78 INVC0 ............................................ 129 INVC1 ............................................ 130 K KUPIC ............................................. 77 O ONSF ............................................ 107 P P0 .................................................. P1 .................................................. P2 .................................................. P3 .................................................. P4 .................................................. P5 .................................................. P6 .................................................. P7 .................................................. 239 239 239 239 239 239 239 239 Under development This document is under development and its contents are subject to change. M16C/6N4 Group Register Index P8 .................................................. 239 T U P9 .................................................. 239 P10 ................................................ 239 TA0 ................................................ 105 U0BCNIC ........................................ 77 TA0IC .............................................. 77 TA0MR ............... 105,108,110,115,117 U0BRG .......................................... 141 U0C0 ............................................. 142 TA1 ......................................... 105,132 TA11 .............................................. 132 U0C1 ............................................. 143 U0MR ............................................ 142 TA1IC .............................................. 77 TA1MR ........ 105,108,110,115,117,135 U0RB ............................................. 141 U0SMR .......................................... 144 TA2 ......................................... 105,132 TA21 .............................................. 132 U0SMR2 ........................................ 145 U0SMR3 ........................................ 145 TA2IC .............................................. 77 TA2MR ... 105,108,110,112,115,117,135 U0SMR4 ........................................ 146 U0TB ............................................. 141 TA3 ................................................ 105 TA3IC .............................................. 77 U1BCNIC ........................................ 77 U1BRG .......................................... 141 TA3MR ........ 105,108,110,112,115,117 TA4 ......................................... 105,132 U1C0 ............................................. 142 U1C1 ............................................. 143 TA41 .............................................. 132 TA4IC .............................................. 77 U1MR ............................................ 142 U1RB ............................................. 141 TA4MR ... 105,108,110,112,115,117,135 TABSR ............................ 106,121,134 U1SMR .......................................... 144 U1SMR2 ........................................ 145 TB0 ................................................ 120 TB0IC .............................................. 77 U1SMR3 ........................................ 145 U1SMR4 ........................................ 146 TB0MR ..................... 120,122,123,125 TB1 ................................................ 120 U1TB ............................................. 141 U2BCNIC ........................................ 77 TB1IC .............................................. 77 TB1MR ..................... 120,122,123,125 U2BRG .......................................... 141 U2C0 ............................................. 142 TB2 ......................................... 120,132 TB2IC .............................................. 77 U2C1 ............................................. 143 U2MR ............................................ 142 TB2MR .............. 120,122,123,125,135 TB2SC ........................................... 133 U2RB ............................................. 141 U2SMR .......................................... 144 TB3 ................................................ 120 TB3IC .............................................. 77 U2SMR2 ........................................ 145 U2SMR3 ........................................ 145 TB3MR ..................... 120,122,123,125 TB4 ................................................ 120 U2SMR4 ........................................ 146 U2TB ............................................. 141 TB4IC .............................................. 77 TB4MR ..................... 120,122,123,125 UCON ............................................ 144 UDF ............................................... 106 TB5 ................................................ 120 TB5IC .............................................. 77 W PCLKR ............................................ 52 PCR ............................................... 241 PD0 ............................................... 238 PD1 ............................................... 238 PD2 ............................................... 238 PD3 ............................................... 238 PD4 ............................................... 238 PD5 ............................................... 238 PD6 ............................................... 238 PD7 ............................................... 238 PD8 ............................................... 238 PD9 ............................................... 238 PD10 ............................................. 238 PLC0 ............................................... 54 PM0 ................................................. 31 PM1 ................................................. 32 PM2 ................................................. 53 PRCR .............................................. 71 PUR0 ............................................. 240 PUR1 ............................................. 240 PUR2 ............................................. 240 R RMAD0 ............................................ 89 RMAD1 ............................................ 89 RMAD2 ............................................ 89 RMAD3 ............................................ 89 ROMCP ......................................... 265 S S0RIC .............................................. 77 S0TIC .............................................. 77 S1RIC .............................................. 77 S1TIC .............................................. 77 S2RIC .............................................. 77 S2TIC .............................................. 77 S3BRG .......................................... 183 S3C ............................................... 183 S3IC ................................................ 78 S3TRR .......................................... 183 SAR0 ............................................... 96 SAR1 ............................................... 96 Rev.1.00 2003.05.30 page 294 TB5MR ..................... 120,122,123,125 TBSR ............................................. 121 TCR0 ............................................... 96 TCR1 ............................................... 96 TRGSR ................................... 107,134 WDC ................................................ 91 WDTS .............................................. 91 REVISION HISTORY Rev. Date 1.00 May 30, 2003 M16C/6N4 Group Hardware Manual Description Page - Summary First edition issued C-1 Blank page RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL M16C/6N4 Group Rev.1.00 Editioned by Committee of editing of RENESAS Semiconductor Hardware Manual This book, or parts thereof, may not be reproduced in any form without permission of Renesas Technology Corporation. Copyright (c) 2003. Renesas Technology Corporation, All rights reserved. M16C/6N4 Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan REJ09B0010-0100Z M16C/6N4 Group 16 Usage Notes Reference Book RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES For the most current Usage Notes Reference Book, please visit our website. Before using this material, please visit our website to confirm that this is the most current document available. Rev. 1.00 Revision date: May 30, 2003 www.renesas.com Keep safety first in your circuit designs! * Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. 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Preface The "Usage Notes Reference Book" is a compilation of usage notes from the Hardware Manual as well as technical news related to this product. Blank page Table of Contents 1. Usage Precaution 1.1 Precautions for External Bus ....................................................................................................................... 1 1.2 Precautions for PLL Frequency Synthesizer ................................................................................................ 2 1.3 Precautions for Power Control ..................................................................................................................... 3 1.4 Precautions for Protection ............................................................................................................................ 4 1.5 Precautions for Interrupts ............................................................................................................................. 5 1.5.1 Reading Address 0000016 .................................................................................................................................................................................................. 5 1.5.2 _______ SP Setting ............................................................................................................................................ 5 1.5.3 NMI Interrupt ........................................................................................................................................ 5 1.5.4 Changing the Interrupt Generate Factor .............................................................................................. 6 _____ 1.5.5 INT Interrupt ......................................................................................................................................... 6 1.5.6 Rewrite the Interrupt Control Register ................................................................................................. 7 1.5.7 Watchdog Timer Interrupt .................................................................................................................... 7 1.6 Precautions for DMAC ................................................................................................................................. 8 1.6.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) ................................................................................ 8 1.7 Precautions for Timers ................................................................................................................................. 9 1.7.1 Timer A ................................................................................................................................................. 9 1.7.2 Timer B ............................................................................................................................................... 12 1.8 Precautions for Serial I/O (Clock Synchronous Serial I/O Mode) .............................................................. 14 1.8.1 Transmission/reception ...................................................................................................................... 14 1.8.2 Transmission ...................................................................................................................................... 14 1.8.3 Reception ........................................................................................................................................... 14 1.9 Precaution for Serial I/O (Special Modes) .................................................................................................. 15 1.9.1 Special Mode 2 ................................................................................................................................. 15 1.9.2 Special Mode 4 (SIM Mode) ............................................................................................................. 15 1.10 Precautions for A-D Converter ................................................................................................................. 16 1.11 Precautions for CAN Module .................................................................................................................... 18 1.11.1 Reading CiSTR Register (i = 0, 1) .................................................................................................... 18 1.11.2 CAN Transceiver in Boot Mode ........................................................................................................ 20 1.12 Precautions for Programmable I/O Ports ................................................................................................. 21 1.13 Precautions for Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers ... 22 1.14 Precautions for Flash Memory Version .................................................................................................... 23 1.14.1 Precautions for Functions to Prevent Flash Memory from Rewriting ............................................... 23 1.14.2 Precautions for Stop Mode .............................................................................................................. 23 1.14.3 Precautions for Wait Mode ............................................................................................................... 23 1.14.4 Precautions for Low Power Dissipation Mode and Ring Oscillator Low Power Dissipation Mode ... 23 1.14.5 Writing command and data .............................................................................................................. 23 1.14.6 Precautions for Program Command ................................................................................................ 23 1.14.7 Precautions for Lock Bit Program Command ................................................................................... 23 1.14.8 Operation speed .............................................................................................................................. 24 1.14.9 Instructions to prevent from using .................................................................................................... 24 1.14.10 Interrupts ........................................................................................................................................ 24 1.14.11 How to access ................................................................................................................................ 24 1.14.12 Writing in user ROM area .............................................................................................................. 24 1.14.13 DMA transfer .................................................................................................................................. 24 A-1 Blank page Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.1 Precautions for External Bus 1. Usage Precaution 1.1 Precautions for External Bus 1. The external ROM version can operate only in the microprocessor mode, connect the CNVSS pin to VCC. 2. When resetting CNVSS pin with "H" input, contents of internal ROM cannot be read out. Rev.1.00 2003.05.30 page 1 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.2 Precautions for PLL Frequency Synthesizer 1.2 Precautions for PLL Frequency Synthesizer Make the supply voltage stable to use the PLL frequency synthesizer. For ripple with the supply voltage 5 V, keep below 10 kHz as frequency, below 0.5 V (peak to peak) as voltage fluctuation band and below 1 V/mS as voltage fluctuation rate. Rev.1.00 2003.05.30 page 2 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.3 Precautions for Power Control 1.3 Precautions for Power Control ____________ 1. When exiting stop mode by hardware reset, set RESET pin to "L" until a main clock oscillation is stabilized. 2. Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit of the CM1 register to "1" (all clock stopped). When shifting to wait mode or stop mode, an instruction queue reads ahead to the next instruction to halt a program by an WAIT instruction and an instruction to set the CM10 bit to "1". The next instruction may be executed before entering wait mode or stop mode, depending on a combination of instruction and an execution timing. 3. Wait until the td(M-L) elapses or main clock oscillation stabilization time, whichever is longer, before switching the clock source for CPU clock to the main clock. Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the sub clock. 4. Suggestions to reduce power consumption (a) Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When entering wait mode or stop mode, set non-used ports to input and stabilize the potential. (b) A-D converter When A-D conversion is not performed, set the VCUT bit of the ADCON1 register to "0" (VREF not connection). When A-D conversion is performed, start the A-D conversion at least 1 s or longer after setting the VCUT bit to "1" (VREF connection). (c) D-A converter When not performing D-A conversion, set the DAiE bit (i = 0, 1) of the DACON register to "0" (input inhibited) and DAi register to "0016". (d) Stopping peripheral functions Use the CM02 bit of the CM0 register to stop the unnecessary peripheral functions during wait mode. However, because the peripheral function clock (fC32) generated from the sub clock does not stop, this measure is not conducive to reducing the power consumption of the chip. If low speed mode or low power dissipation mode is to be changed to wait mode, set the CM02 bit to "0" (do not peripheral function clock stopped when in wait mode), before changing wait mode. (e) Switching the oscillation-driving capacity Set the driving capacity to "LOW" when oscillation is stable. (f) External clock When using an external clock input for the CPU clock, set the CM05 bit of the CM0 register to "1" (stop). Setting the CM05 bit to "1" disables the XOUT pin from functioning, which helps to reduce the amount of current drawn in the chip. (When using an external clock input, note that the clock remains fed into the chip regardless of how the CM05 bit is set.) Rev.1.00 2003.05.30 page 3 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.4 Precautions for Protection 1.4 Precautions for Protection Set the PRC2 bit to "1" (write enabled) and then write to any address, and the PRC2 bit will be set to "0" (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to "1". Make sure no interrupts or no DMA transfers will occur between the instruction in which the PRC2 bit is set to "1" and the next instruction. Rev.1.00 2003.05.30 page 4 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.5 Precautions for Interrupts 1.5 Precautions for Interrupts 1.5.1 Reading Address 0000016 Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is set to "0". If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to "0". This causes a problem that the interrupt is canceled, or an unexpected interrupt is generated. 1.5.2 SP Setting Set any value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is set to "000016" after reset. Therefore, if an interrupt is accepted before setting any value in the SP (USP, ISP), the program may go out of control. _______ Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the _______ first and only the first instruction after reset, all interrupts including NMI interrupt are disabled. _______ 1.5.3 NMI Interrupt _______ _______ 1. The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC via a resistor (pull-up). _______ 2. The input level of the NMI pin can be read by accessing the P8_5 bit of the P8 register. Note that the _______ P8_5 bit can only be read when determining the pin level in NMI interrupt routine. _______ 3. Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on _______ the NMI pin is low the CM10 bit of the CM1 register is fixed to "0". _______ _______ 4. Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip does not drop. In this case, normal condition is restored by an interrupt generated thereafter. _______ 5. The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles + 300 ns or more. Rev.1.00 2003.05.30 page 5 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.5 Precautions for Interrupts 1.5.4 Changing the Interrupt Generate Factor If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to "1" (interrupt requested). If you changed the interrupt generate factor for an interrupt that needs to be used, be sure to set the IR bit for that interrupt to "0" (interrupt not requested). "Changing the interrupt generate factor" referred to here means any act of changing the source, polarity or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to set the IR bit for that interrupt to "0" (interrupt not requested) after making such changes. Refer to the description of each peripheral function for details about the interrupts from peripheral functions. Figure 1.5.1 shows the procedure for changing the interrupt generate factor. Changing the interrupt source Disable interrupts (Notes 2, 3) Change the interrupt generate factor (including a mode change of peripheral function) Use the MOV instruction to set the IR bit to "0" (interrupt not requested) (Note 3) Enable interrupts (Notes 2, 3) End of change R bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed Note 1: The above settings must be executed individually. Do not execute two or more settings simultaneously (using one instruction). Note 2: Use the I flag for the INTi interrupt (i = 0 to 5). For the interrupts from peripheral functions other than the INTi interrupt, turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt generate factor. In this case, if the maskable interrupts can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is to be changed. Note 3: Refer to "Rewrite the Interrupt Control Register" for details about the instructions to use and the notes to be taken for instruction execution. Figure 1.5.1 Procedure for Changing Interrupt Generate Factor _____ 1.5.5 INT Interrupt 1. Either an "L" level of at least tW(INH) or an "H" level of at least tW(INL) width is necessary for the signal _______ _______ input to pins INT0 through INT5 regardless of the CPU operation clock. 2. If the POL bit in the INT0IC to INT5IC registers or the IFSR17 to IFSR10 bits in the IFSR1 register are changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to "0" (interrupt not requested) after changing any of those register bits. Rev.1.00 2003.05.30 page 6 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.5 Precautions for Interrupts 1.5.6 Rewrite the Interrupt Control Register (1) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register. (2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used. Changing any bit other than the IR bit If while executing an instruction, a request for an interrupt controlled by the register being modified occurs, the IR bit in the register may not be set to "1" (interrupt requested), with the result that the interrupt request is ignored. If such a situation presents a problem, use the instructions shown below to modify the register. Usable instructions: AND, OR, BCLR, BSET Changing the IR bit Depending on the instruction used, the IR bit may not always be set to "0" (interrupt not requested). Therefore, be sure to use the MOV instruction to set the IR bit to "0". (3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample program fragments.) Examples 1 through 3 show how to prevent the I flag from being set to "1" (interrupts enabled) before the interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue buffer. Example 1: Using the NOP instruction to keep the program waiting until the interrupt control register is modified INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00H, 0055H ; Set the TA0IC register to "0016". NOP ; NOP FSET I ; Enable interrupts. The number of NOP instruction is as follows. * PM20 of the PM2 register = 1 (1 wait) : 2 * PM20 = 0 (2 waits) : 3 * When using HOLD function : 4. Example 2: Using the dummy read to keep the FSET instruction waiting INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h,0055h ; Set the TA0IC register to "0016". MOV.W MEM,R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: Using the POPC instruction to changing the I flag INT_SWITCH3: PUSHC FLG FCLR I ;Disable interrupts. AND.B #00h,0055h ;Set the TA0IC register to "0016 ". POPC FLG ;Enable interrupts. 1.5.7 Watchdog Timer Interrupt Initialize the watchdog timer after the watchdog timer interrupt occurs. Rev.1.00 2003.05.30 page 7 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.6 Precautions for DMAC 1.6 Precautions for DMAC 1.6.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) When both of the conditions below are met, follow the steps below. Conditions * The DMAE bit is set to "1" again while it remains set (DMAi is in an active state). * A DMA request may occur simultaneously when the DMAE bit is being written. Step 1: Write "1" to the DMAE bit and DMAS bit in DMiCON register simultaneously (Note 1) . Step 2: Make sure that the DMAi is in an initial state (Note 2) in a program. If the DMAi is not in an initial state, the above steps should be repeated. Note 1: The DMAS bit remains unchanged even if "1" is written. However, if "0" is written to this bit, it is set to "0" (DMA not requested). In order to prevent the DMAS bit from being modified to "0, "1" should be written to the DMAS bit when "1" is written to the DMAE bit. In this way the state of the DMAS bit immediately before being written can be maintained. Similarly, when writing to the DMAE bit with a read-modify-write instruction, "1" should be written to the DMAS bit in order to maintain a DMA request which is generated during execution. Note 2: Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state. (If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is "1".) If the read value is a value in the middle of transfer, the DMAi is not in an initial state. Rev.1.00 2003.05.30 page 8 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.7 Precautions for Timers 1.7 Precautions for Timers 1.7.1 Timer A 1.7.1.1 Timer A (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to "1" (count starts). Always make sure the TAiMR register is modified while the TAiS bit remains "0" (count stops) regardless whether after reset or not. 2. While counting is in progress, the counter value can be read out at any time by reading the TAi register. However, if the counter is read at the same time it is reloaded, the value "FFFF16" is read. Also, if the counter is read before it starts counting after a value is set in the TAi register while not counting, the set value is read. ______ 3. If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible ______ cutoff by input on NMI pin enabled) of the TB2SC register, the TA1OUT, TA2OUT and TA4OUT pins go to a high-impedance state. 1.7.1.2 Timer A (Event Counter Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to "1" (count starts). Always make sure the TAiMR register, the UDF register, the ONSF register TAZIE, TA0TGL and TA0TGH bits and the TRGSR register are modified while the TAiS bit remains "0" (count stops) regardless whether after reset or not. 2. While counting is in progress, the counter value can be read out at any time by reading the TAi register. However, "FFFF16" can be read in underflow, while reloading, and "000016" in overflow. When setting TAi register to a value during a counter stop, the setting value can be read before a counter starts counting. Also, if the counter is read before it starts counting after a value is set in the TAi register while not counting, the set value is read. ______ 3. If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible ______ cutoff by input on NMI pin enabled) of the TB2SC register, the TA1OUT, TA2OUT and TA4OUT pins go to a high-impedance state. Rev.1.00 2003.05.30 page 9 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.7 Precautions for Timers 1.7.1.3 Timer A (One-shot Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to "1" (count starts). Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register are modified while the TAiS bit remains "0" (count stops) regardless whether after reset or not. 2. When setting the TAiS bit of the TABSR register to "0" (count stop), the followings occur: * A counter stops counting and a content of reload register is reloaded. * TAiOUT pin outputs "L". * After one cycle of the CPU clock, the IR bit of the TAiIC register is set to "1" (interrupt request). 3. Output in one-shot timer mode synchronizes with a count source internally generated. When an external trigger has been selected, one-cycle delay of a count source as maximum occurs between a trigger input to TAiIN pin and output in one-shot timer mode. 4. The IR bit is set to "1" when timer operation mode is set with any of the following procedures: * Select one-shot timer mode after reset. * Change an operation mode from timer mode to one-shot timer mode. * Change an operation mode from event counter mode to one-shot timer mode. To use the timer Ai interrupt (the IR bit), set the IR bit to "0" after the changes listed above have been made. 5. When a trigger occurs, while counting, a counter reloads the reload register to continue counting after generating a re-trigger and counting down once. To generate a trigger while counting, generate a second trigger between occurring the previous trigger and operating longer than one cycle of a timer count source. ______ 6. If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible ______ cutoff by input on NMI pin enabled) of the TB2SC register, the TA1OUT, TA2OUT and TA4OUT pins go to a high-impedance state. Rev.1.00 2003.05.30 page 10 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.7 Precautions for Timers 1.7.1.4 Timer A (Pulse Width Modulation Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to "1" (count starts). Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register are modified while the TAiS bit remains "0" (count stops) regardless whether after reset or not. 2. The IR bit is set to "1" when setting a timer operation mode with any of the following procedures: * Select the PWM mode after reset. * Change an operation mode from timer mode to PWM mode. * Change an operation mode from event counter mode to PWM mode. To use the timer Ai interrupt (the IR bit), set the IR bit to "0" by program after the above listed changes have been made. 3. When setting TAiS bit to "0" (count stop) during PWM pulse output, the following action occurs: * Stop counting. * When TAiOUT pin is output "H", output level is set to "L" and the IR bit is set to "1". * When TAiOUT pin is output "L", both output level and the IR bit remain unchanged. ______ 4. If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible ______ cutoff by input on NMI pin enabled) of the TB2SC register, the TA1OUT, TA2OUT and TA4OUT pins go to a high-impedance state. Rev.1.00 2003.05.30 page 11 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.7 Precautions for Timers 1.7.2 Timer B 1.7.2.1 Timer B (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to "1" (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains "0" (count stops) regardless whether after reset or not. The TB0S to TB2S bits are the bits 5 to 7 of the TABSR register, the TB3S to TB5S bits are the bits 5 to 7 of the TBSR register. 2. A value of a counter, while counting, can be read in the TBi register at any time. "FFFF16" is read while reloading. Setting value is read between setting values in TBi register at count stop and starting a counter. 1.7.2.2 Timer B (Event Counter Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to "1" (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains "0" (count stops) regardless whether after reset or not. The TB0S to TB2S bits are the bits 5 to 7 of the TABSR register, the TB3S to TB5S bits are the bits 5 to 7 of the TBSR register. 2. A value of a counter, while counting, can be read in the TBi register at any time. "FFFF16" is read while reloading. Setting value is read between setting values in TBi register at count stop and starting a counter. Rev.1.00 2003.05.30 page 12 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.7 Precautions for Timers 1.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) 1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5) register before setting the TBiS bit in the TABSR or the TBSR register to "1" (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains "0" (count stops) regardless whether after reset or not. To clear the MR3 bit to "0" by writing to the TBiMR register while the TBiS bit = "1" (count starts), be sure to write the same value as previously written to the TM0D0, TM0D1, MR0, MR1, TCK0 and TCK1 bits and a 0 to the MR2 bit. 2. The IR bit of TBiIC register (i = 0 to 5) goes to "1" (interrupt request), when an effective edge of a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the MR3 bit of TBiMR register within the interrupt routine. 3. If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse input and a timer overflow occur at the same time, use another timer to count the number of times timer B has overflowed. 4. To set the MR3 bit to "0" (no overflow), set TBiMR register with setting the TBiS bit to "1" and counting the next count source after setting the MR3 bit to "1" (overflow). 5. Use the IR bit of the TBiIC register to detect only overflows. Use the MR3 bit only to determine the interrupt factor within the interrupt routine. 6. When a count is started and the first effective edge is input, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. 7. A value of the counter is indeterminate at the beginning of a count. The MR3 bit may be set to "1" and timer Bi interrupt request may be generated between a count start and an effective edge input. 8. For pulse width measurement, pulse widths are successively measured. Use program to check whether the measurement result is an "H" level width or an "L" level width. Rev.1.00 2003.05.30 page 13 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.8 Precautions for Serial I/O (Clock Synchronous Serial I/O Mode) 1.8 Precautions for Serial I/O (Clock Synchronous Serial I/O Mode) 1.8.1 Transmission/reception _______ 1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to "L" when the data-receivable status becomes ready, which informs the transmission side that the reception has become ready. The output level of the RTSi pin goes to "H" when reception ________ starts. So if the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can _______ transmission and reception data with consistent timing. With the internal clock, the RTS function has no effect. _______ 2. If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible _______ ________ cutoff by input on NMI pin enabled) of the TB2SC register, the RTS2 and CLK2 pins go to a highimpedance state. 1.8.2 Transmission When an external clock is selected, the conditions must be met while if the CKPOL bit of the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit of the UiC0 register = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. * The TE bit of the UiC1 register = 1 (transmission enabled) * The TI bit of the UiC1 register = 0 (data present in UiTB register) _______ _______ * If CTS function is selected, input on the CTSi pin = L 1.8.3 Reception 1. In operating the clock synchronous serial I/O, operating a transmitter generates a shift clock. Fix settings for transmission even when using the device only for reception. Dummy data is output to the outside from the TxDi (i = 0 to 2) pin when receiving data. 2. When an internal clock is selected, set the TE bit of the UiC1 register to "1" (transmission enabled) and write dummy data to the UiTB register, and the shift clock will thereby be generated. When an external clock is selected, set the TE bit to "1" and write dummy data to the UiTB register, and the shift clock will be generated when the external clock is fed to the CLKi input pin. 3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive register while the RI bit of the UiC1 register = 1 (data present in the UiRB register), an overrun error occurs and the OER bit of the UiRB register is set to "1" (overrun error occurred). In this case, because the content of the UiRB register is indeterminate, a corrective measure must be taken by programs on the transmit and receive sides so that the valid data before the overrun error occurred will be retransmitted. Note that when an overrun error occurred, the IR bit of the SiRIC register does not change state. 4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time reception is made. 5. When an external clock is selected, the conditions must be met while if the CKPOL bit = 0, the external clock is in the high state; if the CKPOL bit = 1, the external clock is in the low state. * The RE bit of the UiC1 register = 1 (reception enabled) * The TE bit of the UiC1 register = 1 (transmission enabled) * The TI bit of the UiC1 register = 0 (data present in the UiTB register) Rev.1.00 2003.05.30 page 14 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.9 Precautions for Serial I/O (Special Modes) 1.9 Precaution for Serial I/O (Special Modes) 1.9.1 Special Mode 2 _______ If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = 1 (three-phase _______ output forcible cutoff by input on NMI pin enabled), the RTS2 and CLK2 pins go to a high-impedance state. 1.9.2 Special Mode 4 (SIM Mode) A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to "1" (transmission complete) and U2ERE bit to "1" (error signal output) after reset. Therefore, when using SIM mode, be sure to set the IR bit to "0" (no interrupt request) after setting these bits. Rev.1.00 2003.05.30 page 15 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.10 Precautions for A-D Converter 1.10 Precautions for A-D Converter 1. Set the ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A-D conversion is stopped (before a trigger occurs). 2. When the VCUT bit of the ADCON1 register is changed from "0" (VREF not connected) to "1" (VREF connected), start A-D conversion after passing 1 s or longer. 3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert capacitors between the AVCC, VREF, and analog input pins (ANi (i = 0 to 7), AN0i, and AN2i) each and the AVSS pin. Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 1.10.1 is an example connection of each pin. 4. Make sure the port direction bits for those pins that are used as analog inputs are set to "0" (input mode). Also, if the TGR bit of the ADCON0 register = 1 (external trigger), make sure the port direction __________ bit for the ADTRG pin is set to "0" (input mode). 5. When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key input interrupt request is generated when the A-D input voltage goes low.) 6. The AD frequency must be 10 MHz or less. Without sample-and-hold function, limit the AD frequency to 250 kHz or more. With the sample and hold function, limit the AD frequency to 1 MHz or more. 7. When changing an A-D operation mode, select analog input pin again in the CH2 to CH0 bits of the ADCON0 register and the SCAN1 to SCAN0 bits of the ADCON1 register. Microcomputer VCC C4 AVCC VREF C1 VSS C2 AVSS C3 ANi ANi: ANi, AN0i, and AN2i (i =0 to 7) Note 1: C1 0.47 F, C2 0.47 F, C3 100 pF, C4 0.1 F (reference). Note 2: Use thick and shortest possible wiring to connect capacitors. Figure 1.10.1 Use of capacitors to reduce noise Rev.1.00 2003.05.30 page 16 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.10 Precautions for A-D Converter 8. If the CPU reads the ADi register at the same time the conversion result is stored in the ADi register after completion of A-D conversion, an incorrect value may be stored in the ADi register. This problem occurs when a divide-by-n clock derived from the main clock or a sub clock is selected for CPU clock. * When operating in one-shot or single-sweep mode Check to see that A-D conversion is completed before reading the target ADi register. (Check the IR bit of the ADIC register to see if A-D conversion is completed.) * When operating in repeat mode or repeat sweep mode 0 or 1 Use the main clock for CPU clock directly without dividing it. 9. If A-D conversion is forcibly terminated while in progress by setting the ADST bit of the ADCON0 register to "0" (A-D conversion halted), the conversion result of the A-D converter is indeterminate. The contents of ADi registers irrelevant to A-D conversion may also become indeterminate. If while A-D conversion is underway the ADST bit is set to "0" in a program, ignore the values of all ADi registers. Rev.1.00 2003.05.30 page 17 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.11 Precautions for CAN Module 1.11 Precautions for CAN Module 1.11.1 Reading CiSTR Register (i = 0, 1) The CAN module on the M16C/6N4 group updates the status of the CiSTR register in a certain period. When the CPU and the CAN module access to the CiSTR register at the same time, the CPU has the access priority; the access from the CAN module is disabled. Consequently, when the updating period of the CAN module matches the access period from the CPU, the status of the CAN module cannot be updated. (Refer to Figure 1.11.1.) Accordingly, be careful about the following points so that the access period from the CPU should not match the updating period of the CAN module: (1) There should be a wait time of 3fCAN or longer (refer to Table 1.11.1) before the CPU reads the CiSTR register. (Refer to Figure 1.11.2.) (2) When the CPU polls the CiSTR register, the polling period must be 3fCAN or longer. (Refer to Figure 1.11.3.) Table 1.11.1 CAN Module Status Updating Period 3f CAN period = 3 XIN (Original oscillation period) Division value of the CAN clock (CCLK) (Example 1) Condition XIN 16 MHz CCLK: Divided by 1 3f CAN period = 3 62.5 ns 1 = 187.5 ns (Example 2) Condition XIN 16 MHz CCLK: Divided by 2 3f CAN period = 3 62.5 ns 2 = 375 ns (Example 3) Condition XIN 16 MHz CCLK: Divided by 4 3f CAN period = 3 62.5 ns 4 = 750 ns (Example 4) Condition XIN 16 MHz CCLK: Divided by 8 3f CAN period = 3 62.5 ns 8 = 1.5 s (Example 5) Condition XIN 16 MHz CCLK: Divided by 16 3f CAN period = 3 62.5 ns 16 = 3 s Rev.1.00 2003.05.30 page 18 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.11 Precautions for CAN Module fCAN CPU read signal Updating period of CAN module CPU reset signal CiSTR register b8: State_Reset bit 0: CAN operation mode 1: CAN reset/initialization mode : When the CAN module's State_Reset bit updating period matches the CPU's read period, it does not enter reset mode, for the CPU read has the higher priority. i = 0, 1 Figure 1.11.1 When Updating Period of CAN Module Matches Access Period from CPU Wait time CPU read signal Updating period of the CAN module CPU reset signal CiSTR register b8: Reset state flag 0: CAN operation mode 1: CAN reset/initialization mode : Updated without fail in period of 3fCAN i = 0, 1 Figure 1.11.2 With a Wait Time of 3fCAN Before CPU Read CPU read signal 4fCAN Updating period of the CAN module CPU reset signal CiSTR register b8: State_Reset bit 0: CAN operation mode 1: CAN reset/initialization mode : When the CAN module's State_Reset bit updating period matches the CPU's read period, it does not enter reset mode, for the CPU read has the higher priority. : Updated without fail in period of 4fCAN i = 0, 1 Figure 1.11.3 When Polling Period of CPU is 3fCAN or Longer Rev.1.00 2003.05.30 page 19 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.11 Precautions for CAN Module 1.11.2 CAN Transceiver in Boot Mode When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver should be set to "high-speed mode" or "normal operation mode". If the operation mode is controlled by the microcomputer, CAN transceiver must be set the operation mode to "high-speed mode" or "normal operation mode" before programming the flash memory by changing the switch etc. Table 1.11.2 and 1.11.3 show pin connections of CAN transceiver. Table 1.11.2 Pin Connections of CAN Transceiver (In case of PCA82C250: Philips product) Standby mode High-speed mode Rs pin (Note 1) "H" "L" CAN communication impossible possible Connection M16C/6N4 M16C/6N4 PCA82C250 PCA82C250 CTxi TxD CANH CTxi TxD CANH CRxi RxD CANL CRxi RxD CANL Port (Note 2) Rs Port (Note 2) Rs Table 1.11.3 Pin Connections ofSwitch CAN Transceiver (In case of PCA82C252:Switch Philips product) OFF ON i = 0, 1 Note 1: The pin which controls the operation mode of CAN transceiver. Note 2: Connect to enabled port to control CAN transceiver. Table 1.11.3 Pin Connections of CAN Transceiver (In case of PCA82C252: Philips product) Sleep mode Normal operation mode _______ STB pin (Note 1) "L" "H" EN pin (Note 1) "L" "H" CAN communication impossible possible Connection M16C/6N4 PCA82C252 M16C/6N4 CTxi TxD CANH CTxi TxD CANH CRxi RxD CANL CRxi RxD CANL Port (Note 2) STB Port (Note 2) STB Port (Note 2) EN Port (Note 2) EN Switch OFF i = 0, 1 Note 1: The pin which controls the operation mode of CAN transceiver. Note 2: Connect to enabled port to control CAN transceiver. Rev.1.00 2003.05.30 PCA82C252 page 20 Switch ON Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.12 Precautions for Programmable I/O Ports 1.12 Precautions for Programmable I/O Ports _______ 1. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = "1" (three-phase _______ output forcible cutoff by input on NMI pin enabled), the P72 to P75, P80 and P81 pins go to a highimpedance state. 2. Setting the SM32 bit in the S3C register to "1" causes the P92 pin to go to a high-impedance state. 3. The input threshold voltage of pins differs between programmable input/output ports and peripheral functions. Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the input level at this pin is outside the range of recommended operating conditions VIH and VIL (neither "high" nor "low"), the input level may be determined differently depending on which side--the programmable input/output port or the peripheral function--is currently selected. Rev.1.00 2003.05.30 page 21 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.13 Precautions for Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers 1.13 Precautions for Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests conducted in the flash memory version. Rev.1.00 2003.05.30 page 22 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.14 Precautions for Flash Memory Version 1.14 Precautions for Flash Memory Version 1.14.1 Precautions for Functions to Prevent Flash Memory from Rewriting ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial I/O mode and CAN I/O mode. The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash memory cannot be read or written in parallel I/O mode. In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H) of fixed vectors. 1.14.2 Precautions for Stop Mode When shifting to stop mode, the following settings are required: * Set the FMR01 bit to "0" (CPU rewrite mode disabled) and disable DMA transfers before setting the CM10 bit to "1" (stop mode). * Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to "1" (stop mode) Example program BSET 0, CM1 ; Stop mode JMP.B L1 L1: Program after returning from stop mode 1.14.3 Precautions for Wait Mode When shifting to wait mode, set the FMR01 bit to "0" (CPU rewrite mode disabled) before executing the WAIT instruction. 1.14.4 Precautions for Low Power Dissipation Mode and Ring Oscillator Low Power Dissipation Mode If the CM05 bit is set to "1" (main clock stop), the following commands must not be executed. * Program * Block erase * Erase all unlocked blocks * Lock bit program 1.14.5 Writing command and data Write the command code and data at even addresses. 1.14.6 Precautions for Program Command Write "xx4016" in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle. 1.14.7 Precautions for Lock Bit Program Command Write "xx7716" in the first bus cycle and write "xxD016" to the uppermost address of a block (even address, however) in the second bus cycle, and the lock bit for the specified block is set to "0". Make sure the address value specified in the first bus cycle is the same uppermost block address that is specified in the second bus cycle. Rev.1.00 2003.05.30 page 23 Under development This document is under development and its contents are subject to change. M16C/6N4 Group 1.14 Precautions for Flash Memory Version 1.14.8 Operation speed Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for BCLK using the CM06 bit of the CM0 register and the CM17 to CM16 bits of the CM1 register. Also, set the PM17 bit of the PM1 register to "1" (with wait state). 1.14.9 Instructions to prevent from using The following instructions cannot be used in EW0 mode because the flash memory's internal data is referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction 1.14.10 Interrupts EW0 Mode * Any interrupt which has a vector in the variable vector table can be used providing that its vector is transferred into the RAM area. _______ * The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register are initialized when one of those interrupts occurs. The jump addresses for those interrupt service routines should be set in the fixed vector table. _______ Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. * The address match interrupt cannot be used because the flash memory's internal data is referenced. EW1 Mode * Make sure that any interrupt which has a vector in the variable vector table or address match interrupt will not be accepted during the auto program or auto erase period. * Avoid using watchdog timer interrupts. _______ * The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed vector table. _______ Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. 1.14.11 How to access To set the FMR01, FMR02, or FMR11 bit to "1", write "0" and then "1" in succession. This is necessary to ensure that no interrupts or no DMA transfers will occur before writing "1" after writing "0". Also only _______ when NMI pin is "H" level. 1.14.12 Writing in user ROM area EW0 Mode * If the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, consequently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial I/O, parallel I/O or CAN I/O mode should be used. EW1 Mode * Avoid rewriting any block in which the rewrite control program is stored. 1.14.13 DMA transfer In EW1 mode, make sure that no DMA transfers will occur while the FMR00 bit of the FMR0 register = 0 (during the auto program or auto erase period). Rev.1.00 2003.05.30 page 24 REVISION HISTORY Rev. Date 1.00 May 30, 2003 M16C/6N4 Group Usage Notes Description Page - Summary First edition issued B-1 Blank page RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER USAGE NOTES REFERENCE BOOK M16C/6N4 Group Rev.1.00 Editioned by Committee of editing of RENESAS Semiconductor Usage Notes Reference Book This book, or parts thereof, may not be reproduced in any form without permission of Renesas Technology Corporation. Copyright (c) 2003. Renesas Technology Corporation, All rights reserved. M16C/6N4 Group Usage Notes Reference Book 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan