Keep safety first in your circuit designs!
Notes regarding these materials
•Renesas Technology Corporation puts the maximum effort into making semiconductor prod-
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them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
• These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corporation product best suited to the customer's application; they do
not convey any license under any intellectual property rights, or any other rights, belonging
to Renesas Technology Corporation or a third party.
• Renesas Technology Corporation assumes no responsibility for any damage, or infringe-
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programs, algorithms, or circuit application examples contained in these materials.
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grams and algorithms represents information on products at the time of publication of these
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listed herein.
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How to Use This Manual
This hardware manual provides detailed information on features in the M16C/6N4 Group microcomputer.
Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputer.
Each register diagram contains bit functions with the following symbols and descriptions.
*1
Blank:Set to “0” or “1” according to your intended use
0: Set to “0”
1: Set to “1”
X: Nothing is assigned
*2
RW: Read and write
RO: Read only
WO: Write only
–: Nothing is assigned
*3
Terms to use here are explained as follows.
• Nothing is assigned
Nothing is assigned to the bit concerned. When write, set to “0” for new function in future plan.
• Reserved bit
Reserved bit. Set the specified value.
• Avoid this setting
The operation at having selected is not guaranteed.
• Function varies depending on each operation mode
Bit function varies depending on peripheral function mode.
Refer to register diagrams in each mode.
Function
XXX register
Bit name
Bit
symbol
Symbol
XXX
Address
XXX
After reset
00
16
RW
RW
RW
RW
WO
RO
XXX
0
XXX
1
-
(b2)
-
(b3)
XXX bit
Reserved bit
XXX
7
Set to "0"
0: XXX
1: XXX
Nothing is assigned. When write, set to "0",
When read, its content is indeterminate.
XXX bit
0 0: XXX
0 1: XXX
1 0: Avoid this setting
1 1: XXX
b1 b0
XXX bit
Function varies depending on
each operation mode
XXX4
XXX
5
XXX
6
0
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0 *1
*2
*3
M16C Family Documents
The following document is prepared with the M16C family.
Document Contents
Short Sheet Hardware overview
Data Sheet Hardware overview and electrical characteristics
Hardware Manual Hardware specifications (pin assignments, memory maps, specifications
of peripheral functions, electrical characteristics, timing charts)
Software Manual Detailed description about instructions and microcomputer performance
by each instruction
Application Note • Application examples of peripheral functions
• Sample programs
• Introductory description about basic functions in M16C family
• Programming method with the assembly and C languages
A-1
Table of Contents
Quick Reference to Pages Classified by Address
Overview ................................................................................................................................... 1
Applications ........................................................................................................................................................ 1
Performance Outline .......................................................................................................................................... 2
Block Diagram .................................................................................................................................................... 3
Product List ........................................................................................................................................................ 4
Pin Configuration ............................................................................................................................................... 5
Pin Description ................................................................................................................................................... 6
Memory ..................................................................................................................................... 8
Central Processing Unit (CPU) ................................................................................................. 9
(1) Data Registers (R0, R1, R2, and R3) ........................................................................................................... 9
(2) Address Registers (A0 and A1) .................................................................................................................... 9
(3) Frame Base Register (FB) .......................................................................................................................... 10
(4) Interrupt Table Register (INTB) ................................................................................................................... 10
(5) Program Counter (PC) ................................................................................................................................ 10
(6) User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ............................................................................ 10
(7) Static Base Register (SB) ........................................................................................................................... 10
(8) Flag Register (FLG) .................................................................................................................................... 10
SFR ......................................................................................................................................... 11
Reset ....................................................................................................................................... 27
Hardware Reset ............................................................................................................................................... 27
Software Reset ................................................................................................................................................ 27
Watchdog Timer Reset ..................................................................................................................................... 27
Oscillation Stop Detection Reset ..................................................................................................................... 27
Processor Mode ...................................................................................................................... 30
(1) Types of Processor Mode ........................................................................................................................... 30
(2) Setting Processor Modes ........................................................................................................................... 30
Bus .......................................................................................................................................... 36
Bus Mode ......................................................................................................................................................... 36
Bus Control ...................................................................................................................................................... 37
(1) Address Bus .......................................................................................................................................... 37
(2) Data Bus ................................................................................................................................................ 37
(3) Chip Select Signal ................................................................................................................................. 37
(4) Read and Write Signals ......................................................................................................................... 39
(5) ALE Signal ............................................................................................................................................. 39
________
(6) The RDY Signal ..................................................................................................................................... 40
__________
(7) HOLD Signal.......................................................................................................................................... 41
(8) BCLK Output ......................................................................................................................................... 41
(9) External Bus Status When Internal Area Accessed............................................................................... 43
(10) Software Wait ...................................................................................................................................... 43
A-2
Clock Generation Circuit ......................................................................................................... 47
(1) Main Clock ............................................................................................................................................. 55
(2) Sub Clock .............................................................................................................................................. 56
(3) Ring Oscillator Clock ............................................................................................................................. 57
(4) PLL Clock .............................................................................................................................................. 57
CPU Clock and Peripheral Function Clock ...................................................................................................... 59
(1) CPU Clock and BCLK............................................................................................................................ 59
(2) Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fCAN0, fCAN1, fC32)................................... 59
Clock Output Function ..................................................................................................................................... 59
Power Control .................................................................................................................................................. 60
(1) Normal Operation Mode ........................................................................................................................ 60
(2) Wait Mode ............................................................................................................................................. 62
(3) Stop Mode ............................................................................................................................................. 64
Oscillation Stop and Re-oscillation Detection Function ................................................................................... 69
Protection ................................................................................................................................ 71
Interrupts ................................................................................................................................. 72
Type of Interrupts ............................................................................................................................................. 72
Software Interrupts ........................................................................................................................................... 73
Hardware Interrupts ......................................................................................................................................... 74
Interrupts and Interrupt Vector ......................................................................................................................... 75
Interrupt Control ............................................................................................................................................... 77
______
INT Interrupt ..................................................................................................................................................... 85
______
NMI Interrupt .................................................................................................................................................... 87
Key Input Interrupt ........................................................................................................................................... 87
CAN0/1 Wake-up Interrupt ............................................................................................................................... 87
Address Match Interrupt ................................................................................................................................... 88
Watchdog Timer ...................................................................................................................... 90
DMAC...................................................................................................................................... 92
1. Transfer Cycle .............................................................................................................................................. 97
2. DMA Transfer Cycles ................................................................................................................................... 99
3. DMA Enable ............................................................................................................................................... 100
4. DMA Request ............................................................................................................................................. 100
5. Channel Priority and DMA Transfer Timing ................................................................................................ 101
Timers ................................................................................................................................... 102
Timer A ........................................................................................................................................................... 104
1. Timer Mode ........................................................................................................................................... 108
2. Event Counter Mode ............................................................................................................................. 109
3. One-shot Timer Mode ........................................................................................................................... 114
4. Pulse Width Modulation (PWM) Mode .................................................................................................. 116
Timer B........................................................................................................................................................... 119
1. Timer Mode ........................................................................................................................................... 122
2. Event Counter Mode ............................................................................................................................. 123
3. Pulse Period and Pulse Width Measurement Mode ............................................................................. 124
Three-phase Motor Control Timer Function .......................................................................... 127
A-3
Serial I/O ............................................................................................................................... 138
UARTi (i = 0 to 2) ........................................................................................................................................... 138
Clock Synchronous Serial I/O Mode ......................................................................................................... 147
Clock Asynchronous Serial I/O (UART) Mode .......................................................................................... 154
Special Mode 1 (I2C Mode) ....................................................................................................................... 161
Special Mode 2 ......................................................................................................................................... 170
Special Mode 3 (IE Mode) ........................................................................................................................ 175
Special Mode 4 (SIM Mode) (UART2) ...................................................................................................... 177
SI/O3 .............................................................................................................................................................. 182
A-D Converter ....................................................................................................................... 187
(1) One-shot Mode ......................................................................................................................................... 191
(2) Repeat Mode ............................................................................................................................................ 193
(3) Single Sweep Mode .................................................................................................................................. 195
(4) Repeat Sweep Mode 0 ............................................................................................................................. 197
(5) Repeat Sweep Mode 1 ............................................................................................................................. 199
D-A Converter ....................................................................................................................... 203
CRC Calculation.................................................................................................................... 205
CAN Module .......................................................................................................................... 207
CAN Module-Related Registers ..................................................................................................................... 208
CANi Message Box (i = 0, 1) .................................................................................................................... 209
Acceptance Mask Registers ..................................................................................................................... 211
CAN SFR Registers .................................................................................................................................. 212
Operational Modes ......................................................................................................................................... 220
Configuration of the CAN Module System Clock ........................................................................................... 222
CAN Bus Timing Control ................................................................................................................................ 222
Acceptance Filtering Function and Masking Function ................................................................................... 224
Acceptance Filter Support Unit (ASU) ........................................................................................................... 225
Basic CAN Mode ............................................................................................................................................ 226
Return from Bus off Function ......................................................................................................................... 227
Time Stamp Counter and Time Stamp Function ............................................................................................ 227
Listen-Only Mode ........................................................................................................................................... 227
Reception and Transmission .......................................................................................................................... 228
CAN Interrupts ............................................................................................................................................... 231
Programmable I/O Ports ....................................................................................................... 232
(1) Port Pi Direction Register (PDi Register, i = 0 to 10) ................................................................................ 232
(2) Port Pi Register (Pi Register, i = 0 to 10) .................................................................................................. 232
(3) Pull-up Control Register j (PURj Register, j = 0 to 2) ................................................................................ 232
(4) Port Control Register (PCR Register) ....................................................................................................... 232
Electrical Characteristics ....................................................................................................... 244
Flash Memory ....................................................................................................................... 262
Flash Memory Performance ........................................................................................................................... 262
Memory Map .................................................................................................................................................. 263
Boot Mode ...................................................................................................................................................... 264
Functions to Prevent Flash Memory from Rewriting ...................................................................................... 264
CPU Rewrite Mode ........................................................................................................................................ 266
Standard Serial I/O Mode .............................................................................................................................. 283
Parallel I/O Mode ........................................................................................................................................... 287
CAN I/O Mode ................................................................................................................................................ 288
Electrical Characteristics ................................................................................................................................ 291
A-4
Package Dimension .............................................................................................................. 292
Register Index ....................................................................................................................... 293
M16C/6N4 Group Usage Note Reference Book
For the most current Usage Notes Reference Book, please visit our website.
Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free
of error. Specifications in this manual may be changed for functional or performance improvements.
Please make sure your manual is the latest edition.
B-1
Quick Reference to Pages Classified by Address
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
Chip select control register
Address match interrupt enable register
Protect register
Oscillation stop detection register
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
Address match interrupt register 1
Chip select expansion control register
PLL control register 0
Processor mode register 2
DMA0 source pointer
DMA0 destination pointer
DMA0 transfer counter
DMA0 control register
DMA1 source pointer
DMA1 destination pointer
DMA1 transfer counter
DMA1 control register
PM0
PM1
CM0
CM1
CSR
AIER
PRCR
CM2
WDTS
WDC
RMAD0
RMAD1
CSE
PLC0
PM2
SAR0
DAR0
TCR0
DM0CON
SAR1
DAR1
TCR1
DM1CON
31
32
49
50
37
89
71
51
91
91
89
89
43
54
53
96
96
96
95
96
96
96
95
Address Register Symbol Page
The blank areas are reserved.
C01WKIC
C0RECIC
C0TRMIC
INT3IC
TB5IC
TB4IC
U1BCNIC
TB3IC
U0BCNIC
C1RECIC
INT5IC
C1TRMIC
S3IC
INT4IC
U2BCNIC
DM0IC
DM1IC
C01ERRIC
ADIC
KUPIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
CAN0/1 wake up interrupt control register
CAN0 successful reception interrupt control register
CAN0 successful transmission interrupt control register
INT3 interrupt control register
Timer B5 interrupt control register
Timer B4 interrupt control register
UART1 bus collision detection interrupt control register
Timer B3 interrupt control register
UART0 bus collision detection interrupt control register
CAN1 successful reception interrupt control register
INT5 interrupt control register
CAN1 successful transmission interrupt control register
SI/O3 interrupt control register
INT4 interrupt control register
UART2 bus collision detection interrupt control register
DMA0 interrupt control register
DMA1 interrupt control register
CAN0/1 error interrupt control register
A-D conversion interrupt control register
Key input interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
CAN0 message box 0: Identifier / DLC
CAN0 message box 0: Data field
CAN0 message box 0: Time stamp
CAN0 message box 1: Identifier / DLC
CAN0 message box 1: data Field
CAN0 message box 1: Time stamp
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
77
77
77
78
77
77
77
77
77
78
78
78
78
78
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
78
78
78
209
210
Address Register Symbol Page
B-2
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
009E16
009F16
00A016
00A116
00A216
00A316
00A416
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
209
210
CAN0 message box 2: Identifier / DLC
CAN0 message box 2: Data field
CAN0 message box 2: Time stamp
CAN0 message box 3: Identifier / DLC
CAN0 message box 3: Data field
CAN0 message box 3: Time stamp
CAN0 message box 4: Identifier / DLC
CAN0 message box 4: Data field
CAN0 message box 4: Time stamp
CAN0 message box 5: Identifier / DLC
CAN0 message box 5: Data field
CAN0 message box 5: Time stamp
Address Register Symbol Page
CAN0 message box 6: Identifier / DLC
CAN0 message box 6: Data field
CAN0 message box 6: Time stamp
CAN0 message box 7: Identifier / DLC
CAN0 message box 7: Data field
CAN0 message box 7: Time stamp
CAN0 message box 8: Identifier / DLC
CAN0 message box 8: Data field
CAN0 message box 8: Time stamp
CAN0 message box 9: Identifier / DLC
CAN0 message box 9: Data field
CAN0 message box 9: Time stamp
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
209
210
Address Register Symbol Page
B-3
CAN0 message box 10:
Identifier / DLC
CAN0 message box 10: Data field
CAN0 message box 10: Time stamp
CAN0 message box 11:
Identifier / DLC
CAN0 message box 11: Data field
CAN0 message box 11: Time stamp
CAN0 message box 12:
Identifier / DLC
CAN0 message box 12: Data field
CAN0 message box 12: Time stamp
CAN0 message box 13:
Identifier / DLC
CAN0 message box 13: Data field
CAN0 message box 13: Time stamp
209
210
010016
010116
010216
010316
010416
010516
010616
010716
010816
010916
010A16
010B16
010C16
010D16
010E16
010F16
011016
011116
011216
011316
011416
011516
011616
011716
011816
011916
011A16
011B16
011C16
011D16
011E16
011F16
012016
012116
012216
012316
012416
012516
012616
012716
012816
012916
012A16
012B16
012C16
012D16
012E16
012F16
013016
013116
013216
013316
013416
013516
013616
013716
013816
013916
013A16
013B16
013C16
013D16
013E16
013F16
Address Register Symbol Page
The blank areas are reserved.
CAN0 message box 14:
Identifier /DLC
CAN0 message box 14: Data field
CAN0 message box 14: Time stamp
CAN0 message box 15:
Identifier /DLC
CAN0 message box 15: Data field
CAN0 message box 15: Time stamp
CAN0 global mask register
CAN0 local mask A register
CAN0 local mask B register
014016
014116
014216
014316
014416
014516
014616
014716
014816
014916
014A16
014B16
014C16
014D16
014E16
014F16
015016
015116
015216
015316
015416
015516
015616
015716
015816
015916
015A16
015B16
015C16
015D16
015E16
015F16
016016
016116
016216
016316
016416
016516
016616
016716
016816
016916
016A16
016B16
016C16
016D16
016E16
016F16
017016
017116
017216
017316
017416
017516
017616
017716
017816
017916
017A16
017B16
017C16
017D16
017E16
017F16
209
210
211
211
211
C0GMR
C0LMAR
C0LMBR
Address Register Symbol Page
B-4
0180
16
0181
16
0182
16
0183
16
0184
16
0185
16
0186
16
0187
16
0188
16
0189
16
018A
16
018B
16
018C
16
018D
16
018E
16
018F
16
0190
16
0191
16
0192
16
0193
16
0194
16
0195
16
0196
16
0197
16
0198
16
0199
16
019A
16
019B
16
019C
16
019D
16
019E
16
019F
16
01A0
16
01A1
16
01A2
16
01A3
16
01A4
16
01A5
16
01A6
16
01A7
16
01A8
16
01A9
16
01AA
16
01AB
16
01AC
16
01AD
16
01AE
16
01AF
16
01B0
16
01B1
16
01B2
16
01B3
16
01B4
16
01B5
16
01B6
16
01B7
16
01B8
16
01B9
16
01BA
16
01BB
16
01BC
16
01BD
16
01BE
16
01BF
16
269
269
89
89
89
The blank areas are reserved.
Flash memory control register 1
Flash memory control register 0
Address match interrupt register 2
Address match interrupt enable register 2
Address match interrupt register 3
FMR1
FMR0
RAMD2
AIER2
RAMD3
Address Register Symbol Page
01C0
16
01C1
16
01C2
16
01C3
16
01C4
16
01C5
16
01C6
16
01C7
16
01C8
16
01C9
16
01CA
16
01CB
16
01CC
16
01CD
16
01CE
16
01CF
16
01D0
16
01D1
16
01D2
16
01D3
16
01D4
16
01D5
16
01D6
16
01D7
16
01D8
16
01D9
16
01DA
16
01DB
16
01DC
16
01DD
16
01DE
16
01DF
16
01E0
16
01E1
16
01E2
16
01E3
16
01E4
16
01E5
16
01E6
16
01E7
16
01E8
16
01E9
16
01EA
16
01EB
16
01EC
16
01ED
16
01EE
16
01EF
16
01F0
16
01F1
16
01F2
16
01F3
16
01F4
16
01F5
16
01F6
16
01F7
16
01F8
16
01F9
16
01FA
16
01FB
16
01FC
16
01FD
16
01FE
16
01FF
16
121
132
132
132
129
130
131
131
131
133
120
120
120
120
122
123
125
86
86
183
183
183
146
145
145
144
146
145
145
144
146
145
145
144
142
141
141
142
143
141
Timer B3,4,5 count start flag
Timer A1-1 register
Timer A2-1 register
Timer A4-1 register
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Dead time timer
Timer B2 interrupt occurrence frequency set counter
Timer B3 register
Timer B4 register
Timer B5 register
Timer B3 mode register
Timer B4 mode register
Timer B5 mode register
Interrupt cause select register 0
Interrupt cause select register 1
SI/O3 transmit/receive register
SI/O3 control register
SI/O3 bit rate generator
UART0 special mode register 4
UART0 special mode register 3
UART0 special mode register 2
UART0 special mode register
UART1 special mode register 4
UART1 special mode register 3
UART1 special mode register 2
UART1 special mode register
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate generator
UART2 transmit buffer register
UART2 transmit/receive mode register 0
UART2 transmit/receive mode register 1
UART2 receive buffer register
TBSR
TA11
TA21
TA41
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
TB3
TB4
TB5
TB3MR
TB4MR
TB5MR
IFSR0
IFSR1
S3TRR
S3C
S3BRG
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
U2C0
U2C1
U2RB
Address Register Symbol Page
B-5
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
C0CTLR
C0STR
C0SSTR
C0ICR
C0IDR
C0CONR
C0RECR
C0TECR
C0TSR
C1MCTL0
C1MCTL1
C1MCTL2
C1MCTL3
C1MCTL4
C1MCTL5
C1MCTL6
C1MCTL7
C1MCTL8
C1MCTL9
C1MCTL10
C1MCTL11
C1MCTL12
C1MCTL13
C1MCTL14
C1MCTL15
C1CTLR
C1STR
C1SSTR
C1ICR
C1IDR
C1CONR
C1RECR
C1TECR
C1TSR
020016
020116
020216
020316
020416
020516
020616
020716
020816
020916
020A16
020B16
020C16
020D16
020E16
020F16
021016
021116
021216
021316
021416
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
022016
022116
022216
022316
022416
022516
022616
022716
022816
022916
022A16
022B16
022C16
022D16
022E16
022F16
023016
023116
023216
023316
023416
023516
023616
023716
023816
023916
023A16
023B16
023C16
023D16
023E16
023F16
212
213
214
215
216
216
217
218
218
219
212
213
214
215
216
216
217
218
218
219
CAN0 message control register 0
CAN0 message control register 1
CAN0 message control register 2
CAN0 message control register 3
CAN0 message control register 4
CAN0 message control register 5
CAN0 message control register 6
CAN0 message control register 7
CAN0 message control register 8
CAN0 message control register 9
CAN0 message control register 10
CAN0 message control register 11
CAN0 message control register 12
CAN0 message control register 13
CAN0 message control register 14
CAN0 message control register 15
CAN0 control register
CAN0 status register
CAN0 slot status register
CAN0 interrupt control register
CAN0 extended register
CAN0 configuration register
CAN0 receive error count register
CAN0 transmit error count register
CAN0 time stamp register
CAN1 message control register 0
CAN1 message control register 1
CAN1 message control register 2
CAN1 message control register 3
CAN1 message control register 4
CAN1 message control register 5
CAN1 message control register 6
CAN1 message control register 7
CAN1 message control register 8
CAN1 message control register 9
CAN1 message control register 10
CAN1 message control register 11
CAN1 message control register 12
CAN1 message control register 13
CAN1 message control register 14
CAN1 message control register 15
CAN1 control register
CAN1 status register
CAN1 slot status register
CAN1 interrupt control register
CAN1 extended register
CAN1 configuration register
CAN1 receive error count register
CAN1 transmit error count register
CAN1 time stamp register
Address Register Symbol Page
The blank areas are reserved.
0240
16
0241
16
0242
16
0243
16
0244
16
0245
16
0246
16
0247
16
0248
16
0249
16
024A
16
024B
16
024C
16
024D
16
024E
16
024F
16
0250
16
0251
16
0252
16
0253
16
0254
16
0255
16
0256
16
0257
16
0258
16
0259
16
025A
16
025B
16
025C
16
025D
16
025E
16
025F
16
0260
16
0261
16
0262
16
0263
16
0264
16
0265
16
0266
16
0267
16
0268
16
0269
16
026A
16
026B
16
026C
16
026D
16
026E
16
026F
16
0270
16
0271
16
0272
16
0273
16
0274
16
0275
16
0276
16
0277
16
0278
16
0279
16
027A
16
027B
16
027C
16
027D
16
027E
16
027F
16
219
219
52
52
209
210
CAN0 acceptance filter support register
CAN1 acceptance filter support register
Peripheral function clock select register
CAN0/1 clock select register
CAN1 message box 0: Identifier / DLC
CAN1 message box 0: Data field
CAN1 message box 0:Time stamp
CAN1 message box 1: Identifier / DLC
CAN1 message box 1: Data field
CAN1 message box 1:Time stamp
C0AFS
C1AFS
PCLKR
CCLKR
Address Register Symbol Page
B-6
CAN1 message box 2: Identifier / DLC
CAN1 message box 2: Data field
CAN1 message box 2: Time stamp
CAN1 message box 3: Identifier / DLC
CAN1 message box 3: Data field
CAN1 message box 3: Time stamp
CAN1 message box 4: Identifier / DLC
CAN1 message box 4: Data field
CAN1 message box 4: Time stamp
CAN1 message box 5: Identifier / DLC
CAN1 message box 5: Data field
CAN1 message box 5: Time stamp
028016
028116
028216
028316
028416
028516
028616
028716
028816
028916
028A16
028B16
028C16
028D16
028E16
028F16
029016
029116
029216
029316
029416
029516
029616
029716
029816
029916
029A16
029B16
029C16
029D16
029E16
029F16
02A016
02A116
02A216
02A316
02A416
02A516
02A616
02A716
02A816
02A916
02AA16
02AB16
02AC16
02AD16
02AE16
02AF16
02B016
02B116
02B216
02B316
02B416
02B516
02B616
02B716
02B816
02B916
02BA16
02BB16
02BC16
02BD16
02BE16
02BF16
209
210
Address Register Symbol Page
CAN1 message box 6: Identifier / DLC
CAN1 message box 6: Data field
CAN1 message box 6: Time stamp
CAN1 message box 7: Identifier / DLC
CAN1 message box 7: Data field
CAN1 message box 7: Time stamp
CAN1 message box 8: Identifier / DLC
CAN1 message box 8: Data field
CAN1 message box 8: Time stamp
CAN1 message box 9: Identifier / DLC
CAN1 message box 9: Data field
CAN1 message box 9: Time stamp
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
02EB16
02EC16
02ED16
02EE16
02EF16
02F016
02F116
02F216
02F316
02F416
02F516
02F616
02F716
02F816
02F916
02FA16
02FB16
02FC16
02FD16
02FE16
02FF16
209
210
Address Register Symbol Page
B-7
CAN1 message box 10:
Identifier / DLC
CAN1 message box 10: Data field
CAN1 message box 10: Time stamp
CAN1 message box 11:
Identifier / DLC
CAN1 message box 11: Data field
CAN1 message box 11: Time stamp
CAN1 message box 12:
Identifier / DLC
CAN1 message box 12: Data field
CAN1 message box 12: Time stamp
CAN1 message box 13:
Identifier / DLC
CAN1 message box 13: Data field
CAN1 message box 13: Time stamp
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
209
210
Address Register Symbol Page
The blank areas are reserved.
CAN1 message box 14:
Identifier / DLC
CAN1 message box 14: Data field
CAN1 message box 14: Time stamp
CAN1 message box 15:
Identifier / DLC
CAN1 message box 15: Data field
CAN1 message box 15: Time stamp
CAN1 global mask register
CAN1 local mask A register
CAN1 local mask B register
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
209
210
211
211
211
C0GMR
C0LMAR
C0LMBR
Address Register Symbol Page
B-8
TABSR
CPSRF
ONSF
TRGSR
UDF
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
U0MR
U0BRG
U0TB
U0C0
U0C1
U0RB
U1MR
U1BRG
U1TB
U1C0
U1C1
U1RB
UCON
DM0SL
DM1SL
CRCD
CRCIN
Count start flag
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-down flag
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Timer B2 special mode register
UART0 transmit/receive mode register
UART0 bit rate generator
UART0 transmit buffer register
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 bit rate generator
UART1 transmit buffer register
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 receive buffer register
UART transmit/receive control register 2
DMA0 request cause select register
DMA1 request cause select register
CRC data register
CRC input register
0380
16
0381
16
0382
16
0383
16
0384
16
0385
16
0386
16
0387
16
0388
16
0389
16
038A
16
038B
16
038C
16
038D
16
038E
16
038F
16
0390
16
0391
16
0392
16
0393
16
0394
16
0395
16
0396
16
0397
16
0398
16
0399
16
039A
16
039B
16
039C
16
039D
16
039E
16
039F
16
03A0
16
03A1
16
03A2
16
03A3
16
03A4
16
03A5
16
03A6
16
03A7
16
03A8
16
03A9
16
03AA
16
03AB
16
03AC
16
03AD
16
03AE
16
03AF
16
03B0
16
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
03B6
16
03B7
16
03B8
16
03B9
16
03BA
16
03BB
16
03BC
16
03BD
16
03BE
16
03BF
16
106,121,134
107,121
107
107,134
106
105
105
132
105
132
105
105
132
120
120
120
132
135
133
142
141
141
142
143
141
142
141
141
142
143
141
144
94
95
205
205
135
112,135
112
112,135
The blank areas are reserved.
105
108
110
115
117
120,122
123,125
Address Register Symbol Page
03C0
16
03C1
16
03C2
16
03C3
16
03C4
16
03C5
16
03C6
16
03C7
16
03C8
16
03C9
16
03CA
16
03CB
16
03CC
16
03CD
16
03CE
16
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
03D5
16
03D6
16
03D7
16
03D8
16
03D9
16
03DA
16
03DB
16
03DC
16
03DD
16
03DE
16
03DF
16
03E0
16
03E1
16
03E2
16
03E3
16
03E4
16
03E5
16
03E6
16
03E7
16
03E8
16
03E9
16
03EA
16
03EB
16
03EC
16
03ED
16
03EE
16
03EF
16
03F0
16
03F1
16
03F2
16
03F3
16
03F4
16
03F5
16
03F6
16
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
03FD
16
03FE
16
03FF
16
190
190
189,192,194
196,198,200
204
204
204
239
239
238
238
239
239
238
238
239
239
238
238
239
239
238
238
239
239
238
238
239
238
240
240
240
241
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
A-D control register 2
A-D control register 0
A-D control register 1
D-A register 0
D-A register 1
D-A control register
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P9 register
Port P8 direction register
Port P9 direction register
Port P10 register
Port P10 direction register
Pull-up control register 0
Pull-up control register 1
Pull-up control register 2
Port control register
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ADCON2
ADCON0
ADCON1
DA0
DA1
DACON
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
PD10
PUR0
PUR1
PUR2
PCR
Address Register Symbol Page
Rev.1.00 2003.05.30 page 1
M16C/6N4 Group Overview
Under development
This document is under development and its contents are subject to change.
Overview
The M16C/6N4 group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using an M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed.
Being equipped with two CAN (Controller Area Network) modules in M16C/6N4 group, the microcomputer
is suited to drive automotive and industrial control systems. The CAN modules comply with the 2.0B
specification. In addition, this microcomputer contains a multiplier and DMAC which combined with fast
instruction processing capability, makes it suitable for control of various OA, communication, and industrial
equipment which requires high-speed arithmetic/logic operations.
Applications
Automotive, industrial control systems and other autmobile, other
Rev.1.00 2003.05.30 page 2
M16C/6N4 Group Overview
Under development
This document is under development and its contents are subject to change.
}
Performance Outline
Table 1.1.1 lists a performance outline of M16C/6N4 group.
Table 1.1.1 Performance outline of M16C/6N4 Group
Item Performance
Number of basic instructions 91 instructions
Shortest instruction execution time 50.0 ns (f(BCLK)=20MHz, 1/1 prescaler, without software wait)
Memory ROM (Refer to the product list)
capacity RAM (Refer to the product list)
I/O port P0 to P10 (except P85) 8 bits ✕ 10, 7 bits ✕ 1
Input port P85
_______
1 bit ✕ 1 (NMI pin level judgment)
Multifunction TA0, TA1, TA2, TA3, TA4 Output: 16 bits ✕ 5 channels
timer TB0, TB1, TB2, TB3, TB4, TB5 Input: 16 bits ✕ 6 channels
Serial I/O UART0, UART1, UART2 3 channels: UART, clock synchronous, I2C-bus (Note 1) (option)
or IEBus (Note 2) (option)
SI/O3 1 channel: Clock synchronous
A-D converter 10 bits ✕ (8 ✕ 3 + 2) channels
D-A converter 8 bits ✕ 2 channels
DMAC 2 channels (trigger: 24 sources)
CRC calculation circuit 1 circuit: CRC-CCITT
CAN Module 2 channels with 2.0B specification
Watchdog timer 15 bits ✕ 1 (with prescaler)
Interrupt 31 internal and 9 external sources,
4 software sources, 7 levels
Clock generation circuit 4 circuits
· Main clock
· Sub clock
· Ring oscillator
· PLL frequency synthesizer
Main clock oscillation stop and re-oscillation detection function
Power supply voltage
4.2 to 5.5V (f(BCLK) = 20MHz, 1/1 prescaler, without software wait)
Flash memory Program/erase voltage 5.0 ± 0.5 V
Number of program/erase 100 times
Power consumption Mask ROM version: 18 mA
(Vcc=5V, (f(BCLK)=20MHz, 1/1 prescaler, without software wait)
Flash memory version: 20 mA
(Vcc=5V, (f(BCLK)=20MHz, 1/1 prescaler, without software wait)
I/O characteristics I/O withstand voltage 5.0 V
Output current 5 mA
Operating ambient temperature -40 to 85°C (T version)
-40 to 125°C (V version) (option)
Memory expansion Available (to 1 Mbyte)
Device configuration CMOS high performance silicon gate
Package 100-pin plastic mold QFP
Note 1: I2C-bus is a registered trademark of Koninklijke Philips Electronics N.V.
Note 2: IEBus is a registered trademark of NEC Electronics Corporation.
option: If you desire this option, please so specify.
These circuit contain a built-in feedback resistor;
and external ceramic/quartz oscillator
Rev.1.00 2003.05.30 page 3
M16C/6N4 Group Overview
Under development
This document is under development and its contents are subject to change.
Block Diagram
Figure 1.1.1 shows a block diagram of M16C/6N4 group.
Figure 1.1.1 Block Diagram
Timer (16 bits)
Output (timer A): 5
Input (timer B): 6
Three-phase motor
control circuit
Internal peripheral functions
Watchdog timer
(15 bits)
A-D converter
(10 bits ✕ 8 channels
Expandable up to 26 channels)
UART or
Clock synchronous serial I/O
(8 bits ✕ 3 channels)
System clock generator
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
Ring oscillator
Port P0
8
Port P1
8
Port P2
8 8 8 8
Port P6
8
8788
Port
P10
Port P9
Port
P8
5
Port P8
Port P7
Port P5Port P4Port P3
CRC arithmetic circuit (CCITT)
(Polynomial: X
16
+X
12
+X
5
+1)
Clock synchronous serial I/O
(8 bits ✕ 1 channel)
CAN module
(2 channels)
DMAC
(2 channels)
D-A converter
(8 bits ✕ 2 channels)
MemoryM16C/60 series CPU core
R1H R1L
R1H R1L
R2
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
Multiplier
INTB
PC
USP
ISP
SB
FLG
ROM
(Note 1)
RAM
(Note 2)
Note 1: ROM size depends on microcomputer type.
Note 2: RAM size depends on microcomputer type.
Rev.1.00 2003.05.30 page 4
M16C/6N4 Group Overview
Under development
This document is under development and its contents are subject to change.
Product List
Table 1.1.2 lists the M16C/6N4 group products and Figure 1.1.2 shows the type numbers, memory sizes
and packages.
Table 1.1.2 Product List
Figure 1.1.2 Type No., Memory Size, and Package
Package type:
FP : Package 100P6S-A
ROM No.
Omitted on flash memory version
ROM capacity:
C : 128 Kbytes
G : 256 Kbytes
Memory type:
M : Mask ROM version
F : Flash ROM version
Type No. M 3 0 6 N 4 M C T X X X F P
M16C Family
M16C/6N4 Group
Shows the number of CAN module,
RAM capacity, pin count, etc.
(The value itself has no specific meaning)
Temperature Range
T : Automotive 85
o
C version
V : Automotive 125
o
C version
Type No. ROM capacity RAM capacity Package type Remarks
M306N4MCT-XXXFP ** 128 Kbytes 5 Kbytes 100P6S-A Mask ROM version
M306N4MCV-XXXFP *
M306N4FCTFP ** Flash memory version
M306N4FCVFP *
M306N4MGT-XXXFP * 256 Kbytes 10 Kbytes Mask ROM version
M306N4MGV-XXXFP *
M306N4FGTFP ** Flash memory version
M306N4FGVFP *
*: Under planning
**: Under development
As of May 2003
Rev.1.00 2003.05.30 page 5
M16C/6N4 Group Overview
Under development
This document is under development and its contents are subject to change.
PIN CONFIGURATION (top view)
Figure 1.1.3 Pin Configuration (Top View)
Pin Configuration
Figures 1.1.3 shows the pin configuration (top view).
12345 6789101112131415161718192021222324252627282930
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
515253545556575859606162636465666768697071727374757677787980
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
1
00
P0
7
/AN
07
/D
7
P1
0
/D
8
P1
1
/D
9
P1
2
/D
10
P1
3
/D
11
P1
4
/D
12
V
REF
AV
SS
V
CC1
X
IN
X
OUT
V
SS
RESET
CNVss
P8
7
/X
CIN
P8
6
/X
COUT
BYTE
P3
0
/A
8
(/-/D
7
)
P3
1
/A
9
P3
2
/A
10
P3
3
/A
11
P3
4
/A
12
P3
5
/A
13
P3
6
/A
14
P3
7
/A
15
P4
0
/A
16
P4
1
/A
17
P4
2
/A
18
P4
3
/A
19
P7
4
/TA2
OUT
/W
P5
6
/ALE
P5
5
/HOLD
P5
4
/HLDA
P5
3
/BCLK
P5
2
/RD
Vcc2
Vss
P5
7
/RDY/CLK
OUT
P4
5
/CS1
P4
6
/CS2
P4
7
/CS3
AVcc
P6
3
/T /SDA
0X
D
0
P6
5
/CLK
1
P6
6
/RxD /SCL
11
P6
7
/T /SDA
1X
D
1
P6
1
/CLK
0
P6
2
/RxD /SCL
00
P10
0
/AN
0
P10
1
/AN
1
P10
2
/AN
2
P10
3
/AN
3
P9
3
/DA
0
/TB3
IN
P9
4
/DA
1
/TB4
IN
P9
6
/ANEX1/CTX
0
P9
1
/TB1
IN
/S
IN
3
P9
2
/TB2
IN
/S
OUT
3
P8
0
/TA4
OUT
/U
P6
0
/CTS
0
/RTS
0
P6
4
/CTS
1
/RTS
1
/CTS
0
/CLKS
1
P7
2
/CLK
2
/TA1
OUT
/V
P8
2
/INT
0
P7
(Note)
(Note)
1
/RxD
2
/SCL
2
/TA0
IN
/TB5
IN
P8
3
/INT
1
P8
5
/NMI
P9
Note: P71 and P91 are N channel open-drain output pins.
7
/AD
TRG
P4
4
/CS0
P5
0
/WRL/WR
P5
1
/WRH/BHE
P9
0
/TB0
IN
/CLK3
P7
0
/T
X
D
2
/SDA
2
/TA0
OUT
P8
4
/INT
2
P8
1
/TA4
IN
/U
P7
5
/TA2
IN
/W
P1
5
/D
13
/INT3
P1
6
/D
14
/INT4
P1
7
/D
15
/INT5
P10
7
/AN
7
/KI
3
P10
6
/AN
6
/KI
2
P10
5
/AN
5
/KI
1
P10
4
/AN
4/
KI
0
M16C/6N4 Group
P7
3
/CTS
2
/RTS
2
/TA1
IN
/V
P0
6
/AN
06
/D
6
P0
5
/AN
05
/D
5
P0
4
/AN
04
/D
4
P0
3
/AN
03
/D
3
P0
2
/AN
02
/D
2
P0
1
/AN
01
/D
1
P0
0
/AN
00
/D
0
P2
0
/AN
20
/A
0
/(D
0
/-)
P2
1
/AN
21
/A
1
/(D
1
/D
0
)
P2
2
/AN
22
/A
2
/(D
2
/D
1
)
P2
3
/AN
23
/A
3
/(D
3
/D
2
)
P2
4
/AN
24
/A
4
/(D
4
/D
3
)
P2
5
/AN
25
/A
5
/(D
5
/D
4
)
P2
6
/AN
26
/A
6
/(D
6
/D
5
)
P2
7
/AN
27
/A
7
/(D
7
/D
6
)
P9
5
/ANEX0/CRX
0
P7
7
/TA3
IN
/CRX
1
P7
6
/TA3
OUT
/CTX
1
Package: 100P6S-A
Rev.1.00 2003.05.30 page 6
M16C/6N4 Group Overview
Under development
This document is under development and its contents are subject to change.
Pin Description
Tables 1.1.3 and 1.1.4 list the pin descriptions.
Table 1.1.3 Pin Description (1)
XIN
XOUT
AVCC
AVSS
P00 to P07
A0/D0 to A7/D7
P30 to P37
Signal name
Power supply
input
Reset input
Clock input
Clock output
External data
bus width
select input
Reference
voltage input
I/O port P0
I/O port P3
Function
This pin switches between processor modes. Connect this pin to the VSS
pin when after a reset you want to start operation in single-chip mode
(memory expansion mode) or the VCC1 pin when starting operation in
microprocessor mode.
"L" on this input resets the microcomputer.
These pins are provided for the main clock generating circuit input/output.
Connect a ceramic resonator or crystal between the XIN and the XOUT
pins. To use an externally derived clock, input it to the XIN pin and leave
the XOUT pin open.
This pin selects the width of an external data bus. A 16-bit width is selected
when this input is "L"; an 8-bit width is selected when this input is "H".
This input must be fixed to either "H" or "L". Connect this pin to the VSS
pin when operating in single-chip mode.
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this pin
to VCC1.
This is an 8-bit CMOS I/O port. This port has an input/output select direction
register, allowing each pin in that port to be directed for input or output
individually.
If any port is set for input, selection can be made for it in a program whether
or not to have a pull-up resistor in 4-bit unit. This selection is unavailable
in memory expansion and microprocessor modes.
This port can function as input pins for the A-D converter when so selected
in a program.
This is an 8-bit I/O port equivalent to P0. P1
5
to P1
7
also function as INT
interrupt input pins as selected by a program.
If the external bus is set as a 16-bit width multiplexed bus, these pins input
and output data (D0 to D6) and output address (A1 to A7) separated in time
by multiplexing. They also output address (A0).
This is an 8-bit I/O port equivalent to P0.
If the external bus is set as a 16-bit width multiplexed bus, these pins input
and output data (D7) and output address (A8) separated in time by
multiplexing. They also output address (A9 to A15).
Pin name
CNVSS CNVSS Input
Input
Input
Output
BYTE Input
Input
VREF This pin is a reference voltage input for the A-D converter and D-A
converter.
Input/output
P10 to P17I/O port P1 Input/output
D8 to D15 When set as a separate bus, these pins input and output data (D
8 to D15).
Input/output
P20 to P27I/O port P2 Input/output
I/O type
This pin is a power supply input for the A-D converter. Connect this pin
to VSS.
Analog power
supply input
D0 to D7When set as a separate bus, these pins input and output data (D0 to D7).Input/output
A0 to A7These pins output 8 low-order address bits (A
0
to A
7
).Output
If the external bus is set as an 8-bit width multiplexed bus, these pins input
and output data (D0 to D7) and output 8 low-order address bits (A0 to A7)
separated in time by multiplexing.
Input/output
A0,
A1/D0 to A7/D6
Output
Input/output
Input/output
A8 to A15 These pins output 8 middle-order address bits (A
8
to A
15
).Output
A8/D7,
A9 to A15
Input/output
Output
P40 to P47I/O port P4 This is an 8-bit I/O port equivalent to P0.Input/output
Output
Output
A16 to A19,
CS0 to CS3
These pins output A16 to A19 and CS0 to CS3 signals. A16 to A19 are
4 high-order address bits. CS0 to CS3 are chip select signals used to
specify an access space.
RESET
This is an 8-bit I/O port equivalent to P0. This port can function as input
pins for the A-D converter when so selected in a program.
VCC1, VCC2
VSS
Apply 4.2 V to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin.
The VCC apply condition is that VCC2 = VCC1.
Rev.1.00 2003.05.30 page 7
M16C/6N4 Group Overview
Under development
This document is under development and its contents are subject to change.
Table 1.1.4 Pin Description (2)
Signal name FunctionPin name I/O type
I/O port P5 Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
I/O port P6
I/O port P7
I/O port P8
Input port P8
5
P5
0
to P5
7
P6
0
to P6
7
P7
0
to P7
7
P8
0
to P8
4
,
P8
6
,
P8
7
P8
5
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this
port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the
same frequency as X
CIN
as selected by program.
Output
Output
Output
Output
Output
Input
Output
Input
This is an 8-bit I/O port equivalent to P0. Pins in this port also function as
UART0 and UART1 I/O pins as selected by program.
Input/outputI/O port P9P9
0
to P9
7
This is an 8-bit I/O port equivalent to P0 (P9
1
is an N channel open-drain
output). Pins in this port also function as input/output pins for SI/O3, input
pins for times B0 to B4, output pins for D-A converter, and input pins for
A-D converter or input/output pins for CAN0, or input pins for A-D trigger
as selected by program.
Input/outputI/O port P10P10
0
to P10
7
This is an 8-bit I/O port equivalent to P0. Pins in this port also function as
input pins for A-D converter as selected by program.
Furthermore, P104 to P107 also function as input pins for the key input
interrupt function.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
Output WRL/WR, WRH/BHE, RD, BCLK, HLDA, and ALE signals.
WRL/WR and WRH/BHE are switchable in a program. Note that WRL and
WRH are always used as a pair, so as WR and BHE.
WRL, WRH, and RD selected
If the external data bus is a 16-bit width, data are written to even addresses
when the WRL signal is low, and written to odd addresses when the
WRH signal is low. Data are read out when the RD signal is low.
WR, BHE, and RD selected
Data are written when the WR signal is low, or read out when the RD
signal is low. Odd addresses are accessed when the BHE signal is low.
Use this mode when the external data bus is an 8-bit width.
The microcomputer goes to a hold state when input to the HOLD pin is
held low. While in the hold state, HLDA outputs a low level. ALE is used
to latch the address. While the input level of the RDY pin is low, the bus
of the microcomputer goes to a wait state.
P8
0
to P8
4
, P8
6
and P8
7
are I/O ports with the same functions as P0.
When so selected in a program, P8
0
, P8
1
, and P8
2
to P8
4
can function as
input/output pins for timer A4 or output pins for the three-phase motor
control timer and INT interrupt input pins, respectively.
P86 and P87, when so selected in a program, both can function as input/output
pins for the sub clock oscillator circuit.
In that case, connect a crystal resonator between P8
6
(X
COUT
pin) and
P8
7
(X
CIN
pin).
P8
5
is an input-only port shared with NMI. An NMI interrupt request is
generated when input on this pin changes state from high to low.
The NMI function cannot be disabled in a program.
A pull-up cannot be set for this pin.
This is an 8-bit I/O port equivalent to P0 (P7
1
is an N channel open-drain
output). This port can function as input/output pins for timers A0 to A3
when so selected in a program.
Furthermore, P7
0
to P7
3
, P7
1
, P7
2
to P7
5
and P7
6
, P7
7
can also function
as input/output pins for UART2, an input pin for timer B5, output pins for
the three-phase motor control timer, and input/output pin for the CAN1,
respectively.
Input
Rev.1.00 2003.05.30 page 8
M16C/6N4 Group Memory
Under development
This document is under development and its contents are subject to change.
Memory
Figure 1.2.1 shows a memory map of the M16C/6N4 group. The address space extends the 1 Mbyte from
address 0000016 to FFFFF16.
The internal ROM is allocated in a lower address direction beginning with address FFFFF16. For example,
a 128-Kbyte internal ROM is allocated to the addresses from E000016 to FFFFF16.
The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store the
start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,
a 5-Kbyte internal RAM is allocated to the addresses from 0040016 to 017FF16. In addition to storing data,
the internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot
be used by users.
The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used by
the JMPS or JSRS instruction. For details, refer to the “M16C/60 and M16C/20 Series Software Manual”.
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be
used by users.
Figure 1.2.1 Memory Map
00000
16
YYYYY
16
FFFFF
16
00400
16
27000
16
28000
16
08000
16
80000
16
XXXXX
16
External area
External area
Internal ROM
SFR
Internal RAM
Reserved area
FFE00
16
FFFDC
16
FFFFF
16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: In memory expansion mode, can not be used.
Note 3: Shown here is a memory map for the case where the PM13 bit in the PM1 register is "0".
However, this shows the case where the PM13 bit is "1" on the devices whose internal ROM is 192 Kbytes or more.
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Oscillation stop and re-oscillation
detection / watchdog timer
Reset
Special page
vector table
DBC
NMI
Address XXXXX
16
Size
Internal RAM
5 Kbytes
10 Kbytes
017FF
16
02BFF
16
Address YYYYY
16
Size
Internal ROM
128 Kbytes
256 Kbytes
E0000
16
C0000
16
Reserved area
(Note 1)
Reserved area
(Note 2)
Rev.1.00 2003.05.30 page 9
M16C/6N4 Group CPU
Under development
This document is under development and its contents are subject to change.
(1) Data Registers (R0, R1, R2, and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is the same as R2R0.
(2) Address Registers (A0 and A1)
The A0 register consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Figure 1.3.1 CPU Registers
Central Processing Unit (CPU)
Figure 1.3.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
SB
USP
ISP
b15 b0
Static base register
User stack pointer
Interrupt stack pointer
b19
INTBLINTBH
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b0
Interrupt table register
b19
PC
b0
Program counter
R0H (R0's high bits) R0L (R0's low bits)
R1H (R1's high bits) R1L (R1's low bits)
R2
R3
b31 b15 b8 b7 b0
R2
R3
A0
A1
FB
Data registers (Note)
Address registers (Note)
Frame base registers (Note)
Note: These registers comprise a register bank. There are two register banks.
b15 b0
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
b15 b0
FLG Flag register
IPL U I O B S Z D C
b7b8
Rev.1.00 2003.05.30 page 10
M16C/6N4 Group CPU
Under development
This document is under development and its contents are subject to change.
(3) Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
(4) Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
(5) Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
(6) User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
(7) Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
(8) Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
• Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Debug Flag (D Flag)
This flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
• Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
• Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
• Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
• Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is set to “0” when the interrupt request is accepted.
• Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0” ; USP is selected when the U flag is “1”.
The U flag is set to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
• Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt request is enabled.
• Reserved Area
When white to this bit, write “0”. When read, its content is indeterminate.
Rev.1.00 2003.05.30 page 11
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
Figure 1.4.1 Location of Peripheral Function Control Registers and Value at After Reset (1)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Processor mode register 0 (Note 1)
Processor mode register 1
System clock control register 0
System clock control register 1
Chip select control register
Address match interrupt enable register
Protect register
Oscillation stop detection register (Note 2)
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
Address match interrupt register 1
Chip select expansion control register
PLL control register 0
Processor mode register 2
DMA0 source pointer
DMA0 destination pointer
DMA0 transfer counter
DMA0 control register
DMA1 source pointer
DMA1 destination pointer
DMA1 transfer counter
DMA1 control register
PM0
PM1
CM0
CM1
CSR
AIER
PRCR
CM2
WDTS
WDC
RMAD0
RMAD1
CSE
PLC0
PM2
SAR0
DAR0
TCR0
DM0CON
SAR1
DAR1
TCR1
DM1CON
X: Undefined
Note 1: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 2: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
Note 3: The blank areas are reserved and cannot be accessed by users.
Address Register Symbol After reset
00000000
2
(CNV
SS
pin is "L")
00000011
2
(CNV
SS
pin is "H")
0XXX1000
2
01001000
2
00100000
2
00000001
2
XXXXXX00
2
XX000000
2
0X00X000
2
XX
16
00XXXXXX
2
00
16
00
16
X0
16
00
16
00
16
X0
16
00
16
0001X010
2
XXX00000
2
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
00000X00
2
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
00000X00
2
SFR
Figures 1.4.1 to 1.4.16 show the location of peripheral function control registers and the value after reset.
Rev.1.00 2003.05.30 page 12
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
Figure 1.4.2 Location of Peripheral Function Control Registers and Value at After Reset (2)
X: Undefined
Note: The blank area is reserved and cannot be accessed by users.
XXXXX0002
XXXXX0002
XXXXX0002
XX00X0002
XXXXX0002
XXXXX0002
XXXXX0002
XX00X0002
XX00X0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XX00X0002
XX00X0002
XX00X0002
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
CAN0/1 wake up interrupt control register
CAN0 successful reception interrupt control register
CAN0 successful transmission interrupt control register
INT3 interrupt control register
Timer B5 interrupt control register
Timer B4 interrupt control register
UART1 bus collision detection interrupt control register
Timer B3 interrupt control register
UART0 bus collision detection interrupt control register
CAN1 successful reception interrupt control register
INT5 interrupt control register
CAN1 successful transmission interrupt control register
SI/O3 interrupt control register
INT4 interrupt control register
UART2 bus collision detection interrupt control register
DMA0 interrupt control register
DMA1 interrupt control register
CAN0/1 error interrupt control register
A-D conversion interrupt control register
Key input interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
CAN0 message box 0: Identifier / DLC
CAN0 message box 0: Data field
CAN0 message box 0: Time stamp
CAN0 message box 1: Identifier / DLC
CAN0 message box 1: data Field
CAN0 message box 1: Time stamp
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
C01WKIC
C0RECIC
C0TRMIC
INT3IC
TB5IC
TB4IC
U1BCNIC
TB3IC
U0BCNIC
C1RECIC
INT5IC
C1TRMIC
S3IC
INT4IC
U2BCNIC
DM0IC
DM1IC
C01ERRIC
ADIC
KUPIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
Address Register Symbol After reset
Rev.1.00 2003.05.30 page 13
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
Figure 1.4.3 Location of Peripheral Function Control Registers and Value at After Reset (3)
X: Undefined
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
009E16
009F16
00A016
00A116
00A216
00A316
00A416
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
CAN0 message box 2: Identifier / DLC
CAN0 message box 2: Data field
CAN0 message box 2: Time stamp
CAN0 message box 3: Identifier / DLC
CAN0 message box 3: Data field
CAN0 message box 3: Time stamp
CAN0 message box 4: Identifier / DLC
CAN0 message box 4: Data field
CAN0 message box 4: Time stamp
CAN0 message box 5: Identifier / DLC
CAN0 message box 5: Data field
CAN0 message box 5: Time stamp
Address Register Symbol After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Rev.1.00 2003.05.30 page 14
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
Figure 1.4.4 Location of Peripheral Function Control Registers and Value at After Reset (4)
X: Undefined
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
CAN0 message box 6: Identifier / DLC
CAN0 message box 6: Data field
CAN0 message box 6: Time stamp
CAN0 message box 7: Identifier / DLC
CAN0 message box 7: Data field
CAN0 message box 7: Time stamp
CAN0 message box 8: Identifier / DLC
CAN0 message box 8: Data field
CAN0 message box 8: Time stamp
CAN0 message box 9: Identifier / DLC
CAN0 message box 9: Data field
CAN0 message box 9: Time stamp
Address Register Symbol After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Rev.1.00 2003.05.30 page 15
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
Figure 1.4.5 Location of Peripheral Function Control Registers and Value at After Reset (5)
X: Undefined
010016
010116
010216
010316
010416
010516
010616
010716
010816
010916
010A16
010B16
010C16
010D16
010E16
010F16
011016
011116
011216
011316
011416
011516
011616
011716
011816
011916
011A16
011B16
011C16
011D16
011E16
011F16
012016
012116
012216
012316
012416
012516
012616
012716
012816
012916
012A16
012B16
012C16
012D16
012E16
012F16
013016
013116
013216
013316
013416
013516
013616
013716
013816
013916
013A16
013B16
013C16
013D16
013E16
013F16
CAN0 message box 10: Identifier / DLC
CAN0 message box 10: Data field
CAN0 message box 10: Time stamp
CAN0 message box 11: Identifier / DLC
CAN0 message box 11: Data field
CAN0 message box 11: Time stamp
CAN0 message box 12: Identifier / DLC
CAN0 message box 12: Data field
CAN0 message box 12: Time stamp
CAN0 message box 13: Identifier / DLC
CAN0 message box 13: Data field
CAN0 message box 13: Time stamp
Address Register Symbol After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Rev.1.00 2003.05.30 page 16
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
Figure 1.4.6 Location of Peripheral Function Control Registers and Value at After Reset (6)
X: Undefined
Note: The blank areas are reserved and cannot be accessed by users.
0140
16
0141
16
0142
16
0143
16
0144
16
0145
16
0146
16
0147
16
0148
16
0149
16
014A
16
014B
16
014C
16
014D
16
014E
16
014F
16
0150
16
0151
16
0152
16
0153
16
0154
16
0155
16
0156
16
0157
16
0158
16
0159
16
015A
16
015B
16
015C
16
015D
16
015E
16
015F
16
0160
16
0161
16
0162
16
0163
16
0164
16
0165
16
0166
16
0167
16
0168
16
0169
16
016A
16
016B
16
016C
16
016D
16
016E
16
016F
16
0170
16
0171
16
0172
16
0173
16
0174
16
0175
16
0176
16
0177
16
0178
16
0179
16
017A
16
017B
16
017C
16
017D
16
017E
16
017F
16
CAN0 message box 14: Identifier /DLC
CAN0 message box 14: Data field
CAN0 message box 14: Time stamp
CAN0 message box 15: Identifier /DLC
CAN0 message box 15: Data field
CAN0 message box 15: Time stamp
CAN0 global mask register
CAN0 local mask A register
CAN0 local mask B register
Address Register Symbol After reset
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
C0GMR
C0LMAR
C0LMBR
Rev.1.00 2003.05.30 page 17
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
Figure 1.4.7 Location of Peripheral Function Control Registers and Value at After Reset (7)
X: Undefined
Note 1: This register is included in flash memory version.
Note 2: The blank areas are reserved and cannot be accessed by users.
0180
16
0181
16
0182
16
0183
16
0184
16
0185
16
0186
16
0187
16
0188
16
0189
16
018A
16
018B
16
018C
16
018D
16
018E
16
018F
16
0190
16
0191
16
0192
16
0193
16
0194
16
0195
16
0196
16
0197
16
0198
16
0199
16
019A
16
019B
16
019C
16
019D
16
019E
16
019F
16
01A0
16
01A1
16
01A2
16
01A3
16
01A4
16
01A5
16
01A6
16
01A7
16
01A8
16
01A9
16
01AA
16
01AB
16
01AC
16
01AD
16
01AE
16
01AF
16
01B0
16
01B1
16
01B2
16
01B3
16
01B4
16
01B5
16
01B6
16
01B7
16
01B8
16
01B9
16
01BA
16
01BB
16
01BC
16
01BD
16
01BE
16
01BF
16
Flash memory control register 1 (Note 1)
Flash memory control register 0 (Note 1)
Address match interrupt register 2
Address match interrupt enable register 2
Address match interrupt register 3
FMR1
FMR0
RAMD2
AIER2
RAMD3
Address Register Symbol After reset
0X00XX0X
2
XX000001
2
00
16
00
16
X0
16
XXXXXX00
2
00
16
00
16
X0
16
Rev.1.00 2003.05.30 page 18
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
Figure 1.4.8 Location of Peripheral Function Control Registers and Value at After Reset (8)
X: Undefined
Note: The blank areas are reserved and cannot be accessed by users.
01C0
16
01C1
16
01C2
16
01C3
16
01C4
16
01C5
16
01C6
16
01C7
16
01C8
16
01C9
16
01CA
16
01CB
16
01CC
16
01CD
16
01CE
16
01CF
16
01D0
16
01D1
16
01D2
16
01D3
16
01D4
16
01D5
16
01D6
16
01D7
16
01D8
16
01D9
16
01DA
16
01DB
16
01DC
16
01DD
16
01DE
16
01DF
16
01E0
16
01E1
16
01E2
16
01E3
16
01E4
16
01E5
16
01E6
16
01E7
16
01E8
16
01E9
16
01EA
16
01EB
16
01EC
16
01ED
16
01EE
16
01EF
16
01F0
16
01F1
16
01F2
16
01F3
16
01F4
16
01F5
16
01F6
16
01F7
16
01F8
16
01F9
16
01FA
16
01FB
16
01FC
16
01FD
16
01FE
16
01FF
16
Timer B3,4,5 count start flag
Timer A1-1 register
Timer A2-1 register
Timer A4-1 register
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Dead time timer
Timer B2 interrupt occurrence frequency set counter
Timer B3 register
Timer B4 register
Timer B5 register
Timer B3 mode register
Timer B4 mode register
Timer B5 mode register
Interrupt cause select register 0
Interrupt cause select register 1
SI/O3 transmit/receive register
SI/O3 control register
SI/O3 bit rate generator
UART0 special mode register 4
UART0 special mode register 3
UART0 special mode register 2
UART0 special mode register
UART1 special mode register 4
UART1 special mode register 3
UART1 special mode register 2
UART1 special mode register
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate generator
UART2 transmit buffer register
UART2 transmit/receive mode register 0
UART2 transmit/receive mode register 1
UART2 receive buffer register
TBSR
TA11
TA21
TA41
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
TB3
TB4
TB5
TB3MR
TB4MR
TB5MR
IFSR0
IFSR1
S3TRR
S3C
S3BRG
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
U2C0
U2C1
U2RB
Address Register Symbol After reset
000XXXXX
2
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
00
16
00
16
00
16
00
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
00XX0000
2
00XX0000
2
00XX0000
2
00XXX000
2
00
16
XX
16
01000000
2
XX
16
00
16
000X0X0X
2
X0000000
2
X0000000
2
00
16
000X0X0X
2
X0000000
2
X0000000
2
00
16
000X0X0X
2
X0000000
2
X0000000
2
00
16
XX
16
XX
16
XX
16
00001000
2
00000010
2
XX
16
XX
16
Rev.1.00 2003.05.30 page 19
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
X: Undefined
020016
020116
020216
020316
020416
020516
020616
020716
020816
020916
020A16
020B16
020C16
020D16
020E16
020F16
021016
021116
021216
021316
021416
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
022016
022116
022216
022316
022416
022516
022616
022716
022816
022916
022A16
022B16
022C16
022D16
022E16
022F16
023016
023116
023216
023316
023416
023516
023616
023716
023816
023916
023A16
023B16
023C16
023D16
023E16
023F16
CAN0 message control register 0
CAN0 message control register 1
CAN0 message control register 2
CAN0 message control register 3
CAN0 message control register 4
CAN0 message control register 5
CAN0 message control register 6
CAN0 message control register 7
CAN0 message control register 8
CAN0 message control register 9
CAN0 message control register 10
CAN0 message control register 11
CAN0 message control register 12
CAN0 message control register 13
CAN0 message control register 14
CAN0 message control register 15
CAN0 control register
CAN0 status register
CAN0 slot status register
CAN0 interrupt control register
CAN0 extended register
CAN0 configuration register
CAN0 receive error count register
CAN0 transmit error count register
CAN0 time stamp register
CAN1 message control register 0
CAN1 message control register 1
CAN1 message control register 2
CAN1 message control register 3
CAN1 message control register 4
CAN1 message control register 5
CAN1 message control register 6
CAN1 message control register 7
CAN1 message control register 8
CAN1 message control register 9
CAN1 message control register 10
CAN1 message control register 11
CAN1 message control register 12
CAN1 message control register 13
CAN1 message control register 14
CAN1 message control register 15
CAN1 control register
CAN1 status register
CAN1 slot status register
CAN1 interrupt control register
CAN1 extended register
CAN1 configuration register
CAN1 receive error count register
CAN1 transmit error count register
CAN1 time stamp register
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
C0CTLR
C0STR
C0SSTR
C0ICR
C0IDR
C0CONR
C0RECR
C0TECR
C0TSR
C1MCTL0
C1MCTL1
C1MCTL2
C1MCTL3
C1MCTL4
C1MCTL5
C1MCTL6
C1MCTL7
C1MCTL8
C1MCTL9
C1MCTL10
C1MCTL11
C1MCTL12
C1MCTL13
C1MCTL14
C1MCTL15
C1CTLR
C1STR
C1SSTR
C1ICR
C1IDR
C1CONR
C1RECR
C1TECR
C1TSR
Address Register Symbol After reset
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
X00000012
XX0X00002
0016
X00000012
0016
0016
0016
0016
0016
0016
XX16
XX16
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
X00000012
XX0X00002
0016
X00000012
0016
0016
0016
0016
0016
0016
XX16
XX16
0016
0016
0016
0016
Figure 1.4.9 Location of Peripheral Function Control Registers and Value at After Reset (9)
Rev.1.00 2003.05.30 page 20
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
X: Undefined
Note: The blank areas are reserved and cannot be accessed by users.
XX
16
XX
16
XX
16
XX
16
00
16
00
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
CAN0 acceptance filter support register
CAN1 acceptance filter support register
Peripheral function clock select register
CAN0/1 clock select register
CAN1 message box 0: Identifier / DLC
CAN1 message box 0: Data field
CAN1 message box 0:Time stamp
CAN1 message box 1: Identifier / DLC
CAN1 message box 1: Data field
CAN1 message box 1:Time stamp
0240
16
0241
16
0242
16
0243
16
0244
16
0245
16
0246
16
0247
16
0248
16
0249
16
024A
16
024B
16
024C
16
024D
16
024E
16
024F
16
0250
16
0251
16
0252
16
0253
16
0254
16
0255
16
0256
16
0257
16
0258
16
0259
16
025A
16
025B
16
025C
16
025D
16
025E
16
025F
16
0260
16
0261
16
0262
16
0263
16
0264
16
0265
16
0266
16
0267
16
0268
16
0269
16
026A
16
026B
16
026C
16
026D
16
026E
16
026F
16
0270
16
0271
16
0272
16
0273
16
0274
16
0275
16
0276
16
0277
16
0278
16
0279
16
027A
16
027B
16
027C
16
027D
16
027E
16
027F
16
C0AFS
C1AFS
PCLKR
CCLKR
Address Register Symbol After reset
Figure 1.4.10 Location of Peripheral Function Control Registers and Value at After Reset (10)
Rev.1.00 2003.05.30 page 21
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
X: Undefined
028016
028116
028216
028316
028416
028516
028616
028716
028816
028916
028A16
028B16
028C16
028D16
028E16
028F16
029016
029116
029216
029316
029416
029516
029616
029716
029816
029916
029A16
029B16
029C16
029D16
029E16
029F16
02A016
02A116
02A216
02A316
02A416
02A516
02A616
02A716
02A816
02A916
02AA16
02AB16
02AC16
02AD16
02AE16
02AF16
02B016
02B116
02B216
02B316
02B416
02B516
02B616
02B716
02B816
02B916
02BA16
02BB16
02BC16
02BD16
02BE16
02BF16
CAN1 message box 2: Identifier / DLC
CAN1 message box 2: Data field
CAN1 message box 2: Time stamp
CAN1 message box 3: Identifier / DLC
CAN1 message box 3: Data field
CAN1 message box 3: Time stamp
CAN1 message box 4: Identifier / DLC
CAN1 message box 4: Data field
CAN1 message box 4: Time stamp
CAN1 message box 5: Identifier / DLC
CAN1 message box 5: Data field
CAN1 message box 5: Time stamp
Address Register Symbol After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Figure 1.4.11 Location of Peripheral Function Control Registers and Value at After Reset (11)
Rev.1.00 2003.05.30 page 22
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
X: Undefined
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
02EB16
02EC16
02ED16
02EE16
02EF16
02F016
02F116
02F216
02F316
02F416
02F516
02F616
02F716
02F816
02F916
02FA16
02FB16
02FC16
02FD16
02FE16
02FF16
CAN1 message box 6: Identifier / DLC
CAN1 message box 6: Data field
CAN1 message box 6: Time stamp
CAN1 message box 7: Identifier / DLC
CAN1 message box 7: Data field
CAN1 message box 7: Time stamp
CAN1 message box 8: Identifier / DLC
CAN1 message box 8: Data field
CAN1 message box 8: Time stamp
CAN1 message box 9: Identifier / DLC
CAN1 message box 9: Data field
CAN1 message box 9: Time stamp
Address Register Symbol After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Figure 1.4.12 Location of Peripheral Function Control Registers and Value at After Reset (12)
Rev.1.00 2003.05.30 page 23
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
X: Undefined
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
CAN1 message box 10: Identifier / DLC
CAN1 message box 10: Data field
CAN1 message box 10: Time stamp
CAN1 message box 11: Identifier / DLC
CAN1 message box 11: Data field
CAN1 message box 11: Time stamp
CAN1 message box 12: Identifier / DLC
CAN1 message box 12: Data field
CAN1 message box 12: Time stamp
CAN1 message box 13: Identifier / DLC
CAN1 message box 13: Data field
CAN1 message box 13: Time stamp
Address Register Symbol After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Figure 1.4.13 Location of Peripheral Function Control Registers and Value at After Reset (13)
Rev.1.00 2003.05.30 page 24
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
X: Undefined
Note: The blank areas are reserved and cannot be accessed by users.
0340
16
0341
16
0342
16
0343
16
0344
16
0345
16
0346
16
0347
16
0348
16
0349
16
034A
16
034B
16
034C
16
034D
16
034E
16
034F
16
0350
16
0351
16
0352
16
0353
16
0354
16
0355
16
0356
16
0357
16
0358
16
0359
16
035A
16
035B
16
035C
16
035D
16
035E
16
035F
16
0360
16
0361
16
0362
16
0363
16
0364
16
0365
16
0366
16
0367
16
0368
16
0369
16
036A
16
036B
16
036C
16
036D
16
036E
16
036F
16
0370
16
0371
16
0372
16
0373
16
0374
16
0375
16
0376
16
0377
16
0378
16
0379
16
037A
16
037B
16
037C
16
037D
16
037E
16
037F
16
CAN1 message box 14: Identifier / DLC
CAN1 message box 14: Data field
CAN1 message box 14: Time stamp
CAN1 message box 15: Identifier / DLC
CAN1 message box 15: Data field
CAN1 message box 15: Time stamp
CAN1 global mask register
CAN1 local mask A register
CAN1 local mask B register
Address Register Symbol After reset
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
C1GMR
C1LMAR
C1LMBR
Figure 1.4.14 Location of Peripheral Function Control Registers and Value at After Reset (14)
Rev.1.00 2003.05.30 page 25
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
X: Undefined
Note: The blank areas are reserved and cannot be accessed by users.
0380
16
0381
16
0382
16
0383
16
0384
16
0385
16
0386
16
0387
16
0388
16
0389
16
038A
16
038B
16
038C
16
038D
16
038E
16
038F
16
0390
16
0391
16
0392
16
0393
16
0394
16
0395
16
0396
16
0397
16
0398
16
0399
16
039A
16
039B
16
039C
16
039D
16
039E
16
039F
16
03A0
16
03A1
16
03A2
16
03A3
16
03A4
16
03A5
16
03A6
16
03A7
16
03A8
16
03A9
16
03AA
16
03AB
16
03AC
16
03AD
16
03AE
16
03AF
16
03B0
16
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
03B6
16
03B7
16
03B8
16
03B9
16
03BA
16
03BB
16
03BC
16
03BD
16
03BE
16
03BF
16
Count start flag
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-down flag
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Timer B2 special mode register
UART0 transmit/receive mode register
UART0 bit rate generator
UART0 transmit buffer register
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 bit rate generator
UART1 transmit buffer register
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 receive buffer register
UART transmit/receive control register 2
DMA0 request cause select register
DMA1 request cause select register
CRC data register
CRC input register
TABSR
CPSRF
ONSF
TRGSR
UDF
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
U0MR
U0BRG
U0TB
U0C0
U0C1
U0RB
U1MR
U1BRG
U1TB
U1C0
U1C1
U1RB
UCON
DM0SL
DM1SL
CRCD
CRCIN
Address Register Symbol After reset
00
16
0XXXXXXX
2
00
16
00
16
00
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
00
16
00
16
00
16
00
16
00
16
00XX0000
2
00XX0000
2
00XX0000
2
XXXXXX00
2
00
16
XX
16
XX
16
XX
16
00001000
2
00000010
2
XX
16
XX
16
00
16
XX
16
XX
16
XX
16
00001000
2
00000010
2
XX
16
XX
16
X0000000
2
00
16
00
16
XX
16
XX
16
XX
16
Figure 1.4.15 Location of Peripheral Function Control Registers and Value at After Reset (15)
Rev.1.00 2003.05.30 page 26
M16C/6N4 Group SFR
Under development
This document is under development and its contents are subject to change.
X: Undefined
Note 1: At hardware reset, the register is as follows:
"00000000
2
" where "L" is input to the CNV
SS
pin
"00000010
2
" where "H" is input to the CNV
SS
pin
At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:
"00000000
2
" where the PM01 to PM00 bits in the PM0 register are "00
2
" (single-chip mode)
"00000010
2
" where the PM01 to PM00 bits in the PM0 register are "01
2
" (memory expansion mode) or "11
2
"
(microprocessor mode)
Note 2: The blank areas are reserved and cannot be accessed by users.
03C0
16
03C1
16
03C2
16
03C3
16
03C4
16
03C5
16
03C6
16
03C7
16
03C8
16
03C9
16
03CA
16
03CB
16
03CC
16
03CD
16
03CE
16
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
03D5
16
03D6
16
03D7
16
03D8
16
03D9
16
03DA
16
03DB
16
03DC
16
03DD
16
03DE
16
03DF
16
03E0
16
03E1
16
03E2
16
03E3
16
03E4
16
03E5
16
03E6
16
03E7
16
03E8
16
03E9
16
03EA
16
03EB
16
03EC
16
03ED
16
03EE
16
03EF
16
03F0
16
03F1
16
03F2
16
03F3
16
03F4
16
03F5
16
03F6
16
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
03FD
16
03FE
16
03FF
16
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
A-D control register 2
A-D control register 0
A-D control register 1
D-A register 0
D-A register 1
D-A control register
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P9 register
Port P8 direction register
Port P9 direction register
Port P10 register
Port P10 direction register
Pull-up control register 0
Pull-up control register 1
Pull-up control register 2
Port control register
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ADCON2
ADCON0
ADCON1
DA0
DA1
DACON
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
PD10
PUR0
PUR1
PUR2
PCR
Address Register Symbol After reset
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
XX
16
00
16
00000XXX
2
00
16
XX
16
XX
16
00
16
XX
16
XX
16
00
16
00
16
XX
16
XX
16
00
16
00
16
XX
16
XX
16
00
16
00
16
XX
16
XX
16
00
16
00
16
XX
16
XX
16
00X00000
2
00
16
XX
16
00
16
00
16
00000000
2
00000010
2
00
16
00
16
(Note 1)
Figure 1.4.16 Location of Peripheral Function Control Registers and Value at After Reset (16)
Rev.1.00 2003.05.30 page 27
M16C/6N4 Group Reset
Under development
This document is under development and its contents are subject to change.
Reset
There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscillation
stop detection reset.
Hardware Reset
____________ ____________
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power
supply voltage is within the recommended operating condition, the pins are initialized (refer to “Table
____________
1.5.1 Pin Status When RESET Pin Level is “L” ”). The oscillation circuit is initialized and the main clock
____________
starts oscillating. When the input level at the RESET pin is released from “L” to “H”, the CPU and SFR are
initialized, and the program is executed starting from the address indicated by the reset vector. The
____________
internal RAM is not initialized. If the RESET pin is pulled “L” while writing to the internal RAM, the internal
RAM becomes indeterminate.
Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence. Table 1.5.1 shows
____________
the statuses of the other pins while the RESET pin is “L”. Figure 1.5.3 shows the CPU register status after
reset. Refer to “SFR” for SFR status after reset.
1. When the power supply is stable
____________
(1) Apply an “L” signal to the RESET pin.
(2) Supply a clock for 20 cycles or more to the XIN pin.
____________
(3) Apply an “H” signal to the RESET pin.
2. Power on ____________
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condition.
(3) Wait for td(P-R) or more until the internal power supply stabilizes.
(4) Supply a clock for 20 cycles or more to the XIN pin.
____________
(5) Apply an “H” signal to the RESET pin.
Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins,
CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset
vector.
Select the main clock for the CPU clock source, and set the PM03 bit to “1” with main clock oscillation
satisfactorily stable.
At software reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00 bits in the
PM0 register are not initialized, the processor mode remains unchanged.
Watchdog Timer Reset
Where the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcom-
puter initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed
starting from the address indicated by the reset vector.
At watchdog timer reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00
bits in the PM0 register are not initialized, the processor mode remains unchanged.
Oscillation Stop Detection Reset
Where the CM27 bit in the CM2 register is “0” (reset at oscillation stop, re-oscillation detection), the
microcomputer initializes its pins, CPU and SFR, coming to a halt if it detects main clock oscillation circuit
stop. Refer to “Oscillation Stop and Re-oscillation Detection Function”.
At oscillation stop detection reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to
PM00 bits in the PM0 register are not initialized, the processor mode remains unchanged.
Rev.1.00 2003.05.30 page 28
M16C/6N4 Group Reset
Under development
This document is under development and its contents are subject to change.
Figure 1.5.2 Reset Sequence
Figure 1.5.1 Example Reset Circuit
R
E
S
E
TVCC1
R
E
S
E
T
VC
C
1
0
V
0
V
More than 20 cycles of XIN + td(P-R)
are needed.
E
q
u
a
l
t
o
o
r
l
e
s
s
t
h
a
n
0
.
2
VC
C
1
E
q
u
a
l
t
o
o
r
l
e
s
s
t
h
a
n
0
.
2
VC
C
1
Re
c
o
m
m
e
n
d
e
d
o
p
e
r
a
t
i
n
g
v
o
l
t
a
g
e
t
d(P-R)
More than
20 cycles
are needed
BCLK
Address
Address
Address
Microprocessor
mode BYTE = H
Microprocessor
mode BYTE = L
X
IN
RESET
RD
WR
CS
0
RD
WR
CS
0
Content of reset vector
BCLK 28cycles
FFFFC
16
FFFFD
16
FFFFE
16
Content of reset vector
FFFFC
16
FFFFE
16
Content of reset vector
FFFFE
16
FFFFC
16
V
CC1
Single-chip
mode
Rev.1.00 2003.05.30 page 29
M16C/6N4 Group Reset
Under development
This document is under development and its contents are subject to change.
____________
Table 1.5.1 Pin Status When RESET Pin Level is “L”
Figure 1.5.3 CPU Register Status After Reset
000016
000016
000016
b15 b0
Static base register (SB)
User stack pointer (USP)
Interrupt stack pointer (ISP)
b19
0000016
b0
Interrupt table register (INTB)
Content of addresses FFFFE16 to FFFFC16 Program counter (PC)
b15 b0
000016
000016
000016
000016
000016
000016
000016
Data register (R0)
Data register (R1)
Data register (R2)
Data register (R3)
Address register (A0)
Address register (A1)
Frame base register (FB)
b15 b0
b15 b0
000016 Flag register (FLG)
IPL U I O B S Z D C
b7b8
P0 Input port Data input Data input
P1 Input port Data input Input port
P2, P3, P40 to P43Input port Address output (undefined) Address output (undefined)
P44Input port
______
CS0 output (“H” is output)
______
CS0 output (“H” is output)
P45 to P47Input port Input port (Pulled high) Input port (Pulled high)
P50Input port
______
WR output (“H” is output)
______
WR output (“H” is output)
P51Input port
________
BHE output (undefined)
________
BHE output (undefined)
P52Input port
______
RD output (“H” is output)
______
RD output (“H” is output)
P53Input port BCLK output BCLK output
P54Input port
___________
HLDA output
___________
HLDA output
(The output value depends on (The output value depends on
__________
the input to the HOLD pin)
__________
the input to the HOLD pin)
P55Input port
__________
HOLD input
__________
HOLD input
P56Input port ALE output (“L” is output) ALE output (“L” is output)
P57Input port
________
RDY input
________
RDY input
P6, P7, P80 to P84, Input port Input port Input port
P86, P87, P9, P10
Pin name
Status
CNVSS = VCC1 (Note)
BYTE = VSS BYTE = VCC1
CNVSS = VSS
Note: Shown here is the valid pin state when the internal power supply voltage has stabilized after power-on.
When CNVSS = VCC1, the pin state is indeterminate until the internal power supply voltage stabilizes.
Rev.1.00 2003.05.30 page 30
M16C/6N4 Group Processor Mode
Under development
This document is under development and its contents are subject to change.
Processor Mode
(1) Types of Processor Mode
Three processor modes are available to choose from: single-chip mode, memory expansion mode, and
microprocessor mode. Table 1.6.1 shows the features of these processor modes.
Table 1.6.1 Features of Processor Modes
Note: Refer to “Bus”.
(2) Setting Processor Modes
Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register.
Table 1.6.2 shows the processor mode after hardware reset. Table 1.6.3 shows the PM01 to PM00 bits
set values and processor modes.
Processor mode Access space Pins which are assigned I/O ports
Single-chip mode SFR, internal RAM, internal ROM All pins are I/O ports or
peripheral function I/O pins
Memory expansion mode SFR, internal RAM, internal ROM, Some pins serve as bus control pins (Note)
external area (Note)
Microprocessor mode SFR, internal RAM, external area (Note) Some pins serve as bus control pins (Note)
CNVSS pin input level Processor mode
VSS Single-chip mode
VCC1 (Notes 1, 2) Microprocessor mode
PM01 to PM 00 bits Processor mode
002Single-chip mode
012Memory expansion mode
102Must not be set
112Microprocessor mode
Note 1: If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin, the internal ROM cannot
be accessed regardless of PM01 to PM00 bits.
_____
Note 2: The multiplexed bus cannot be assigned to the entire CS space.
Table 1.6.3 PM01 to PM00 Bits Set Values and Processor Modes
Rewriting the PM01 to PM00 bits places the microcomputer in the corresponding processor mode regardless
of whether the input level on the CNVSS pin is “H” or “L”. Note, however, that the PM01 to PM00 bits
cannot be rewritten to “012” (memory expansion mode) or “112” (microprocessor mode) at the same time
the PM07 to PM02 bits are rewritten. Note also that these bits cannot be rewritten to enter microprocessor
mode in the internal ROM, nor can they be rewritten to exit microprocessor mode in areas overlapping the
internal ROM.
If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset), the internal
ROM cannot be accessed regardless of PM01 to PM00 bits.
Figures 1.6.1 and 1.6.2 show the processor mode related registers. Figure 1.6.3 shows the memory map
_____
in single-chip mode. Figures 1.6.4 to 1.6.7 show the memory map and CS area in memory expansion
mode and microprocessor mode.
Table 1.6.2 Processor Mode After Hardware Reset
Rev.1.00 2003.05.30 page 31
M16C/6N4 Group Processor Mode
Under development
This document is under development and its contents are subject to change.
Figure 1.6.1 PM0 Register
Processor mode register 0 (Note 1)
Symbol Address After reset (Note 2)
000000002 (CNVSS pin = L)
000000112 (CNVSS pin = H)
Bit name Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
PM0 0004
16
Processor mode bit
(Note 2)
R/W mode select bit
(Note 3)
Software reset bit
Multiplexed bus space
select bit (Note 3)
BCLK output disable bit
(Note 3)
PM03
PM01
PM00
PM02
PM04
PM05
PM06
PM07
RW
RW
RW
RW
RW
RW
RW
RW
RW
Port P40 to P43 function
select bit (Note 3)
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Must not be set
1 1 : Microprocessor mode
b1 b0
0 : RD, BHE, WR
1 : RD, WRH, WRL
Setting this bit to "1" resets the
microcomputer. When read, its
content is "0"
.
0 0 : Multiplexed bus is unused
(Separate bus in the entire CS space)
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 :
Allocated to the entire CS space (Note 4)
b5 b4
0 : Address output
1 : Port function
(Address is not output)
0 : BCLK is output
1 : BCLK is not output
(Pin is left high-impedance)
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Note 2: The PM01 to PM00 bits do not change at software reset, watchdog timer reset and oscillation stop detection
reset.
Note 3: Effective when the PM01 to PM00 bits are set to "01
2
" (memory expansion mode) or "11
2
" (microprocessor
mode).
Note 4: To set the PM01 to PM00 bits are "01
2
" and the PM05 to PM04 bits are "11
2
" (multiplexed bus assigned to
the entire CS space), apply an "H" signal to the BYTE pin (external data bus is 8-bit width).
While the CNV
SS
pin is held "H" (V
CC1
), do not rewrite the PM05 to PM04 bits to "11
2
" after reset.
If the PM05 to PM04 bits are set to "11
2
" during memory expansion mode, P3
1
to P3
7
and P4
0
to P4
3
become I/O ports, in which case the accessible area for each CS is 256 bytes.
Rev.1.00 2003.05.30 page 32
M16C/6N4 Group Processor Mode
Under development
This document is under development and its contents are subject to change.
Figure 1.6.2 PM1 Register
Symbol Address After reset
PM1 000516 0XXX10002
PM17
PM13
PM12
PM10
PM11
(b6-b4)
-
CS2 area switch bit
(data block enable bit)
(Note 2)
Port P37 to P34 function
select bit (Note 3)
Watchdog timer function
select bit
RW
RW
RW
RW
RW
RW
RW
0 : No wait state
1 : With wait state (1 wait)
Set to "0".
Internal ROM area is:
0 : 192 Kbytes or smaller
1 : Expanded over 192 Kbytes
0 : Watchdog timer interrupt
1 : Watchdog timer reset (Note 4)
0 : 0800016 to 26FFF16
(block A disable)
1 : 1000016 to 26FFF16
(block A enable)
0 : Address output
1 : Port function
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Note 2: For the mask ROM version, this bit must be set to "0".
For the flash memory version, the PM10 bit also controls block A by enabling or disabling it.
However, the PM10 bit is automatically set to "1" when the FMR01 bit in the FMR0 register is "1" (CPU
rewrite mode).
Note 3: Effective when the PM01 to PM00 bits are set to "012" (memory expansion mode) or "112" (microprocessor
mode).
Note 4: The PM12 bit is set to "1" by writing a "1" in a program. (Writing a "0" has no effect.)
Note 5: Be sure to set this bit to "0" except for products with internal ROM area over 192 Kbytes.
The PM13 bit is automatically set to "1" when the FMR01 bit in the FMR0 register is "1" (CPU rewrite mode).
Note 6: When the PM17 bit is set to "1" (with wait state), one wait state is inserted when accessing the internal RAM,
internal ROM, or an external area.
If the CSiW bit (i = 0 to 3) in the CSR register is "0" (with wait state), the CSi area is always accessed with
one or more wait states regardless of whether the PM17 bit is set or not.
Where the RDY signal is used or multiplexed bus is used, set the CSiW bit to "0" (with wait state).
Bit name Function
Internal reserved area
expansion bit (Note 5)
Reserved bit
Wait bit (Note 6)
Processor mode register 1 (Note 1)
000
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Rev.1.00 2003.05.30 page 33
M16C/6N4 Group Processor Mode
Under development
This document is under development and its contents are subject to change.
Figure 1.6.3 Memory Map in Single-chip Mode
Single-chip mode
SFR
Internal RAM
Can not use
Internal ROM
Capacity
5 Kbytes
10 Kbytes
Address XXXXX
16
017FF
16
02BFF
16
Capacity
128 K
bytes
256 K
bytes
Address YYYYY
16
E0000
16
D0000
16
Internal RAM
PM13 = 0
PM13 = 1
Internal ROM
Capacity
5 Kbytes
10 Kbytes
Address XXXXX
16
017FF
16
02BFF
16
Capacity
128 K
bytes
256 K
bytes
Address YYYYY
16
E0000
16
C0000
16
Internal RAM Internal ROM
00000
16
00400
16
XXXXX
16
YYYYY
16
FFFFF
16
(Note 1)
Note 1: When the PM13 bit in the PM1 register = 0, 192 Kbytes or smaller of the internal ROM
can be used.
Note 2: For the mask ROM version, set the PM10 bit in the PM1 register to "0" (08000
16
to 26FFF
16
for CS
2
area).
Rev.1.00 2003.05.30 page 34
M16C/6N4 Group Processor Mode
Under development
This document is under development and its contents are subject to change.
_____
Figure 1.6.4 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (1)
XXXXX16
0000016
YYYYY16
FFFFF16
0040016
0800016
2700016
2800016
3000016
8000016
SFR
Reserved area
Internal ROM
Reserved area
External area
SFR
Internal RAM
Reserved area
Reserved area
External area
Memory expansion mode Microprocessor mode
CS2 (124 Kbytes)
CS1 (32 Kbytes)
CS0
Memory expansion mode: 320 Kbytes
Microprocessor mode: 832 Kbytes
Address XXXXX16
Capacity
Internal RAM
5 Kbytes
10 Kbytes
017FF16
02BFF16
Address YYYYY16
Capacity
Internal ROM
128 Kbytes
256 Kbytes
E000016
C000016
Internal RAM
Reserved area
When PM13 = 1 and PM10 = 0 (A memory space of 1MB)
_____
Figure 1.6.5 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (2)
XXXXX
16
04000
16
SFR
Internal RAM
Reserved area
Reserved area
Internal ROM
Reserved area
External area
SFR
Internal RAM
Reserved area
CS
3
(16 Kbytes)
Reserved area
External area
00000
16
YYYYY
16
FFFFF
16
Memory expansion mode Microprocessor mode
00400
16
08000
16
27000
16
28000
16
30000
16
80000
16
CS
2
(124 Kbytes)
CS
1
(32 Kbytes)
CS
0
Memory expansion mode: 640 Kbytes
Microprocessor mode: 832 Kbytes
Address XXXXX
16
Capacity
Internal RAM
5 Kbytes
10 Kbytes
017FF
16
02BFF
16
Address YYYYY
16
Capacity
Internal ROM
128 Kbytes
256 Kbytes
When PM13 = 0 and PM10 = 0 (A memory space of 1MB)
Note: When the PM13 bit in the PM1 register = 0, 192 Kbytes or smaller of the internal ROM can
be used.
E0000
16
D0000
16
(Note)
Rev.1.00 2003.05.30 page 35
M16C/6N4 Group Processor Mode
Under development
This document is under development and its contents are subject to change.
XXXXX
16
04000
16
00000
16
YYYYY
16
FFFFF
16
00400
16
08000
16
10000
16
27000
16
28000
16
30000
16
80000
16
SFR
Internal RAM
Reserved area
Reserved area
Internal ROM
Reserved area
External area
SFR
Internal RAM
Reserved area
CS
3
(16 Kbytes)
Reserved area
Reserved area Reserved area
External area
Memory expansion mode Microprocessor mode
CS
2
(92 Kbytes)
CS
1
(32 Kbytes)
CS
0
Memory expansion mode: 640 Kbytes
Microprocessor mode: 832 Kbytes
Address XXXXX
16
Capacity
Internal RAM
5 Kbytes
10 Kbytes
017FF
16
02BFF
16
Address YYYYY
16
Capacity
Internal ROM
128 Kbytes
256 Kbytes
When PM13 = 0 and PM10 = 1 (A memory space of 1MB)
Note: When the PM13 bit in the PM1 register = 0, 192 Kbytes or smaller of the internal ROM can
be used.
E0000
16
D0000
16
(Note)
_____
Figure 1.6.6 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (3)
XXXXX16
0000016
YYYYY16
FFFFF16
0040016
1000016
2700016
2800016
3000016
8000016
SFR
Reserved area
Internal ROM
Reserved area
External area
SFR
Internal RAM
Reserved area
Reserved area
External area
Memory expansion mode
When PM13 = 1 and PM10 = 1 (A memory space of 1MB)
Microprocessor mode
CS2 (92 Kbytes)
CS1 (32 Kbytes)
CS0
Memory expansion mode: 320 Kbytes
Microprocessor mode: 832 Kbytes
Address XXXXX16
Capacity
Internal RAM
5 Kbytes
10 Kbytes
017FF16
02BFF16
Address YYYYY16
Capacity
Internal ROM
128 Kbytes
256 Kbytes
E000016
C000016
Internal RAM
Reserved area
_____
Figure 1.6.7 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (4)
Rev.1.00 2003.05.30 page 36
M16C/6N4 Group Bus
Under development
This document is under development and its contents are subject to change.
Bus
During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform
_______
data input/output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0 to
_______ _____ ________ ______ ________ ________ ________ __________ _________
CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK.
Bus Mode
The bus mode, either multiplexed or separate, can be selected using the PM05 to PM04 bits in the PM0
register.
Separate Bus
In this bus mode, data and address are separate.
Multiplexed Bus
In this bus mode, data and address are multiplexed.
• When the input level on BYTE pin is high (8-bit data bus)
D0 to D7 and A0 to A7 are multiplexed.
• When the input level on BYTE pin is low (16-bit data bus)
D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15.
External buses connecting to a multiplexed bus are allocated to only the even addresses of the
microcomputer. Odd addresses cannot be accessed.
Rev.1.00 2003.05.30 page 37
M16C/6N4 Group Bus Control
Under development
This document is under development and its contents are subject to change.
Figure 1.7.1 CSR Register
Bus Control
The following describes the signals needed for accessing external devices and the functionality of software
wait.
(2) Data Bus
When input on the BYTE pin is high (data bus is an 8-bit width), 8 lines D0 to D7 comprise the data bus;
when input on the BYTE pin is low (data bus is a 16-bit width), 16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.
(3) Chip Select Signal ______ ______
The chip select (hereafter referred to as the CSi) signals are output from the CSi (i = 0 to 3) pins. These
_____
pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 1.7.1 shows the CSR register. ______
During 1 Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output
______
from the CSi pin. ______
Figure 1.7.2 shows the example of address bus and CSi signal output in 1 Mbyte mode.
Set value (Note) Pin function Address bus width
PM11 = 1 P34 to P3712 bits
PM06 = 1 P40 to P43
PM11 = 0 A12 to A15 16 bits
PM06 = 1 P40 to P43
PM11 = 0 A12 to A15 20 bits
PM06 = 0 A16 to A19
Note: No values other than those shown above can
be set.
(1) Address Bus
The address bus consists of 20 lines, A0 to A19.
The address bus width can be chosen to be 12,
16 or 20 bits by using the PM06 bit in the PM0
register and the PM11 bit in the PM1 register.
Table 1.7.1 shows the PM06 and PM11 bits set
values and address bus widths.
When processor mode is changed from single-
chip mode to memory expansion mode, the
address bus is indeterminate until any external
area is accessed.
Table 1.7.1 PM06 and PM11 Bits Set Value and
Address Bus Width
0 : Chip select output disabled
(functions as I/O port)
1 : Chip select output enabled
0 : With wait state
1 : Without wait state
(Notes 1, 2, 3)
Chip select control register
Symbol Address After reset
Bit name Function
Bit symbol
Note 1: Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplexed bus is used, set the
CSiW bit to "0" (Wait state).
Note 2: If the PM17 bit in the PM1 register is set to "1" (with wait state), the external area indicated by CS0 to CS3
is always accessed with one wait state even when the CSiW bit is "1" (without wait state).
Note 3: When the CSiW bit is "0" (with wait state), the number of wait states (in terms of clock cycles) can be selected
using the CSEi1W to CSEi0W bits in the CSE register.
b7 b6 b5 b4 b3 b2 b1 b0
CSR 0008
16
01
16
CS
3 wait bit
CS
2 wait bit
CS
1 wait bit
CS
0 wait bit
CS
3 output enable bit
CS
2 output enable bit
CS
0 output enable bit
CS
1 output enable bit
RW
RW
RW
RW
RW
RW
RW
RW
RW
CS1
CS0
CS3
CS2
CS1W
CS0W
CS3W
CS2W
Rev.1.00 2003.05.30 page 38
M16C/6N4 Group Bus Control
Under development
This document is under development and its contents are subject to change.
______
Figure 1.7.2 Example of Address Bus and CSi Signal Output in 1 Mbyte Mode
Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3 (not including i, however)
Note : These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle
may be extended more than two cycles depending on a combination of these examples.
To access the external area indicated by CSj in the next cycle
after accessing the external area indicated by CSi.
The address bus and the chip select signal both change state
between these two cycles.
Example 2
To access the internal ROM or internal RAM in the next cycle
after accessing the external area indicated by CSi.
The chip s elect signal c hanges state but the address bus
does not change state.
Example 1
BCLK
Read signal
Data bus
Address bus
CSi
Access to the external
area indicated by CSi
Access to the external
area indicated by CSj
Address
Data
CSj
Data
BCLK
Read signal
Data bus
Address bus
CSi
Access to the external
area indicated by CSi
Access to the internal
ROM or internal RAM
Address
Data
Address
Example 4
Not to access any area (nor instruction prefetch generated)
in the next cycle after accessing the external area indicated
by CSi.
Neither the address bus nor the chip select signal changes
state between these two cycles.
To a ccess the external area indicated by CSi in the next cycle
after accessing the external area indicated by the same CSi.
The address bus changes state but the chip select signal
does not change state.
Example 3
BCLK
Read signal
Data bus
Address bus
CSi
Access to the external
area indicated by CSi
Access to the same
external area
Address
Data Data
BCLK
Read signal
CSi
Access to the external
area indicated by CSi
No access
Address
Data
Address
Data bus
Address bus
Rev.1.00 2003.05.30 page 39
M16C/6N4 Group Bus Control
Under development
This document is under development and its contents are subject to change.
_____ ______ ________
Table 1.7.3 Operation of RD, WR and BHE Signals
_____ ________ _________
Table 1.7.2 Operation of RD, WRL and WRH Signals
(4) Read and Write Signals
_____
When the data bus is 16-bit width, the read and write signals can be chosen to be a combination of RD,
______ ________ _____ ________ ________
WR and BHE or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When
_____ ______ ________
the data bus is 8-bit width, use a combination of RD, WR and BHE.
_____ ________ _________ _____
Table 1.7.2 shows the operation of RD, WRL, and WRH signals. Table 1.7.3 shows the operation of RD,
______ ________
WR, and BHE signals.
Note: Do not use.
(5) ALE Signal
The ALE signal latches the address when accessing the multiplexed bus space. Latch the address when
the ALE signal falls. Figure 1.7.3 shows the ALE signal, address bus and data bus.
Figure 1.7.3 ALE Signal, Address Bus, Data Bus
L
H
L
H
L
H
L
H
Data bus width
_____
RD
________
WRL
_________
WRH Status of external data bus
16 bits
(BYTE pin
input = L)
L
H
H
H
H
L
H
L
H
H
L
L
Read data
Write 1 byte of data to an even address
Write 1 byte of data to an odd address
Write data to both even and odd addresses
Data bus width
_____
RD
______
WR
________
BHE Status of external data bus
16 bits
(BYTE pin
input = L)
8 bits
(BYTE pin input = H)
H
L
H
L
H
L
H
L
L
L
H
H
L
L
-
(Note)
-
(Note)
Write 1 byte of data to an odd address
Read 1 byte of data from an odd address
Write 1 byte of data to an even address
Read 1 byte of data from an even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
H
H
L
L
L
L
H to L
H to L
A0
When BYTE pin input = H When BYTE pin input = L
ALE
Address Data
Address (Note)
A
0
/D
0
to A
7
/D
7
A
8
to A
19
ALE
Address Data
Address
A
1
/D
0
to A
8
/D
7
A
9
to A
19
Address
A
0
Note: If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.
Rev.1.00 2003.05.30 page 40
M16C/6N4 Group Bus Control
Under development
This document is under development and its contents are subject to change.
________
Figure 1.7.4 Example in which Wait State was Inserted into Read Cycle by RDY Signal
BCLK
RD
CS
i
(i=0 to 3)
RDY
t
su(RDY - BCLK)
BCLK
RD
CS
i
(i=0 to 3)
RDY
t
su(RDY - BCLK)
In an instance of separate bus
In an instance of multiplexed bus
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
Accept timing of RDY signal
tSU(RDY-BCLK): RDY input setup time
Shown above is the case where CSEi1W to CSEi0W (i = 0 to 3) bits in the CSE register are
"002" (one wait state).
________
(6) The RDY Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If input on
________
the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in
________
the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY
signal was acknowledged.
______ ______ ______ ________ ________ ______ ________ __________
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
________
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle
is executed. Figure 1.7.4 shows example in which the wait state was inserted into the read cycle by the
________ ________
RDY signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register
________ ________
to “0” (with wait state). When not using the RDY signal, process the RDY pin as an unused pin.
Rev.1.00 2003.05.30 page 41
M16C/6N4 Group Bus Control
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This document is under development and its contents are subject to change.
__________
HOLD > DMAC > CPU
__________
(7) HOLD Signal
This signal is used to transfer control of the bus from CPU or DMAC to an external circuit. When the input
__________
on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in
__________
process finishes. The microcomputer remains in a hold state while the HOLD pin is held low, during which
__________
time the HLDA pin outputs a low-level signal.
Table 1.7.4 shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence (refer to
“Figure 1.7.5 Bus-using Priorities”). However, if the CPU is accessing an odd address in word units, the
DMAC cannot gain control of the bus during two separate accesses.
Figure 1.7.5 Bus-using Priorities
Table 1.7.4 Microcomputer Status in Hold State
Note 1: When I/O port function is selected.
Note 2: The watchdog timer does not stop when the PM22 bit in the PM2 register is set to “1” (the count
source for the watchdog timer is the ring oscillator clock).
(8) BCLK Output
If the PM07 bit in the PM0 register is set to “0” (output enable), a clock with the same frequency as that
of the CPU clock is output as BCLK from the BCLK pin. Refer to “CPU Clock and Peripheral Function
Clock”.
Table 1.7.5 shows the pin functions for each processor mode.
Item Status
BCLK Output
______ ______ ______ _________ _________ _______ ________
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE High-impedance
I/O ports P0, P1, P3, P4 (Note 1) High-impedance
P6 to P10 Maintains status when hold signal is received
__________
HLDA Output “L”
Internal peripheral circuits ON (but watchdog timer stops (Note 2))
ALE signal Undefined
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M16C/6N4 Group Bus Control
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This document is under development and its contents are subject to change.
Table 1.7.5 Pin Functions for Each Processor Mode
Processor mode Memory expansion mode or microprocessor mode
Memory expansion mode
PM05 to PM04 bits 002 (separate bus)
______
012 (CS2 is for multiplexed bus and
112 (multiplexed bus
others are for separate bus)
for the entire space)
______
102 (CS1 is for multiplexed bus and
(Note 1)
others are for separate bus)
Data bus width 8 bits 16 bits 8 bits 16 bits 8 bits
BYTE pin “H”“L”“H”“L” “H”
P00 to P07D0 to D7D0 to D7 (Note 4) I/O ports
P10 to P17I/O ports D8 to D15 I/O ports
D8 to D15
(Note 4)
I/O ports
P20A0A0/D0 (Note 2) A0A0/D0
P21 to P27A1 to A7A1 to A7/D1 to D7A1 to A7/D0 to D6A1 to A7/D1 to D7
(Note 2) (Note 2)
P30A8A8/D7
(Note 2)
A8
P31 to P33A9 to A11 I/O ports
P34 to P37PM11 = 0 A12 to A15 I/O ports
PM11 = 1 I/O ports
P40 to P43PM06 = 0 A16 to A19 I/O ports
PM06 = 1 I/O ports
P44CS0 = 0 I/O ports
CS0 = 1
______
CS0
P45CS1 = 0 I/O ports
CS1 = 1
______
CS1
P46CS2 = 0 I/O ports
CS2 = 1
______
CS2
P47CS3 = 0 I/O ports
CS3 = 1
______
CS3
P50PM02 = 0
_______
WR
PM02 = 1
-
(Note 3)
________
WRL
-
(Note 3)
________
WRL
-
(Note 3)
P51PM02 = 0
________
BHE
PM02 = 1
-
(Note 3)
_________
WRH
-
(Note 3)
_________
WRH
-
(Note 3)
P52
______
RD
P53BCLK
P54
___________
HLDA
P55
___________
HOLD
P56ALE
P57
_________
RDY
I/O ports: Function as I/O ports or peripheral function I/O pins.
Note 1: For setting the PM01 to PM00 bits to “012” (memory expansion mode) and the PM05 to PM04 bits to
_____
“112” (multiplexed bus assigned to the entire CS space), apply “H” to the BYTE pin (external data bus
is an 8-bit width). While the CNVSS pin is held “H” (VCC1), do not rewrite the PM05 to PM04 bits to “112”
after reset. If the PM05 to PM04 bits are set to “112” during memory expansion mode, P31 to P37 and
_____
P40 to P43 become I/O ports, in which case the accessible area for each CS is 256 bytes.
Note 2: In separate bus mode, these pins serve as the address bus.
Note 3:
_____ ________ ______
If the data bus is 8-bit width, make sure the PM02 bit is set to “0” (RD, BHE, WR).
Note 4: When accessing the area that uses a multiplexed bus, these pins output an indeterminate value
during a write.
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M16C/6N4 Group Bus Control
Under development
This document is under development and its contents are subject to change.
(10) Software Wait
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits
in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is
always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. Refer
to “Table 1.7.7 Bit and Bus Cycle Related to Software Wait ” for details.
________
To use the RDY signal, set the corresponding CS3W to CS0W bit to “0” (with wait state). Figure 1.7.6
shows the CSE register. Table 1.7.7 shows the software wait related bits and bus cycles. Figures 1.7.7
and 1.7.8 show the typical bus timings using software wait.
(9) External Bus Status When Internal Area Accessed
Table 1.7.6 shows the external bus status when the internal area is accessed.
Table 1.7.6 External Bus Status When Internal Area Accessed
Figure 1.7.6 CSE Register
Item SFR accessed Internal ROM, internal RAM accessed
A0 to A19 Address output Maintain status before accessed address
of external area or SFR
D0 to D15 When read High-impedance High-impedance
When write Output data Undefined
_____ ______ ________ _________
RD, WR, WRL, WRH
_____ ______ _________ __________
RD, WR, WRL, WRH output Output “H”
________
BHE
________
BHE output Maintain status before accessed status of
external area or SFR
_______ _______
CS0 to CS3Output “H”Output “H”
ALE Output “L”Output “L”
CS0 wait expansion bit
(Note)
CS1 wait expansion bit
(Note)
CS2 wait expansion bit
(Note)
CS3 wait expansion bit
(Note)
0 0 : 1 wait
0 1 : 2 waits
1 0 : 3 waits
1 1 : Must not be set
b1 b0
0 0 : 1 wait
0 1 : 2 waits
1 0 : 3 waits
1 1 : Must not be set
b3 b2
0 0 : 1 wait
0 1 : 2 waits
1 0 : 3 waits
1 1 : Must not be set
b5 b4
0 0 : 1 wait
0 1 : 2 waits
1 0 : 3 waits
1 1 : Must not be set
b7 b6
Bit name Function
Bit symbol RW
Chip select expansion control register
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
RW
RW
RW
RW
RW
RW
Symbol Address After reset
CSE 001B16 0016
CSE00W
CSE01W
CSE10W
CSE11W
CSE20W
CSE21W
CSE30W
CSE31W
Note: Set the CSiW bit (i = 0 to 3) in the CSR register to "0" (with wait state) before writing to the CSEi1W to CSEi0W
bits. If the CSiW bit needs to be set to "1" (without wait state), set the CSEi1W to CSEi0W bits to "002" before
setting it.
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M16C/6N4 Group Bus Control
Under development
This document is under development and its contents are subject to change.
Table 1.7.7 Software Wait Related Bits and Bus Cycles
Area
Bus mode
SFR
Internal
ROM, RAM
External
area
-
-
-
-
Separate
bus
Multiplexed
bus
(Note 2)
PM1 Register
PM17 bit
-
-
0
1
0
-
-
-
1
-
-
-
1
2 BCLK cycles
(Note 4)
3 BCLK cycles
(Note 4)
1 BCLK cycle
(Note 3)
2 BCLK cycles
1 BCLK cycle (read)
2 BCLK cycles (write)
2 BCLK cycles
(Note 3)
3 BCLK cycles
4 BCLK cycles
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
4 BCLK cycles
3 BCLK cycles
Bus cycle
-
-
-
-
1
0
0
0
1
0
0
0
0
-
-
-
-
002
002
012
102
002
002
012
102
002
CSR register
CS3W bit (Note 1)
CS2W bit (Note 1)
CS1W bit (Note 1)
CS0W bit (Note 1)
CSE register
CS31W to CS30W bits
CS21W to CS20W bits
CS11W to CS10W bits
CS01W to CS00W bits
Note 1:
________
To use the RDY signal, set this bit to “0 ”.
Note 2: To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to “0” (with wait state).
Note 3: After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0”
______ ______
(with wait state), and the CSE register is set to “0016” (one wait state for CS0 to CS3). Therefore, the
internal RAM and internal ROM are accessed with no wait state, and all external areas are
accessed with one wait state.
Note 4: When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by
the PM20 bit in the PM2 register. When using a 16 MHz or higher PLL clock, be sure to set the PM20
bit to “0” (2 wait cycles).
Software
wait
-
-
No wait
1 wait
No wait
1 wait
2 waits
3 waits
1 wait
1 wait
2 waits
3 waits
1 wait
0
1
-
-
-
-
-
-
-
-
-
-
-
PM2 Register
PM20 bit
Rev.1.00 2003.05.30 page 45
M16C/6N4 Group Bus Control
Under development
This document is under development and its contents are subject to change.
Figure 1.7.7 Typical Bus Timings Using Software Wait (1)
Note: These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and
write cycles in succession.
Output
Input
Address Address
Bus cycle (Note) Bus cycle (Note)
BCLK
Read signal
Write signal
Data bus
Address bus
CS
(2) Separate bus, 1-wait setting
BCLK
Read signal
Write signal
Data bus
Address bus Address Address
Bus cycle (Note)
Output Input
Bus cycle (Note)
CS
(1) Separate bus, No wait setting
Output
Address Address
Bus cycle (Note) Bus cycle (Note)
Input
BCLK
CS
Read signal
Write signal
Data bus
Address bus
(3) Separate bus, 2-wait setting
Rev.1.00 2003.05.30 page 46
M16C/6N4 Group Bus Control
Under development
This document is under development and its contents are subject to change.
Figure 1.7.8 Typical Bus Timings Using Software Wait (2)
Note: These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and
write cycles in succession.
Address
Bus cycle (Note)
Output
Bus cycle (Note)
Input
Address
BCLK
CS
Write signal
Read signal
Data bus
Address bus
(1) Separate bus, 3-wait setting
Address bus/
Data bus Address
Address
Data output
Address
Address
Input
ALE
Bus cycle (Note) Bus cycle (Note)
BCLK
CS
Write signal
Read signal
Address bus
(2)Multiplexed bus, 1- or 2-wait setting
Address
Data output
Address
Address
Input
Bus cycle (Note)
Read signal
Write signal
Address bus/
Data bus
CS
Address bus
ALE
Bus cycle (Note)
Address
BCLK
(3)Multiplexed bus, 3-wait setting
Rev.1.00 2003.05.30 page 47
M16C/6N4 Group Clock Generation Circuit
Under development
This document is under development and its contents are subject to change.
Clock Generation Circuit
The clock generation circuit contains four oscillator circuits as follows:
(1) Main clock oscillation circuit
(2) Sub clock oscillation circuit
(3) Ring oscillator
(4) PLL frequency synthesizer
Table 1.8.1 lists the clock generation circuit specifications. Figure 1.8.1 shows the clock generation circuit.
Figures 1.8.2 to 1.8.8 show the clock-related registers.
Table 1.8.1 Clock Generation Circuit Specifications
Item Main clock
oscillation circuit
Sub clock
oscillation circuit Ring oscillator PLL frequency
synthesizer
Use of clock
Clock frequency
Usable
oscillator
Pins to connect
oscillator
Oscillation stop
and re-oscillation
detection function
Oscillation status
after reset
Other
•CPU clock source
•Peripheral function
clock source
0 to 16 MHz
•Ceramic oscillator
•Crystal oscillator
XIN, XOUT
Present
Oscillating
Externally derived clock can be input
•CPU clock source
•Timer A, B’s clock
source
32.768 kHz
•Crystal oscillator
XCIN, XCOUT
Present
Stopped
•CPU clock source
•Peripheral function
clock source
•CPU and peripheral
function clock sources
when the main clock
stops oscillating
About 1 MHz
-
-
Present
Stopped
-
•CPU clock source
•Peripheral function
clock source
20 MHz
-
-
Present
Stopped
-
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M16C/6N4 Group Clock Generation Circuit
Under development
This document is under development and its contents are subject to change.
Figure 1.8.1 Clock Generation Circuit
1/16
CLKOUT
CM01-CM00=00
2
PM01-PM00=00
2
, CM01-CM00=01
2
PM01-PM00=00
2
, CM01-CM00=10
2
fCAN0
PM01-PM00=00
2
,
CM01-CM00=11
2
By CCLK0,1 and 2
I/O ports
1/32 f
C32
f
C
f
1
f
2
fCAN1
fAD
By CCLK4,5 and 6
PCLK0=1
PCLK0=0
PCLK0=1
PCLK0=0
f
1SIO
f
2SIO
PCLK1=1
PCLK1=0
CM07=0
CPU clock
BCLK
CM07=1
f
C
f
8
f
32
f
8SIO
f
32SIO
Divider
bcdef
g
a
CM21=1
CM21=0
1
0CM11
PLL frequency
synthesizer
Oscillation stop,
re-oscillation
detection circuit
Ring oscillator
X
OUT
X
IN
Main clock
oscillation circuit
Main clock
CM05
X
COUT
X
CIN
Sub clock oscillation circuit
CM04
PLL clock
Ring oscillator
clock
CM02
QS
R
QS
R
CM10=1
(stop mode)
WAIT instruction
RESET
NMI
Software reset
Interrupt request level
judgment output
1/2 1/2 1/2 1/2 1/2
g
Details of divider
dcbef
1/81/41/2
a1/32
CM06=0
CM17-CM16=11
2
CM06=0
CM17-CM16=10
2
CM06=1
CM06=0
CM17-CM16=01
2
CM06=0
CM17-CM16=00
2
CM02, CM04, CM05, CM06, CM07 : CM0 register’s bits
CM10, CM11, CM16, CM17 : CM1 register’s bits
PCLK0, PCLK1 : PCLKR register’s bits
CM21, CM27 : CM2 register’s bits
CCLK0 to CCLK2 and CCLK4 to CCLK6: CCLKR register’s bits
Sub clock
CM21
Reset
generation
circuit
Oscillation stop,
re-oscillation detection
interrupt generating
circuit
Main clock
Oscillation stop
detection reset
CM21 switch signal
Oscillation stop,
re-oscillation detection
interrupt signal
Oscillation stop, re-oscillation detection circuit
Charge,
discharge
circuit
Pulse generation circuit
for clock edge detection
and charge,
discharge control
CM27 = 0
CM27 = 1
Main clock
PLL clock
PLL frequency synthesizer
Phase
comparator
Voltage
control
oscillator
(VCO)
Internal
lowpass filter
Charge
pump
Programmable
counter 1/2
Rev.1.00 2003.05.30 page 49
M16C/6N4 Group Clock Generation Circuit
Under development
This document is under development and its contents are subject to change.
Figure 1.8.2 CM0 Register
System clock control register 0 (Note 1)
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Note 2: The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to "1"
(peripheral clock turned off when in wait mode).
Note 3: The CM03 bit is set to "1" (high) when the CM04 bit is set to "0" (I/O port) or the microcomputer goes to
stop mode.
Note 4: To use a sub clock, set this bit to "1". Also make sure ports P86 and P87 are directed for input, with no
pull-ups.
Note 5: This bit is provided to stop the main clock when the low power dissipation mode or ring oscillator low power
dissipation mode is selected. This bit cannot be used for detection as to whether the main clock stopped
or not. To stop the main clock, the following setting is required:
(1) Set the CM07 bit to "1" (sub clock select) or the CM21 bit of CM2 register to "1" (ring oscillator select)
with the sub clock stably oscillating.
(2) Set the CM20 bit of CM2 register to "0" (oscillation stop, re-oscillation detection function disabled).
(3) Set the CM05 bit to "1" (stop).
Note 6: To use the main clock as the clock source for the CPU clock, follow the procedure below.
(1) Set the CM05 bit to "0" (oscillate)
(2) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer.
(3) Set the CM11, CM21 and CM07 bits all to "0".
Note 7: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06
bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
Note 8: During external clock input, only the clock oscillation buffer is turned off and clock input is accepted if the
sub clock is not selected as a CPU clock.
Note 9: When CM05 bit is set to "1", the XOUT pin goes "H". Furthermore, because the internal feedback resistor
remains connected, the XIN pin is pulled "H" to the same level as XOUT via the feedback resistor.
Note 10: When entering stop mode from high- or middle-speed mode, ring oscillator mode or ring oscillator low power
mode, the CM06 bit is set to "1" (divide-by-8 mode).
Note 11: After setting the CM04 bit to "1" (XCIN-XCOUT oscillator function), wait until the sub clock oscillates stably
before switching the CM07 bit from "0" to "1" (sub clock).
Note 12: To return from ring oscillator mode to high-speed or middle-speed mode, set the CM06 and CM15 bits
both to "1".
Bit name FunctionBit symbol
b1 b0
RW
RW
RW
RW
RW
RW
RW
RW
RW
0 0 : I/O port P57
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
0 : Do not stop peripheral function
clock in wait mode
1 : Stop peripheral function clock
in wait mode (Note 2)
0 : I/O port P86, P87
1 : XCIN-XCOUT generation function
(Note 4)
0 : On
1 : Off (Notes 8, 9)
0 : CM16 and CM17 valid
1 : Division by 8 mode
0 : Main clock, PLL clock, or ring
oscillator clock
1 : Sub clock
0 : LOW
1 : HIGH
CM07
CM05
CM04
CM01
CM02
CM00
CM06
Clock output function
select bit
(Valid only in single-chip
mode)
CM03
WAIT peripheral function
clock stop bit
Port XC select bit (Note 3)
Main clock stop bit
(Notes 5, 6, 7)
Main clock division select
bit 0 (Notes 7, 10, 12)
XCIN-XCOUT drive capacity
select bit (Note 3)
System clock select bit
(Notes 6, 11)
Symbol Address After reset
CM0 000616 010010002
b7 b6 b5 b4 b3 b2 b1 b0
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M16C/6N4 Group Clock Generation Circuit
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This document is under development and its contents are subject to change.
Figure 1.8.3 CM1 Register
RW
RW
RW
RW
RW
RW
RW
Bit name FunctionBit symbol
CM10
CM15
CM16
CM17
CM11
-
(b4-b2)
All clock stop control bit
(Notes 2, 3)
XIN-XOUT drive capacity
select bit (Note 6)
Reserved bit
Main clock division
select bit 1 (Note 7)
System clock select bit 1
(Notes 3, 4)
0 : Clock on
1 : All clocks off (stop mode)
0 : LOW
1 : HIGH
Set to "0"
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
0 : Main clock
1 : PLL clock (Note 5)
Symbol
Address After reset
CM1 0007
16
00100000
2
System clock control register 1 (Note 1)
000
b7 b6 b5 b4 b3 b2 b1 b0
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable)
Note 2: If the CM10 bit is "1" (stop mode), X
OUT
goes "H" and the internal feedback resistor is disconnected.
The X
CIN
and X
COUT
pins are placed in the high-impedance state. When the CM11 bit is set to "1" (PLL clock),
or the CM20 bit of CM2 register is set to "1" (oscillation stop, re-oscillation detection function enabled), do
not set the CM10 bit to "1".
Note 3: When the PM22 bit of PM2 register is set to "1" (watchdog timer count source is ring oscillator clock), writing
to the CM10 bit has no effect.
Note 4: Effective when CM07 bit is "0" and CM21 bit is "0".
Note 5: After setting the PL07 bit in PLC0 register to "1" (PLL operation), wait until t
su
(PLL) elapses before setting
the CM11 bit to "1" (PLL clock).
Note 6: When entering stop mode from high- or middle-speed mode, or when the CM05 bit is set to "1" (main clock
turned off) in low-speed mode, the CM15 bit is set to "1" (drive capability high).
Note 7: Effective when the CM06 bit is "0" (CM16 and CM17 bits enabled).
Rev.1.00 2003.05.30 page 51
M16C/6N4 Group Clock Generation Circuit
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This document is under development and its contents are subject to change.
Figure 1.8.4 CM2 Register
Oscillation stop detection register (Note 1)
Symbol
Address
After reset
CM2 000C
16
0X00X000
2
(Note 2)
Function
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name
0 : Oscillation stop, re-oscillation
detection function disabled
1 : Oscillation stop, re-oscillation
detection function enabled
0 : Main clock or PLL clock
(Ring oscillator turned off)
1 : Ring oscillator clock
(Ring oscillator oscillating)
CM20
CM21
CM22
0 : Main clock stop, re-oscillation
not detected
1 : Main clock stop, re-oscillation
detected
System clock select bit 2
CM23
-
(b5-b4)
-
(b6)
XIN monitor flag (Note 10) 0 : Main clock oscillating
1 : Main clock turned off
CM27
Operation select bit
(
behavior if oscillation stop,
re-oscillation is detected)
(Note 2)
0 : Oscillation stop detection reset
1 : Oscillation stop, re-oscillation
detection interrupt
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(Notes 2, 5, 6, 7, 8, 11)
Reserved bit Set to "0"
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Note 2: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
Note 3: Set the CM20 bit to "0" (disable) before entering stop mode. After exiting stop mode, set the CM20 bit
back to "1" (enable).
Note 4: Set the CM20 bit to "0" (disable) before setting the CM05 bit of CM0 register
Note 5: When the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1"
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21
bit is set to "1" (ring oscillator clock) if the main clock stop is detected.
Note 6: If the CM20 bit is "1" and the CM23 bit is "1" (main clock turned off), do not set the CM21 bit to "0".
Note 7: Effective when the CM07 bit of CM0 register is "0".
Note 8: Where the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1"
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is "1" (the CPU clock source is PLL
clock), the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is "0"
under these conditions, oscillation stop, re-oscillation detection interrupt generate at main clock stop detection;
it is, therefore, necessary to set the CM21 bit to "1" (ring oscillator clock) inside the interrupt routine.
Note 9: This bit is set to "1" when the main clock is detected to have stopped and when the main clock is detected
to have restarted oscillating. When this bit changes state from "0" to "1", an oscillation stop, re-oscillation
detection interrupt request is generated. Use this bit in an interrupt routine to discriminate the causes of
interrupts between the oscillation stop, re-oscillation detection interrupt and the watchdog timer interrupt.
This bit is set to "0" by writing "0" in a program. (Writing "1" has no effect. Nor is it set to "0" by an oscillation
stop, re-oscillation detection interrupt request acknowledged.)
If an oscillation stop or a re-oscillation is detected when the CM22 bit = 1, no oscillation stop and re-oscillation
detection interrupt requests are generated.
Note 10: Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine
the main clock status.
Note 11: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06
bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
RW
RO
-
RW
RW
RW
RW
RW
00
Oscillation stop, re-oscillation
detection enable bit
(Notes 2, 3, 4)
Oscillation stop, re-oscillation
detection flag (Note 9)
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Figure 1.8.6 CCLKR Register
Figure 1.8.5 PCLKR Register
Note: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Peripheral clock select register (Note)
Symbol Address After reset
PCLKR 025E16 0016
0000 00
b7 b6 b5 b4 b3 b2 b1 b0
PCLK0
PCLK1
-
(b7-b2)
Timers A, B, and A-D clock select bit
(Clock source for the timers A, B,
the dead time timer and A-D)
SI/O clock select bit
(Clock source for UART0 to
UART2, SI/O3)
0 : Divide-by-2 of fAD2, f2
1 : fAD, f1
0 : f2SIO
1 : f1SIO
Reserved bit Set to "0"
RW
RW
RW
Bit name FunctionBit symbol RW
b6 b5 b4
0: CAN1 CPU interface operating
1: CAN1 CPU interface in sleep
RW
RW
RW
RW
RW
RW
RW
RW
0 0 0 No division
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
0 1 1 : Divide-by-8
1 0 0: Divide-by-16
1 0 1 :
1 1 0 : Inhibited
1 1 1 :
0 0 0 No division
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
0 1 1 : Divide-by-8
1 0 0: Divide-by-16
1 0 1 :
1 1 0 : Inhibited
1 1 1 :
b2 b1 b0
CAN0 clock select bits
CAN0 CPU interface
sleep bit
0: CAN0 CPU interface operating
1: CAN0 CPU interface in sleep
CAN1 clock select bits
CAN1 CPU interface
sleep bit
Bit name FunctionBit symbol RW
CCLK7
CCLK5
CCLK4
CCLK3
CCLK1
CCLK2
CCLK0
CCLK6
Symbol Address After reset
CCLKR 025F16 0016
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Note 2: Configuration of this register can be done only when the Reset bit of C0CTLR, C1CTLR registers = 1
(Reset/Initialization mode).
CAN0/1 clock select register (Notes 1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
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Symbol Address After reset
PM2 001E
16
XXX00000
2
Processor mode register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Specifying wait when
accessing SFR at PLL
operation (Note 2)
0 : 2 waits
1 : 1 wait
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Reserved bit
RW
RW
RW
RW
-
WDT count source
protective bit (Notes 3, 4)
0 : CPU clock is used for the
watchdog timer count source
1 : Ring oscillator clock is used for
the watchdog timer count source
Reserved bit Set to "0"
Set to "0"
Bit name Function
Bit symbol RW
PM20
-
(b1)
-
(b4-b3)
-
(b7-b5)
PM22
Note 1: Write to this register after setting the PRC1 bit of PRCR register to "1" (write enable).
Note 2: This bit can only be rewritten while the PLC07 bit is "0" (PLL turned off). Also, to select a 16 MHz or higher
PLL clock, set this bit to "0" (2 waits). Note that if the clock source for the CPU clock is to be changed from
the PLL clock to another, the PLC07 bit must be set to "0" before setting the PM20 bit.
Note 3: Once this bit is set to "1", it cannot be set to "0" in a program.
Note 4: Setting the PM22 bit to "1" results in the following conditions:
The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source.
The CM10 bit of CM1 register is disabled against write. (Writing a "1" has no effect, nor is stop mode entered.)
The watchdog timer does not stop when in wait mode or hold state.
Figure 1.8.7 PM2 Register
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Figure 1.8.8 PLC0 Register
PLC07
Function
PLL control register 0 (Note 1)
Operation enable bit
(Note 3)
0 : PLL Off
1 : PLL On
Bit nameBit symbol
Symbol Address After reset
PLC0 001C16 0001X0102
RW
PLC00
b2 b1 b0
0 0 0 : Must not be set
0 0 1 : Multiply by 2
0 1 0 : Multiply by 4
0 1 1 : Multiply by 6
1 0 0 : Multiply by 8
1 0 1 :
1 1 0 :
1 1 1 :
PLC01
PLC02
-
(b3)
-
(b4)
-
(b6-b5)
Reserved bit Set to "1"
Reserved bit Set to "0"
PLL multiplying factor
select bit (Note 2)
Must not be set
RW
RW
RW
-
RW
RW
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Note 2:
These three bits can only be modified when the PLC07 bit = 0 (PLL turned off). The value once written to
this bit cannot be modified.
Note 3: Before setting this bit to "1", set the CM07 bit to "0" (main clock), set the CM17 to CM16 bits to "002"
(main clock undivided mode), and set the CM06 bit to "0" (CM16 and CM17 bits enable).
b7 b6 b5 b4 b3 b2 b1 b0
0 10
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Note: Insert a damping resistor if required. The resistance will vary depending on the
oscillator and the oscillation drive capacity setting. Use the value recommended
by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Also, if the oscillator manufacturer’s data sheet specifies that a feedback resistor
be added external to the chip, insert a feedback resistor between X
IN
and X
OUT
following the instruction.
Microcomputer
(Built-in feedback resistor)
XIN XOUT
Externally derived clock
Open
Vcc
Vss
Microcomputer
(Built-in feedback resistor)
XIN XOUT
R
d
C
IN
C
OUT
(Note)
Figure 1.8.9 Examples of Main Clock Connection Circuit
The following describes the clocks generated by the clock generation circuit.
(1) Main Clock
This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscilla-
tor circuit is configured by connecting a resonator between the XIN and XOUT pins. The main clock oscilla-
tor circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode
in order to reduce the amount of power consumed in the chip. The main clock oscillator circuit may also
be configured by feeding an externally generated clock to the XIN pin. Figure 1.8.9 shows the examples of
main clock connection circuit.
After reset, the main clock divided by 8 is selected for the CPU clock.
The power consumption in the chip can be reduced by setting the CM05 bit of CM0 register to “1” (main
clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or ring
oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback resistor remains
on, XIN is pulled “H” to XOUT via the feedback resistor. Note, that if an externally generated clock is fed into
the XIN pin, the main clock cannot be turned off by setting the CM05 bit to “1” unless the sub clock is
selected as a CPU clock. If necessary, use an external circuit to turn off the clock.
During stop mode, all clocks including the main clock are turned off. Refer to “power control”.
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Figure 1.8.10 Examples of Sub Clock Connection Circuit
(2) Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for
the CPU clock, as well as the timer A and timer B count sources. In addition, an fC clock with the same
frequency as that of the sub clock can be output from the CLKOUT pin.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT
pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator
circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub clock
oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure
1.8.10 shows the examples of sub clock connection circuit.
After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscillator
circuit.
To use the sub clock for the CPU clock, set the CM07 bit of CM0 register to “1 ” (sub clock) after the sub
clock becomes oscillating stably.
During stop mode, all clocks including the sub clock are turned off. Refer to “power control”.
Note: Insert a damping resistor if required. The resistance will vary depending on the
oscillator and the oscillation drive capacity setting. Use the value recommended
by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Also, if the oscillator manufacturer’s data sheet specifies that a feedback resistor
be added external to the chip, insert a feedback resistor between XCIN and XCOUT
following the instruction.
Microcomputer
(Built-in feedback resistor)
XCIN XCOUT
Externally derived clock
Open
Vcc
Vss
Microcomputer
(Built-in feedback resistor)
XCIN XCOUT
(Note)
CCIN CCOUT
RCd
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(3) Ring Oscillator Clock
This clock, approximately 1 MHz, is supplied by a ring oscillator. This clock is used as the clock source for
the CPU and peripheral function clocks. In addition, if the PM22 bit of PM2 register is “1” (ring oscillator
clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer
(refer to “Watchdog Timer • Count source protective mode”).
After reset, the ring oscillator is turned off. It is turned on by setting the CM21 bit of CM2 register to “1”
(ring oscillator clock), and is used as the clock source for the CPU and peripheral function clocks, in place
of the main clock. If the main clock stops oscillating when the CM20 bit of CM2 register is “1” (oscillation
stop, re-oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop, re-oscillation
detection interrupt), the ring oscillator automatically starts operating, supplying the necessary clock for the
microcomputer.
(4) PLL Clock
The PLL clock is generated by a PLL frequency synthesizer. This clock is used as the clock source for the
CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthe-
sizer is activated by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is used as the clock
source for the CPU clock, wait a fixed period of tsu(PLL) for the PLL clock to be stable, and then set the
CM11 bit in the CM1 register to “1”.
Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0”
(PLL stops). Figure 1.8.11 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
Figure 1.8.11 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
PLL clock frequency = f(XIN) ✕ (multiplying factor set by the PLC02 to PLC00 bits of the PLC0 register)
(However, PLL clock frequency = 20 MHz)
The PLC02 to PLC00 bits can be set only once after reset. Table 1.8.2 shows the example for setting PLL
clock frequencies.
Table 1.8.2
Example for Setting PLL Clock Frequencies
XIN
(MHz)
10
5
Multiply
factor
PLL clock
(MHz) (Note)
PLC01 PLC00
0
0
0
1
1
0
2
420
Note: PLL clock frequency = 20 MHz
PLC02
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Figure 1.8.11 Procedure to Use PLL Clock as CPU Clock Source
Set the PLC02 to PLC00 bits (multiplying factor).
(To select a 16 MHz or higher PLL clock)
Set the PM20 bit to "0" (2-wait state).
Set the PLC07 bit to "1" (PLL operation).
Set the CM11 bit to "1" (PLL clock for the CPU clock source).
END
Using the PLL clock as the clock source for the CPU
Set the CM07 bit to "0" (main clock), the CM17 to CM16
bits to "00
2
" (main clock undivided), and the CM06 bit to "0"
(CM16 and CM17 bits enabled). (Note)
Note: PLL operation mode can be entered from high-speed mode.
Wait until the PLL clock becomes stable (tsu(PLL)).
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CPU Clock and Peripheral Function Clock
There are existing two type clocks: The CPU clock to operate the CPU and the peripheral function clocks
to operate the peripheral functions.
(1) CPU Clock and BCLK
These are operating clocks for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, ring oscillator clock or
the PLL clock.
If the main clock or ring oscillator clock is selected as the clock source for the CPU clock, the selected
clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit of
CM0 register and the CM17 to CM16 bits of CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to “0”
and the CM17 to CM16 bits to “002” (undivided).
After reset, the main clock divided by 8 provides the CPU clock.
During memory expansion or microprocessor mode, a BCLK signal with the same frequency as the CPU
clock can be output from the BCLK pin by setting the PM07 bit of PM0 register to “0” (output enabled).
Note that when entering stop mode from high- or middle-speed mode, ring oscillator mode or ring oscillator
low power dissipation mode, or when the CM05 bit of CM0 register is set to “1” (main clock turned off) in
low-speed mode, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode).
(2) Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fCAN0, fCAN1, fC32)
These are operating clocks for the peripheral functions.
Two of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or ring oscillator clock
by dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial I/O. The f8 and f32
clocks can be output from the CLKOUT pin.
The fAD clock is produced from the main clock, PLL clock or ring oscillator clock, and is used for the A-D
converter.
The fCANi (i = 0, 1) clock is derived from the main clock, PLL clock or ring oscillator clock by dividing them
by 1 (undivided), 2, 4, 8 or 16, and is used for the CAN module.
When the WAIT instruction is executed after setting the CM02 bit of CM0 register to “1” (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,
the fi, fiSIO, fAD, fCAN0 and fCAN1 clocks are turned off (Note).
The fC32 clock is derived from the sub clock, and is used for timers A and B. This clock can be used when
the sub clock is activated.
Note: fCAN0 and fCAN1 clocks stop at “H” in CAN0, 1 sleep mode.
Clock Output Function
During single-chip mode, the f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to CM00
bits of CM0 register to select.
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Power Control
There are three power control modes. For convenience’ sake, all modes other than wait and stop modes
are referred to as normal operation mode here.
(1) Normal Operation Mode
Normal operation mode is further classified into seven sub modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock
frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU
clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are
turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched
must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a
sufficient wait time in a program until it becomes oscillating stably.
Note that operation modes cannot be changed directly from low speed or low power dissipation mode to
ring oscillator or ring oscillator low power dissipation mode. Nor can operation modes be changed directly
from ring oscillator or ring oscillator low power dissipation mode to low speed or low power dissipation
mode. Where the CPU clock source is changed from the ring oscillator to the main clock, change the
operation mode to the medium-speed mode (divide-by-8 mode) after the clock was divided by 8 (the
CM06 bit of CM0 register was set to “1”) in the ring oscillator mode.
• High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is activated, fC32 can be used as
the count source for timers A and B.
• PLL Operation Mode
The main clock multiplied by 2, 4, 6 or 8 provides the PLL clock, and this PLL clock serves as the CPU
clock. If the sub clock is activated, fC32 can be used as the count source for timers A and B. PLL
operation mode can be entered from high speed mode. If PLL operation mode is to be changed to wait
or stop mode, first go to high speed mode before changing.
• Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is activated, fC32 can be
used as the count source for timers A and B.
• Low-speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral
function clock when the CM21 bit is set to “0” (ring oscillator turned off), and the ring oscillator clock is
used when the CM21 bit is set to “1” (ring oscillator oscillating).
The fC32 clock can be used as the count source for timers A and B.
• Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock
provides the CPU clock. The fC32 clock can be used as the count source for timers A and B.
Simultaneously when this mode is selected, the CM06 bit of CM0 register becomes “1” (divide-by-8
mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium
speed (divide-by-8) mode is to be selected when the main clock is operated next.
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• Ring Oscillator Mode
The ring oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The ring
oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is activated,
fC32 can be used as the count source for timers A and B.
• Ring Oscillator Low Power Dissipation Mode
The main clock is turned off after being placed in ring oscillator mode. The CPU clock can be selected
like in the ring oscillator mode. The ring oscillator clock is the clock source for the peripheral function
clocks. If the sub clock is activated, fC32 can be used as the count source for timers A and B. When the
operation mode is returned to the high- and medium-speed modes, set the CM06 bit to “1” (divide-by-
8 mode).
Table 1.8.3 lists the setting clock related bit and modes
Table 1.8.3 Setting Clock Related Bit and Modes
Modes
CM2 register
CM1 register CM0 register
CM21 CM11
CM17
,
CM16
CM07 CM06 CM05 CM04
PLL operation mode 0 1 002000-
High-speed mode 0 0 002000-
Medium-
divided by 2
00012000-
speed
divided by 4
00102000-
mode
divided by 8
00- 0 10-
divided by 16
00112000-
Low-speed mode - - - 1 - 0 1
Low power - - - 1 1 1 1
dissipation mode (Note 1) (Note 1)
Ring
divided by 1
1-002000-
oscillator
divided by 2
1-012000-
mode
divided by 4
1-102000-
divided by 8
1--010-
divided by 16
1-112000-
Ring oscillator 1 - (Note 2) 0 (Note 2) 1 -
low power dissipation
mode
Note 1: When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low
power dissipation mode and CM06 bit is set to “1” (divide-by-8 mode) simultaneously.
Note 2: The divide-by-n value can be selected the same way as in ring oscillator mode.
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(2) Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. However, if the PM22 bit of PM2 register is “1” (ring oscillator clock for the watchdog
timer count source), the watchdog timer remains active. Because the main clock, sub clock, ring oscillator
clock and PLL clock all are on, the peripheral functions using these clocks keep operating.
• Peripheral Function Clock Stop Function
If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO, f8SIO,
f32SIO, fAD, fCAN0 and fCAN1 clocks are turned off when in wait mode, with the power consumption reduced
that much. However, fC32 remains on.
• Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
When the CM11 bit = 1 (CPU clock source is the PLL clock), be sure to set the CM11 bit to “0” (CPU
clock source is the main clock) before going to wait mode. The power consumption of the chip can be
reduced by setting the PLC07 bit to “0” (PLL stops).
• Pin Status During Wait Mode
Table 1.8.4 lists the pin status during wait mode.
Table 1.8.4 Pin Status During Wait Mode
• Exiting Wait Mode
______
The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral function
interrupt.
______
If the microcomputer is to be moved out of exit wait mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disabled) before executing
the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If the CM02 bit is “0” (peripheral
function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit
wait mode. If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the periph-
eral functions using the peripheral function clocks stop operating, so that only the peripheral functions
clocked by external signals can be used to exit wait mode.
Table 1.8.5 lists the interrupts to exit wait mode.
Pin Memory expansion mode Single-chip mode
Microprocessor mode
A0 to A19, D0 to D15, Retains status before wait mode -
_______ _______ ________
CS0 to CS3, BHE
______ _______ _________ _________
RD, WR, WRL, WRH “H”-
___________
HLDA, BCLK “H”-
ALE “H”-
I/O ports Retains status before wait mode Retains status before wait mode
CLKOUT - Does not stop
-•CM02 bit = 0: Does not stop
•CM02 bit = 1: Retains status before
wait mode
When fC selected
When f8, f32
selected
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Interrupt CM02 = 0 CM02 = 1
_______
NMI interrupt Can be used Can be used
Serial I/O interrupt Can be used when operating with Can be used when operating with
internal or external clock external clock
Key input interrupt Can be used Can be used
A-D conversion interrupt Can be used in one-shot mode or - (Do not use)
single sweep mode
Timer A interrupt Can be used in all modes Can be used in event counter mode
Timer B interrupt or when the count source is fc32
______
INT interrupt Can be used Can be used
CAN0/1 Wake-up interrupt
Can be used Can be used
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the
following before executing the WAIT instruction.
1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the peripheral
function interrupt to be used to exit wait mode.
Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0
bits to “0002” (interrupt disable).
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit wait mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt routine is executed.
The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU
clock that was on when the WAIT instruction was executed.
Table 1.8.5 Interrupts to Exit Wait Mode
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(3) Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least
amount of power is consumed in this mode. If the voltage applied to VCC is VRAM or more, the internal RAM
is retained.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.
______
• NMI interrupt
• Key interrupt
______
• INT interrupt
• Timer A, Timer B interrupt (when counting external pulses in event counter mode)
• Serial I/O interrupt (when external clock is selected)
• CAN0/1 Wake-up interrupt
• Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to “1” (all clocks
turned off). At the same time, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode) and the
CM15 bit of CM1 register is set to “1” (main clock oscillator circuit drive capability high).
Before entering stop mode, set the CM20 bit to “0” (oscillation stop, re-oscillation detection function
disabled).
Also, if the CM11 bit is “1” (PLL clock for the CPU clock source), set the CM11 bit to “0” (main clock for
the CPU clock source) and the PLC07 bit to “0” (PLL turned off) before entering stop mode.
• Pin Status During Stop Mode
Table 1.8.6 lists the pin status during stop mode.
Table 1.8.6 Pin Status During Stop Mode
Pin Memory expansion mode Single-chip mode
Microprocessor mode
A0 to A19, D0 to D15, Retains status before stop mode -
_______ _______ ________
CS0 to CS3, BHE
______ _______ _________ _________
RD, WR, WRL, WRH “H”-
___________
HLDA, BCLK “H”-
ALE “H”-
I/O ports Retains status before stop mode Retains status before stop mode
CLKOUT -“H”
- Retains status before stop mode
When fC selected
When f8, f32
selected
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This document is under development and its contents are subject to change.
• Exiting Stop Mode
______
The microcomputer is moved out of stop mode by a hardware reset, NMI interrupt or peripheral function
interrupt.
______
If the microcomputer is to be moved out of stop mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disable) before setting the
CM10 bit to “1”.
If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the
following before setting the CM10 bit to “1”.
1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the peripheral
function interrupt to be used to exit stop mode.
Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0
bits to “0002”.
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit stop mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt service routine is executed.
______
Which CPU clock will be used after exiting stop mode by a peripheral function or NMI interrupt is
determined by the CPU clock that was on when the microcomputer was placed into stop mode as
follows:
•If the CPU clock before entering stop mode was derived from the sub clock: sub clock
•If the CPU clock before entering stop mode was derived from the main clock: main clock divide-by-8
•If the CPU clock before entering stop mode was derived from the ring oscillator clock: ring oscillator
clock divide-by-8
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Figure 1.8.12 State Transition to Stop Mode and Wait Mode
Note 1: Do not go directly from PLL operation mode to wait or stop mode.
Note 2: PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high
speed mode.
Note 3: Write to the CM0 register and CM1 register simultaneously by accessing in word unit while CM21 = 0 (ring oscillator turned off).
Note 4: The ring oscillator clock divided by 8 provides the CPU clock.
Note 5: Before entering stop mode, be sure to set the CM20 bit in the CM2 register to "0" (oscillation stop, re-oscillation detection function
disabled).
CM05, CM06, CM07 : CM0 register’s bits
CM10, CM11 : CM1 register’s bits
Reset
Medium-speed mode
(divided-by-8 mode)
High-speed, medium-
speed mode
Wait mode
Interrupt
Interrupt
Normal mode
Low-speed, low power
dissipation mode
Interrupt
Wait mode
Interrupt
All oscillators stopped
Interrupt
Wait mode
WAIT
instruction
Interrupt
CPU operation stopped
When
low-
speed
mode
When
low power
dissipation
mode PLL operation
mode
(Notes 1, 2)
Ring oscillator, Ring oscillator
dissipation mode
Wait mode
Interrupt
WAIT
instruction
WAIT
instruction
WAIT
instruction
Stop mode
Stop mode
Stop mode
Stop mode
CM07=0
CM06=1
CM05=0
CM11=0
CM10=1
(Note 3)
CM10=1
(Note 5)
CM10=1
(Note 5)
CM10=1
(Note 5)
CM10=1
(Note 5)
Interrupt
(Note 4)
Figure 1.8.12 shows the state transition from normal operation mode to stop mode and wait mode. Figure
1.8.13 shows the state transition in normal operation mode.
Table 1.8.7 shows a state transition matrix describing allowed transition and setting. The vertical line shows
current state and horizontal line show state after transition.
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Figure 1.8.13 State Transition in Normal Operation Mode
CM04=0
CPU clock: f(PLL)
CM07=0
CM06=0
CM17=0
CM16=0
PLL operation mode
CM07=0
CM06=0
CM17=0
CM16=0
CM07=0
CM17=0
CM06=0
CM16=0
CM07=0
CM17=0
CM06=0
CM16=1
CM07=0
CM17=1
CM06=0
CM16=0
CM07=0
CM06=1
CM07=0
CM17=1
CM06=0
CM16=1
High-speed mode
CM07=0
CM17=0
CM06=0
CM16=0
CM07=0
CM17=0
CM06=0
CM16=1
CM07=0
CM17=1
CM06=0
CM16=0
CM07=0
CM06=1
CM07=0
CM17=1
CM06=0
CM16=1
CM07=1
Low-speed mode
CM07=1
Low power dissipation mode
CM06=1
CM15=1
Ring oscillator mode
CPU clock
Ring oscillator
mode
CPU clock
CPU clock
Ring oscillator
low power
dissipation mode
CPU clock
CM07=1
Low-speed mode
PLC07=1
CM11=1
(Note 6)
PLC07=0
CM11=0
(Note 7)
CM04=0
PLC07=1
CM11=1
PLC07=0
CM11=0
CM04=0CM04=1CM04=1 CM04=1 CM04=0CM04=1
CM07=0
(Notes 2, 4)
CM07=1
(Note 3)
CM05=1
(Notes 1, 9)
CM05=0
CM21=0
(Note 8)
CM21=1
CM21=0
(Note 8)
CM21=1
Main clock oscillation Ring oscillator clock
oscillation
Sub clock oscillation
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
PLL operation
mode
CPU clock: f(PLL) CPU clock: f(XIN)
High-speed mode Middle-speed mode
(divide by 2)
CPU clock: f(XIN)/2 CPU clock: f(XIN)/4 CPU clock: f(XIN)/8 CPU clock: f(XIN)/16
CPU clock: f(XCIN)
CPU clock: f(XCIN)
CPU clock: f(XCIN)
CM05=0
CM05=1
(Note 1)
CM05=1
(Note 1)
CM05=0
(Note 6)
(Note 7)
Middle-speed mode
(divide by 4)
Middle-speed mode
(divide by 8)
Middle-speed mode
(divide by 16)
Middle-speed mode
(divide by 2)
Middle-speed mode
(divide by 4)
Middle-speed mode
(divide by 8)
Middle-speed mode
(divide by 16)
CPU clock: f(XIN)
CPU clock: f(XIN)/2 CPU clock: f(XIN)/4 CPU clock: f(XIN)/8 CPU clock: f(XIN)/16
Ring oscillator low power
dissipation mode
Note 1: Avoid making a transition when the CM20 bit is set to "1" (oscillation stop, re-oscillation detection function enabled). Set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disabled)
before transiting.
Note 2: Wait for td(M-L) or the main clock oscillation stabilization time whichever is longer before switching over.
Note 3: Switch clock after oscillation of sub clock is sufficiently stable.
Note 4: Change CM17 and CM16 before changing CM06.
Note 5: Transit in accordance with arrow.
Note 6: PLL operation mode can only be entered from high speed mode. Also, wait until the PLL clock is sufficiently stable before changing operation modes. To select a 16 MHz or higher PLL clock, set the
PM20 bit to "0" (SFR accessed with two wait states) before setting PLC07 to "1" (PLL operation).
Note 7: PLL operation mode can only be changed to high speed mode. If the PM20 bit = 0 (SFR accessed with two wait states), set PLC07 to "0" (PLL turned off) before setting the PM20 bit to "1" (SFR
accessed with one wait state).
Note 8: Set the CM06 bit to "1" (division by 8 mode) before changing back the operation mode from ring oscillator mode to high- or middle-speed mode.
Note 9: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
CM04, CM05, CM06, CM07 : CM0 register’s bits
CM11, CM15, CM16, CM17 : CM1 register’s bits
CM20, CM21 : CM2 register’s bits
PLC07 : PLC0 register’s bit
CM21=0
CM21=1
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Table 1.8.7 Allowed Transition and Setting
State after transition
High-speed mode,
Low-speed Low power
PLL operation Ring oscillator
Ring oscillator
Stop Wait
middle-speed
mode
dissipation mode
mode mode
low power
mode mode
mode
(Note 2) (Note 2)
dissipation mode
High-speed mode, (Note 8) (9)
-
(13) (15)
-
(16) (17)
Middle-speed mode (Note 7) (Note 3) (Note 1)
Low-speed mode (8) (11)
---
(16) (17)
(Note 2)
(Notes 1, 6)
(Note 1)
Low power
-
(10)
---
(16) (17)
dissipation mode (Note 1)
PLL operation (12)
-- ----
mode (Note 2) (Note 3)
Ring oscillator (14)
---
(Note 8) (11) (16) (17)
mode (Note 4) (Note 1) (Note 1)
Ring oscillator low power
----
(10) (Note 8) (16) (17)
dissipation mode (Note 1)
Stop mode (18) (18) (18)
-
(18) (18)
-
(Note 5) (Note 5) (Note 5)
Wait mode (18) (18) (18)
-
(18) (18)
-
Current state
Sub clock oscillating Sub clock turned off
No
Divided Divided Divided Divided
No
Divided Divided Divided Divided
division
by 2 by 4 by 8 by 16
division
by 2 by 4 by 8 by 16
No division
(4) (5) (7) (6) (1)
----
Divided by 2
(3) (5) (7) (6)
-
(1)
---
Divided by 4
(3) (4) (7) (6)
--
(1)
--
Divided by 8
(3) (4) (5) (6)
---
(1)
-
Divided by 16
(3) (4) (5) (7)
----
(1)
No division
(2)
----
(4) (5) (7) (6)
Divided by 2
-
(2)
---
(3) (5) (7) (6)
Divided by 4
--
(2)
--
(3) (4) (7) (6)
Divided by 8
---
(2)
-
(3) (4) (5) (6)
Divided by 16
----
(2) (3) (4) (5) (7)
Sub clock oscillating
Sub clock turned off
Setting Operation
(1) CM04=0 Sub clock turned off
(2) CM04=1 Sub clock oscillating
(3) CM06=0 CPU clock no division
CM17=0 mode
CM16=0
(4) CM06=0
CPU clock division by 2
CM17=0 mode
CM16=1
(5) CM06=0
CPU clock division by 4
CM17=1 mode
CM16=0
(6) CM06=0
CPU clock division by 16
CM17=1 mode
CM16=1
(7) CM06=1
CPU clock division by 8 mode
(8) CM07=0 Main clock, PLL clock
or ring oscillator clock
selected
(9) CM07=1 Sub clock selected
(10)
CM05=0 Main clock oscillating
(11)
CM05=1 Main clock turned off
(12)
PLC07=0 Main clock selected
CM11=0
(13)
PLC07=1 PLL clock selected
CM11=1
(14)
CM21=0 Main clock or
PLL clock selected
(15)
CM21=1
Ring oscillator clock selected
(16)
CM10=1 Transition to stop mode
(17)
WAIT Transition to wait mode
instruction
(18)
Hardware Exit stop mode or wait
interrupt mode
-: Cannot transit
Note 1: Avoid making a transition when the CM20 bit = 1 (oscillation stop,
re-oscillation detection function enabled). Set the CM20 bit to “0” (oscillation
stop, re-oscillation detection function disabled) before transiting.
Note 2: Ring oscillator clock oscillates and stops in low-speed mode. In this mode,
the ring oscillator can be used as peripheral function clock. Sub clock
oscillates and stops in PLL operation mode. In this mode, sub clock can
be used as peripheral function clock.
Note 3: PLL operation mode can only be entered from and changed to high-speed
mode.
Note 4: Set the CM06 bit to “1” (division by 8 mode) before transiting from ring
oscillator mode to high- or middle-speed mode.
Note 5: When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).
Note 6: If the CM05 bit is set to “1” (main clock stop), then the CM06 bit is set to “1”
(division by 8 mode).
Note 7: A transition can be made only when sub clock is oscillating.
Note 8: State transitions within the same mode (divide-by-n values changed or
sub clock oscillation turned on or off) are shown in the table below.
CM04, CM05, CM06, CM07:CM0 register’s bits
CM10, CM11, CM16, CM17:CM1 register’s bits
CM20, CM21 :CM2 register’s bits
PLC07 :PLC0 register’s bit
Note 9: ( ):setting method. Refer to right table.
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Oscillation Stop and Re-oscillation Detection Function
The oscillation stop and re-oscillation detection function is such that main clock oscillation circuit stop
and re-oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-
oscillation detection interrupt are generated. Which one is to be generated can be selected using the CM27
bit of CM2 register.
The oscillation stop and re-oscillation detection function can be enabled or disabled using the CM20 bit of
CM2 register.
Table 1.8.8 lists a specification overview of the oscillation stop and re-oscillation detection function.
Table 1.8.8 Specification Overview of Oscillation Stop and Re-oscillation Detection Function
Item Specification
Oscillation stop detectable clock and f(XIN) ≥ 2 MHz
frequency bandwidth
Enabling condition for oscillation stop Set CM20 bit to “1” (enable)
and re-oscillation detection function
Operation at oscillation stop, •Reset occurs (when CM27 bit = 0)
re-oscillation detection •
Oscillation stop, re-oscillation detection interrupt occurs (when the CM27 bit =1)
(1) Operation When CM27 Bit = 0 (Oscillation Stop Detection Reset)
Where main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection
function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to “SFR”,
“Reset”).
This status is reset with hardware reset. Also, even when re-oscillation is detected, the microcomputer
can be initialized and stopped; it is, however, necessary to avoid such usage. (During main clock stop, do
not set the CM20 bit to “1” and the CM27 bit to “0”.)
(2)
Operation When CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt)
Where the main clock corresponds to the CPU clock source and the CM20 bit is “1” (oscillation stop, re-
oscillation detection function enabled), the system is placed in the following state if the main clock comes
to a halt:
• Oscillation stop, re-oscillation detection interrupt request occurs.
• The ring oscillator starts oscillation, and the ring oscillator clock becomes the clock source for CPU clock
and peripheral functions in place of the main clock.
• CM21 bit = 1 (ring oscillator clock is the clock source for CPU clock)
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
Where the PLL clock corresponds to the CPU clock source and the CM20 bit is “1”, the system is placed
in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to “1”
(ring oscillator clock) inside the interrupt routine.
• Oscillation stop, re-oscillation detection interrupt request occurs.
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
• CM21 bit remains unchanged
Where the CM20 bit is “1”, the system is placed in the following state if the main clock re-oscillates from
the stop condition:
• Oscillation stop, re-oscillation detection interrupt request occurs.
• CM22 bit = 1 (main clock re-oscillation detected)
• CM23 bit = 0 (main clock oscillation)
• CM21 bit remains unchanged
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How to Use Oscillation Stop and Re-oscillation Detection Function
•The oscillation stop, re-oscillation detection interrupt shares the vector with the watchdog timer interrupt. If
the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22
bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
•Where the main clock re-oscillated after oscillation stop, the clock source for CPU clock and peripheral
function must be switched to the main clock in the program. Figure 1.8.14 shows the procedure to
switch the clock source from the ring oscillator to the main clock.
•Simultaneously with oscillation stop, re-oscillation detection interrupt request occurrence, the
CM22 bit becomes “1”. When the CM22 bit is set at “1”, oscillation stop, re-oscillation detection inter-
rupt are disabled. By setting the CM22 bit to “0” in the program, oscillation stop, re-oscillation detection
interrupt are enabled.
•If the main clock stops during low speed mode where the CM20 bit is “1”, an oscillation stop, re-oscillation
detection interrupt request is generated. At the same time, the ring oscillator starts oscillating. In this
case, although the CPU clock is derived from the sub clock as it was before the interrupt occurred, the
peripheral function clocks now are derived from the ring oscillator clock.
•To enter wait mode while using the oscillation stop and re-oscillation detection function, set the CM02
bit to “0” (peripheral function clocks not turned off during wait mode).
•Since the oscillation stop and re-oscillation detection function is provided in preparation for main clock
stop due to external factors, set the CM20 bit to “0” (Oscillation stop, re-oscillation detection function
disabled) where the main clock is stopped or oscillated in the program, that is where the stop mode is
selected or the CM05 bit is altered.
•This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit
to “0”.
Figure 1.8.14 Procedure to Switch Clock Source from Ring Oscillator to Main Clock
Main clock switch
Inspect the CM23 bit
Do this check a number of times
Set the CM22 bit to "0" (main clock stop,
re-oscillation not detected).
Set the CM21 bit to "0"
(main clock for the CPU clock source) (Note)
1 (Main clock stop)
0 (Main clock oscillation)
The main clock is confirmed to be active a number of times.
CM21, CM22, CM 23 bits are the CM2 register bits
End
Note: If the clock source for CPU clock is to be changed to PLL clock, set to
PLL operation mode after set to high-speed mode.
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M16C/6N4 Group Protection
Under development
This document is under development and its contents are subject to change.
Protection
In the event that a program runs out of control, this function protects the important registers so that they will
not be rewritten easily. Figure 1.9.1 shows the PRCR register. The following lists the registers protected by
the PRCR register.
• Registers protected by the PRC0 bit: CM0, CM1, CM2, PLC0, PCLKR and CCLKR registers
• Registers protected by the PRC1 bit: PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers
• Registers protected by the PRC2 bit: PD7, PD9 and S3C registers
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be set to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction. The PRC0 and PRC1 bits are not automatically set
to “0” by writing to any address. They can only be set to “0” in a program.
Figure 1.9.1 PRCR Register
RW
RW
RW
RW
PRC1
PRC0
PRC2
Protect bit 1
Protect bit 0
Protect bit 2
Enable write to CM0, CM1, CM2,
PLC0, PCLKR, CCLKR
registers
0 : Write protected
1 : Write enabled
Enable write to PM0, PM1, PM2,
TB2SC, INVC0, INVC1
registers
0 : Write protected
1 : Write enabled
Enable write to PD7, PD9, S3C
registers
0 : Write protected
1 : Write enabled (Note)
Reserved bit Set to "0" RW
-
-
(b5-b3)
-
(b7-b6) Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
Protect register
Symbol Address After reset
PRCR 000A16 XX0000002
Bit nameBit symbol Function
Note: The PRC2 bit is set to "0" by writing to any address after setting it to "1". Other bits are not set to "0" by writing
to any address, and must therefore be set in a program.
00 0
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M16C/6N4 Group Interrupts
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This document is under development and its contents are subject to change.
Figure 1.10.1 Interrupts
• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Interrupt
Software
(Non-maskable interrupt)
Hardware
Special
(Non-maskable interrupt)
Peripheral function (Note 1)
(Maskable interrupt)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
_______
NMI
________
DBC (Note 2)
Oscillation stop and re-oscillation detection
Watchdog timer
Single step (Note 2)
Address match
Note 1: Peripheral function interrupts are generated by the microcomputer's internal functions.
Note 2: Do not normally use this interrupt because it is provided exclusively for use by development
support tools.
Interrupts
Type of Interrupts
Figure 1.10.1 shows the types of interrupts.
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Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the opera-
tion resulted in an overflow). The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63
can be specified for the INT instruction. Because software interrupt Nos. 1 to 31 are assigned to
peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be
executed by executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is
set to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack
when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not
change state during instruction execution, and the SP then selected is used.
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M16C/6N4 Group Interrupts
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Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
(1) Special Interrupts
Special interrupts are non-maskable interrupts.
_______
• NMI Interrupt
_______ _______
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details,
_______
refer to "NMI Interrupt".
________
• DBC Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
• Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize
the watchdog timer. For details about the watchdog timer, refer to "Watchdog Timer".
• Oscillation Stop and Re-oscillation Detection Interrupt
Generated by the oscillation stop and re-oscillation detection function. For details about the oscillation
stop and re-oscillation detection function, refer to "Clock Generation Circuit".
• Single-step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
• Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMAD0 to RMAD3 registers that corresponds to one of the AIER register’s AIER0 or
AIER1 bit or the AIER2 register’s AIER20 or AIER21 bit which is "1" (address match interrupt
enabled). For details, refer to "Address Match Interrupt".
(2) Peripheral Function Interrupts
Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt sources for peripheral function interrupts are listed in “Table 1.10.2
Relocatable Vector Tables”.
For details about the peripheral functions, refer to the description of each peripheral function in this
manual.
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Figure 1.10.2 Interrupt Vector
• Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 1.10.1 lists the
fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed
vectors are used by the ID code check function. For details, refer to "Functions to Prevent Flash
Memory from Rewriting".
Table 1.10.1 Fixed Vector Tables
Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 1.10.2 shows the interrupt vector.
Low address
Medium address
Vector address (L)
Vector address (H)
0 0 0 0
0 0 0 0 0 0 0 0
MSB LSB
High address
Interrupt source
Vector table addresses
Remarks Reference
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction M16C/60, M16C/20
Overflow FFFE016 to FFFE316 Interrupt on INTO instruction series software manual
BRK instruction FFFE416 to FFFE716
If the contents of address FFFE7
16
is FF16, program execution starts
from the address shown by the
vector in the relocatable vector table.
Address match FFFE816 to FFFEB16
Address match interrupt
Single step (Note) FFFEC16 to FFFEF16
Oscillation stop and FFFF016 to FFFF316
Clock generation circuit
re-oscillation detection,
Watchdog timer Watchdog timer
_________
DBC (Note) FFFF416 to FFFF716
________
NMI FFFF816 to FFFFB16
________
NMI interrupt
Reset FFFFC16 to FFFFF16 Reset
Note: Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
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Table 1.10.2 Relocatable Vector Tables
• Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector
table area. Table 1.10.2 lists the relocatable vector tables. Setting an even address in the INTB register
results in the interrupt sequence being executed faster than in the case of odd addresses.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
•
•
•
63
BRK instruction (Note 2)
CAN0/1 wake-up
CAN0 successful reception
CAN0 successful transmission
________
INT3
Timer B5
Timer B4, UART1 bus collision detection (Note 3. 9)
Timer B3, UART0 bus collision detection (Note 4, 9)
________
CAN1 successful reception, INT5 (Note 5)
________
SIO3, CAN1 successful transmission, INT4 (Note 6)
UART2 bus collision detection (Note 9)
DMA0
DMA1
CAN0/1 error
A-D, Key input (Note 7)
UART2 transmission, NACK2 (Note 8)
UART2 reception, ACK2 (Note 8)
UART0 transmission, NACK0 (Note 8)
UART0 reception, ACK0 (Note 8)
UART1 transmission, NACK1 (Note 8)
UART1 reception, ACK1 (Note 8)
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
________
INT0
________
INT1
________
INT2
Software interrupt (Note 2)
+0 to +3(000016 to 000316)
+4 to +7 (000416 to 000716)
+8 to +11 (000816 to 000B16)
+12 to +15 (000C16 to 000F16)
+16 to +19 (001016 to 001316)
+20 to +23 (001416 to 001716)
+24 to +27 (001816 to 001B16)
+28 to +31 (001C16 to 001F16)
+32 to +35 (002016 to 002316)
+36 to +39 (002416 to 002716)
+40 to +43 (002816 to 002B16)
+44 to +47 (002C16 to 002F16)
+48 to +51 (003016 to 003316)
+52 to +55 (003416 to 003716)
+56 to +59 (003816 to 003B16)
+60 to +63 (003C16 to 003F16)
+64 to +67 (004016 to 004316)
+68 to +71 (004416 to 004716)
+72 to +75 (004816 to 004B16)
+76 to +79 (004C16 to 004F16)
+80 to +83 (005016 to 005316)
+84 to +87 (005416 to 005716)
+88 to +91 (005816 to 005B16)
+92 to +95 (005C16 to 005F16)
+96 to +99 (006016 to 006316)
+100to +103 (006416 to 006716)
+104to +107 (006816 to 006B16)
+108to +111 (006C16 to 006F16)
+112to +115 (007016 to 007316)
+116to +119 (007416 to 007716)
+120to +123 (007816 to 007B16)
+124to +127 (007C16 to 007F16)
+128to +131 (008016 to 008316)
•
•
•
+252to +255 (00FC16 to 00FF16)
Software
interrupt number
M16C/60, M16C/20 series
software manual
CAN module
_______
INT interrupt
Timer
Timer, Serial I/O
_______
CAN module, INT interrupt
_______
Serial I/O, CAN module, INT interrupt
Serial I/O
DMAC
CAN module
A-D convertor, Key input interrupt
Serial I/O
Timer
_______
INT interrupt
M16C/60, M16C/20 series
software manual
Interrupt source Vector address (Note 1)
Address (L) to address (H) Reference
Note 1: Address relative to address in INTB.
Note 2: These interrupts cannot be disabled using the I flag.
Note 3: Use the IFSR0 register's IFSR07 bit to select.
Note 4: Use the IFSR0 register's IFSR06 bit to select.
Note 5: Use the IFSR1 register's IFSR17 bit to select.
Note 6: Use the IFSR1 register's IFSR16 bit to select.
Furthermore, use the IFSR0 register's IFSR00 bit to select, when selecting SI/O3 or CAN1 successful transmission.
Note 7: Use the IFSR0 register's IFSR01 bit to select.
Note 8: During I2C mode, NACK and ACK interrupts comprise the interrupt source.
Note 9: Bus collision detection: During IE mode, this bus collision detection constitutes the cause of an interrupt.
During I2C mode, a start condition or a stop condition detection constitutes the cause of
an interrupt.
Rev.1.00 2003.05.30 page 77
M16C/6N4 Group Interrupts
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This document is under development and its contents are subject to change.
Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which
order they are accepted. What is explained here does not apply to non-maskable interrupts.
Use the FLG register’s I flag, IPL, and each interrupt control register’s ILVL2 to ILVL0 bits to enable/disable
the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figures 1.10.3 and 1.10.4 show the interrupt control registers.
Figure 1.10.3 Interrupt Control Registers (1)
0041
16
0042
16
0043
16
0045
16
0046
16
0047
16
004A
16
004B
16
, 004C
16
004D
16
004E
16
0051
16
, 0053
16
, 004F
16
0052
16
, 0054
16
, 0050
16
0055
16
to 0059
16
005A
16
to 005C
16
Interrupt control register (Note 1)
C01WKIC
C0RECIC
C0TRMIC
TB5IC
TB4IC/U1BCNIC (Note 2)
TB3IC/U0BCNIC (Note 3)
U2BCNIC
DM0IC, DM1IC
C01ERRIC
ADIC/KUPIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
Note 1: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, refer to "Precautions for Interrupts" of the Usage Notes Reference Book.
Note 2: Use the IFSR07 bit of IFSR0 register to select.
Note 3: Use the IFSR06 bit of IFSR0 register to select.
Note 4: This bit can only be reset by writing "0" (Do not write "1").
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
RW
RW
RW
RW
(Note 4)
-
Interrupt request bit
Interrupt priority level
select bit
Bit name Function
Bit symbol
RW
ILVL0
IR
ILVL1
ILVL2
-
(b7-b4)
Symbol Address After reset
b7 b6 b5 b4 b3 b2 b1 b0
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M16C/6N4 Group Interrupts
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This document is under development and its contents are subject to change.
Figure 1.10.4 Interrupt Control Registers (2)
0044
16
0048
16
0049
16
005D
16
to 005F
16
Interrupt control register (Note 1)
INT3IC (Note 2)
C1RECIC/INT5IC
C1TRMIC/S3IC/INT4IC
INT0IC to INT2IC
XX00X000
2
XX00X000
2
XX00X000
2
XX00X000
2
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
RW
RW
RW
RW
RW
(Note 3)
-
Interrupt request bit
Interrupt priority level
select bit
Bit name FunctionBit symbol
RW
Symbol Address After reset
b7 b6 b5 b4 b3 b2 b1 b0
ILVL0
IR
0 : Selects falling edge (Notes 4, 5)
1 : Selects rising edge
ILVL1
ILVL2
-
(b7-b6)
Set to "0"
Polarity select bit
POL
Reserved bit
-
(b5)
RW
0
Note 1: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, refer to "Precautions for Interrupts" of the Usage Notes Reference Book.
Note 2: When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the
ILVL2 to ILVL0 bits in the INT5IC to INT3IC registers to "000
2
" (interrupt disabled).
Note 3: This bit can only be reset by writing "0" (Do not write "1").
Note 4: If the IFSR1 register’s IFSR1i bit (i = 0 to 5) is "1" (both edges), set the INTiIC register’s POL bit to "0" (falling edge).
Note 5: Set the S3IC register’s POL bit to "0" (falling edge) when the IFSR0 register’s IFSR00 bit = 1 and the IFSR1
register’s IFSR16 bit = 0 (SI/O3 selected).
Rev.1.00 2003.05.30 page 79
M16C/6N4 Group Interrupts
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This document is under development and its contents are subject to change.
I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the
maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts.
IR Bit
The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is set
to “0” (interrupt not requested).
The IR bit can be set to “0” in a program. Note that do not write “1” to this bit.
Table 1.10.4 Interrupt Priority Levels Enabled
by IPL
Table 1.10.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 1.10.3 shows the settings of interrupt priority levels and Table 1.10.4 shows the interrupt priority
levels enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = 1
· IR bit = 1
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
IPL Enabled interrupt priority levels
0002
Interrupt levels 1 and above are enabled
0012
Interrupt levels 2 and above are enabled
0102
Interrupt levels 3 and above are enabled
0112
Interrupt levels 5 and above are enabled
1002
Interrupt levels 5 and above are enabled
1012
Interrupt levels 6 and above are enabled
1102
Interrupt levels 7 and above are enabled
1112
All maskable interrupts are disabled
ILVL2 to ILVL0 bits
Interrupt priority level
Priority order
0002Level 0
(Interrupt disabled)
-
0012Level 1 Low
0102Level 2
0112Level 3
1002Level 4
1012Level 5
1102Level 6
1112Level 7 High
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M16C/6N4 Group Interrupts
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This document is under development and its contents are subject to change.
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the
processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 1.10.5 shows time required for
executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the
address 0000016. Then it set the IR bit for the corresponding interrupt to “0” (interrupt not requested).
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal
temporary register (Note).
(3) The I, D and U flags in the FLG register become as follows:
•The I flag = 0 (interrupts disabled).
•The D flag = 0 (single-step interrupt disabled).
•The U flag = 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(4) The CPU’s internal temporary register (Note) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
Note: This register cannot be used by user.
Figure 1.10.5 Time Required for Executing Interrupt Sequence
123456789 101112 13 14 15 16 17 18
SP-2
contents SP-4
contents vec
contents vec+2
contents
Interrupt
information
Address
0000
16
SP-2 SP-4 vec vec+2 PC
CPU clock
Address bus
Data bus
WR
RD
Note 1: The indeterminate state depends on the instruction queue buffer.
A read cycle occurs when the instruction queue buffer is ready to accept instructions.
Note 2: The WR signal timing shown here is for the case where the stack is located in the internal RAM.
Indeterminate (Note 1)
Indeterminate (Note 1)
Indeterminate (Note 1)
(Note 2)
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M16C/6N4 Group Interrupts
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This document is under development and its contents are subject to change.
Figure 1.10.6 Interrupt response time
Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 1.10.5 is set in the IPL. Table 1.10.5 shows the IPL values of software and special interrupts
when they are accepted.
Table 1.10.5 IPL Level that is Set to IPL When A Software or Special Interrupt is Accepted
Interrupt Response Time
Figure 1.10.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when
the instruction then executing is completed ((a) in Figure 1.10.6) and a time during which the interrupt
sequence is executed ((b) in Figure 1.10.6).
Interrupt sources Value set in the IPL
_______
Oscillation stop and re-oscillation detection, Watchdog timer, NMI
_________
Software, address match, DBC, single-step
Interrupt vector address SP value 16-bit bus, without wait 8-bit bus, without wait
Even
Odd
Even
Odd
Even
Odd
18 cycles
19 cycles
19 cycles
20 cycles
20 cycles
Instruction Interrupt sequence Instruction in
interrupt routine
Time
Interrupt response time
(a) (b)
Interrupt request acknowledgedInterrupt request generated
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
7
Not changed
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M16C/6N4 Group Interrupts
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Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
1.10.7 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Figure 1.10.7 Stack Status Before and After Acceptance of Interrupt Request
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP
(Note), at the time of acceptance of an interrupt request, is even or odd. If the SP (Note) is even, the FLG
register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure
1.10.8 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
m
-
4
m
-
3
m
-
2
m
-
1
m
m + 1
[SP]
SP value before
interrupt request
is accepted.
Stack status before interrupt request is acknowledged
Address
MSB LSB
Stack
m
-
4
m
-
3
m
-
2
m
-
1
m
m + 1
[SP]
New SP value
Stack status after interrupt request is acknowledged
Address
MSB LSB
Stack
PC
L
PC
M
FLG
L
Content of previous stack
Content of previous stack
Content of previous stack
Content of previous stack
FLG
H
PC
H
Figure 1.10.8 Operation of Saving Registers
[SP]
-
5 (Odd)
[SP]
-
4 (Even)
[SP]
-
3 (Odd)
[SP]
-
2 (Even)
[SP]
-
1 (Odd)
[SP]
(Even)
[SP]
-
5 (Even)
[SP]
-
4 (Odd)
[SP]
-
3 (Even)
[SP]
-
2 (Odd)
[SP]
-
1 (Even)
[SP]
(Odd)
(2)
Saved simultaneously,
all 16 bits
(1)
Saved simultaneously,
all 16 bits
Address Stack Sequence in which order
registers are saved
Sequence in which order
registers are saved
Address Stack
PC
L
PC
M
FLG
L
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
FLG
H
PC
H
PC
L
PC
M
FLG
L
FLG
H
PC
H
(1)SP contains even number (2)SP contains odd number
Finished saving registers
in two operations.
Finished saving registers
in four operations.
(3)
(4)
(1)
(2)
Saved,8 bits
at a time
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M16C/6N4 Group Interrupts
Under development
This document is under development and its contents are subject to change.
Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt
sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt
request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to
ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority
is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 1.10.9
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Figure 1.10.9 Hardware Interrupt Priority
Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 1.10.10 shows the circuit that judges the interrupt priority level.
Reset
Oscillation stop and re-oscillation detection
Watchdog timer
Peripheral function
Single step
Address match
High
Low
NMI
DBC
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M16C/6N4 Group Interrupts
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This document is under development and its contents are subject to change.
Figure 1.10.10 Interrupts Priority Select Circuit
Timer B2
Timer B0
Timer A3
Timer A1
Timer B1
Timer A4
UART1 transmission, NACK1
UART0 transmission, NACK0
A-D conversion, Key input
DMA1
UART2 bus collision detection
CAN0 successful reception
UART2 transmission, NACK2
CAN0/1 error
DMA0
SI/O3, CAN1 successful transmission, INT4
INT1
UART2 reception, ACK2
Level 0
(initial value)
Priority level of each interrupt Highest
Lowest
Priority of peripheral function interrupts
(if priority levels are same)
UART1 reception, ACK1
UART0 reception, ACK0
Timer A2
Timer A0
Timer B4, UART1 bus collision detection
Timer B3, UART0 bus collision detection
INT2
INT0
INT3
Timer B5
CAN0 successful transmission
CAN0/1 wake-up
Interrupt request level resolution output
to clock generation circuit (Figure 1.8.1)
Interrupt request accepted
IPL
I flag
Oscillation stop and re-oscillation detection
Watchdog timer
Address match
DBC
NMI
CAN1 successful reception, INT5
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M16C/6N4 Group Interrupts
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This document is under development and its contents are subject to change.
______
INT Interrupt
________
INTi interrupt (i = 0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSR1 register's IFSR1i bit.
________
INT4 share the interrupt vector and interrupt control register with SI/O3 and CAN1 successful transmission.
________
INT5 share the interrupt vector and interrupt control register with CAN1 successful reception. To use the
________ ________ ________
INT4 interrupt, set the IFSR1 register’s IFSR16 bit to “1” (INT4). To use the INT5 interrupt, set the IFSR1
________
register’s IFSR17 bit to “1” (INT5).
After modifying the IFSR16 or IFSR17 bit, set the corresponding IR bit to “0” (interrupt not requested)
before enabling the interrupt.
Figure 1.10.11 shows the IFSR0 register and IFSR1 register.
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Figure 1.10.11 IFSR0 Register and IFSR1 Register
0 : CAN0/1 wake-up error
1 : CAN0 wake-up error/
CAN1 wake-up error
0 : Timer B3
1 :
UART0 bus collision detection
0 : Timer B4
1 :
UART1 bus collision detection
IFSR00
IFSR01
Interrupt request cause select bit
Interrupt request cause select bit
IFSR02
-
(b5-b3)
Interrupt request cause select bit
IFSR06
IFSR07
Interrupt request cause select register 1
RW
Symbol Address After reset
IFSR1 01DF
16
0016
RW
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
0 :
SI/O3/CAN1 successful transmission
(Note 3)
1 : INT4
0 :
CAN1 successful reception
1 : INT5
0 : One edge
1 : Both edges (Note 1)
0 : One edge
1 : Both edges (Note 1)
0 : One edge
1 : Both edges (Note 1)
0 : One edge
1 : Both edges (Note 1)
0 : One edge
1 : Both edges (Note 1)
0 : One edge
1 : Both edges (Note 1)
IFSR10
Interrupt request cause select bit
(Note 2)
Interrupt request cause select bit
(Note 1)
Interrupt request cause select bit
(Note 2)
Interrupt request cause select bit
IFSR11
IFSR12
IFSR13
IFSR14
IFSR15
IFSR16
IFSR17
Interrupt request cause select register 0
Bit name Function
Bit symbol
Bit name Function
Bit symbol
RW
RW
RW
RW
-
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
0 :
CAN1 successful transmission
1 : SI/O3
0 : A-D conversion
1 : Key input
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
Symbol Address After reset
IFSR0 01DE
16
00XXX0002
INT0 interrupt polarity
switching bit
INT1 interrupt polarity
switching bit
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
INT4 interrupt polarity
switching bit
INT5 interrupt polarity
switching bit
Note 1: When setting this bit to "1" (both edges), make sure the INT0IC to INT5IC register’s POL bit is set
to "0" (falling edge).
Note 2: During memory expansion and microprocessor modes, set this bit to "0" (SI/O3, CAN1 successful
transmission).
Note 3: When setting this bit to "0" (SI/O3, CAN1 successful transmission), make sure the IFSR0 register’s
IFSR00 bit is set to "0" (CAN1 successful transmission) or "1" (SI/O3).
And, make sure the C1TRMIC register’s POL bit is set to "0" (falling edge).
Note 1: Timer B3 and UART0 bus collision detection share the vector and interrupt control register.
When using the timer B3 interrupt, set the IFSR06 bit in the IFSR0 register to "0" (timer B3).
When using UART0 bus collision detection, set the IFSR06 bit to "1" (UART0 bus collision detection).
Note 2: Timer B4 and UART1 bus collision detection share the vector and interrupt control register.
When using the timer B4 interrupt, set the IFSR07 bit in the IFSR0 register to "0" (timer B4).
When using UART1 bus collision detection, set the IFSR07 bit to "1" (UART1 bus collision detection).
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______
NMI Interrupt
_______ _______ ______
An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI
interrupt is a non-maskable interrupt.
_______
The input level of this NMI interrupt input pin can be read by accessing the P8 register’s P8_5 bit.
This pin cannot be used as an input port.
Key Input Interrupt
Of P104 to P107, a key input interrupt is generated when input on any of the P104 to P107 pins which has had
the PD10 register’s PD10_4 to PD10_7 bits set to “0” (input) goes low. Key input interrupts can be used as
a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode. However, if
you intend to use the key input interrupt, do not use P104 to P107 as analog input ports. Figure 1.10.12
shows the block diagram of the key input interrupt. Note, however, that while input on any pin which has had
the PD10_4 to PD10_7 bits set to “0” (input mode) is pulled low, inputs on all other pins of the port are not
detected as interrupts.
Figure 1.10.12 Key Input Interrupt Block Diagram
CAN0/1 Wake-up Interrupt
CAN0/1 wake-up interrupt is occurs when a falling edge is input to CRx0 or CRx1. Use the interrupt in stop/wait
mode or CAN sleep mode. The CAN0/1 wake-up interrupt is enabled only when the port is defined as the CAN port.
One interrupt is allocated to CAN0/1. Figure 1.10.13 shows the block diagram of the CAN0/1 wake-up interrupt.
Please note that the wake-up message will be lost.
Figure 1.10.13 CAN0/1 Wake-up Interrupt Block Diagram
CRX1
Interrupt control
circuit
C01WKIC register
CAN0/1 wake-up
interrupt request
C0CTLR register’s PortEn bit
C1CTLR register’s PortEn bit
CRX0
Interrupt control circuit
KUPIC register
Key input interrupt
request
KI
3
KI
2
KI
1
KI
0
PUR2 register’s PU25 bit
PD10 register’s
PD10_7 bit
Pull-up
transistor
PD10 register’s PD10_7 bit
PD10 register’s
PD10_6 bit
PD10 register’s
PD10_5 bit
PD10 register’s
PD10_4 bit
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
Rev.1.00 2003.05.30 page 88
M16C/6N4 Group Interrupts
Under development
This document is under development and its contents are subject to change.
Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the
address indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi
register. Use the AIER register’s AIER0 and AIER1 bits and the AIER2 register’s AIER20 and AIER21 bits
to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
For address match interrupts, the value of the PC that is saved to the stack area varies depending on the
instruction being executed (refer to “Saving Registers”). (The value of the PC that is saved to the stack area
is not the correct return address.) Therefore, follow one of the methods described below to return from the
address match interrupt.
•Rewrite the content of the stack and then use the REIT instruction to return.
•Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 1.10.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Note that when using the external bus in 8-bit width, no address match interrupts can be used for external
areas. Table 1.10.7 shows the relationship between address match interrupt sources and associated registers.
Figure 1.10.14 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.
Table 1.10.6
Value of PC That is Saved to Stack Area When Address Match Interrupt Request is Accepted
Address match interrupt sources
Address match interrupt enable bit Address match interrupt register
Address match interrupt 0 AIER0 RMAD0
Address match interrupt 1 AIER1 RMAD1
Address match interrupt 2 AIER20 RMAD2
Address match interrupt 3 AIER21 RMAD3
Instruction at address indicated by RMADi register
• 16-bit operation code
• Instruction shown below among 8-bit operation code instructions
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest
STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest PUSHM src POPM dest
JMPS #IMM8 JSRS #IMM8
MOV.B:S #IMM,dest (However, dest = A0 or A1)
• Instructions other than the above
Value of PC that is saved to stack area: Refer to “Saving Registers”.
Table 1.10.7 Relationship Between Address Match Interrupt Sources and Associated Registers
Value at PC that is saved to stack area
• Address indicated by RMADi
register + 2
• Address indicated by RMADi
register + 1
Rev.1.00 2003.05.30 page 89
M16C/6N4 Group Interrupts
Under development
This document is under development and its contents are subject to change.
Figure 1.10.14 AIER Register, AIER2 Register and RMAD0 to RMAD3 Registers
RW
-
Address match interrupt enable register
Address match interrupt 0
enable bit
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Symbol Address After reset
AIER 0009
16
XXXXXX00
2
AIER0
AIER1
-
(b7-b2)
RW
Bit name Function
Bit symbol RW
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
RW
-
Address match interrupt enable register 2
Address match interrupt 2
enable bit
Address match interrupt 3
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Symbol Address After reset
AIER2 01BB
16
XXXXXX00
2
AIER20
AIER21
-
(b7-b2)
RW
Bit name Function
Bit symbol RW
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
RW
-
-
(b19-b0)
-
(b23-b20)
Bit symbol
AddressSymbol After reset
0012
16
to 0010
16
0016
16
to 0014
16
01BA
16
to 01B8
16
01BE
16
to 01BC
16
RMAD0
RMAD1
RMAD2
RMAD3
X00000
16
X00000
16
X00000
16
X00000
16
Function Setting range RW
Address setting register for address
match interrupt
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
Address match interrupt register i (i = 0 to 3)
00000
16
to FFFFF
16
b0 b7 b0b3
(b19) (b16)
b7 b0
(b15) (b8)
b7
(b23)
Rev.1.00 2003.05.30 page 90
M16C/6N4 Group Watchdog Timer
Under development
This document is under development and its contents are subject to change.
Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend
using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter
which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a
watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the
watchdog timer underflows after reaching the terminal count can be selected using the PM12 bit of PM1
register. The PM12 bit can only be set to “1” (watchdog timer reset). Once this bit is set to “1”, it cannot be
set to “0” (watchdog timer interrupt) in a program. Refer to “Watchdog Timer Reset” for details about watchdog
timer reset.
When the main clock is selected for CPU clock, ring oscillator clock, PLL clock, the divide-by-n value for the
prescaler can be selected to be 16 or 128. If a sub clock is selected for CPU clock, the divide-by-n value for
the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calcu-
lated as given below. The period of watchdog timer is, however, subject to an error due to the prescaler.
For example, when CPU clock = 16 MHz and the divide-by-n value for the prescaler = 16, the watchdog timer
period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is
resumed from the held value when the modes or state are released.
Figure 1.11.1 shows the block diagram of the watchdog timer. Figure 1.11.2 shows the watchdog timer-
related registers.
• Count source protective mode
In this mode, a ring oscillator clock is used for the watchdog timer count source. The watchdog timer can
be kept being clocked even when CPU clock stops as a result of runaway.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit of the PRCR register to “1” (enable writes to the PM1 and PM2 registers).
(2) Set the PM12 bit of the PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit of the PM2 register to “1” (ring oscillator clock used for the watchdog timer count source).
(4) Set the PRC1 bit of the PRCR register to “0” (disable writes to the PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
With main clock selected for CPU clock, ring oscillator clock, PLL clock
Watchdog timer period =
Prescaler dividing (16 or 128) ✕ Watchdog timer count (32768)
CPU clock
With sub clock selected for CPU clock
Watchdog timer period =
Prescaler dividing (2) ✕ Watchdog timer count (32768)
CPU clock
Rev.1.00 2003.05.30 page 91
M16C/6N4 Group Watchdog Timer
Under development
This document is under development and its contents are subject to change.
Figure 1.11.2 WDC Register and WDTS Register
Figure 1.11.1 Watchdog Timer Block Diagram
Setting the PM22 bit to “1” results in the following conditions:
• The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source.
• The CM10 bit of the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode entered.)
• The watchdog timer does not stop when in wait mode or hold state.
CPU
clock
Write to WDTS register
RESET
PM12 = 0
Watchdog timer
Set to
"7FFF16"
1/128
1/16
CM07 = 0
WDC7 = 1
CM07 = 0
WDC7 = 0
CM07 = 1
HOLD
1/2
Prescaler
PM12 = 1
Watchdog timer
interrupt request
Watchdog timer
Reset
PM22 = 0
PM22 = 1
Ring oscillator clock
High-order bit of watchdog timer
Prescaler select bit 0 : Divided by 16
1 : Divided by 128
Reserved bit Set to "0"
WDC7
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
00
RW
RO
RW
RW
-
(b4-b0)
-
(b6-b5)
FunctionBit symbol Bit name
Symbol Address After reset
WDC 000F16 00XXXXXX2
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to "7FFF16" regardless
of whatever value is written.
Watchdog timer start register (Note)
Symbol Address After reset
WDTS 000E16 Indeterminate
Function RW
b7 b0
WO
Note: Write to the WDTS register after the watchdog timer interrupt occurs.
Watchdog timer count (32768)
ring oscillator clock
Watchdog timer period =
Rev.1.00 2003.05.30 page 92
M16C/6N4 Group DMAC
Under development
This document is under development and its contents are subject to change.
DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit)
data from the source address to the destination address. The DMAC uses the same data bus as used by
the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of
a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time
after a DMA request is generated. Figure 1.12.1 shows the block diagram of the DMAC. Table 1.12.1
shows the DMAC specifications. Figures 1.12.2 to 1.12.4 show the DMAC related-registers.
Figure 1.12.1 DMAC Block Diagram
A DMA request is generated by a write to the DSR bit of the DMiSL register (i = 0, 1), as well as by an
interrupt request which is generated by any function specified by the DMS and DSEL3 to DSEL0 bits of the
DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I
flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt
request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not
affect interrupts, the IR bit of the interrupt control register does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMAE bit = 1 (DMA enabled) of
the DMiCON register. However, if the cycle in which a DMA request is generated is faster than the DMA
transfer cycle, the number of transfer requests generated and the number of times data is transferred may
not match. For details, refer to “DMA Requests”.
Data bus low-order bits
DMA latch high-order bits DMA latch low-order bits
DMA0 source pointer SAR0(20)
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20) (Note)
Data bus high-order bits
Address bus
DMA1 destination pointer DAR1 (20)
DMA1 source pointer SAR1 (20)
DMA1 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
(addresses 0029
16
, 0028
16
)
(addresses 0039
16
, 0038
16
)
(addresses 0022
16
to 0020
16
)
(addresses 0026
16
to 0024
16
)
(addresses 0032
16
to 0030
16
)
(addresses 0036
16
to 0034
16
)
Note: Pointer is incremented by a DMA request.
Rev.1.00 2003.05.30 page 93
M16C/6N4 Group DMAC
Under development
This document is under development and its contents are subject to change.
Item Specification
No. of channels 2 (cycle steal method)
Transfer memory space •From any address in the 1 Mbyte space to a fixed address
•From a fixed address to any address in the 1 Mbyte space
•From a fixed address to a fixed address
Maximum No. of bytes transferred
128 Kbytes (with 16-bit transfer) or 64 Kbytes (with 8-bit transfer)
DMA request factors
________ ________
Falling edge of INT0 or INT1
(Notes 1, 2)
________ ________
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3 interrupt request
A-D conversion interrupt requests
Software triggers
Channel priority DMA0 > DMA1 (DMA0 takes precedence)
Transfer unit 8 bits or 16 bits
Transfer address direction forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer mode Single transfer Transfer is completed when the DMAi transfer counter underflows
after reaching the terminal count.
Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is
continued with it.
DMA interrupt request generation timing
When the DMAi transfer counter underflowed
DMA start-up Data transfer is initiated each time a DMA request is generated when the
DMAiCON register’s DMAE bit = 1 (enabled).
DMA shutdown
Single transfer •When the DMAE bit is set to “0” (disabled)
•After the DMAi transfer counter underflows
Repeat transfer When the DMAE bit is set to “0” (disabled)
When a data transfer is started after setting the DMAE bit to “1” (enabled),
the forward address pointer is reloaded with the value of the SARi or the
DARi pointer whichever is specified to be in the forward direction and the
DMAi transfer counter is reloaded with the value of the DMAi transfer
counter reload register.
Table 1.12.1 DMAC Specifications
i = 0, 1
Note 1: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
Note 2: The selectable causes of DMA requests differ with each channel.
Note 3: Make sure that no DMAC-related registers (addresses 002016 to 003F16) are accessed by the DMAC.
Reload timing for forward
address pointer and transfer
counter
Rev.1.00 2003.05.30 page 94
M16C/6N4 Group DMAC
Under development
This document is under development and its contents are subject to change.
Figure 1.12.2 DM0SL Register
DMA0 request cause select register
Symbol Address After reset
DM0SL 03B816 0016
DSEL0
DSEL1
DSEL2
DSEL3
DSR
DMS
-
(b5-b4)
FunctionBit symbol Bit name
DMA request cause
select bit
Nothing is assigned. When write, set to "0".
When read, its content is "0".
Software DMA
request bit
A DMA request is generated by setting
this bit to "1" when the DMS bit is "0"
(basic cause) and the DSEL3 to DSEL0
bits are "0001
2
" (software trigger).
The value of this bit when read is "0".
DMA request cause
expansion select bit
0 : Basic cause of request
1 : Extended cause of request
Refer to note
RW
RW
RW
RW
-
RW
RW
RW
Note: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0 DMS = 0 (basic cause of request) DMS = 1 (extended cause of request)
0 0 0 0
2
Falling edge of INT0 pin —
0 0 0 1
2
Software trigger —
0 0 1 0
2
Timer A0 —
0 0 1 1
2
Timer A1 —
0 1 0 0
2
Timer A2 —
0 1 0 1
2
Timer A3 —
0 1 1 0
2
Timer A4 Two edges of INT0 pin
0 1 1 1
2
Timer B0 Timer B3
1 0 0 0
2
Timer B1 Timer B4
1 0 0 1
2
Timer B2 Timer B5
1 0 1 0
2
UART0 transmit —
1 0 1 1
2
UART0 receive —
1 1 0 0
2
UART2 transmit —
1 1 0 1
2
UART2 receive —
1 1 1 0
2
A-D conversion —
1 1 1 1
2
UART1 transmit —
b7 b6 b5 b4 b3 b2 b1 b0
Rev.1.00 2003.05.30 page 95
M16C/6N4 Group DMAC
Under development
This document is under development and its contents are subject to change.
Figure 1.12.3 DM1SL Register, DM0CON Register and DM1CON Register
DMA1 request cause select register
Symbol Address After reset
DM1SL 03BA16 0016
DSEL0
DSEL1
DSEL2
DSEL3
DSR
DMS
-
(b5-b4)
FunctionBit symbol Bit name
DMA request cause
select bit
Nothing is assigned. When write, set to "0".
When read, its content is "0".
Software DMA
request bit
A DMA request is generated by setting
this bit to "1" when the DMS bit is "0"
(basic cause) and the DSEL3 to DSEL0
bits are "0001
2
" (software trigger).
The value of this bit when read is "0".
DMA request cause
expansion select bit
0 : Basic cause of request
1 : Extended cause of request
Refer to note
RW
RW
RW
RW
-
RW
RW
RW
Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0 DMS = 0 (basic cause of request) DMS = 1 (extended cause of request)
0 0 0 0
2
Falling edge of INT1 pin —
0 0 0 1
2
Software trigger —
0 0 1 0
2
Timer A0 —
0 0 1 1
2
Timer A1 —
0 1 0 0
2
Timer A2 —
0 1 0 1
2
Timer A3 SI/O3
0 1 1 0
2
Timer A4
0 1 1 1
2
Timer B0 Two edges of INT1 pin
1 0 0 0
2
Timer B1
1 0 0 1
2
Timer B2
1 0 1 0
2
UART0 transmit —
—
—
—
1 0 1 1
2
UART0 receive/ACK0 —
1 1 0 0
2
UART2 transmit —
1 1 0 1
2
UART2 receive/ACK2 —
1 1 1 0
2
A-D conversion —
1 1 1 1
2
UART1 transmit/ACK1 —
b7 b6 b5 b4 b3 b2 b1 b0
DMAi control register (i = 0, 1)
DMBIT
DMASL
DMAS
DAD
DSD
-
(b7-b6)
FunctionBit symbol Bit name
Transfer unit bit
select bit
Nothing is assigned. When write, set to "0".
When read, its content is "0".
Destination address
direction select bit (Note 2)
Source address direction
select bit (Note 2)
0 : 16 bits
1 : 8 bits RW
RW
RW
(Note 1)
RW
-
RW
RW
RW
Note 1: The DMAS bit can be set to "0" by writing "0" in a program. (This bit remains unchanged even if "1" is written.)
Note 2: At least one of the DAD and DSD bits must be "0" (address direction fixed).
b7 b6 b5 b4 b3 b2 b1 b0
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMA request bit
DMAE DMA enable bit
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
0 : Fixed
1 : Forward
Symbol Address After reset
DM0CON 002C16 00000X002
DM1CON 003C16 00000X002
Rev.1.00 2003.05.30 page 96
M16C/6N4 Group DMAC
Under development
This document is under development and its contents are subject to change.
Figure 1.12.4 SAR0, SAR1, DAR0, DAR1, TCR0 and TCR1 Registers
AddressSymbol After reset
0022
16
to 0020
16
0032
16
to 0030
16
SAR0
SAR1
Indeterminate
Indeterminate
Setting range RW
RW
-
00000
16
to FFFFF
16
b0 b7 b0b3
(b19) (b16)
b7 b0
(b15) (b8)
b7
(b23)
DMAi source pointer (i = 0, 1) (Note)
Note: If the DSD bit of the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit of the
DMiCON register is "0" (DMA disabled).
If the DSD bit is "1" (forward direction), this register can be written to at any time.
If the DSD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
AddressSymbol After reset
0026
16
to 0024
16
0036
16
to 0034
16
DAR0
DAR1
Indeterminate
Indeterminate
Setting range RW
RW
-
00000
16
to FFFFF
16
b0 b7 b0b3
(b19) (b16)
b7 b0
(b15) (b8)
b7
(b23)
DMAi destination pointer (i = 0, 1) (Note)
Note: If the DAD bit of the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit of the
DMiCON register is "0" (DMA disabled).
If the DAD bit is "1" (forward direction), this register can be written to at any time.
If the DAD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi transfer counter (i = 0, 1)
AddressSymbol After reset
0029
16
, 0028
16
0039
16
, 0038
16
TCR0
TCR1
Indeterminate
Indeterminate
b0 b7
(b8)
b0b7
(b15)
Setting range RW
RW
00000
16
to FFFFF
16
Function
Set the destination address of transfer
Nothing is assigned. When write, set to "0".
When read, these contents are "0".
Nothing is assigned. When write, set to "0".
When read, these contents are "0".
Set the source address of transfer
Function
Set the transfer count minus 1.
The written value is stored in the DMAi transfer counter
reload register, and when the DMAE bit of the DMiCON
register is set to "1" (DMA enabled) or the DMAi transfer
counter underflows when the DMASL bit of the DMiCON
register is "1" (repeat transfer), the value of the DMAi
transfer counter reload register is transferred to the DMAi
transfer counter.
When read, the DMAi transfer counter is read.
Function
Rev.1.00 2003.05.30 page 97
M16C/6N4 Group DMAC
Under development
This document is under development and its contents are subject to change.
1. Transfer Cycle
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination
write) bus cycle. The number of read and write bus cycles is affected by the source and destination
addresses of transfer. During memory expansion and microprocessor modes, it is also affected by the
________
BYTE pin level. Furthermore, the bus cycle itself is extended by a software wait or RDY signal.
(a) Effect of Source and Destination Addresses
If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd
address, the source read cycle consists of one more bus cycle than when the source address of
transfer begins with an even address.
Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer
begins with an odd address, the destination write cycle consists of one more bus cycle than when the
destination address of transfer begins with an even address.
(b) Effect of BYTE Pin Level
During memory expansion and microprocessor modes, if 16 bits of data are to be transferred on an 8-
bit data bus (input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data
twice. Therefore, this operation requires two bus cycles to read data and two bus cycles to write data.
Furthermore, if the DMAC is to access the internal area (internal ROM, internal RAM, or SFR), unlike
in the case of the CPU, the DMAC does it through the data bus width selected by the BYTE pin.
(c) Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of
bus cycles required for that access increases by an amount equal to software wait states.
_______
(d) Effect of RDY Signal
During memory expansion and microprocessor modes, DMA transfers to and from an external area
________ ________
are affected by the RDY signal. Refer to “RDY Signal”.
Figure 1.12.5 shows the example of the cycles for a source read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality,
the destination write cycle is subject to the same conditions as the source read cycle, with the transfer
cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for
the source read and the destination write cycle, respectively. For example, when data is transferred in 16-
bit unit using an 8-bit bus ((2) in Figure 1.12.5), two source read bus cycles and two destination write bus
cycles are required.
Rev.1.00 2003.05.30 page 98
M16C/6N4 Group DMAC
Under development
This document is under development and its contents are subject to change.
Figure 1.12.5 Transfer Cycles for Source Read
Note: The same timing changes occur with the respective conditions at the destination as at the source.
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU use
Source
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
Rev.1.00 2003.05.30 page 99
M16C/6N4 Group DMAC
Under development
This document is under development and its contents are subject to change.
2. DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible.
Table 1.12.2 shows the number of DMA transfer cycles. Table 1.12.3 shows the coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles ✕ j + No. of write cycles ✕ k
Table 1.12.2 DMA Transfer Cycles
Table 1.12.3 Coefficient j, k
Single-chip mode Memory expansion mode
Transfer unit Bus width Access address
Microprocessor mode
No. of read No. of write No. of read No. of write
cycles cycles cycles cycles
16 bits Even 1111
8-bit transfer (BYTE = L) Odd 1111
(DMBIT =1) 8 bits Even
--
11
(BYTE= H) Odd
-
-11
16 bits Even 1111
16-bit transfer (BYTE =L) Odd 2222
(DMBIT = 0) 8 bits Even
--
22
(BYTE = H) Odd
--
22
Internal area External area
Internal ROM, RAM
SFR Separate bus Multiplexed bus
No wait
With wait
1 wait 2 waits No wait With wait (Note 2) With wait (Note 2)
(Note 1) (Note 1) 1 wait 2 waits 3 waits 1 wait 2 waits 3 waits
j122312 34334
k122322 34334
Note 1: Depends on the set value of the PM20 bit of the PM2 register.
Note 2: Depends on the set value of the CSE register.
Rev.1.00 2003.05.30 page 100
M16C/6N4 Group DMAC
Under development
This document is under development and its contents are subject to change.
3. DMA Enable
When a data transfer starts after setting the DMAE bit of the DMiCON register (i = 0, 1) to “1” (enabled),
the DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit of the DMiCON
register is “1” (forward) or the DARi register value when the DAD bit of the DMiCON register is “1” (forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation.
However, if a DMA request may occur simultaneously when the DMAE bit is being written, follow the
steps below.
Step 1: Write “1” to the DMAE bit and DMAS bit of the DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
4. DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the
DMS and DSEL3 to DSEL0 bits of the DMiSL register (i = 0, 1) on either channel. Table 1.12.4 shows the
timing at which the DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether
or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is
set to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in
a program (it can only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,
always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.
Table 1.12.4 Timing at Which DMAS bit Changes State
i = 0, 1
DMA factor DMAS bit of DMiCON register
Timing at which the bit is set to “1” Timing at which the bit is set to “0”
Software trigger When the DSR bit of the DMiSL register • Immediately before a data transfer starts
is set to “1”• When set by writing “0” in a program
Peripheral function When the interrupt control register for
the peripheral function that is selected
by the DSEL3 to DSEL0 and DMS bits
of the DMiSL register has its IR bit set to “1”.
Rev.1.00 2003.05.30 page 101
M16C/6N4 Group DMAC
Under development
This document is under development and its contents are subject to change.
5. Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are
detected active in the same sampling period (one period from a falling edge to the next falling edge of
BCLK), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the
DMA requests are arbitrated according to the channel priority, DMA0 > DMA1.
The following describes DMAC operation when DMA0 and DMA1 requests are detected active in the
same sampling period.
Figure 1.12.6 shows an example of DMA transfer effected by external factors.
In Figure 1.12.6, DMA0 request having priority is received first to start a transfer when a DMA0 request
and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, a bus arbitra-
tion is returned to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After
one DMA1 transfer is completed, the bus arbitration is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when
DMA requests, as DMA1 in Figure 1.12.6, occurs more than one time, the DMAS bit is set to “0” as soon
as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
__________
Refer to “(7) HOLD Signal in Bus Control” for details about bus arbitration between the CPU and DMA.
Figure 1.12.6 DMA Transfer by External Factors
An example where DMA requests for external causes are detected active at the same time,
a DMA transfer is executed in the shortest cycle.
BCLK
DMA0
DMA1
DMA0
request bit
DMA1
request bit
CPU
INT0
INT1
Bus arbitration
Rev.1.00 2003.05.30 page 102
M16C/6N4 Group Timers
Under development
This document is under development and its contents are subject to change.
Timers
Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function
as either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such
timer operations as counting, reloading, etc.
Figures 1.13.1 and 1.13.2 show block diagrams of timer A and timer B configuration, respectively.
Timer mode
One-shot timer mod e
Pulse Width Measuring (PWM) mode
Timer mode
One-shot timer mod e
PWM mode
Timer mode
One-shot timer mod e
PWM mode
Timer mod e
One-shot timer mod e
PWM mode
Timer mode
One-shot timer mod e
PWM mode
Event counter mod e
Event counter mod e
Event counter mod e
Event counter mod e
Event counter mod e
TA0IN
TA1IN
TA2IN
TA3IN
TA4IN
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
f8 f32 fC32
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
1/32 fC32
1/8
1/4
f1 or f2
f8
f32
XCIN
Set the CPSR bit of CPSRF
register to "1" (= prescaler
reset)
Reset
Clock prescaler
Timer B2 overflow or underflow
Note: Be aware that TA0
IN
shares the pin with RxD
2
, SCL
2
and TB5
IN
.
1/2
f1
f2PCLK0 bit = 0
PCLK0 bit = 1
f1 or f2
Main clock
PLL clock
Ring oscillator
clock
Figure 1.13.1 Timer A Configuration
Rev.1.00 2003.05.30 page 103
M16C/6N4 Group Timers
Under development
This document is under development and its contents are subject to change.
Figure 1.13.2 Timer B Configuration
TB0IN
TB1IN
TB2IN
Timer B0
Timer B1
Timer B2
f8 f32 fC32
Timer B0 interrupt
Noise
filter
Noise
filter
Noise
filter
1/32 f
C32
XCIN
Reset
Clock prescaler
Timer B2 overflow or underflow (to Timer A count source)
TB3IN
TB4IN
TB5IN
Timer B3
Timer B4
Timer B5
Timer B3 interrupt
Noise
filter
Noise
filter
Noise
filter
Timer B1 interrupt
Timer B2 interrupt
Timer B4 interrupt
Timer B5 interrupt
1/8
1/4
f
8
f32
1/2 f1 or f2
Main clock
PLL clock
Ring oscillator
clock Set the CPSR bit of CPSRF
register to "1" (= prescaler
reset)
f1
f2PCLK0 bit = 0
PCLK0 bit = 1
f1 or f2
Note: Be aware that TB5
IN shares the pin with RxD2, SCL2 and TA0IN.
Event counter mode
Timer mode
Pulse width measuring mode,
pulse period measuring mode
Event counter mode
Timer mode
Pulse width measuring mode,
pulse period measuring mode
Event counter mode
Timer mode
Pulse width measuring mode,
pulse period measuring mode
Event counter mode
Timer mode
Pulse width measuring mode,
pulse period measuring mode
Event counter mode
Timer mode
Pulse width measuring mode,
pulse period measuring mode
Event counter mode
Timer mode
Pulse width measuring mode,
pulse period measuring mode
Rev.1.00 2003.05.30 page 104
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Timer A
Figure 1.13.3 shows a block diagram of the timer A. Figures 1.13.4 to 1.13.6 show the timer A-related
registers.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows and underflows of other timers.
• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count “000016.”
• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.
TABSR register
Up-count/down-count
TAi Addresses TAj TAk
Timer A0 038716 038616 Timer A4 Timer A1
Timer A1 038916 038816 Timer A0 Timer A2
Timer A2 038B16 038A16 Timer A1 Timer A3
Timer A3 038D16 038C16 Timer A2 Timer A4
Timer A4 038F16 038E16 Timer A3 Timer A0
Always counts down except
in event counter mode
Reload register
Counter
Low-order
8 bits
High-order
8 bits
Clock source
selection
f1 or f2
f8
f32
TAiIN
TB2 overflow
fC32
Clock selection
TAj overflow
Pulse output
Toggle flip-flop
TAiOUT
Data bus low-order bits
Data bus high-order bits
UDF register
Down count
TAk overflow
Polarity
selection
To external
trigger circuit
(Note)
(Note)
Clock selection
Timer mode
(gate function)
Timer mode
One shot mode
PWM mode
Event counter mode
i = 0 to 4
j = i
—
1. Note, however, that j = 4 when i = 0
k = i + 1. Note, however, that k = 0 when i = 4
Note: Overflow or underflow
-
-
-
-
-
Figure 1.13.3 Timer A Block Diagram
Rev.1.00 2003.05.30 page 105
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Figure 1.13.4 TA0MR to TA4MR Registers and TA0 to TA4 Registers
Timer Ai mode register (i = 0 to 4)
TA0MR to TA4MR 039616 to 039A16 0016
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each
operation mode
Count source select bit
Operation mode select bit
RW
RW
RW
RW
RW
RW
RW
RW
Function varies with each
operation mode
Symbol Address After reset
Symbol Address After reset
TA0 0387
16
, 0386
16
Indeterminate
TA1 0389
16
, 0388
16
Indeterminate
TA2 038B
16
, 038A
16
Indeterminate
TA3 038D
16
, 038C
16
Indeterminate
TA4 038F
16
, 038E
16
b7 b0 b7 b0
(b15) (b8)
Timer Ai register (i = 0 to 4) (Note 1)
RW
Divide the count source by n + 1 where n =
set value
Function Setting range
Divide the count source by n where n = set
value and cause the timer to sto p
Modify the pulse width as follows:
PWM period: (2
16
—
1) / fj
High level PWM pulse width: n / fj
where n = set value, fj = count source
frequency
0000
16
to FFFE
16
(Note 4, 5)
Note 1: The register must be accessed in 16-bit unit.
Note 2: The timer counts pulses from an external device or overflows or underflows in other timers.
Note 3: If the TAi register is set to "000016", the counter does not work and timer Ai interrupt requests
are not generated either. Furthermore, if "pulse output" is selected, no pulses are output from
the TAiOUT pin.
Note 4: Use the MOV instruction to write to the TAi register.
Note 5: If the TAi register is set to "000016", the pulse width modulator does not work, the output level
on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated either.
The same applies when the 8 high-order bits of the timer TAi register are set to "0016" while
operating as an 8-bit pulse width modulator.
00
16
to FE
16
(High-order address)
00
16
to FF
16
(Low-order address)
RW
RW
WO
WO
WO
Timer
mode
Event
counter
mode
One-shot
timer mode
Pulse width
modulation
mode
(16-bit PWM)
Pulse width
modulation
mode
(8-bit PWM)
0000
16
to FFFF
16
0000
16
to FFFF
16
0000
16
to FFFF
16
(Notes 3, 4)
Mode
Modify the pulse width as follows:
PWM period: (2
8
—
1) ✕ (m + 1)/ fj
High level PWM pulse width: (m + 1)n / fj
where n = high-order address set value,
m = low-order address set value, fj =
count source frequency
(Note 4, 5)
Divide the count source by FFFF
16
—
n + 1
where n = set value when counting up or
by n + 1 when counting down (Note 2)
Indeterminate
Rev.1.00 2003.05.30 page 106
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Figure 1.13.5 TABSR Register and UFD Register
Timer A4 up/down flag
Timer A3 up/down flag
Timer A2 up/down flag
Timer A1 up/down flag
Timer A0 up/down flag
Timer A2 two-phase pulse
signal processing select bit
Timer A3 two-phase pulse
signal processing select bit
Timer A4 two-phase pulse
signal processing select bit
Symbol Address After reset
UDF 038416 0016
TA4P
TA3P
TA2P
Up/down flag (Note 1)
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
TA4UD
TA3UD
TA2UD
TA1UD
TA0UD 0 : Down count
1 : Up count
Enabled by setting the TAiMR
register’s MR2 bit to "0"
(switching source in UDF register)
during event counter mode.
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
Symbol Address After reset
TABSR 038016 0016
Count start flag
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
WO
(Notes 2, 3)
Note 1: Use MOV instruction to write to this register.
Note 2: Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set to
"0" (input mode).
Note 3: When not using the two-phase pulse signal processing function, set the corresponding bit to timer
A2 to timer A4 to "0".
Rev.1.00 2003.05.30 page 107
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Figure 1.13.6 ONSF Register, TRGSR Register and CPSRF Register
Symbol Address After reset
CPSRF 038116 0XXXXXXX2
Clock prescaler reset flag
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
(b6-b0)
Setting this bit to "1" initializes the
prescaler for the timekeeping clock.
(When read, its content is "0".)
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
CPSR Clock prescaler reset flag
One-shot start flag
Symbol Address After reset
ONSF 038216 0016
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 :
Input on TA0IN is selected
(Note)
0 1 : TB2 is selected
1 0 : TA4 is selected
1 1 : TA1 is selected
Timer A0 event/trigger
select bit
b7 b6
RW
The timer starts counting by setting
this bit to "1" while the TMOD1 to
TMOD0 bits of TAiMR register (i =
0 to 4) is "102" (one-shot timer mode)
and the MR2 bit of TAiMR register is
"0" (TAiOS bit enabled).
When read, its content is "0".
Z-phase input enable bit 0 : Z-phase input disabled
1 : Z-phase input enabled
RW
RW
RW
RW
RW
RW
RW
RW
Note: Make sure the PD7_1 bit of PD7 register is set to "0" (input mode).
TA1OS
TA2OS
TA0OS
TA3OS
TA4OS
TA0TGL
TA0TGH
TAZIE
Symbol Address After reset
TRGSR 038316 0016
Timer A1 event/trigger
select bit
Trigger select register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Timer A2 event/trigger
select bit
Timer A3 event/trigger
select bit
Timer A4 event/trigger
select bit
b1 b0
b3 b2
b5 b4
b7 b6
Note: Make sure the port direction bits for the TA1IN to TA4IN pins are set to "0" (input mode).
0 0 :
Input on TA1IN is selected
(Note)
0 1 : TB2 is selected
1 0 : TA0 is selected
1 1 : TA2 is selected
0 0 :
Input on TA2IN is selected
(Note)
0 1 : TB2 is selected
1 0 : TA1 is selected
1 1 : TA3 is selected
0 0 :
Input on TA3IN is selected
(Note)
0 1 : TB2 is selected
1 0 : TA2 is selected
1 1 : TA4 is selected
0 0 :
Input on TA4IN is selected
(Note)
0 1 : TB2 is selected
1 0 : TA3 is selected
1 1 : TA0 is selected
RW
RW
RW
RW
RW
RW
RW
RW
RW
TA1TGL
TA1TGH
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TGH
Rev.1.00 2003.05.30 page 108
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Item Specification
Count source f1, f2, f8, f32, fC32
Count operation • Down-count
•
When the timer underflows, it reloads the reload register contents and continues counting
Divide ratio 1/(n+1) n: set value of TAiMR register 000016 to FFFF16
Count start condition Set TAiS bit of TABSR register to “1” (start counting)
Count stop condition Set TAiS bit to “0” (stop counting)
Interrupt request generation timing
Timer underflow
TAiIN pin function I/O port or gate input
TAiOUT pin function I/O port or pulse output
Read from timer Count value can be read by reading TAi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function • Gate function
Counting can be started and stopped by an input signal to TAiIN pin
• Pulse output function
Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.
When not counting, the pin outputs a low.
1. Timer Mode
In timer mode, the timer counts a count source generated internally. Table 1.13.1 lists specifications in
timer mode. Figure 1.13.7 shows TAiMR register in timer mode.
Table 1.13.1. Specifications in Timer Mode
Figure 1.13.7 Timer Ai Mode Register in Timer Mode
Note: The port direction bit for the TAi
IN
pin must be set to "0" (input mode).
Timer Ai mode register (i = 0 to 4)
Symbol Address After reset
TA0MR to TA4MR 0396
16 to 039A16 0016
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output
(TAiOUT pin is a pulse output pin)
Gate function select bit
0 0 : Gate function not available
0 1 : (TAiIN pin functions as I/O port)
1 0 : Counts while input on the TAiIN pin
is low (Note)
1 1 : Counts while input on the TAiIN pin
is high (Note)
b4 b3
MR2
MR1
MR3 Set to "0" in timer mode
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
b7 b6
TCK1
TCK0
Count source select bit
00
0
RW
RW
RW
RW
RW
RW
RW
RW
}
i = 0 to 4
Rev.1.00 2003.05.30 page 109
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Item Specification
Count source • External signals input to TAiIN pin (effective edge can be selected in pro-
gram)
• Timer B2 overflows or underflows,
timer Aj (j = i - 1, except j = 4 if i = 0) overflows or underflows,
timer Ak (k = i + 1, except k = 0 if i = 4) overflows or underflows
Count operation •Up-count or down-count can be selected by external signal or program
•When the timer overflows or underflows, it reloads the reload register con-
tents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divided ratio 1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16
Count start condition Set TAiS bit of TABSR register to “1” (start counting)
Count stop condition Set TAiS bit to “0” (stop counting)
Interrupt request generation timing
Timer overflow or underflow
TAiIN pin function I/O port or count source input
TAiOUT pin function I/O port, pulse output, or up/down-count select input
Read from timer Count value can be read by reading TAi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function •Free-run count function
Even when the timer overflows or underflows, the reload register content is
not reloaded to it
•Pulse output function
Whenever the timer underflows or underflows, the output polarity of TAiOUT
pin is inverted. When not counting, the pin outputs a low.
2. Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 1.13.2 lists specifications
in event counter mode (when not processing two-phase pulse signal). Figure 1.13.8 shows TAiMR register
in event counter mode (when not processing two-phase pulse signal). Table 1.13.3 lists specifications in
event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4). Figure
1.13.9 shows TA2MR to TA4MR registers in event counter mode (when processing two-phase pulse
signal with the timers A2, A3 and A4).
Table 1.13.2 Specifications in Event Counter Mode (when not processing two-phase pulse signal)
i = 0 to 4
Rev.1.00 2003.05.30 page 110
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Figure 1.13.8
TAiMR Register in Event Counter Mode (when not using two-phase pulse signal processing)
Symbol Address After reset
TA0MR to TA4MR 0396
16
to 039A
16
00
16
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit
0 1 : Event counter mode
(Note 1)
b1 b0
TMOD0
MR0
Pulse output function
select bit
0 : Pulse is not output
(TA
iOUT
pin functions as I/O port)
1 : Pulse is output
(TAi
OUT
pin functions as pulse output pin)
Count polarity
select bit (Note 2)
MR2
MR1
MR3 Set to "0" in event counter mode
TCK0 Count operation type
select bit
010
0 : Counts external signal’s falling edge
1 : Counts external signal’s rising edge
Up/down switching
cause select bit
0 : UDF register
1 : Input signal to TA
iOUT
pin (Note 3)
0 : Reload type
1 : Free-run type
Bit symbol Bit name Function RW
TCK1 Can be "0" or "1" when not using two-phase pulse signal processing.
TMOD1
Timer Ai mode register (i = 0 to 4)
(When not using two-phase pulse signal processing)
RW
RW
RW
RW
RW
RW
RW
RW
Note 1: During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
Note 2: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are"002" (TAiIN pin input).
Note 3: Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port
direction bit for TAiOUT pin must be set to "0" (input mode).
Rev.1.00 2003.05.30 page 111
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Item Specification
Count source •Two-phase pulse signals input to TAiIN or TAiOUT pins
Count operation •Up-count or down-count can be selected by two-phase pulse signal
•When the timer overflows or underflows, it reloads the reload register con-
tents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divide ratio 1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16
Count start condition Set TAiS bit of TABSR register to “1” (start counting)
Count stop condition Set TAiS bit to “0” (stop counting)
Interrupt request generation timing
Timer overflow or underflow
TAiIN pin function Two-phase pulse input
TAiOUT pin function Two-phase pulse input
Read from timer Count value can be read by reading timer A2, A3 or A4 register
Write to timer •
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to reload register
(Transferred to counter when reloaded next)
Select function (Note) •Normal processing operation (timer A2 and timer A3)
The timer counts up rising edges or counts down falling edges on TAjIN pin
when input signals on TAjOUT pin is “H”.
•Multiply-by-4 processing operation (timer A3 and timer A4)
If the phase relationship is such that TAkIN pin goes “H” when the input sig-
nal on TAkOUT pin is “H”, the timer counts up rising and falling edges on
TAkOUT and TAkIN pins. If the phase relationship is such that TAkIN pin goes
“L” when the input signal on TAkOUT pin is “H”, the timer counts down rising
and falling edges on TAkOUT and TAkIN pins.
Table 1.13.3
Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4)
• Counter initialization by Z-phase input (timer A3)
The timer count value is initialized to “0” by Z-phase input.
i = 2 to 4
j = 2, 3
k = 3, 4
Note : Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to
multiply-by-4 processing operation.
TAjOUT
Up-
count
Up-
count
Up-
count
Down-
count
Down-
count
Down-
count
TAjIN
TAkOUT
TAkIN
Count up all edges
Count up all edges
Count down all edges
Count down all edges
Rev.1.00 2003.05.30 page 112
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Figure 1.13.9 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse
signal processing with timer A2, A3 or A4)
Timer Ai mode register (i = 2 to 4)
(When using two-phase pulse signal processing)
Symbol Address After reset
TA2MR to TA4MR 0398
16
to 039A
16
00
16
b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3
TCK1
TCK0
010
Bit name Function RW
Count operation type
select bit
Two-phase pulse signal
processing operation
select bit (Notes 1, 2)
0 : Reload type
1 : Free-run type
0 : Normal processing operation
1 : Multiply-by-4 processing operation
001
RW
RW
RW
RW
RW
RW
RW
RW
.
To use two-phase pulse signal processing, set this bit to "0".
To use two-phase pulse signal processing, set this bit to "1"
To use two-phase pulse signal processing, set this bit to "0".
Note 1: TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in
normal processing mode and x4 processing mode, respectively.
Note 2: If two-phase pulse signal processing is desired, following register settings are required:
Set the UDF register’s TAiP bit to "1" (two-phase pulse signal processing function enabled).
Set the TRGSR register’s TAiTGH and TAiTGL bits to "00
2
" (TAi
IN
pin input).
Set the port direction bits for TAi
IN
and TAi
OUT
to "0" (input mode).
Rev.1.00 2003.05.30 page 113
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
• Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal process-
________
ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Counter initialization by Z-phase input is enabled by writing “000016” to the TA3 register and setting the
TAZIE bit in ONSF register to “1” (Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be
selected to be the rising or falling edge by using the POL bit of INT2IC register. The Z-phase pulse
________
width applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count
source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 1.13.10
shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase.
If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
m m+1 1 2 3 4 5
TA3OUT
(A phase)
Count source
TA3IN
(B phase)
Timer A3
INT2
(Z phase)
(Note)
Input equal to or greater than one clock cycle
of count source
Note: This timing diagram is for the case where the POL bit of INT2IC register = 1 (rising edge).
Figure 1.13.10 Two-phase Pulse (A phase and B phase) and Z Phase
Rev.1.00 2003.05.30 page 114
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Item Specification
Count source f1, f2, f8, f32, fC32
Count operation •Down-count
•
When the counter reaches 0000
16
, it stops counting after reloading a new value
•If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio 1/n n : set value of TAi register 000016 to FFFF16
However, the counter does not work if the divide-by-n value is set to 000016.
Count start condition TAiS bit of TABSR register = 1 (start counting) and one of the following
triggers occurs.
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
timer Aj (j = i - 1, except j = 4 if i = 0) overflow or underflow,
timer Ak (k = i + 1, except k = 0 if i = 4) overflow or underflow
• The TAiOS bit of ONSF register is set to “1” (timer starts)
Count stop condition • When the counter is reloaded after reaching “000016”
• TAiS bit is set to “0” (stop counting)
Interrupt request generation timing
When the counter reaches “000016”
TAiIN pin function I/O port or trigger input
TAiOUT pin function I/O port or pulse output
Read from timer An indeterminate value is read by reading TAi register
Write to timer
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function • Pulse output function
The timer outputs a low when not counting and a high when counting.
3. One-shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger. When the trigger occurs, the timer
starts up and continues operating for a given period. Table 1.13.4 lists specifications in one-shot timer
mode. Figure 1.13.11 shows the TAiMR register in one-shot timer mode.
Table 1.13.4 Specifications in One-shot Timer Mode
i = 0 to 4
Rev.1.00 2003.05.30 page 115
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Bit name
Symbol Address After reset
TA0MR to TA4MR 0396
16
to 039A
16
00
16
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 1 0 : One-shot timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit
0 : Pulse is not output
(TA
iOUT
pin functions as I/O port)
1 : Pulse is output
(TAi
OUT
pin functions as a pulse output pin)
MR2
MR1
MR3 Set to "0" in one-shot timer mode
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0
Count source select bit
100
0 : TAiOS bit is enabled
1 : Selected by TAiTGH to TAiTGL bits
Trigger select bit
External trigger select
bit (Note 1)
0 : Falling edge of input signal to TAi
IN
pin (Note 2)
1 : Rising edge of input signal to TAi
IN
pin (Note 2)
Note 1: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are "00
2
" (TAi
IN
pin input).
Note 2: The port direction bit for the TAi
IN
pin must be set to "0" (input mode).
RW
RW
RW
RW
RW
RW
RW
RW
RW
Timer Ai mode register (i = 0 to 4)
Figure 1.13.11 TAiMR Register in One-shot Timer Mode
Rev.1.00 2003.05.30 page 116
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
4. Pulse Width Modulation (PWM) Mode
In PWM mode, the timer outputs pulses of a given width in succession. The counter functions as either
16-bit pulse width modulator or 8-bit pulse width modulator.
Table 1.13.5 lists specifications in PWM mode. Figure 1.13.12 shows TAiMR register in PWM mode.
Figures 1.13.13 and 1.13.14 show examples of how a 16-bit pulse width modulator operates and how an
8-bit pulse width modulator operates, respectively.
Table 1.13.5 Specifications in PWM Mode
Item Specification
Count source f1, f2, f8, f32, fC32
Count operation •Down-count (operating as an 8-bit or a 16-bit pulse width modulator)
•
The timer reloads a new value at a rising edge of PWM pulse and continues counting
•The timer is not affected by a trigger that occurs during counting
16-bit PWM •High level width n / fj n : set value of TAi register
•Cycle time (216-1) / fj fixed fj: count source frequency (f1, f2, f8, f32, fC32)
8-bit PWM
•
High level width n ✕ (m+1) / fj
n : set value of TAiMR register high-order address
•
Cycle time
(2
8
-1) ✕ (m+1) / fj
m : set value of TAiMR register low-order address
Count start condition • TAiS bit of TABSR register is set to “1” (start counting)
• TAiS bit = 1 and external trigger input from the TAiIN pin
• TAiS bit = 1 and one of the following external triggers occurs
Timer B2 overflow or underflow,
timer Aj (j = i - 1, except j = 4 if i = 0) overflow or underflow,
timer Ak (k = i + 1, except k = 0 if i = 4) overflow or underflow
Count stop condition TAiS bit is set to “0” (stop counting)
Interrupt request generation timing
PWM pulse goes “L”
TAiIN pin function I/O port or trigger input
TAiOUT pin function Pulse output
Read from timer An indeterminate value is read by reading TAi register
Write to timer
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
i = 0 to 4
Rev.1.00 2003.05.30 page 117
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Figure 1.13.12 TAiMR Register in PWM Mode
Bit name
Timer Ai mode register (i = 0 to 4)
Symbol Address After reset
TA0MR to TA4MR 039616 to 039A16 0016
FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 1 1 : PWM mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
b7 b6
TCK1
TCK0
Count source select bit
RW
111
Set to "1" in PWM mode
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
Trigger select bit
External trigger select
bit (Note 1)
0: Falling edge of input signal to TAi
IN
pin (Note 2)
1: Rising edge of input signal to TAi
IN
pin (Note 2)
RW
RW
RW
RW
RW
RW
RW
RW
0 : Write "1" to TAiS bit in the TABSR register
1 : Selected by TAiTGH to TAiTGL bits
Note 1: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are "002" (TAiIN pin input).
Note 2: The port direction bit for the TAiIN pin must be set to "0" (input mode).
Rev.1.00 2003.05.30 page 118
M16C/6N4 Group Timer A
Under development
This document is under development and its contents are subject to change.
Figure 1.13.13 Example of 16-bit Pulse Width Modulator Operation
1 / f
i
✕ (2
—
1)
16
Count source
Input signal to
TA
iIN
pin
PWM pulse output
from TA
iOUT
pin
Trigger is not generated by this signal
"H"
"H"
"L"
"L"
IR bit of TAiIC
register
i = 0 to 4
f
j
: Frequency of count source (f
1
, f
2
, f
8
, f
32
, f
C32
)
"1"
"0"
Note 1: n = 0000
16
to FFFE
16
.
Note 2: This timing diagram is the following case.
TAi register = 0003
16
The TAiTGH and TAiTGL bits of ONSF or TRGSR register = 00
2
(TAi
IN
pin input)
The MR1 bit of TAiMR register = 1 (rising edge)
The MR2 bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits)
1 / f
j
✕ n
Set to "0" upon accepting an interrupt request or by writing in program
Count source (Note1)
Input signal to
TAiIN pin
Underflow signal of
8-bit prescaler (Note2)
PWM pulse output
from TAiOUT pin
"H"
"H"
"H"
"L"
"L"
"L"
"1"
"0"
Set to "0" upon accepting an interrupt request or by writing in program
1 / f
j
✕ (m
+ 1) ✕ (2
—
1)
8
1 / f
j
✕ (m + 1) ✕ n
1 / f
j
✕ (m + 1)
IR bit of TAiIC
register
i = 0 to 4
fj: Frequency of count source (f
1
, f
2
, f
8
, f
32
, f
C32
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler’s underflow signal.
Note 3: m = 00
16
to FF
16
; n = 00
16
to FE
16
.
Note 4: This timing diagram is the following case.
TAi register = 0202
16
The TAiTGH and TAiTGL bits of ONSF or TRGSR register = 00
2
(TAiIN pin input)
The MR1 bit of TAiMR register = 0 (falling edge)
The MR2 bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits)
Figure 1.13.14 Example of 8-bit Pulse Width Modulator Operation
Rev.1.00 2003.05.30 page 119
M16C/6N4 Group Timer B
Under development
This document is under development and its contents are subject to change.
Timer B
Figure 1.13.15 shows a block diagram of the timer B. Figures 1.13.16 and 1.13.17 show the timer B-related
registers.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to 5)
to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows or underflows of
other timers.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Figure 1.13.15 Timer B Block Diagram
Clock source selection
Reload register
Low-order 8 bits High-order 8 bits
Data bus low-order bits
Data bus high-order bits
f
1
or f
2
f
8
f
32
TBj overflow (Note)
Can be selected in only
event counter mode
TABSR register
TBSR register
f
C32
Polarity switching
and edge pulse
TBi
IN
Counter reset circuit
Counter
TBi Addresses TBj
Timer B0 0391
16
-0390
16
Timer B2
Timer B1 0393
16
-0392
16
Timer B0
Timer B2 0395
16
-0394
16
Timer B1
Timer B3 01D1
16
-01D0
16
Timer B5
Timer B4 01D3
16
-01D2
16
Timer B3
Timer B5 01D5
16
-01D4
16
Timer B4
Clock selection
Event counter mode
Timer mode
Pulse period measurement mode,
pulse width measurement mode
i = 0 to 5
j = i
—
1. Note, however, j = 2 when i = 0, j = 5 when i = 3
Note: Overflow or underflow
Rev.1.00 2003.05.30 page 120
M16C/6N4 Group Timer B
Under development
This document is under development and its contents are subject to change.
Figure 1.13.16 TB0MR to TB5MR Registers and TB0 to TB5 Registers
Timer Bi mode register (i = 0 to 5)
Symbol Address After reset
TB0MR to TB2MR 039B16 to 039D16 00XX00002
TB3MR to TB5MR 01DB16 to 01DD16 00XX00002
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Must not be set
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation
mode
Count source select bit
Operation mode select bit
(Note 1)
(Note 2)
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
RW
RW
RW
RW
RW
RW
RW
RO
Function varies with each operation
mode
Symbol Address After reset
TB0 0391
16
, 0390
16
Indeterminate
TB1 0393
16
, 0392
16
Indeterminate
TB2 0395
16
, 0394
16
Indeterminate
TB3 01D1
16
, 01D0
16
Indeterminate
TB4 01D3
16
, 01D2
16
Indeterminate
TB5 01D5
16
, 01D4
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
Timer Bi register (i = 0 to 5) (Note 1)
RW
Measures a pulse period or width
Function
RW
RW
RO
Note 1: The register must be accessed in 16-bit unit.
Note 2: The timer counts pulses from an external device or overflows or underflows of other timers.
Divide the count source by n + 1
where n = set value
Timer mode
Event counter
mode
0000
16
to FFFF
16
Divide the count source by n + 1
where n = set value (Note 2)
0000
16
to FFFF
16
Pulse period
modulation mode,
Pulse width
modulation mode
Mode Setting range
Rev.1.00 2003.05.30 page 121
M16C/6N4 Group Timer B
Under development
This document is under development and its contents are subject to change.
Figure 1.13.17 TABSR Register, TBSR Register and CPSRF Register
Symbol Address After reset
TABSR 038016 0016
Count start flag
Bit name
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
Function
Symbol Address After reset
CPSRF 038116 0XXXXXXX2
Clock prescaler reset flag
Bit name Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Clock prescaler reset flag
CPSR
Symbol Address After reset
TBSR 01C016 000XXXXX2
Timer B3, B4, B5 count start flag
Bit name
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Timer B5 count start flag
Timer B4 count start flag
Timer B3 count start flag 0 : Stops counting
1 : Starts counting
TB5S
TB4S
TB3S
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
Function
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(b4-b0)
(b6-b0)
Setting this bit to "1" initializes the
prescaler for the timekeeping clock.
(When read, the value of this bit is "0".)
Rev.1.00 2003.05.30 page 122
M16C/6N4 Group Timer B
Under development
This document is under development and its contents are subject to change.
Item Specification
Count source f1, f2, f8, f32, fC32
Count operation •Down-count
•When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio 1/(n+1) n: set value of TBiMR register 000016 to FFFF16
Count start condition Set TBiS bit (Note) to “1” (start counting)
Count stop condition Set TBiS bit to “0” (stop counting)
Interrupt request generation timing
Timer underflow
TBiIN pin function I/O port
Read from timer Count value can be read by reading TBi register
Write to timer
•
When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
1. Timer Mode
In timer mode, the timer counts a count source generated internally.
Table 1.13.6 lists specifications in timer mode. Figure 1.13.18 shows TBiMR register in timer mode.
Table 1.13.6 Specifications in Timer Mode
Timer Bi mode register (i = 0 to 5)
Symbol Address After reset
TB0MR to TB2MR 039B16 to 039D16 00XX00002
TB3MR to TB5MR 01DB16 to 01DD16 00XX00002
Bit name Function
Bit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Has no effect in timer mode
Can be set to "0" or "1"
MR2
MR1
MR3
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
TCK1
TCK0
Count source select bit
00
TB0MR, TB3MR registers
Set to "0" in timer mode
b7 b6
RW
RW
RW
RW
RW
RW
RW
RO
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
When write in timer mode, set to "0".
When read in timer mode, its content is indeterminate.
i = 0 to 5
Note : The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.
Figure 1.13.18 TBiMR Register in Timer Mode
Rev.1.00 2003.05.30 page 123
M16C/6N4 Group Timer B
Under development
This document is under development and its contents are subject to change.
Item Specification
Count source • External signals input to TBiIN pin (effective edge can be selected in program)
• Timer Bj overflow or underflow (j = i - 1, except j = 2 if i = 0, j = 5 if i = 3)
Count operation •Down-count
•When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio 1/(n+1) n: set value of TBi register 000016 to FFFF16
Count start condition Set TBiS bit (Note) to “1” (start counting)
Count stop condition Set TBiS bit to “0” (stop counting)
Interrupt request generation timing
Timer underflow
TBiIN pin function Count source input
Read from timer Count value can be read by reading TBi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
2. Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Table 1.13.7 lists specifications in event counter mode. Figure 1.13.19 shows TBiMR register
in event counter mode.
Table 1.13.7 Specifications in Event Counter Mode
Figure 1.13.19 TBiMR Register in Event Counter Mode
Timer Bi mode register ( i= 0 to 5)
Symbol Address After reset
TB0MR to TB2MR 039B16 to 039D16 00XX00002
TB3MR to TB5MR 00XX00002
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0
Count polarity select
bit (Note 1)
MR2
MR1
MR3
TCK1
TCK0
01
0 0 : Counts external signal’s
falling edges
0 1 : Counts external signal’s
rising edges
1 0 : Counts external signal’s
falling and rising edges
1 1 : Must not be set
b3 b2
Note 1: Effective when the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow), these bits
can be set to "0" or "1" .
Note 2: The port direction bit for the TBiIN pin must be set to "0" (input mode).
Has no effect in event counter mode.
Can be set to "0" or "1".
Event clock select bit
0 : Input from TBiIN pin (Note 2)
1 : TBj overflow or underflow
(j = i
—
1, except j = 2 if i = 0,
j = 5 if i = 3)
RW
RW
RW
RW
RW
RW
RW
RO
TB0MR, TB3MR registers
Set to "0" in event counter mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
When write in event counter mode, set to "0".
When read in event counter mode, its content is indeterminate.
01DB16 to 01DD16
i = 0 to 5
Note: The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits are
assigned to the TBSR register bit 5 to bit 7.
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M16C/6N4 Group Timer B
Under development
This document is under development and its contents are subject to change.
Item Specification
Count source f1, f2, f8, f32, fC32
Count operation •Up-count
•Counter value is transferred to reload register at an effective edge of
measurement pulse. The counter value is set to “000016” to continue counting.
Count start condition Set TBiS bit (Note 1) to “1” (start counting)
Count stop condition Set TBiS bit to “0” (stop counting)
Interrupt request generation timing
• When an effective edge of measurement pulse is input (Note 2)
• Timer overflow. When an overflow occurs, the MR3 bit of TBiMR register is
set to “1” (overflow) simultaneously. The MR3 bit is set to “0” (no overflow) by
writing to TBiMR register at the next count timing or later after the MR3 bit
was set to “1”. At this time, make sure TBiS bit is set to “1” (start counting).
TBiIN pin function Measurement pulse input
Read from timer Contents of the reload register (measurement result) can be read by reading
TBi register (Note 3)
Write to timer Value written to TBi register is written to neither reload register nor counter
3. Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal. Table 1.13.8 lists specifications in pulse period and pulse width measurement mode.
Figure 1.13.20 shows TBiMR register in pulse period and pulse width measurement mode. Figure
1.13.21 shows the operation timing when measuring a pulse period. Figure 1.13.22 shows the operation
timing when measuring a pulse width.
Table 1.13.8 Specifications in Pulse Period and Pulse Width Measurement Mode
i = 0 to 5
Note 1: The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.
Note 2: Interrupt request is not generated when the first effective edge is input after the timer started counting.
Note 3: Value read from TBi register is indeterminate until the second valid edge is input after the timer starts
counting.
Rev.1.00 2003.05.30 page 125
M16C/6N4 Group Timer B
Under development
This document is under development and its contents are subject to change.
Figure 1.13.20
TBiMR Register in Pulse Period and Pulse Width Measurement Mode
Timer Bi mode register (i = 0 to 5)
Symbol Address After reset
TB0MR to TB2MR 039B16 to 039D16 00XX00002
TB3MR to TB5MR 00XX00002
Bit nameBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit
1 0 : Pulse period / pulse width
measurement mode
b1 b0
TMOD1
TMOD0
MR0
Measurement mode
select bit
MR2
MR1
MR3
TCK1
TCK0
01
0 0 : Pulse period measurement
(Measurement between a falling edge and the
next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
rising edge of measured pulse)
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
a rising edge and the next falling edge)
1 1 : Must not be set.
Function
b3 b2
Count source
select bit
Timer Bi overflow
flag ( Note)
0 : Timer did not overflow
1 : Timer has overflown
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
b7 b6
RW
RW
RW
RW
RW
RW
RW
RO
TB0MR and TB3MR registers
Set to "0" in pulse period and pulse width measurement mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
01DB16 to 01DD16
Note: This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is set to "0" (no overflow) by writing to the
TBiMR register at the next count timing or later after the MR3 bit was set to "1" (overflow). The MR3 bit cannot be set to "1" in a
program. The TB0S to TB2S bits are assigned to the TABSR register’s bit 5 to bit 7, and the TB3S to TB5S bits are assigned to the
TBSR register’s bit 5 to bit 7.
Rev.1.00 2003.05.30 page 126
M16C/6N4 Group Timer B
Under development
This document is under development and its contents are subject to change.
Figure 1.13.22 Operation Timing When Measuring Pulse Width
Figure 1.13.21 Operation Timing When Measuring Pulse Period
Count source
Measurement pulse
TBiS bit
TBiIC register’s
IR bit
Timing at which counter
reaches "0000
16
"
"H"
"1"
Transfer
(indeterminate value)
"L"
"0"
"0"
TBiMR register’s
MR3 bit
"1"
"0"
i = 0 to 5
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflown.
Note 3: This timing diagram is for the case where the TBiMR register’s MR1 to MR0 bits are "00
2
" (measure the interval
from falling edge to falling edge of the measurement pulse).
(Note 1)(Note 1) (Note 2)
Transfer
(measured value)
"1"
Reload register counter
transfer timing
The TB0S to TB2S bits are assigned to the TABSR register’s bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register’s bit 5 to bit 7.
Set to "0" upon accepting an interrupt request or by writing in program
Measurement pulse
"H"
Count source
Timing at which counter
reaches "000016"
"1"
"1"
Transfer
(measured value)
Transfer
(measured value)
"L"
"0"
"0"
"1"
"0"
(Note 1)(Note 1)(Note 1)
Transfer
(measured
value)
(Note 1) (Note 2)
Transfer
(indeterminate
value)
Reload register counter
transfer timing
TBiS bit
TBiIC register’s
IR bit
TBiMR register’s
MR3 bit
Set to "0" upon accepting an interrupt request or by
writing in program
i = 0 to 5
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflown.
Note 3: This timing diagram is for the case where the TBiMR register’s MR1 to MR0 bits are "102" (measure the interval
from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
The TB0S to TB2S bits are assigned to the TABSR register’s bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register’s bit 5 to bit 7.
Rev.1.00 2003.05.30 page 127
M16C/6N4 Group Three-phase Motor Control Timer Function
Under development
This document is under development and its contents are subject to change.
Three-phase Motor Control Timer Function
Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 1.14.1 lists the
specifications of the three-phase motor control timer function. Figure 1.14.1 shows the block diagram for
three-phase motor control timer function. Also, the related registers are shown on Figures 1.14.2 to 1.14.8.
Table 1.14.1 Three-phase Motor Control Timer Function Specifications
Item Specification
Three-phase waveform output pin
___ ___ ___
Six pins (U, U, V, V, W, W)
Forced cutoff input (Note)
_______
Input “L” to NMI pin
Used Timers Timer A4, A1, A2 (used in the one-shot timer mode)
___
• Timer A4: U- and U-phase waveform control
___
• Timer A1: V- and V-phase waveform control
___
• Timer A2: W- and W-phase waveform control
Timer B2 (used in the timer mode)
• Carrier wave cycle control
Dead time timer (3 eight-bit timer and shared reload register)
• Dead time control
Output waveform Triangular wave modulation, Sawtooth wave modification
• Enable to output “H” or “L” for one cycle
•
Enable to set positive-phase level and negative-phase level respectively
Carrier wave cycle Triangular wave modulation: count source ✕ (m+1) ✕ 2
Sawtooth wave modulation: count source ✕ (m+1)
m: Setting value of TB2 register, 0 to 65535
Count source: f1, f2, f8, f32, fC32
Three-phase PWM output width Triangular wave modulation: count source ✕ n ✕ 2
Sawtooth wave modulation: count source ✕ n
n:
Setting value of TA4, TA1 and TA2 registers (of TA4, TA41, TA1,
TA11, TA2 and TA21 registers when setting the INV11 bit to
“1”), 1 to 65535
Count source: f1, f2, f8, f32, fC32
Dead time Count source ✕ p, or no dead time
p: Setting value of DTT register, 1 to 255
Count source: f1, f2, f1 divided by 2, f2 divided by 2
Active level Enable to select “H” or “L”
Positive and negative-phase concurrent
Positive and negative-phases concurrent active disable function
active disable function Positive and negative-phases concurrent active detect function
Interrupt frequency For Timer B2 interrupt, select a carrier wave cycle-to-cycle basis
through 15 times carrier wave cycle-to-cycle basis
_______
Note: Forced cutoff with NMI input is effective when the IVPCR1 bit of TB2SC register is set to “1” (three-
_______ _______
phase output forcible cutoff by NMI input enabled). If an “L” signal is applied to the NMI pin when the
IVPCR1 bit is “1”, the related pins go to a high-impedance state regardless of which functions of those
pins are being used.
Related pins: • P72/CLK2/TA1OUT/V
_________ _________ ___
• P73/CTS2/RTS2/TA1IN/V
• P74/TA2OUT/W
____
• P75/TA2IN/W
• P80/TA4OUT/U
___
• P81/TA4IN/U
Rev.1.00 2003.05.30 page 128
M16C/6N4 Group Three-phase Motor Control Timer Function
Under development
This document is under development and its contents are subject to change.
Figure 1.14.1 Three-phase Motor Control Timer Function Block Diagram
D
R
Q
0INV12
1
Trigger
Trigger
Timer B2
(Timer mode)
Signal to be
written to
timer B2
1Timer B2
interrupt request bit
DU1
bit
D
T
QQ
Q
U
Three-phase output
shift register
(U phase)
Dead time timer
n = 1 to 255
Trigger
Trigger
Reload register
n = 1 to 255
Trigger
Trigger
U
phase output signal
U
V
V
V
W
W
W phase output
control circuit
DQ
T
DQ
T
W
DQ
T
DQ
T
V
DQ
T
U
DQ
T
Reverse
control
U
W
V
Reload
Timer A 1 counter
(One-shot timer mode)
Trigger
TQ
Reload
Timer A 2 counter
(One-shot timer mode)
Trigger
TQ
Reload
Timer A4 counter
(One-shot timer mode)
Trigger
TQ
Transfer trigger
(Note)
Timer B2 underflow
DU0
bit
DUB0
bit
TA4 register
TA41
register
TA1
register
TA11
register
TA2
register
TA21
register
Timer Ai (i = 1, 2, 4) start trigger signal
Timer A4 reload control signal
Timer A4
one-shot pulse
DUB1
bit
Dead time timer
n = 1 to 255
Dead time timer
n = 1 to 255
Interrupt occurrence set circuit
ICTB2 register
n = 1 to 15
0
INV13
ICTB2 counter
n = 1 to 15
RESET
NMI
INV03
INV14
INV05
INV04
INV00
INV01
INV11
INV11
INV11
INV11
INV06
INV06
INV06
INV07
INV10
1/2
f1
phase output
control circuit
phase output
control circuit
phase output signal
phase output signal
phase output signal
phase output signal
phase output signal
Reverse
control
Reverse
control
Reverse
control
Reverse
control
Reverse
control
D
T
D
T
QD
T
Note : If the INV06 bit = 0 (triangular wave modulation mode), a transfer trigger is generated at only the first occurrence of a timer B2 underflow after writing to the IDB0 and IDB1 registers.
Set to "0" when TA2S bit = 0
Set to "0" when TA1S bit = 0
Set to "0" when TA4S bit = 0
Diagram for switching to P8
0
, P8
1
and P7
2
to P7
5
is not shown.
Rev.1.00 2003.05.30 page 129
M16C/6N4 Group Three-phase Motor Control Timer Function
Under development
This document is under development and its contents are subject to change.
Figure 1.14.2 INVC0 Register
Three-phase PWM control register 0 (Note 1)
Symbol Address After reset
INVC0 01C8
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Effective interrupt output
polarity select bit
(Note 2)
INV00
Bit symbol Bit name Description RW
INV01
Effective interrupt output
specification bit
(Notes 2, 3)
INV02 Mode select bit (Note 4)
INV04
Positive and negative
phases concurrent output
disable bit
INV07 Software trigger select bit
INV06 Modulation mode select
bit
INV05 Positive and negative
phases concurrent output
detect flag
INV03 Output control bit (Note 6)
0: ICTB2 counter incremented by 1 at
odd-numbered occurrences of a timer
B2 underflow
1: ICTB2 counter incremented by 1 at
even-numbered occurrences of a timer
B2 underflow
0:
ICTB2 counter incremented by 1 at a
timer B2 underflow
1: Selected by INV00 bit
0: Three-phase motor control timer
function unused
1: Three-phase motor control timer
function
0: Three-phase motor control timer output
disabled
1: Three-phase motor control timer output
enabled
0: Simultaneous active output enabled
1: Simultaneous active output disabled
0: Not detected yet
1: Already detected
0: Triangular wave modulation mode
1:
Sawtooth wave modulation mode (Note 9)
Setting this bit to "1" generates a transfer
trigger. If the INV06 bit is "1", a trigger for
the dead time timer is also generated.
The value of this bit when read is "0".
(Note 7)
Note 1: Write to this register after setting the PRC1 bit of PRCR register to "1" (write enable). Note also that INV00 to INV02,
INV04 and INV06 bits can only be rewritten when timers A1, A2, A4 and B2 are idle.
Note 2: Effective when the INV11 bit is "1" (three-phase mode 1). If INV11 is "0" (three-phase mode 0), the ICTB2 counter is
incremented by "1" each time the timer B2 underflows, regardless of whether the INV00 and INV01 bits are set.
Note 3: If this bit needs to be set to "1", set any value in the ICTB2 register before writing to it.
Note 4: Setting the INV02 bit to "1" activates the dead time timer, U/V/W-phase output control circuits and ICTB2 counter.
Note 5: All of the U, U, V, V, W and W pins are placed in the high-impedance state by setting the INV02 bit to 1 (three-phase
motor control timer function) and setting the INV03 bit to "0" (three-phase motor control timer output disable).
Note 6: The INV03 bit is set to "0" in the following cases:
When reset
When positive and negative go active simultaneously while INV04 bit is "1"
When set to "0" in a program
When input on the NMI pin changes state from "H" to "L" (The INV03 bit cannot be set to "1" when NMI input is "L".)
Note 7: Can only be set by writing "0" in a program, and cannot be set to "1".
Note 8: The effects of the INV06 bit are described in the table below.
RW
RW
RW
RW
RW
RW
RW
RW
(Note 5)
(Note 8)
Item
Mode
Timing at which transferred from IDB0 to
IDB1 registers to three-phase output shift
register
Timing at which dead time timer trigger is
generated when INV16 bit is "0"
INV13 bit
INV06 = 0
Triangular wave modulation mode
Transferred only once synchronously
with the transfer trigger after writing to
the IDB0 to IDB1 registers
Synchronous with the falling edge of
timer A1, A2, or A4 one-shot pulse
Effective when INV11 is "1" and INV06
is "0"
INV06 = 1
Sawtooth wave modulation mode
Transferred every transfer trigger
Synchronous with the transfer
trigger and the falling edge of timer
A1, A2, or A4 one-shot pulse
Transfer trigger: Timer B2 underflow, write to the INV07 bit or write to the TB2 register when INV10 is "1"
Note 9: If the INV06 bit is "1", set the INV11 bit to "0" (three-phase mode 0) and set the PWCON bit to "0" (timer B2 reloaded
by a timer B2 underflow).
(Note 5)
Has no effect
Rev.1.00 2003.05.30 page 130
M16C/6N4 Group Three-phase Motor Control Timer Function
Under development
This document is under development and its contents are subject to change.
Figure 1.14.3 INVC1 Register
Three-phase PWM control register 1 (Note 1)
Symbol Address After reset
INVC1 01C9
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Timer A1, A2, A4 start
trigger signal select bit
INV10
Bit symbol Bit name Description RW
INV11
Timer A1-1, A2-1, A4-1
control bit
INV12 Dead time timer count
source select bit
INV14 Output polarity control bit
-
(b7) Reserved bit
INV16 Dead time timer trigger
select bit
INV15 Dead time invalid bit
INV13 Carrier wave detect flag
0: Timer B2 underflow
1: Timer B2 underflow and write to the
TB2 register
0: Three-phase mode 0
1: Three-phase mode 1
0 : f
1
or f
2
1 : f
1
divided by 2 or f
2
divided by 2
0:
Timer A output at even-numbered occurrences
(TA11, TA21, TA41 register value counted)
1:
Timer A output at odd-numbered occurrences
(TA1, TA2, TA4 register value counted)
0 : Output waveform "L" active
1 : Output waveform "H" active
0: Dead time timer enabled
1: Dead time timer disabled
0: Falling edge of timer A4, A1 or A2
one-shot pulse (Note 5)
1: Rising edge of three-phase output shift
register (U, V or W phase) output
Set to "0"
(Note 4)
RW
RW
RW
RW
RW
RW
RW
RO
(Note 2)
Item
Mode
TA11, TA21, TA41 registers
INV00 bit, INV01 bit
INV13 bit
INV11 = 0
Three-phase mode 1
Three-phase mode 0
Not used
Has no effect. ICTB2 counted every time
timer B2 underflows regardless of
whether the INV00 to INV01 bits are set.
Has no effect
INV11 = 1
Used
Effect
Effective when INV11 bit is "1" and
INV06 bit is "0"
(Note 3)
0
Note 3: If the INV06 bit is "1" (sawtooth wave modulation mode), set this bit to "0" (three-phase mode 0). Also, if the INV11
bit is "0", set the PWCON bit to "0" (timer B2 reloaded by a timer B2 underflow).
Note 4: The INV13 bit is effective only when the INV06 bit is "0" (triangular wave modulation mode) and the INV11 bit is "1"
(three-phase mode 1).
Note 5: If all of the following conditions hold true, set the INV16 bit to "1" (dead time timer triggered by the rising edge of
three-phase output shift register output).
The INV15 bit is "0" (dead time timer enabled)
When the INV03 bit is set to "1" (three-phase motor control timer output enabled), the Dij bit and DiBj bit (i: U, V,
or W, j: 0, 1) have always different values (the positive-phase and negative-phase always output different levels
during the period other than dead time).
Conversely, if either one of the above conditions holds false, set the INV16 bit to "0" (dead time timer triggered by the
falling edge of one-shot timer pulse).
Note 1: Write to this register after setting the PRC1 bit of PRCR register to "1" (write enable). Note also that this register can
only be rewritten when timers A1, A2, A4 and B2 are idle.
Note 2: The effects of the INV11 bit are described in the table below.
Rev.1.00 2003.05.30 page 131
M16C/6N4 Group Three-phase Motor Control Timer Function
Under development
This document is under development and its contents are subject to change.
Figure 1.14.4 IDB0 Register, IDB1 Register and DTT Register
Three-phase output buffer register i (i = 0, 1) (Note)
Symbol Address After reset
IDB0 01CA
16
00
16
IDB1 01CB
16
00
16
Bit name Function
Bit Symbol
b7 b6 b5 b4 b3 b2 b1 b0
DUi
DUBi
DVi
DWi
DVBi
DWBi
U phase output buffer i Write the output level
0: Active level
1: Inactive level
When read, these bits show the
three-phase output shift register
value.
V phase output buffer i
W phase output buffer i
U phase output buffer i
V phase output buffer i
W phase output buffer i
Dead time timer (Notes 1, 2)
Symbol Address After reset
DTT 01CC
16
Indeterminate
Function
Setting range
b7 b0
Assuming the set value = n, upon a start trigger the
timer starts counting the count source selected by
the INV12 bit and stops after counting it n times.
The positive or negative phase whichever is going from
an inactive to an active level changes at the same
time the dead time timer stops.
1 to 255
RW
RW
RW
RW
RW
RW
RW
Nothing is assigned. When write, set to "0".
When read, its content is "0".
(b7-b6)
RW
WO
Note 1: Use MOV instruction to write to this register.
Note 2: Effective when the INV15 bit is "0" (dead time timer enabled). If the INV15 bit is "1", the dead time timer is disabled
and has no effect.
Note: The IDB0 and IDB1 register values are transferred to the three-phase output shift register by a transfer trigger.
The value written to the IDB0 register after a transfer trigger generates the output signal of each phase, and the
next value written to the IDB1 register at the falling edge of the timer A1, A2 or A4 one-shot pulse represents the
output signal of each phase.
Rev.1.00 2003.05.30 page 132
M16C/6N4 Group Three-phase Motor Control Timer Function
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This document is under development and its contents are subject to change.
Figure 1.14.5 TA1, TA2, TA4, TA11, TA21 and TA41 Registers, and TB2 Register
Symbol Address After reset
TA1
TA2
TA4
TA11 (Note 7)
TA21 (Note 7)
TA41 (Note 7)
b7 b0 b7 b0
(b15) (b8)
RW
Assuming the set value = n, upon a start trigger the timer
starts counting the count source and stops after counting
it n times. The positive and negative phases change at the
same time timer A1, A2 or A4 stops.
Function Setting range
Timer Ai, Ai-1 register (i = 1, 2, 4) (Notes 1 to 6)
WO
000016 to FFFF16
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
038916-038816
038B16-038A16
038F16-038E16
01C316-01C216
01C516-01C416
01C716-01C616
Note 1: The register must be accessed in 16-bit unit.
Note 2: When these registers are set to "000016", the counter does not operate and a timer Ai interrupt does not occur.
Note 3: Use MOV instruction to write to these registers.
Note 4: If the INV15 bit is "0" (dead time timer enabled), the positive or negative phase whichever is going from an
inactive to an active level changes at the same time the dead time timer stops.
Note 5: If the INV11 bit is "0" (three-phase mode 0), the TAi register value is transferred to the reload register by
a timer Ai (i = 1, 2 or 4) start trigger.
If the INV11 bit is "1" (three-phase mode 1), the TAi1 register value is transferred to the reload register by
a timer Ai start trigger first and then the TAi register value is transferred to the reload register by the next
timer Ai start trigger. Thereafter, the TAi1 register and TAi register values are transferred to the reload
register alternately.
Note 6: Do not write to these registers synchronously with a timer B2 underflow.
Note 7: Write to TAi1 register as follows:
(1) Write a value to the TAi1 register.
(2) Wait for one cycle of timer Ai count source.
(3) Write the same value to the TAi1 register again.
Symbol Address After reset
TB2 0395
16
-0394
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
RW
0000
16
to FFFF
16
Function Setting range
Timer B2 register (Note)
Note: The register must be accessed in 16-bit unit.
RW
Divide the count source by n + 1 where n = set value.
Timer A1, A2 and A4 are started at every occurrence of
underflow.
Rev.1.00 2003.05.30 page 133
M16C/6N4 Group Three-phase Motor Control Timer Function
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This document is under development and its contents are subject to change.
Figure 1.14.6 ICTB2 Register and TB2SC Register
Timer B2 interrupt occurrences frequency set counter
Symbol Address After reset
ICTB2 01CD
16
Indeterminate
Function Setting range
b7 b0
If the INV01 bit is "0" (ICTB2 counter counted every
time timer B2 underflows), assuming the set value
= n, a timer B2 interrupt is generated at every n’th
occurrence of a timer B2 underflow.
If the INV01 bit is "1" (ICTB2 counter count timing
selected by the INV00 bit), assuming the set value
= n, a timer B2 interrupt is generated at every n’th
occurrence of a timer B2 underflow that meets the
condition selected by the INV00 bit.
1 to 15
RW
WO
(Note)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Note: Use MOV instruction to write to this register.
If the INV01 bit = 1, make sure the TB2S bit also = 0 (timer B2 count stopped) when writing to this register.
If the INV01 bit = 0, although this register can be written even when the TB2S bit = 1 (timer B2 count start), do not
write synchronously with a timer B2 underflow
PWCOM
Symbol Address After reset
TB2SC 039E16 XXXXXX002
Timer B2 reload timing
switching bit
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
occurrences
Timer B2 special mode register (Note 1)
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned. When write, set to "0".
When read, its content is "0".
IVPCR1
Three-phase output port
NMI control bit 1
0 : Three-phase output forcible cutoff
by NMI input (high-impedance)
disabled
1 : Three-phase output forcible cutoff
by NMI input (high-impedance)
enabled
(Note 3)
Note 1: Write to this register after setting the PRC1 bit of PRCR register to "1" (write enabled).
Note 2: If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (sawtooh wave modulation mode), set this
bit to "0" (timer B2 underflow).
Note 3: Related pins are U(P80/TA4OUT), U(P81/TA4IN), V(P72/CLK2/TA1OUT), V(P73/CTS2/RTS2/TA1IN), W(P74/TA2OUT),
W(P75/TA2IN). If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1, the target pins go to
a high-impedance state regardless of which functions of those pins are being used. After forced interrupt
(cutoff), input "H" to the NMI pin and set IVPCR1 bit to "0": this forced cutoff will be reset.
RW
RW
RW
(b7-b2)
(Note 2)
Rev.1.00 2003.05.30 page 134
M16C/6N4 Group Three-phase Motor Control Timer Function
Under development
This document is under development and its contents are subject to change.
Figure 1.14.7 TRGSR Register and TRBSR Register
Symbol Address After reset
TRGSR 038316 0016
Timer A1 event/trigger
select bit
To use the V-phase output control
circuit, set these bits to "012" (TB2
underflow).
Trigger select register
Bit name Function
Bit symbol
b0
To use the W-phase output control
circuit, set these bits to "012" (TB2
underflow).
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 is selected
1 0 : TA2 is selected
1 1 : TA4 is selected
To use the U-phase output control
circuit, set these bits to "012" (TB2
underflow).
Timer A2 event/trigger
select bit
Timer A3 event/trigger
select bit
Timer A4 event/trigger
select bit
RW
b5 b4
Note: Set the corresponding port direction bit to "0" (input mode).
b7 b6 b5 b4 b3 b2 b1
Symbol Address After reset
TABSR 038016 0016
Count start flag
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
TA1TGL
TA1TGH
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TGH
Function
Rev.1.00 2003.05.30 page 135
M16C/6N4 Group Three-phase Motor Control Timer Function
Under development
This document is under development and its contents are subject to change.
Figure 1.14.8 TA1MR, TA2MR and TA4MR Registers, and TB2MR Register
Bit name
Timer Ai mode register (i = 1, 2, 4)
Symbol Address After reset
TA1MR 0397
16
00
16
TA2MR 0398
16
00
16
TA4MR 039A
16
00
16
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit
Set to "10
2
" (one-shot timer mode) for
the three-phase motor control timer function
TMOD1
TMOD0
MR0 Pulse output function
select bit
Set to "0" for the three-phase motor control
timer function
MR2
MR1
MR3 Set to "0" for the three-phase motor control timer function
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0
Count source select bit
1000
Set to "1" (selected by TRGSR register)
for the three-phase motor control timer
function
Trigger select bit
External trigger select
bit
RW
1
Has no effect for the three-phase motor
control timer function
RW
RW
RW
RW
RW
RW
RW
RW
Timer B2 mode register
Symbol Address After reset
TB2MR 039D
16
00XX0000
2
Bit name Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit Set to "00
2
" (timer mode) for the three-phase
motor control timer function
TMOD1
TMOD0
MR0
MR2
MR1
MR3
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
TCK1
TCK0
Count source select bit
0
When write in the three-phase motor control timer function, write "0".
When read, its content is indeterminate.
0
b7 b6
0
Has no effect for the three-phase motor control timer function .
When write, set to "0". When read, its content is indeterminate .
Set to "0" for the three-phase motor control timer function
RW
RW
RW
RW
RW
RW
RW
RW
RO
Rev.1.00 2003.05.30 page 136
M16C/6N4 Group Three-phase Motor Control Timer Function
Under development
This document is under development and its contents are subject to change.
Figure 1.14.9 Triangular Wave Modulation Operation
The three-phase motor control timer function is enabled by setting the INV02 bit of INVC0 register to “1”.
When this function is selected, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are
__ ___ ___
used to control three-phase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a
dedicated dead-time timer. Figure 1.14.9 shows the example of triangular modulation waveform and
Figure 1.14.10 shows the example of sawtooth modulation waveform.
Start trigger signal
for timer A4*
Timer B2
U phase
Carrier wave
Signal wave
U phase
output signal *
mnn pp
m
U phase
U phase
U phase
INV14 = 0
Carrier wave: triangular waveform
Timer A4
one-shot pulse*
INV14 = 1
Dead time
Dead time
Transfer to three-phase
output shift register
Rewriting IDB0, IDB1 registers
* Internal signals. See the block diagram of the three-phase motor control timer function.
An example for changing PWM outputs is shown below.
(1)When INV11 = 1 (three-phase mode 1)
INV01 = 0, ICTB2 = 2
16
(timer B2 interrupt is generated at every
2’th occurrence of a timer B2 underflow), or INV01 = 1, INV00 = 1,
ICTB2=1
16
(timer B2 interrupt is generated at even-numbered
occurrences of a timer B2 underflow).
Initial timer value: TA41 = m, TA4 = m. The TA4 and TA41 registers
are modified every time a timer B2 interrupt occurs. First time,
TA41 = n, TA4 = n. Second time, TA41 = p, TA4 = p.
Initial values of IDB0 and IDB1 registers: DU0 = 1, DUB0 = 0,
DU1 = 0, DUB1 = 1.The register values are changed to DU0 = 1,
DUB0 = 0, DU1= 1 and DUB1 = 0 the third time a timer B2 interrupt
occurs.
(2)When INV11 = 0 (three-phase mode 0)
INV01 = 0, ICTB2 = 1
16
(timer B2 interrupt is generated at every occurrence
of a timer B2 underflow)
Initial timer value: TA4 = m. The TA4 register is modified each time
a timer B2 interrupt occurs. First time, TA4 = m. Second time, TA4 = n.
Third time, TA4 = n. Fourth time, TA4 = p. Fifth time, TA4 = p.
Initial values of IDB0 and IDB1 registers: DU0 = 1, DUB0 = 0, DU1 = 0,
DUB1 = 1. The register values are changed to DU0 = 1, DUB0 = 0, DU1= 1
and DUB1 = 0 the sixth time a timer B2 interrupt occurs.
TB2S bit of the
TABSR register
INV13
(INV11 = 1 (three-phase
mode 1))
Shown here is a typical waveform for the case where INVC0 = 00XX11XX
2
(X = set as suitable for the system) and INVC1 = 010XXXX0
2
.
U phase
output signal *
("L" active)
("H" active)
The value written to the TA4 register and TA41 register are inverted at odd-numbered timer A outputs.
Rev.1.00 2003.05.30 page 137
M16C/6N4 Group Three-phase Motor Control Timer Function
Under development
This document is under development and its contents are subject to change.
Figure 1.14.10 Sawtooth Wave Modulation Operation
Timer B2
U phase
Carrier wave
Signal wave
U phase
output signal *
U phase
U phase
output signal *
U phase
U phase
INV14 = 0
Carrier wave: sawtooth waveform
INV14 = 1
Transfer to three-phase
output shift register
Rewriting IDB0, IDB1 registers
* Internal signals. See the block diagram of the three-phase motor control timer function.
Shown here is a typical waveform for the case where INVC0 = 01XX110X2 (X = set as suitable for the system) and INVC1 = 010XXX002.
An example for changing PWM outputs is shown below.
Initial values of IDB0 and IDB1 registers: DU0 = 0, DUB0 = 1, DU1 = 1, DUB1 = 1.
The register values are changed to DU0 = 1, DUB0 = 0, DU1 = 1, DUB1 = 1 a timer B2 interrupt occurs.
Start trigger signal
for timer A4*
Timer A4
one-shot pulse*
Dead time
Dead time
("H" active)
("L" active)
Rev.1.00 2003.05.30 page 138
M16C/6N4 Group Serial I/O
Under development
This document is under development and its contents are subject to change.
Serial I/O
Serial I/O is configured with four channels: UART0 to UART2 and SI/O3.
UARTi (i = 0 to 2)
Each UARTi has an exclusive timer to generate a transfer clock, so they operate independently of each
other.
Figure 1.15.1 shows the block diagram of UARTi. Figures 1.15.2 shows the block diagram of the UARTi
transmit/receive.
UARTi has the following modes:
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
•
Special mode 1 (I2C mode)
•
Special mode 2
•
Special mode 3 (Bus collision detection function, IE mode)
: UART0, UART1
•
Special mode 4 (SIM mode)
: UART2
Figures 1.15.3 to 1.15.8 show the UARTi-related registers.
Refer to tables listing each mode for register setting.
Rev.1.00 2003.05.30 page 139
M16C/6N4 Group Serial I/O
Under development
This document is under development and its contents are subject to change.
Figure 1.15.1 UARTi Block Diagram
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
Clock source selection
Internal
External
CTS/RTS disabled
CTS/RTS selected
RxD
0
1 / (n0+1)
1/16
1/16
1/2
U0BRG
register
CLK
0
CTS
0
/ RTS
0
f
1SIO or
f
2SIO
f
8SIO
f
32SIO
"H"
"H"
RTS
0
CTS
0
TxD
0
(UART0)
f
1SIO or
f
2SIO
1/21/2
1/8
f
8SIO
1/4
f
32SIO
f
1SIO
f
2SIO
PCLK1=0
PCLK1=1
CLK1 to CLK0
00
2
01
2
10
2
CKDIR=0
CKDIR=1
CKPOL
CKDIR=0
CKDIR=1
CRS=1
CRS=0
CRD=0
CRD=1
RCSP=0
RCSP=1
CRD=0
CRD=1
RxD polarity
reversing circuit
Main clock, PLL clock, or ring oscillator clock
UART reception
Clock synchronous
type
UART transmission
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
Reception
control circuit
Transmission control
circuit
Transmit/
receive
unit
TxD
polarity
reversing
circuit
CLK
polarity
reversing
circuit
CTS/RTS disabled
CTS
0
from UART1
UART reception
Clock synchronous
type
RxD
1
TxD
1
(UART1)
1 / (n1+1)
1/16
1/16
1/2
U1BRG
register
CLK
1
f
1SIO or
f
2SIO
f
8SIO
f
32SIO
CLK1 to CLK0
00
2
01
2
10
2
CKDIR=0
CKDIR=1
CKPOL
CKDIR=0
CKDIR=1
CRD=0
CRD=1
CLKMD0=0
CLKMD1=0
CRS=1
CRS=0
RCSP=0
RCSP=1
CLKMD0=1
CLKMD1=1
RxD polarity
reversing circuit
Clock source selection
Internal
External
UART transmission
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
Reception
control circuit
Transmission
control circuit
Transmit/
receive
unit
TxD
polarity
reversing
circuit
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
RTS1
CTS1
Clock output
pin select CTS/RTS disabled
CTS/RTS disabled
CTS/RTS selected
CTS
0
from UART0
CTS
1
/ RTS
1
/
CTS
0
/ CLKS
1
i = 0 to 2
n
i
: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: UiMR register’s bits
CLK1 to CLK0, CKPOL, CRD, CRS: UiC0 register’s bits
CLKMD0, CLKMD1, RCSP: UCON register’s bits
RxD
2
CLK
2
CTS
2
/ RTS
2
RTS
2
CTS
2
TxD
2
(UART2)
1 / (n2+1)
1/16
1/16
1/2
U2BRG
register
f
1SIO or
f
2SIO
f
8SIO
f
32SIO
CLK1 to CLK0
00
2
01
2
10
2
CKDIR=0
CKDIR=1
CKPOL
CKDIR=0
CKDIR=1
CRS=1
CRS=0
CRD=0
CRD=1
Reception
control circuit
Transmission
control circuit
UART reception
Clock synchronous
type
UART transmission
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
RxD polarity
reversing circuit
Internal
External
Clock source selection
TxD
polarity
reversing
circuit
Transmit/
receive
unit
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
CLK
polarity
reversing
circuit
CTS/RTS disabled
CTS/RTS disabled
CTS/RTS
selected
"H"
Rev.1.00 2003.05.30 page 140
M16C/6N4 Group Serial I/O
Under development
This document is under development and its contents are subject to change.
Figure 1.15.2 UARTi Transmit/Receive Unit
SP SP
PAR
2SP
1SP
UART
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART
(9 bits)
Clock
synchronous
type
Clock
synchronous type
Data bus low-order bits
TxD
i
UARTi transmit register
PAR
disabled
PAR
enabled
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UARTi receive register
2SP
1SP UART
(7 bits)
UART
(8 bits) UART(7 bits)
UART
(9 bits)
Clock
synchronous type
Clock
synchronous type
RxDi
UART
(8 bits)
UART
(9 bits)
Data bus high-order bits
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
0000000
SP SP
PAR
"0"
Reverse
No reverse
Error signal
output circuit
RxD data
reverse circuit
Error signal output
enable
Error signal output
disable
Reverse
No reverse
Logic reverse circuit + MSB/LSB conversion circuit
Logic reverse circuit + MSB/LSB conversion circuit
PAR
enabled
PAR
disabled
UART
Clock
synchronous
type
TxD data
reverse circuit
i=0 to 2
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: UiMR register’s bits
UiERE: UiC1 register’s bit
IOPOL=1
IOPOL=0
STPS= 0
STPS= 1 PRYE=1
PRYE=0
STPS= 1
STPS
= 0 PRYE=0
PRYE=1
IOPOL=1
IOPOL=0
UiERE=1
UiERE=0
UiRB register
UiTB register
Rev.1.00 2003.05.30 page 141
M16C/6N4 Group Serial I/O
Under development
This document is under development and its contents are subject to change.
Figure 1.15.3 U0TB to U2TB Registers, U0RB to U2RB Registers, and U0BRG to U2BRG Registers
b7
(b15)
(b15)
Symbol Address After reset
U0RB 03A7
16
-03A6
16
Indeterminate
U1RB 03AF
16
-03AE
16
Indeterminate
U2RB 01FF
16
-01FE
16
Indeterminate
b7 b0
(b8) b7 b0
UARTi receive buffer register (i = 0 to 2)
Function
Bit name
Bit
symbol
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note 2: When the UiMR register’s SMD2 to SMD0 bits = 000
2
(serial I/O disabled) or the UiC1 register’s RE bit = 0 (reception disabled), all of the SUM,
PER, FER and OER bits are set to "0" (no error). The SUM bit is set to "0" (no error) when all of the PER, FER and OER bits are = 0 (no error).
Also, the PER and FER bits are set to "0" by reading the lower byte of the UiRB register.
Note 1: The ABT bit is set to "0" by writing "0" in a program. (Writing "1" has no effect.)
OER
FER
PER
SUM
Overrun error flag (Note 2)
Framing error flag (Note 2)
Parity error flag (Note 2)
Error sum flag (Note 2)
0 : No overrun error
1 : Overrun error found
.
Receive data (D
7
to D
0
)
ABT Arbitration lost detecting
flag (Note 1)
0 : Not detected
1 : Detected
UARTi bit rate generator (i = 0 to 2)(Notes 1, 2)
b0
Symbol Address After reset
U0BRG 03A1
16
Indeterminate
U1BRG 03A9
16
Indeterminate
U2BRG 01F9
16
Indeterminate
Function
Assuming that set value = n, UiBRG divides the count source
by n + 1 00
16
to FF
16
Setting range
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
b7 b0
(b8)
b7 b0
UARTi transmit buffer register (i = 0 to 2)(Note)
Function
Transmit data
Nothing is assigned When write, set to "0".
.
When read, their contents are indeterminate.
Nothing is assigned When write, set to "0".
When read, their contents are indeterminate.
.
Symbol Address After reset
U0TB 03A3
16
-03A2
16
Indeterminate
U1TB 03AB
16
-03AA
16
Indeterminate
U2TB 01FB
16
-01FA
16
Indeterminate
RW
Note: Use MOV instruction to write to this register.
WO
RW
RW
RO
RO
RO
RO
RO
(b7-b0)
(b10-b9)
RW
WO
Receive data (D
8
)RO
(b8)
Rev.1.00 2003.05.30 page 142
M16C/6N4 Group Serial I/O
Under development
This document is under development and its contents are subject to change.
Figure 1.15.4 U0MR to U2MR Registers and U0C0 to U2C0 Registers
UARTi transmit/receive mode register (i = 0 to 2)
Symbol Address After reset
U0MR to U2MR 03A0
16
, 03A8
16
, 01F8
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol RW
CKDIR
SMD1
SMD0 Serial I/O mode select bit
(Note 1)
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
Parity enable bit
0 : Internal clock
1 : External clock (Note 3)
Stop bit length select bit
Odd/even parity select bit
TxD, RxD I/O polarity
reverse bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
0 1 0 : I
2
C mode
1 0 0 : UART mode transfer data 7-bit long
1 0 1 : UART mode transfer data 8-bit long
1 1 0 : UART mode transfer data 9-bit long
Must not be set except above
b2 b1 b0
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : No reverse
1 : Reverse
Function
Note 3: Set the corresponding port direction bit for each CLKi pin to "0" (input mode).
Note 1: To receive data, set the corresponding port direction bit for each RxDi pin to "0" (input mode).
Note 2: Set the corresponding port direction bit for SCL and SDA pins to "0" (input mode).
UARTi transmit/receive control register 0 (i = 0 to 2)
Symbol Address After reset
U0C0 to U2C0 03A4
16
, 03AC
16
, 01FC
16
00001000
2
b7 b6 b5 b4 b3 b2 b1 b0
Function
TXEPT
CLK1
CLK0
CRS
CRD
NCH
CKPOL
BRG count source
select bit
Transmit register empty
flag
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
CLK polarity select bit
CTS/RTS function
select bit
CTS/RTS disable bit
Data output select bit
(Note 3)
0 0 : f
1SIO
or f
2SIO
is selected
0 1 : f
8SIO
is selected
1 0 : f
32SIO
is selected
1 1 : Must not be set
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
(transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6
0
, P6
4
and P7
3
can be used as I/O ports)
0 : TxDi/SDAi and SCLi pins are CMOS output
1 : TxDi/SDAi and SCLi pins are N channel open-drain output
UFORM Transfer format select bit
(Note 4)
Effective when CRD = 0
0 : CTS function is selected (Note 2)
1 : RTS function is selected
Bit name
Bit
symbol
Note 2: Set the corresponding port direction bit for each CTSi pin to "0" (input mode).
Note 3: SCL
2
/P7
1
is N channel open-drain output. Cannot be set to the CMOS output. Set the NCH bit of the U2C0 register to "0".
Note 4: Effective for clock synchronous serial I/O mode and UART mode transfer data 8-bit long.
Note 1: CTS
1
/RTS
1
can be used when the UCON register’s CLKMD1 bit = 0 (only CLK1 output) and the UCON register’s RCSP bit = 0
(CTS
0
/RTS
0
not separated).
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
(Note 2)
(Note 1)
Rev.1.00 2003.05.30 page 143
M16C/6N4 Group Serial I/O
Under development
This document is under development and its contents are subject to change.
Figure 1.15.5 U0C1 to U2C1 Registers
UARTj transmit/receive control register 1 (j = 0, 1)
Symbol Address After reset
U0C1, U1C1 03A5
16
,03AD
16
00000010
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol RW
Function
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer empty
flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in UjTB register
1 : No data present in UjTB register
0 : Reception disabled
1 : Reception enabled
0 : No data present in UjRB register
1 : Data present in UjRB register
Nothing is assigned. When write, set to "0".
When read, these contents are "0".
UART2 transmit/receive control register 1
Symbol Address After reset
U2C1 01FD
16
00000010
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol Function
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer empty
flag
0 : Transmission disabled
1 : Transmission enabled
0 : Reception disabled
1 : Reception enabled
U2IRS UART2 transmit interrupt
cause select bit
0 : Transmit buffer empty (TI = 1)
1 : Transmit is completed (TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Data logic select bit 0 : No reverse
1 : Reverse
U2LCH
U2ERE Error signal output
enable bit
0 : Output disabled
1 : Output enabled
Data logic select bit 1 : Reverse
UjLCH
UjERE Error signal output
enable bit
0 : Output disabled
1 : Output enabled
RW
RW
RW
RW
RO
RO
RW
RW
RW
RW
RW
RW
RW
RO
RO
(b5-b4)
0 : Data present in U2TB register
1 : No data present in U2TB register
0 : No data present in U2RB register
1 : Data present in U2RB register
0 : No reverse
Rev.1.00 2003.05.30 page 144
M16C/6N4 Group Serial I/O
Under development
This document is under development and its contents are subject to change.
Figure 1.15.6 UCON Register and U0SMR to U2SMR Registers
Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register’s CKDIR bit = 0 (internal clock)
UART transmit/receive control register 2
Symbol Address After reset
UCON 03B0
16
X0000000
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol RW
Function
CLKMD0
CLKMD1
UART0 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
UART1 continuous
receive mode enable bit
UART1 CLK/CLKS
select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins function
selected
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
U0IRS
U1IRS
U0RRM
U1RRM
UART1 CLK/CLKS
select bit 1 (Note)
Effective when CLKMD1 = 1
0 : Clock output from CLK1
1 : Clock output from CLKS1
UARTi special mode register (i = 0 to 2)
Symbol Address After reset
U0SMR to U2SMR 01EF
16
, 01F3
16
, 01F7
16
X0000000
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit
symbol Function
ABSCS
ACSE
SSS
I
2
C mode select bit
Bus busy flag 0 : STOP condition detected
1 : START condition detected (busy)
Bus collision detect
sampling clock select bit
Arbitration lost detecting
flag control bit
0 : Other than I
2
C mode
1 : I
2
C mode
0 : Update per bit
1 : Update per byte
IICM
ABC
BBS
0 : Not synchronized to RxD
i
1 : Synchronized to RxD
i
(Note 3)
Set to "0"
Transmit start condition
select bit
0 : Rising edge of transfer clock
1 : Underflow signal of timer Aj (Note 2)
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
Note 1: The BBS bit is set to "0" by writing "0" in a program. (Writing "1" has no effect.).
Note 2: Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer A0 in UART2.
Note 3: When a transfer begins, the SSS bit is set to "0" (Not synchronized to RxD
i
).
(Note1)
RCSP Separate UART0
CTS/RTS bit
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS
0
supplied from the P6
4
pin)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
RW
RW
RW
RW
RW
RW
RW
(b7)
RW
RW
RW
RW
RW
RW
RW
RW
(b7)
(b3) Reserved bit
0
Bit name
Rev.1.00 2003.05.30 page 145
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This document is under development and its contents are subject to change.
Figure 1.15.7 U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers
UARTi special mode register 2 (i = 0 to 2)
Symbol Address After reset
U0SMR2 to U2SMR2 01EE
16
, 01F2
16
, 01F6
16
X0000000
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol RW
Function
STAC
SWC2
SDHI
I C mode select bit 2
SCL wait output bit 0 : Disabled
1 : Enabled
SDA output stop bit
UARTi initialization bit
Clock-synchronous bit
Refer to "Table 1.15.11 I2C Mode FUnctions"
0 : Disabled
1 : Enabled
IICM2
CSC
SWC
ALS 0 : Disabled
1 : Enabled
SDA output disable bit
SCL wait output bit 2
0: Enabled
1: Disabled (high-impedance)
0 : Disabled
1 : Enabled
0: Transfer clock
1: "L" output
2
UARTi special mode register 3 (i = 0 to 2)
Symbol Address After reset
U0SMR3 to U2SMR3 01ED
16
, 01F1
16
, 01F5
16
000X0X0X
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol Function
DL2
SDAi digital delay
setup bit
(Notes 1, 2)
DL0
DL1
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
Nothing is assigned When write, set to "0". .
When read, its content is indeterminate.
b7 b6 b5
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
0 : Without clock delay
1 : With clock delay
Clock phase set bit
0 : CLKi is CMOS output
1 : CLKi is N channel open-drain output
Clock output select bit
CKPH
NODC
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I
2
C mode. In other than I
2
C
mode, set these bits to "000
2
" (no delay).
Note 2 : The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
RW
RW
RW
RW
RW
RW
RW
(b7)
RW
RW
RW
RW
RW
RW
(b0)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b2)
(b4)
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This document is under development and its contents are subject to change.
Figure 1.15.8 U0SMR4 to U2SMR4 Registers
UARTi special mode register 4 (i = 0 to 2)
Symbol Address After reset
U0SMR4 to U2SMR4 01EC
16
, 01F0
16
, 01F4
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol RW
Function
ACKC
SCLHI
SWC9
Start condition
generate bit (Note)
Stop condition
generate bit (Note)
0 : Clear
1 : Start
SCL,SDA output
select bit
ACK data bit
Restart condition
generate bit (Note)
0 : Clear
1 : Start
0 : Clear
1 : Start
STAREQ
RSTAREQ
STPREQ
ACKD
0 : Start and stop conditions not output
1 : Start and stop conditions output
SCL output stop
enable bit
ACK data output
enable bit
0 : Disabled
1 : Enabled
0 : ACK
1 : NACK
0 : Serial I/O data output
1 : ACK data output
Note: Set to "0" when each condition is generated.
STSPSEL
0 : SCL "L" hold disabled
1 : SCL "L" hold enabled
SCL wait bit 3
RW
RW
RW
RW
RW
RW
RW
RW
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M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode)
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This document is under development and its contents are subject to change.
Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.15.1
lists the specifications of the clock synchronous serial I/O mode. Table 1.15.2 lists the registers used in
clock synchronous serial I/O mode and the register values set.
Table 1.15.1 Clock Synchronous Serial I/O Mode Specifications
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • UiMR register’s CKDIR bit = 0 (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• CKDIR bit = 1 (external clock ) : Input from CLKi pin
Transmission, reception control
_______ _______ _______ _______
• Selectable from CTS function, RTS function or CTS/RTS function disabled
Transmission start condition
• Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register = 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
_______ _______
_ If CTS function is selected, input on the CTSi pin = L
Reception start condition • Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register = 1 (reception enabled)
_ The TE bit of UiC1 register = 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in the UiTB register)
•For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection • Overrun error (Note 3)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Select function • CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the rising or
the falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic
This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
_______ _______
• Separate CTS/RTS pins (UART0)
_________ _________
CTS0 and RTS0 are input/output from separate pins
Interrupt request
generation timing
i = 0 to 2
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register’s CKPOL bit = 1 (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
Note 2:
The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
Note 3:
If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Rev.1.00 2003.05.30 page 148
M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode)
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This document is under development and its contents are subject to change.
Table 1.15.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register Bit Function
UiTB
(Note 1)
0 to 7 Set transmission data
UiRB
(Note 1)
0 to 7 Reception data can be read
OER Overrun error flag
UiBRG 0 to 7 Set a transfer rate
UiMR
(Note 1)
SMD2 to SMD0 Set to “0012”
CKDIR Select the internal clock or external clock
IOPOL Set to “0”
UiC0 CLK1 to CLK0 Select the count source for the UiBRG register
CRS
_______ _______
Select CTS or RTS to use
TXEPT Transmit register empty flag
CRD
_______ _______
Enable or disable the CTS or RTS function
NCH Select TxDi pin output mode
CKPOL Select the transfer clock polarity
UFORM Select the LSB first or MSB first
UiC1 TE Set this bit to “1” to enable transmission/reception
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 2) Select the source of UART2 transmit interrupt
U2RRM (Note 2) Set this bit to “1” to use continuous receive mode
UiLCH Set this bit to “1” to use inverted data logic
UiERE Set to “0”
UiSMR 0 to 7 Set to “0”
UiSMR2 0 to 7 Set to “0”
UiSMR3 0 to 2 Set to “0”
NODC Select clock output mode
4 to 7 Set to “0”
UiSMR4 0 to 7 Set to “0”
UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM Set this bit to “1” to use continuous receive mode
CLKMD0 Select the transfer clock output pin when CLKMD1 = 1
CLKMD1 Set this bit to “1” to output UART1 transfer clock from two pins
RCSP
_________
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
7 Set to “0”
i = 0 to 2
Note 1: Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
synchronous serial I/O mode.
Note 2: Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Rev.1.00 2003.05.30 page 149
M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode)
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This document is under development and its contents are subject to change.
Table 1.15.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table
1.15.3 shows pin functions for the case where the multiple transfer clock output pin select function is
deselected. Table 1.15.4 lists the P64 pin functions during clock synchronous serial I/O mode.
Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi
pin outputs an “H”. (If the N channel open-drain output is selected, this pin is in a high-impedance state.)
Figure 1.15.9 shows the transmit/receive timings during clock synchronous serial I/O mode.
Table 1.15.3 Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Table 1.15.4 P64 Pin Functions
TxDi
(P63, P67, P70)
RxDi
(P62, P66, P71)
CLKi
(P61, P65, P72)
_________________
CTSi/RTSi
(P60, P64, P73)
Pin name Function Method of selection
Serial data output
Serial data input
Transfer clock output
Transfer clock input
________
CTS input
________
RTS output
I/O port
(Outputs dummy data when performing reception only)
PD6 register’s PD6_2 bit = 0, PD6_6 bit = 0
PD7 register’s PD7_1 bit = 0
(Can be used as an input port when performing transmission only)
UiMR register’s CKDIR bit = 0
UiMR register’s CKDIR bit = 1
PD6 register’s PD6_1 bit = 0, PD6_5 bit = 0
PD7 register’s PD7_2 bit = 0
UiC0 register’s CRD bit = 0
UiC0 register’s CRS bit = 0
PD6 register’s PD6_0 bit = 0, PD6_4 bit = 0
PD7 register’s PD7_3 bit = 0
UiC0 register’s CRD bit = 0
UiC0 register’s CRS bit = 1
UiC0 register’s CRD bit = 1
Note 1:
_________ _________
In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0 enabled) and the U0C0
_________
register’s CRS bit to “1” (RTS0 selected).
Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
• High if the U1C0 register’s CLKPOL bit = 0
• Low if the U1C0 register’s CLKPOL bit = 1
Bit set value
Pin function U1C0 register UCON register PD6 register
CRD CRS RCSP CLKMD1 CLKMD0 PD6_4
P641 - 0 0 - Input: 0, Output: 1
_________
CTS10000 - 0
_________
RTS10100 - -
_________
CTS0 (Note 1) 0 0 1 0 - 0
CLKS1- - - 1 (Note 2) 1 -
Rev.1.00 2003.05.30 page 150
M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode)
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This document is under development and its contents are subject to change.
Figure 1.15.9 Transmit and Receive Operation
(1) Example of transmit timing (when internal clock is selected)
(2) Example of receive timing (when external clock is selected)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Tc
T
CLK
Stopped pulsing because the TE bit = 0
Write data to the UiTB register
Tc = T
CLK
= 2(n + 1) / fj
fj: frequency of UiBRG count source (f
1SIO
, f
2SIO
, f
8SIO
, f
32SIO
)
n: value set to UiBRG register
i = 0 to 2
Transfer clock
UiC1 register
TE bit
UiC1 register
TI bit
CLK
i
TxD
i
"H"
"L"
"0"
"1"
"0"
"1"
"0"
"1"
CTS
i
"0"
"1"
Stopped pulsing because CTS
i
= H
1 / fEXT
Write dummy data to UiTB register
UiC1 register
TE bit
UiC1 register
TI bit
CLKi
RxDi
UiC1 register
RI bit
RTSi
"H"
"L"
"0"
"1"
"0"
"1"
"0"
"1"
UiC1 register
RE bit
"0"
"1"
Receive data is taken in
Transferred from UiTB register to UARTi transmit register
Read out from UiRB register
f
EXT
: frequency of external clock
Transferred from UARTi receive register
to UiRB register
SiRIC register
IR bit
"0"
"1"
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
Transferred from UiTB register to UARTi transmit register
Make sure the following conditions are met when input
to the CLKi pin before receiving data is high:
UiC1 register TE bit = 1 (transmission enabled)
UiC1 register RE bit = 1 (reception enabled)
Write dummy data to the UiTB register
The above timing diagram applies to the case where the register bits are set as follows:
UiMR register CKDIR bit = 0 (internal clock)
UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
UiRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Set to "0" when interrupt request is
accepted, or set to "0" in a program
Set to "0" when interrupt request is accepted, or set to "0" in a program
The above timing diagram applies to the case where the register bits are set
as follows:
UiMR register CKDIR bit = 1 (external clock)
UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive
data taken in at the rising edge of the transfer clock)
UiC0 register
TXEPT bit
SiTIC register
IR bit
Even if the reception is completed, the RTS
does not change. The RTS becomes "L"
when the RI bit changes to "0" from "1".
Rev.1.00 2003.05.30 page 151
M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode)
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This document is under development and its contents are subject to change.
(a) CLK Polarity Select Function
Use the UiC0 register (i = 0 to 2)’s CKPOL bit to select the transfer clock polarity. Figure 1.15.10
shows the polarity of the transfer clock.
Figure 1.15.10 Transfer Clock Polarity
(b) LSB First/MSB First Select Function
Use the UiC0 register (i = 0 to 2)’s UFORM bit to select the transfer format. Figure 1.15.11 shows the
transfer format.
Figure 1.15.11 Transfer Format
(2) When the UiC0 register’s CKPOL bit = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
D1D2D3D4D5D6D7
D1D2D3D4D5D6D7
D0
D0
TXDi
RXDi
CLKi
(1) When the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
D1D2D3D4D5D6D7D0
D1D2D3D4D5D6D7D0
TXDi
RXDi
CLKi
* This applies to the case where the UiC0 register’s UFORM bit = 0
(LSB first) and UiC1 register’s UiLCH bit = 0 (no reverse).
Note 1: When not transferring, the CLKi pin outputs a high signal.
Note 2: When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
(Note 1)
(Note 2)
(1) When UiC0 register’s UFORM bit = 0 (LSB first)
D0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
T
X
D
i
R
X
D
i
CLK
i
(2) When UiC0 register’s UFORM bit = 1 (MSB first)
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
T
X
D
i
R
X
D
i
CLK
i
* This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UiC1 register’s
UiLCH bit = 0 (no reverse).
i = 0 to 2
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This document is under development and its contents are subject to change.
(c) Continuous Receive Mode
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register’s TI bit is set to “0”
(data present in UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not
write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON
register bit 2 and bit 3, respectively, and the U2RRM bit is the U2C1 register bit 5.
(d) Serial Data Logic Switching Function
When the UiC1 register (i = 0 to 2)’s UiLCH bit = 1 (reverse), the data written to the UiTB register has
its logic reversed before being transmitted. Similarly, the received data has its logic reversed when
read from the UiRB register.
Figure 1.15.12 shows serial data logic.
Figure
1.15.12
Serial Data Logic Switching
(e) Transfer Clock Output From Multiple Pins (UART1)
Use the UCON register’s CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins.
Figure 1.15.13 shows the transfer clock output from the multiple pins function usage. This function can
be used when the selected transfer clock for UART1 is an internal clock.
Figure 1.15.13 Transfer Clock Output From Multiple Pins
D0 D1 D2 D3 D4 D5 D6 D7
Transfer clock
TxD
i
(no reverse)
"H"
"L"
"H"
"L"
TxD
i
(reverse)
D0 D1 D2 D3 D4 D5 D6 D7
"H"
"L"
(1) When the UiC1 register’s UiLCH bit = 0 (no reverse)
Transfer clock
"H"
"L"
(2) When the UiC1 register’s UiLCH bit = 1 (reverse)
* This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data
taken in at the rising edge of the transfer clock) and the UFORM
bit = 0 (LSB first).
i = 0 to 2
Microcomputer
T
X
D
1
(P6
7
)
CLKS
1
(P6
4
)
CLK
1
(P6
5
)IN
CLK
IN
CLK
* This applies to the case where the U1MR register’s CKDIR bit
= 0 (internal clock) and the UCON register’s CLKMD1 bit = 1
(transfer clock output from multiple pins).
Transfer enabled
when the UCON
register’s
CLKMD0 bit = 0
Transfer enabled
when the UCON
register’s
CLKMD0 bit = 1
Rev.1.00 2003.05.30 page 153
M16C/6N4 Group Serial I/O (Clock Synchronous Serial I/O Mode)
Under development
This document is under development and its contents are subject to change.
_______ _______
(f) CTS/RTS Separate Function (UART0)
_______ _______ _______ _______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
_______
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
_______ _______
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
_______
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
_______
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
_______ _______ _______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
_______ _______
Figure 1.15.14 shows CTS/RTS separate function usage.
_______ _______
Figure 1.15.14 CTS/RTS Separate Function
Microcomputer
T
X
D
0
(P6
3
)
R
X
D
0
(P6
2
)
IN
OUT
CTS
RTS
CTS
0
(P6
4
)
RTS
0
(P6
0
)
IC
CLK
0
(P6
1
)CLK
Rev.1.00 2003.05.30 page 154
M16C/6N4 Group Serial I/O (UART Mode)
Under development
This document is under development and its contents are subject to change.
Item Specification
Transfer data format • Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
Transfer clock • UiMR register’s CKDIR bit = 0 (internal clock) : fj/ 16(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• CKDIR bit = 1 (external clock) : fEXT/16(n+1)
fEXT: Input from CLKi pin. n :Setting value of UiBRG register 0016 to FF16
Transmission, reception control
_______ _______ _______ _______
• Selectable from CTS function, RTS function or CTS/RTS function disabled
Transmission start condition • Before transmission can start, the following requirements must be met
_ The TE bit of UiC1 register = 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
_______ _______
_ If CTS function is selected, input on the CTSi pin = L
Reception start condition • Before reception can start, the following requirements must be met
_ The RE bit of UiC1 register = 1 (reception enabled)
_ Start bit detection
•For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 1) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection • Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and character
bits does not match the number of 1’s set
• Error sum flag
This flag is set to “1” when any of the overrun, framing, and parity errors is encountered
Select function • LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch
This function reverses the polarities of the TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
_______ _______
• Separate CTS/RTS pins (UART0)
_________ _________
CTS0 and RTS0 are input/output from separate pins
i = 0 to 2
Note 1:
The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
Note 2:
If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.15.5 lists the specifications of the UART mode. Table 1.15.6 lists the registers used
in UART mode and the register values set.
Table 1.15.5 UART Mode Specifications
Interrupt request
generation timing
Rev.1.00 2003.05.30 page 155
M16C/6N4 Group Serial I/O (UART Mode)
Under development
This document is under development and its contents are subject to change.
Table 1.15.6 Registers to Be Used and Settings in UART Mode
Register Bit Function
UiTB 0 to 8 Set transmission data (Note 1)
UiRB 0 to 8 Reception data can be read (Note 1)
OER,FER,PER,SUM
Error flag
UiBRG 0 to 7 Set a transfer rate
UiMR SMD2 to SMD0 Set these bits to “1002” when transfer data is 7-bit long
Set these bits to “1012” when transfer data is 8-bit long
Set these bits to “1102” when transfer data is 9-bit long
CKDIR Select the internal clock or external clock
STPS Select the stop bit
PRY, PRYE Select whether parity is included and whether odd or even
IOPOL Select the TxD/RxD input/output polarity
UiC0 CLK0, CLK1 Select the count source for the UiBRG register
CRS
_______ _______
Select CTS or RTS to use
TXEPT Transmit register empty flag
CRD
_______ _______
Enable or disable the CTS or RTS function
NCH Select TxDi pin output mode
CKPOL Set to “0”
UFORM LSB first or MSB first can be selected when transfer data is 8-bit long. Set this
bit to “0” when transfer data is 7- or 9-bit long.
UiC1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 2) Select the source of UART2 transmit interrupt
U2RRM (Note 2) Set to “0”
UiLCH Set this bit to “1” to use inverted data logic
UiERE Set to “0”
UiSMR 0 to 7 Set to “0”
UiSMR2 0 to 7 Set to “0”
UiSMR3 0 to 7 Set to “0”
UiSMR4 0 to 7 Set to “0”
UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM Set to “0”
CLKMD0 Invalid because CLKMD1 = 0
CLKMD1 Set to “0”
RCSP
_________
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
7 Set to “0”
i = 0 to 2
Note 1: The bits used for transmit/receive data are as follows:
• Bit 0 to bit 6 when transfer data is 7-bit long
• Bit 0 to bit 7 when transfer data is 8-bit long
• Bit 0 to bit 8 when transfer data is 9-bit long.
Note 2: Set the U0C1 and U1C1 registers bit 4 to bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are included in the UCON register.
Rev.1.00 2003.05.30 page 156
M16C/6N4 Group Serial I/O (UART Mode)
Under development
This document is under development and its contents are subject to change.
Table 1.15.7 lists the functions of the input/output pins during UART mode. Table 1.15.8 lists the P64 pin
functions during UART mode. Note that for a period from when the UARTi operation mode is selected to
when transfer starts, the TxDi pin outputs an “H”. (If the N channel open-drain output is selected, this pin
is in a high-impedance state.)
Figure 1.15.15 shows the typical transmit timings in UART mode. Figure 1.15.16 shows the typical receive
timing in UART mode.
Table 1.15.7 I/O Pin Functions
i = 0 to 2
Table 1.15.8 P64 Pin Functions
TxDi
(P63, P67, P70)
RxDi
(P62, P66, P71)
CLKi
(P61, P65, P72)
________ ________
CTSi/RTSi
(P60, P64, P73)
Pin name Function Method of selection
Serial data output
Serial data input
I/O port
Transfer clock input
_______
CTS input
________
RTS output
I/O port
(Outputs dummy data when performing reception only)
PD6 register’s PD6_2 bit = 0, PD6_6 bit = 0
PD7 register’s PD7_1 bit = 0
(Can be used as an input port when performing transmission only)
UiMR register’s CKDIR bit = 0
UiMR register’s CKDIR bit = 1
PD6 register’s PD6_1 bit = 0, PD6_5 bit = 0
PD7 register’s PD7_2 bit = 0
UiC0 register’s CRD bit = 0
UiC0 register’s CRS bit = 0
PD6 register’s PD6_0 bit = 0, PD6_4 bit = 0
PD7 register’s PD7_3 bit = 0
UiC0 register’s CRD bit = 0
UiC0 register’s CRS bit = 1
UiC0 register’s CRD bit = 1
Note :
_________ _________
In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0 enabled) and the U0C0
_________
register’s CRS bit to “1” (RTS0 selected).
Bit set value
Pin function U1C0 register UCON register PD6 register
CRD CRS RCSP CLKMD1 PD6_4
P641 - 0 0 Input: 0, Output: 1
_________
CTS10000 0
_________
RTS10100 -
_________
CTS0 (Note) 0 0 1 0 0
Rev.1.00 2003.05.30 page 157
M16C/6N4 Group Serial I/O (UART Mode)
Under development
This document is under development and its contents are subject to change.
(1) Example of transmit timing when transfer data is 8-bit long (parity enabled, one stop bit)
(2) Example of transmit timing when transfer data is 9-bit long (parity disabled, two stop bits)
Figure 1.15.15 Transmit Operation
Start
bit
Parity
bit
TxDi
CTSi
"1"
"0"
"1"
"L"
"H"
"0"
"1"
Tc = 16 (n + 1) / fj or 16 (n + 1) / f
EXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
i = 0 to 2
"0"
"1"
TxDi
"0"
"1"
"0"
"1"
"0"
"1"
Transfer clock
Tc
"0"
"1"
Tc
Transfer clock
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PD
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
SP ST PSP D
0
D
1
ST
Stop
bit
Start
bit
The transfer clock stops momentarily as CTSi is "H" when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to "L".
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST SP
D
8
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST D
8
D
0
D
1
ST
SPSP
Stop
bit
Stop
bit
"0"
SP
Stopped pulsing
because the TE bit
= 0
Write data to the UiTB register
UiC1 register
TE bit
UiC1 register
TI bit
UiC0 register
TXEPT bit
SiTIC register
IR bit
Transferred from UiTB register to UARTi transmit register
The above timing diagram applies to the case where the register bits are set
as follows:
UiMR register PRYE bit = 1 (parity enabled)
UiMR register STPS bit = 0 (1 stop bit)
UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
UilRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Set to "0" when interrupt request is accepted, or set to "0" in a program
UiC1 register
TE bit
UiC1 register
TI bit
UiC0 register
TXEPT bit
SiTIC register
IR bit
Set to "0" when interrupt request is accepted, or set to "0" in a program
Write data to the UiTB register
Transferred from UiTB register to UARTi
transmit register
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
i = 0 to 2
The above timing diagram applies to the case where the register bits are set
as follows:
UiMR register PRYE bit = 0 (parity disabled)
UiMR register STPS bit = 1 (2 stop bits)
UiC0 register CRD bit = 1 (CTS/RTS disabled)
UilRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Rev.1.00 2003.05.30 page 158
M16C/6N4 Group Serial I/O (UART Mode)
Under development
This document is under development and its contents are subject to change.
• Example of receive timing when transfer data is 8-bit long (parity disabled, one stop bit)
Figure 1.15.16 Receive Operation
(a) LSB First/MSB First Select Function
As shown in Figure 1.15.17, use the UiC0 register’s UFORM bit to select the transfer format. This
function is valid when transfer data is 8-bit long.
Figure 1.15.17 Transfer Format
The above timing diagram applies to the case where the register bits are set as follows:
UiMR register PRYE bit = 0 (parity disabled)
UiMR register STPS bit = 0 (1 stop bit)
UiC0 register CRD bit = 0 (CTS
i
/RTS
i
enabled), CRS bit = 1 (RTS
i
selected)
i = 0 to 2
"1"
"0"
"0"
"1"
"H"
"L"
"0"
"1"
UiBRG count
source
RxD
i
Transfer clock
RTS
i
UiC1 register
RE bit
UiC1 register
RI bit
SiRIC register
IR bit
D
0
Start bit
Sampled "L"
Stop bit
Reception triggered when transfer clock
is generated by falling edge of start bit
Set to "0" when interrupt request is accepted, or set to "0" in a program.
Receive data taken in
D
7
D
1
Transferred from UARTi receive
register to UiRB register
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (transmit data output
at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the UiC1 register’s UiLCH bit = 0 (no reverse), UiMR register’s STPS bit = 0 (1 stop bit)
and UiMR register’s PRYE bit = 1 (parity enabled).
(1) When UiC0 register’s UFORM bit = 0 (LSB first)
(2) When UiC0 register’s UFORM bit = 1 (MSB first)
D1D2D3D4D5D6SPD0
D1D2D3D4D5D6SPD0
TXDi
RXDi
CLKi
D6D5D4D3D2D1D0
D7
TXDi
RXDi
CLKi
ST
ST
D7P
D7P
SP
SP
ST
ST
P
P
D6D5D4D3D2D1D0
D7
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
Rev.1.00 2003.05.30 page 159
M16C/6N4 Group Serial I/O (UART Mode)
Under development
This document is under development and its contents are subject to change.
Figure 1.15.19 TXD and RXD I/O Polarity Inverse
(b) Serial Data Logic Switching Function
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the UiRB register.
Figure 1.15.18 shows serial
data logic.
Figure 1.15.18 Serial Data Logic Switching
(c) TxD and RxD I/O Polarity Inverse Function
This function inverses the polarities of the TxDi pin output and RxDi pin input. The logic levels of all
input/output data (including the start, stop and parity bits) are inversed. Figure 1.15.19 shows the TxD
and RxD input/output polarity inverse.
Transfer clock
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
TxDi
(no reverse)
TxDi
(reverse)
SPST D3 D4 D5 D6 D7 PD0 D1 D2
(1) When the UiC1 register’s UiLCH bit = 0 (no reverse)
(2) When the UiC1 register’s UiLCH bit = 1 (reverse)
Transfer clock
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
Note: This applies to the case where the UiC0 register s CKPOL bit = 0 (transmit data
output at the falling edge of the transfer clock), the UiC0 register’s UFORM bit
= 0 (LSB first), the UiMR register’s STPS bit = 0 (1 stop bit) and UiMR register’s
PRYE bit = 1 (parity enabled).
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
(1) When the UiMR register’s IOPOL bit = 0 (no reverse)
(2) When the UiMR register’s IOPOL bit = 1 (reverse)
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
SPST D3 D4 D5 D6 D7 PD0 D1 D2
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
SPST D3 D4 D5 D6 D7 PD0 D1 D2
Transfer clock
TxDi
(no reverse)
RxDi
(no reverse)
Transfer clock
TxDi
(reverse)
RxDi
(reverse)
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
Note: This applies to the case where the UiC0 register’s UFORM bit = 0 (LSB first),
the UiMR register’s STPS bit = 0 (1 stop bit) and the UiMR register’s PRYE
bit = 1 (parity enabled).
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
Rev.1.00 2003.05.30 page 160
M16C/6N4 Group Serial I/O (UART Mode)
Under development
This document is under development and its contents are subject to change.
_______ _______
(d) CTS/RTS Separate Function (UART0)
________ ________ ________ ________
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
_______
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
_______ _______
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
_______
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
_______
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
_______ _______ _______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
_______ _______
Figure 1.15.20 shows CTS/RTS separate function usage.
_______ _______
Figure 1.15.20 CTS/RTS Separate Function
Microcomputer
T
X
D
0
(P6
3
)
R
X
D
0
(P6
2
)
IN
OUT
CTS
RTS
CTS
0
(P6
4
)
RTS
0
(P6
0
)
IC
Rev.1.00 2003.05.30 page 161
M16C/6N4 Group Serial I/O (Special Modes)
Under development
This document is under development and its contents are subject to change.
Special Mode 1 (I2C Mode)
I2C mode is provided for use as a simplified I2C interface compatible mode. Table 1.15.9 lists the
specifications of the I2C mode. Figure 1.15.21 shows the block diagram for I2C mode. Table 1.15.10 lists
the registers used in the I2C mode and the register values set. Table 1.15.11 lists the features in I2C
mode. Figure 1.15.22 shows SCLi timing.
As shown in Table 1.15.11, the microcomputer is placed in I2C mode by setting the SMD2 to SMD0 bits to
“0102” and the IICM bit to “1”. Because SDAi transmit output has a delay circuit attached, SDAi output
does not change state until SCLi goes low and remains stably low.
Table 1.15.9 I2C Mode Specifications
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • During master
UiMR register’s CKDIR bit = 0 (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• During slave
CKDIR bit = 1 (external clock ) : Input from SCLi pin
Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register = 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
Reception start condition • Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register = 1 (reception enabled)
_ The TE bit of UiC1 register = 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
Error detection • Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 8th bit of the next data
Select function • Arbitration lost
Timing at which the UiRB register’s ABT bit is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
Interrupt request
generation timing
i = 0 to 2
Note 1: When an external clock is selected, the conditions must be met while the external clock is in the high
state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC
register does not change.
Rev.1.00 2003.05.30 page 162
M16C/6N4 Group Serial I/O (Special Modes)
Under development
This document is under development and its contents are subject to change.
Figure 1.15.21 I2C Mode Block Diagram
CLK
control
Falling edge
detection
External
clock
Internal clock
Start/stop condition
detection
interrupt request
Start condition
detection
Stop condition
detection
Reception register
Bus
busy
Transmission
register
Arbitration
Noise
Filter
SDAi
SCLi
UARTi
D
T
Q
D
T
Q
D
T
Q
NACK
ACK
UARTi
UARTi
UARTi
R
UARTi transmit,
NACK interrupt
request
UARTi receive,
ACK interrupt request,
DMA1 request
IICM=1 and
IICM2=0
S
RQ
ALS
R
S
SWC
IICM=1 and
IICM2=0
IICM2=1
IICM2=1
SWC2
SDHI
DMA0, DMA1 request
(UART1: DMA0 only)
Noise
Filter
IICM=0
IICM=1
DMA0
(UART0, UART2)
STSPSEL=0
STSPSEL=1
STSPSEL=1
STSPSEL=0
SDA
STSP
SCL
STSP
ACKC=1
ACKC=0
Q
Port register
(Note)
I/O port
9th bit falling edge
9th bit
ACKD bit
Delay
circuit
Start and stop condition generation block
This diagram applies to the case where the UiMR register’s SMD2 to SMD0 bits = 010
2
and the UiSMR register’s IICM bit = 1.
i = 0 to 2
IICM: UiSMR register’s bit
IICM2, SWC, ALS, SWC2, SDHI: UiSMR2 register’s bits
STSPSEL, ACKD, ACKC: UiSMR4 register’s bits
Note: If the IICM bit =1, the pins can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).
Rev.1.00 2003.05.30 page 163
M16C/6N4 Group Serial I/O (Special Modes)
Under development
This document is under development and its contents are subject to change.
Table 1.15.10 Registers to Be Used and Settings in I2C Mode
Register Bit Function
Master Slave
UiTB
(Note 1)
0 to 7 Set transmission data
UiRB
(Note 1)
0 to 7 Reception data can be read
8 ACK or NACK is set in this bit
ABT Arbitration lost detection flag Invalid
OER Overrun error flag
UiBRG 0 to 7 Set a transfer rate Invalid
UiMR
(Note 1)
SMD2 to SMD0 Set to “0102”
CKDIR Set to “0”Set to “1”
IOPOL Set to “0”
UiC0 CLK1, CLK0
Select the count source for the UiBRG register
Invalid
CRS Invalid because CRD = 1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Set to “1”
CKPOL Set to “0”
UFORM Set to “1”
UiC1 TE
Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 2) Invalid
U2RRM (Note 2), Set to “0”
UiLCH, UiERE
UiSMR IICM Set to “1”
ABC Select the timing at which arbitration-lost Invalid
is detected
BBS Bus busy flag
3 to 7 Set to “0”
UiSMR2 IICM2 Refer to “Table 1.15.11 I2C Mode Functions”
CSC
Set this bit to “1” to enable clock synchronization
Set to “0”
SWC
Set this bit to “1” to have SCLi output fixed to “L” at the falling edge of the 9th bit of clock
ALS Set this bit to “1” to have SDAi output Set to “0”
stopped when arbitration-lost is detected
STAC Set to “0”Set this bit to “1” to initialize UARTi at
start condition detection
SWC2 Set this bit to “1” to have SCLi output forcibly pulled low
SDHI Set this bit to “1” to disable SDAi output
7 Set to “0”
UiSMR3 0, 2, 4 and NODC Set to “0”
CKPH Refer to Table 1.15.11 I2C Mode Functions”
DL2 to DL0 Set the amount of SDAi digital delay
UiSMR4 STAREQ
Set this bit to “1” to generate start condition
Set to “0”
RSTAREQ
Set this bit to “1” to generate restart condition
Set to “0”
STPREQ
Set this bit to “1” to generate stop condition
Set to “0”
STSPSEL
Set this bit to “1” to output each condition
Set to “0”
ACKD Select ACK or NACK
ACKC Set this bit to “1” to output ACK data
SCLHI Set this bit to “1” to have SCLi output Set to “0”
stopped when stop condition is detected
SWC9 Set to “0”
Set this bit to “1” to set the SCLi to “L” hold
at the falling edge of the 9th bit of clock
IFSR0 IFSR06, ISFR07 Set to “1”
UCON U0IRS, U1IRS Invalid
2 to 7 Set to “0”
i = 0 to 2
Note 1: Not all register bits are described above. Set those bits to “0” when writing to the registers in I2C mode.
Note 2: Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register.
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No acknowledgment detection
(NACK)
Rising edge of SCLi 9th bit
Acknowledgment detection (ACK)
Rising edge of SCLi 9th bit
Rising edge of SCLi 9th bit
L
Acknowledgment detection (ACK)
Start condition detection or stop condition detection
(Refer to “Table 1.15.12 STSPSEL Bit Functions”)
UARTi reception
Falling edge of SCLi 9th bit
Delayed
SDAi input/output
SCLi input/output
- (Cannot be used in I2C mode)
200 ns
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I2C mode (Note 2)
H
UARTi reception
Falling edge of SCLi 9th bit
1st to 7th bits are stored in UiRB register
bit 6 to bit 0, with
8th bit stored in UiRB
register bit 8
UARTi transmission
Falling edge of
SCLi next to the
9th bit
Falling and rising
edges of SCLi 9th
bit
L
1st to 8th bits are
stored in UiRB register
bit 7 to bit 0 (Note 3)
Read UiRB register
bit 6 to bit 0 as bit
7 to bit 1, and bit 8
as bit 0 (Note 4)
UARTi transmission
Rising edge of
SCLi 9th bit
Falling edge of
SCLi 9th bit
H
Table 1.15.11 I2C Mode Functions
i = 0 to 2
Note 1: If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to “1” (interrupt requested). (Refer to “Precautions for Interrupts” of the Usage Notes Reference Book.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to
set the IR bit to “0” (interrupt not requested) after changing those bits.
• SMD2 to SMD0 bits in the UiMR register • IICM bit in the UiSMR register
• IICM2 bit in the UiSMR2 register • CKPH bit in the UiSMR3 register
Note 2: Set the initial value of SDAi output while the UiMR register ’s SMD2 to SMD0 bits = 0002 (serial I/O disabled).
Note 3: Second data transfer to UiRB register (rising edge of SCLi 9th bit)
Note 4: First data transfer to UiRB register (falling edge of SCLi 9th bit)
Note 5: Refer to “Figure 1.15.24 STSPSEL Bit Functions”.
Note 6: Refer to “Figure 1.15.22 Transfer to UiRB Register and Interrupt Timing”.
Note 7: When using UART0, be sure to set the IFSR06 bit in the IFSR0 register to “1” (cause of interrupt: UART0 bus collision).
When using UART1, be sure to set the IFSR07 bit in the IFSR0 register to “1” (cause of interrupt: UART1 bus collision).
Function
Clock
synchronous
serial I/O mode
(SMD2 to SMD0 =
0012, IICM = 0)
I2C mode (SMD2 to SMD0 = 0102, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
IICM2 = 1
(UART transmit/UART receive interrupt)
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
Factor of interrupt
number 6, 7 and 10
(Notes 1, 5, 7)
Factor of interrupt
number 15, 17 and 19
(Notes 1, 6)
Factor of interrupt
number 16, 18 and 20
(Notes 1, 6)
Timing for transferring
data from the UART
reception shift register
to the UiRB register
UARTi transmission
output delay
Functions of P63,
P67 and P70 pins
Functions of P62,
P66 and P71 pins
Functions of P61,
P65 and P72 pins
Noise filter width
Read RxDi and
SCLi pins levels
Initial value of TxDi
and SDAi outputs
Initial and end
value of SCLi
DMA1 factor
(Note 6)
Store received
data
Read received
data
-
UARTi transmission
Transmission started
or completed
(selected by UiIRS)
UARTi reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Not delayed
TxDi output
RxDi input
CLKi input or
output selected
15 ns
Possible when the
corresponding port
direction bit = 0
CKPOL = 0 (H)
CKPOL = 1 (L)
-
UARTi reception
UiRB register status is read directly as is
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
1st to 8th bits are stored in UiRB register bit 7 to bit 0
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Figure 1.15.22 Transfer to UiRB Register and Interrupt Timing
i = 0 to 2
This diagram applies to the case where the following condition is met.
UiMR register CKDIR bit = 0 (slave selected)
(1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
D6D5D4D3D2D1D8 (ACK, NACK)
D8 (ACK, NACK)
D8 (ACK, NACK)
D7
SDAi
SCLi
D0
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
b15 b9 b8 b7 b0
D8D7D6D5D4D3D2D1D0
UiRB register
D6D5D4D3D2D1
D7
SDAi
SCLi
D0
b15 b9 b8 b7 b0
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
(2) IICM2 = 0, CKPH = 1 (clock delay)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
UiRB register
(3) IICM2 = 1 (UART transmit/receive interrupt), CKPH = 0
Receive interrupt
(DMA1 request) Transmit interrupt
Transfer to UiRB register
D6D5D4D3D2D1
D7
SDAi
SCLi
D0
b15 b9 b8 b7 b0
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
UiRB register
(4) IICM2 = 1, CKPH = 1
D6D5D4D3D2D1
D7
SDAi
SCLi
D0D8 (ACK, NACK)
b15 b9 b8 b7 b0 b15 b9 b8 b7 b0
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
Transmit interrupt
Transfer to UiRB register
Receive interrupt
(DMA1 request)
Transfer to UiRB register
UiRB register UiRB register
D8D7D6D5D4D3D2D1D0
D7D6D5D4D3D2D1D0
D8D7D6D5D4D3D2D1D0D7D6D5D4D3D2D1D0
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• Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to
low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated
when the SDAi pin changes state from low to high while the SCLi pin is in the high state.
Figure 1.15.23 shows the detection of start and stop condition.
Because the start and stop condition-detected interrupts share the interrupt control register and vector,
check the UiSMR register’s BBS bit to determine which interrupt source is requesting the interrupt.
Figure 1.15.23 Detection of Start and Stop Condition
• Output of Start and Stop Condition
A start condition is generated by setting the UiSMR4 register (i = 0 to 2)’s STAREQ bit to “1” (start).
A restart condition is generated by setting the UiSMR4 register’s RSTAREQ bit to “1” (start).
A stop condition is generated by setting the UiSMR4 register’s STPREQ bit to “1” (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
(2) Set the STSPSEL bit in the UiSMR4 register to “1” (output).
Table 1.15.12 and Figure 1.15.24 show the functions of the STSPSEL bit.
3 to 6 cycles < duration for setting-up (Note)
3 to 6 cycles < duration for holding (Note)
Duration for
setting-up
Duration for
holding
SCLi
SDAi
(Start condition)
SDA i
(Stop condition)
i = 0 to 2
Note: When the PCLKR register’s PCLK1 bit = 1, this is the cycle number
of f
1SIO
, and the PCLK1 bit = 0, this is the cycle number of f
2SIO
.
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Table 1.15.12 STSPSEL Bit Functions
Figure 1.15.24 STSPSEL Bit Functions
• Arbitration
Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising
edge of SCLi. Use the UiSMR register’s ABC bit to select the timing at which the UiRB register’s ABT
bit is updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to “1” at the same time
unmatching is detected during check, and is set to “0” when not detected. In cases when the ABC bit
is set to “1”, if unmatching is detected even once during check, the ABT bit is set to “1” (unmatching
detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated bytewise,
set the ABT bit to “0” (undetected) after detecting acknowledge in the first byte, before transferring the
next byte.
Setting the UiSMR2 register’s ALS bit to “1” (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit
is set to “1” (unmatching detected).
Function
Output of SCLi and SDAi pins
Start/stop condition interrupt
request generation timing
STSPSEL = 0
Output of transfer clock and
data
Output of start/stop condition is
accomplished by a program
using ports (not automatically
generated in hardware)
Start/stop condition detection
STSPSEL = 1
Output of a start/stop condition
according to the STAREQ,
RSTAREQ and STPREQ bit
Finish generating start/stop condition
Start condition
detection interrupt Stop condition
detection interrupt
(1) When slave
CKDIR = 1 (external clock)
Start condition
detection interrupt
Stop condition
detection interrupt
(2) When master
CKDIR = 0 (internal clock), CKPH = 1 (clock delayed)
SDAi
SCLi
Set STAREQ=
1 (start) Set STPREQ=
1 (start)
STSPSEL bit 0
SDAi
SCLi
STSPSEL bit
Set to "1" in
a program Set to "0" in
a program Set to "1" in
a program Set to "0" in
a program
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
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• Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 1.15.24.
The UiSMR2 register’s CSC bit is used to synchronize the internally generated clock (internal SCLi)
and an external clock supplied to the SCLi pin. In cases when the CSC bit is set to “1” (clock synchro-
nization enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the
internal SCLi goes low, at which time the UiBRG register value is reloaded with and starts counting in
the low-level interval. If the internal SCLi changes state from low to high while the SCLi pin is low,
counting stops, and when the SCLi pin goes high, counting restarts.
In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi
pin signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st
bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The UiSMR2 register’s SWC bit allows to select whether the SCLi pin should be fixed to or freed from
low-level output at the falling edge of the 9th clock pulse.
If the UiSMR4 register’s SCLHI bit is set to “1” (enabled), SCLi output is turned off (placed in the high-
impedance state) when a stop condition is detected.
Setting the UiSMR2 register’s SWC2 bit = 1 (0 output) makes it possible to forcibly output a low-level
signal from the SCLi pin even while sending or receiving data. Setting the SWC2 bit to “0” (transfer
clock) allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a
low-level signal.
If the UiSMR4 register’s SWC9 bit is set to “1” (SCL hold low enabled) when the UiSMR3 register’s
CKPH bit = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the
ninth. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.
• SDA Output
The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7.
The ninth bit (D8) is ACK or NACK.
The initial value of SDAi transmit output can only be set when IICM = 1 (I2C mode) and the UiMR
register’s SMD2 to SMD0 bits = 0002 (serial I/O disabled).
The UiSMR3 register’s DL2 to DL0 bits allow to add no delays or a delay of 2 to 8 UiBRG count source
clock cycles to SDAi output.
Setting the UiSMR2 register’s SDHI bit = 1 (SDA output disabled) forcibly places the SDAi pin in the
high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi
transfer clock. This is because the ABT bit may inadvertently be set to “1” (detected).
• SDA Input
When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit
7 to bit 0. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit
6 to bit 0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing
the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the UiRB
register after the rising edge of the corresponding clock pulse of 9th bit.
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• ACK and NACK
If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and
the ACKC bit in the UiSMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the
UiSMR4 register is output from the SDAi pin.
If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising
edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low
at the rising edge of the 9th bit of transmit clock pulse.
If ACKi is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
• Initialization of Transmission/Reception
If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial I/O
operates as described below.
- The transmit shift register is initialized, and the content of the UiTB register is transferred to the
transmit shift register. In this way, the serial I/O starts sending data synchronously with the next
clock pulse applied. However, the UARTi output value does not change state and remains the same
as when a start condition was detected until the first bit of data is output synchronously with the input
clock.
- The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the
next clock pulse applied.
- The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the
falling edge of the ninth clock pulse.
Note that when UARTi transmission/reception is started using this function, the TI bit does not change
state. Note also that when using this function, the selected transfer clock should be an external clock.
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Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 1.15.13 lists the specifications of Special Mode 2. Figure 1.15.25 shows communication
control example for Special Mode 2. Table 1.15.14 lists the registers used in Special Mode 2 and the
register values set.
Table 1.15.13 Special Mode 2 Specifications
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • Master mode
UiMR register’s CKDIR bit = 0 (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• Slave mode
CKDIR bit = 1 (external clock selected) : Input from CLKi pin
Transmit/receive control Controlled by input/output ports
Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register = 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
Reception start condition • Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register = 1 (reception enabled)
_ The TE bit of UiC1 register = 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in the UiTB register)
•For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection • Overrun error (Note 3)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Select function • Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
Interrupt request
generation timing
i = 0 to 2
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register’s CKPOL bit = 1 (transmit data output at the rising edge and
the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
Note 3: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not
change.
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Figure 1.15.25 Serial Bus Communication Control Example (UART2)
P13
P12
P70(TxD2)
P72(CLK2)
P71(RxD2)
P93
P70(TxD2)
P72(CLK2)
P71(RxD2)
P93
P70(TxD2)
P72(CLK2)
P71(RxD2)
Microcomputer
(Master)
Microcomputer
(Slave)
Microcomputer
(Slave)
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Table 1.15.14 Registers to Be Used and Settings in Special Mode 2
Register Bit Function
UiTB
(Note 1)
0 to 7 Set transmission data
UiRB
(Note 1)
0 to 7 Reception data can be read
OER Overrun error flag
UiBRG 0 to 7 Set a transfer rate
UiMR
(Note 1)
SMD2 to SMD0 Set to “0012”
CKDIR Set this bit to “0” for master mode or “1” for slave mode
IOPOL Set to “0”
UiC0 CLK1, CLK0 Select the count source for the UiBRG register
CRS Invalid because CRD = 1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Select TxDi pin output format
CKPOL Clock phases can be set in combination with the UiSMR3 register's CKPH bit
UFORM Set to “0”
UiC1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 2) Select UART2 transmit interrupt cause
U2RRM (Note 2), Set to “0”
U2LCH, UiERE
UiSMR 0 to 7 Set to “0”
UiSMR2 0 to 7 Set to “0”
UiSMR3 CKPH Clock phases can be set in combination with the UiC0 register's CKPOL bit
NODC Set to “0”
0, 2, 4 to 7 Set to “0”
UiSMR4 0 to 7 Set to “0”
UCON U0IRS, U1IRS Select UART0 and UART1 transmit interrupt cause
U0RRM, U1RRM Set to “0”
CLKMD0 Invalid because CLKMD1 = 0
CLKMD1, RCSP, 7 Set to “0”
i = 0 to 2
Note 1: Not all register bits are described above. Set those bits to “0” when writing to the registers in Special
Mode 2.
Note 2: Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
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• Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3
register’s CKPH bit and the UiC0 register’s CKPOL bit.
Make sure the transfer clock polarity and phase are the same for the master and salves to be commu-
nicated.
(a) Master (Internal Clock)
Figure 1.15.26 shows the transmission and reception timing in master (internal clock).
Data output timing
Data input timing
D0D1D2D3D4D6D7D5
Clock output
(CKPOL=0, CKPH=0)
"H"
"L"
Clock output
(CKPOL=1, CKPH=0)
"H"
"L"
Clock output
(CKPOL=0, CKPH=1)
"H"
"L"
Clock output
(CKPOL=1, CKPH=1)
"H"
"L"
"H"
"L"
Figure 1.15.26 Transmission and Reception Timing in Master Mode (Internal Clock)
(b) Slave (External Clock)
Figure 1.15.27 shows the transmission and reception timing (CKPH = 0) in slave (external clock).
Figure 1.15.28 shows the transmission and reception timing (CKPH = 1) in slave (external clock).
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Figure 1.15.27 Transmission and Reception Timing (CKPH = 0) in Slave Mode (External Clock)
Figure 1.15.28 Transmission and Reception Timing (CKPH = 1) in Slave Mode (External Clock)
Slave control input
Clock input
(CKPOL=0, CKPH=0)
Clock input
(CKPOL=1, CKPH=0)
Data output timing
Data input timing
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
D0D1D2D3D4D6D7D5
Indeterminate
Clock input
(CKPOL=0, CKPH=1)
Clock input
(CKPOL=1, CKPH=1)
Data output timing
Data input timing
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
D0D1D2D3D6D7D4D5
Slave control input
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This document is under development and its contents are subject to change.
Special Mode 3 (IE Mode)
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 1.15.15 lists the registers used in IE mode and the register values set. Figure 1.15.29 shows the
functions of bus collision detect function related bits.
If the TxDi pin (i = 0 to 2) output level and RxDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use the IFSR0 register’s IFSR06 and IFSR07 bits to enable the UART0/UART1 bus collision detect
function.
Table 1. 15.15 Registers to Be Used and Settings in IE Mode
Register Bit Function
UiTB 0 to 8 Set transmission data
UiRB 0 to 8 Reception data can be read
(Note 1)
OER,FER,PER,SUM
Error flag
UiBRG 0 to 7 Set a transfer rate
UiMR SMD2 to SMD0 Set to “1102”
CKDIR Select the internal clock or external clock
STPS Set to “0”
PRY Invalid because PRYE = 0
PRYE Set to “0”
IOPOL Select the TxD/RxD input/output polarity
UiC0 CLK1, CLK0 Select the count source for the UiBRG register
CRS Invalid because CRD = 1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Select TxDi pin output mode
CKPOL Set to “0”
UFORM Set to “0”
UiC1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 2) Select the source of UART2 transmit interrupt
UiRRM (Note 2), Set to “0”
UiLCH, UiERE
UiSMR 0 to 3, 7 Set to “0”
ABSCS Select the sampling timing at which to detect a bus collision
ACSE Set this bit to “1” to use the auto clear function of transmit enable bit
SSS Select the transmit start condition
UiSMR2 0 to 7 Set to “0”
UiSMR3 0 to 7 Set to “0”
UiSMR4 0 to 7 Set to “0”
IFSR0 IFSR06, IFSR07 Set to “1”
UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM Set to “0”
CLKMD0 Invalid because CLKMD1 = 0
CLKMD1, RCSP, 7 Set to “0”
i= 0 to 2
Note 1: Not all register bits are described above. Set those bits to “0” when writing to the registers in IE mode.
Note 2: Set the U0C1 and U1C1 registers bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
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Figure 1.15.29 Bus Collision Detect Function-Related Bits
(3) UiSMR register SSS bit (transmit start condition select)
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxDi
TxDi
CLKi
TxDi
RxDi
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
(Note 2)
Note 1: The falling edge of RxDi when IOPOL = 0; the rising edge of RxDi when IOPOL = 1.
Note 2: The transmit condition must be met before the falling edge (Note 1) of RxDi.
(2) UiSMR register ACSE bit (auto clear of transmit enable bit)
TxDi
RxDi
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
Transfer clock
UiBCNIC register
IR bit
UiC1 register
TE bit
If ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is set to "0"
(transmission disabled) when
the UiBCNIC register’s IR bit = 1
(unmatching detected).
(1) UiSMR register ABSCS bit (bus collision detect sampling clock select)
If ABSCS = 0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
Timer Aj
TxDi
RxDi
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
Input to TAjIN
If ABSCS = 1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2
i = 0 to 2
This diagram applies to the case where IOPOL =1 (reversed)
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Item Specification
Transfer data format • Direct format
• Inverse format
Transfer clock • U2MR register’s CKDIR bit = 0 (internal clock) : fi/ 16(n+1)
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register 0016 to FF16
• CKDIR bit = 1 (external clock) : fEXT/16(n+1)
fEXT: Input from CLK2 pin. n: Setting value of U2BRG register 0016 to FF16
Transmission start condition • Before transmission can start, the following requirements must be met
_ The TE bit of U2C1 register = 1 (transmission enabled)
_ The TI bit of U2C1 register = 0 (data present in U2TB register)
Reception start condition • Before reception can start, the following requirements must be met
_ The RE bit of U2C1 register = 1 (reception enabled)
_ Start bit detection
•For transmission
When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit = 1)
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
Error detection • Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TxD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set to “1” when any of the overrun, framing, and parity errors is encountered
Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows to output a low from the TxD2 pin when a parity error is detected.
Tables 1.15.16 lists the specifications of SIM mode. Table 1.15.17 lists the registers used in the SIM
mode and the register values set. Figure 1.15.30 shows the typical transmit/receive timing in SIM mode.
Table 1.15.16 SIM Mode Specifications
Interrupt request
generation timing (Note 2)
Note 1: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC
register does not change.
Note 2: A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1” (transmit
is completed) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM
mode, be sure to set the IR bit to “0” (interrupt not requested) after setting these bits.
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Table 1.15.17 Registers to Be Used and Settings in SIM Mode
Register Bit Function
U2TB
(Note)
0 to 7 Set transmission data
U2RB
(Note)
0 to 7 Reception data can be read
OER,FER,PER,SUM
Error flag
U2BRG 0 to 7 Set a transfer rate
U2MR SMD2 to SMD0 Set to “1012”
CKDIR Select the internal clock or external clock
STPS Set to “0”
PRY Set this bit to “1” for direct format or “0” for inverse format
PRYE Set to “1”
IOPOL Set to “0”
U2C0 CLK1, CLK0 Select the count source for the U2BRG register
CRS Invalid because CRD = 1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Set to “0”
CKPOL Set to “0”
UFORM Set this bit to “0” for direct format or “1” for inverse format
U2C1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS Set to “1”
U2RRM Set to “0”
U2LCH Set this bit to “0” for direct format or “1” for inverse format
U2ERE Set to “1”
U2SMR
(Note)
0 to 3 Set to “0”
U2SMR2 0 to 7 Set to “0”
U2SMR3 0 to 7 Set to “0”
U2SMR4 0 to 7 Set to “0”
Note: Not all register bits are described above. Set those bits to “0” when writing to the registers in SIM mode.
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Figure 1.15.30 Transmit and Receive Timing in SIM Mode
The above timing diagram applies to the case where data is
received in the direct format.
U2MR register STPS bit = 0 (1 stop bit)
U2MR register PRY bit = 1 (even parity)
U2C0 register UFORM bit = 0 (LSB first)
U2C1 register U2LCH bit = 0 (no reverse)
U2C1 register U2IRS bit = 1 (transmit is completed)
Transfer clock
An "L" level is output from TxD
2
due to
the occurrence of a parity error
Read the U2RB register
Set to "0" when interrupt request is accepted, or set to "0" in a program
U2C1 register
TE bit
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PD
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP
Tc
SP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
TxD2
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP
Tc
SP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PD
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
SP
SP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PD
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
SP
SP
TxD2
RxD2 pin level
U2C1 register
TI bit
Parity error signal sent
back from receiver
(Note)
U2C0 register
TXEPT bit
S2TIC register
IR bit
Start
bit
Parity
bit
Stop
bit
Write data to U2TB register
Transferred from U2TB register to UART2 transmit register
An "L" level returns due to the
occurrence of a parity error.
The level is
detected by the
interrupt routine.
The level is detected by the
interrupt routine.
The IR bit is set to "1" at the
falling edge of transfer clock
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
The above timing diagram applies to the case where data is
transferred in the direct format.
U2MR register STPS bit = 0 (1 stop bit)
U2MR register PRY bit = 1 (even parity)
U2C0 register UFORM bit = 0 (LSB first)
U2C1 register U2LCH bit = 0 (no reverse)
U2C1 register U2IRS bit = 1 (transmit is completed)
Start
bit
Parity
bit
Stop
bit
Set to "0" when interrupt request is accepted, or set to "0" in a program
Read the U2RB register
Transfer clock
U2C1 register
RE bit
RxD2 pin level
Transmitter’s
transmit waveform
(Note)
U2C0 register
RI bit
S2RIC register
IR bit
(1) Transmission
(2) Reception
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
Note: Because TxD
2
and RxD
2
are connected, this is composite waveform consisting of the transmitter’s transmit waveform and the parity
error signal received.
Note: Because TxD
2
and RxD
2
are connected, this is composite waveform consisting of the TxD
2
output and the parity error signal sent back
from receiver.
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Figure 1.15.31 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply
pull-up.
Figure 1.15.31 SIM Interface Connection
(a) Parity Error Signal Output
The parity error signal is enabled by setting the U2C1 register’s U2ERE bit to “1”.
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved
by pulling the TxD2 output low with the timing shown in Figure 1.15.32. If the R2RB register is read
while outputting a parity error signal, the PER bit is set to “0” and at the same time the TxD2 output is
returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse
that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service
routine.
Figure 1.15.32 shows the output timing of the parity error signal
Figure 1.15.32 Parity Error Signal Output Timing
Microcomputer
SIM card
TxD2
RxD2
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
(Note)
Transfer
clock
RxD
2
TxD
2
U2C1 register
RI bit
"H"
"L"
"H"
"L"
"H"
"L"
"1"
"0"
This timing diagram applies to the case where the direct format is
implemented.
Note: The output of microcomputer is in the high-impedance state
(pulled up externally).
ST: Start bit
P: Even Parity
SP: Stop bit
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(b) Format
• Direct Format
Set the U2MR register's PRY bit to “1”, U2C0 register's UFORM bit to “0” and U2C1 register's
U2LCH bit to “0”.
• Inverse Format
Set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”.
Figure 1.15.33 shows the SIM interface format.
Figure 1.15.33 SIM Interface Format
P : Even parity
D0 D1 D2 D3 D4 D5 D6 D7 P
Transfer
clock
TxD2
TxD2D7 D6 D5 D4 D3 D2 D1 D0 P
Transfer
clock
"H"
"L"
"H"
"L"
P : Odd parity
"H"
"L"
"H"
"L"
(1) Direct format
(2) Inverse format
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M16C/6N4 Group SI/O3
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This document is under development and its contents are subject to change.
SI/O3
SI/O3 is exclusive clock-synchronous serial I/O.
Figure 1.15.34 shows the block diagram of SI/O3, and Figure 1.15.35 shows the SI/O3-related registers.
Table 1.15.18 lists the specifications of SI/O3.
Figure 1.15.34 SI/O3 Block Diagram
S3TRR register
SI/O counter 3
Synchronous
circuit
Data bus
8
SI/O3
interrupt
request
SM35 LSB MSB
SM32
SM33
SM33
SM36
SM31 to SM30
S3BRG register
SM36
n = A value set in the S3BRG register.
1/(n+1)1/2
CLK polarity
reversing
circuit
1/2
f1SIO
1/8
1/4
f8SIO
f32SIO
f2SIO PCLK1=0
PCLK1=1
SM34
Clock source select
002
012
102
CLK
3
S
OUT3
S
IN3
Main clock,
PLL clock,
or ring oscillator clock
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Figure 1.15.35 S3C Register, S3BRG Register and S3TRR Register
0 0 : Selecting f1SIO or f2SIO
0 1 : Selecting f8SIO
1 0 : Selecting f32SIO
1 1 : Must not be set
0 : Input/output port
1 : SOUT3 output, CLK3 function
0 : SOUT3 output
1 : SOUT3 output disabled (high-impedance)
0 : Transmit data is output at falling edge of
transfer clock and receive data is input
at rising edge
1 : Transmit data is output at rising edge of
transfer clock and receive data is input
at falling edge
b1 b0
0 : LSB first
1 : MSB first
0 : External clock (Note 3)
1 : Internal clock (Note 4)
Effective when SM33 = 0
0 : "L" output
1 : "H" output
b7 b6 b5 b4 b3 b2 b1 b0
SI/O3 control register (Note 1)
Symbol Address After reset
S3C 01E2
16 010000016
Bit
symbol Bit name Description RW
RW
RW
RW
RW
RW
RW
RW
RW
SM35
SM31
SM30
SM33
SM36
SM37
SM32
SM34
Internal synchronous
clock select bit
Transfer direction select
bit
S I/O3 port select bit
SOUT3 initial value set bit
Synchronous clock
select bit
SOUT3 output disable bit
CLK polarity select bit
(Note 2)
Note 1: Make sure this register is written to by the next instruction after setting the PRCR register’s PRC2 bit to "1" (write
enabled).
Note 2: When the SM32 bit is set to "1", the target pin goes to a high-impedance state regardless of which function of the
pin is being used.
Note 3: Set the SM33 bit to "1" and the corresponding port direction bit to "0" (input mode).
Note 4: Set the SM33 bit to "1" (S
OUT3
output, CLK
3
function).
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
Description RW
WO
Assuming that set value = n, S3BRG divides the count
source by n + 1
Symbol Address
After
reset
S3BRG 01E316 Indeterminate
b7 b0
0016 to FF16
Setting range
SI/O3 bit rate generator (Notes 1, 2)
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: To receive data, set the corresponding port direction bit for S
IN3
to "0" (input mode).
b7 b0
Symbol Address
After reset
S3TRR 01E016 Indeterminate
RW
RW
Description
SI/O3 transmit/receive register (Notes 1, 2)
Transmission/reception starts by writing transmit data to this register.
After transmission/reception finishes, reception data can be read by reading this register.
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Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • S3C register’s SM36 bit = 1 (internal clock) : fj/ 2(n+1)
fj = f1SIO, f8SIO, f32SIO. n = Setting value of S3BRG register 0016 to FF16.
• SM36 bit = 0 (external clock) : Input from CLK3 pin (Note 1)
Transmission/reception • Before transmission/reception can start, the following requirements must be met
start condition Write transmit data to the S3TRR register (Notes 2, 3)
• When S3C register's SM34 bit = 0
The rising edge of the last transfer clock pulse (Note 4)
• When SM34 = 1
The falling edge of the last transfer clock pulse (Note 4)
CLK3 pin function I/O port, transfer clock input, transfer clock output
SOUT3 pin function I/O port, transmit data output, high-impedance
SIN3 pin function I/O port, receive data input
Select function • LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Function for setting an SOUT3 initial value set function
When the S3C register's SM36 bit = 0 (external clock), the SOUT3 pin output level
while not transmitting can be selected.
•CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge of
transfer clock can be selected.
Table 1.15.18 SI/O3 Specifications
Interrupt request
generation timing
Note 1: To set the S3C register’s SM36 bit to “0” (external clock), follow the procedure described below.
• If the S3C register’s SM34 bit = 0, write transmit data to the S3TRR register while input on the CLK3 pin is high.
The same applies when rewriting the S3C register’s SM37 bit.
• If the SM34 bit = 1, write transmit data to the S3TRR register while input on the CLK3 pin is low. The same
applies when rewriting the SM37 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/O3 circuit, stop the transfer
clock after supplying eight pulses. If the SM36 bit = 1 (internal clock), the transfer clock automatically stops.
Note 2: Unlike UART0 to UART2, SI/O3 is not separated between the transfer register and buffer. Therefore, do not write
the next transmit data to the S3TRR register during transmission.
Note 3: When the S3C register’s SM36 bit = 1 (internal clock), SOUT3 retains the last data for a 1/2 transfer clock period
after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is written
to the S3TRR register during this period, SOUT3 immediately goes to a high-impedance state, with the data hold
time thereby reduced.
Note 4: When the S3C register’s SM36 bit = 1 (internal clock), the transfer clock stops in the high state if the SM34 bit =
0, or stops in the low state if the SM34 bit = 1.
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(a) SI/O3 Operation Timing
Figure 1.15.36 shows the SI/O3 operation timing.
Figure 1.15.36 SI/O3 Operation Timing
(b) CLK Polarity Selection
The S3C register's SM34 bit allows selection of the polarity of the transfer clock. Figure 1.15.37 shows
the polarity of the transfer clock.
Figure 1.15.37 Polarity of Transfer Clock
* This diagram applies to the case where the S3C register bits are set as follows:
SM32 = 0 (S
OUT3
output)
SM33 = 1 (S
OUT3
output, CLK
3
function)
SM34 = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
SM35 = 0 (LSB first)
SM36 = 1 (internal clock)
Note 1: If the SM36 bit = 1 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
S3TRR register.
Note 2: When the SM36 bit = 1 (internal clock), the S
OUT3
pin is placed in the high-impedance state after the transfer finishes.
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
1.5 cycle (max.)
(Note 2)
(Note 1)
SI/O3 internal clock
CLK
3
output
Signal written to the
S3TRR register
S
OUT3
output
S
IN3
input
S3IC register IR bit
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"1"
"0"
D1D2D3D4D5D6D7
D1D2D3D4D5D6D7
D0
D0
SIN3
SOUT3
CLK3
D1D2D3D4D5D6D7D0
D1D2D3D4D5D6D7D0
SIN3
SOUT3
CLK3
(2) When S3C register’s SM34 bit = 1
(1) When S3C register’s SM34 bit = 0
*This diagram applies to the case where the S3C register bits are set as follows:
SM35 = 0 (LSB first)
SM36 = 1 (internal clock)
Note 1: When the SM36 bit = 1 (internal clock), a high level is output from the CLK3 pin if not
transferring data.
Note 2: When the SM36 bit = 1 (internal clock), a low level is output from the CLK3 pin if not
transferring data.
(Note 2)
(Note 1)
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M16C/6N4 Group SI/O3
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This document is under development and its contents are subject to change.
(c) Functions for Setting an SOUT3 Initial Value
If the S3C register’s SM36 bit = 0 (external clock), the SOUT3 pin output can be fixed high or low when
not transferring. Figure 1.15.38 shows the timing chart for setting an SOUT3 initial value and how to set it.
Figure 1.15.38 SOUT3’s Initial Value Setting
Setting the S
OUT3
initial value to "H"
Port selection switching
(I/O port S
OUT3
)
D0
Initial value = H (Note 1)
Port output D0
(Note 2)
Signal written to
S3TRR register
SOU
T3
(internal)
SM37 bit
S
OUT3
output
SM33 bit
(Example) When "H" selected for S
OUT3
initial value
* This diagram applies to the case where the S3C register bits are set as follows:
SM32 = 0 (S
OUT3
output)
SM35 = 0 (LSB first)
SM36 = 0 (external clock)
Note 1: If the SM36 bit = 1 (internal clock) or if the SM32 bit = 1 (S
OUT3
output disabled), this output
goes to the high-impedance state.
Note 2: S
OUT3
can only be initialized when input on the CLK
3
pin is in the high state if the S3C
register’s SM34 bit = 0 (transmit data output at the falling edge of the transfer clock) or in
the low state if the SM34 bit = 1 (transmit data output at the rising edge of the transfer clock).
"H" level is output
from the SOUT3 pin
Serial transmit/reception starts
Setting of the initial value of SOUT3
output and starting of
transmission/reception
Set the SM33 bit to "1"
(SOUT3 pin functions as SOUT3 output)
Write to the S3TRR register
Set the SM33 bit to "0"
(SOUT3 pin functions as an I/O port)
Set the SM37 bit to "1"
(SOUT3 initial value = H)
Rev.1.00 2003.05.30 page 187
M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
Item Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1)
0V to AVCC (VCC)
Operating clock φAD (Note 2)
fAD, divide-by-2 of fAD, divide-by-3 of fAD, divide-by-4 of fAD, divide-by-6 of fAD,
divide-by-12 of fAD
Resolution 8 bits or 10 bits (selectable)
Integral nonlinearity error • With 8-bit resolution: ±2LSB
• With 10-bit resolution : ±3LSB
When external operation amp connection mode is selected : ±7LSB
Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins 8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN00 to AN07)
+ 8 pins (AN20 to AN27)
A-D conversion start condition
• Software trigger
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
• External trigger (retriggerable)
__________
Input on the ADTRG pin changes state from high to low after the ADST bit is set
to “1” (A-D conversion starts)
Conversion speed per pin •Without sample and hold function
8-bit resolution: 49
φ
AD cycles
,
10-bit resolution: 59
φ
AD cycles
• With sample and hold function
8-bit resolution: 28
φ
AD cycles
,
10-bit resolution: 33
φ
AD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Operation clock frequency (
φ
AD frequency) must be 10 MHz or less.
A case without sample-and-hold function, turn (
φ
AD frequency) into 250 kHz or more.
A case with the sample and hold function, turn (
φ
AD frequency) into 1 MHz or more.
A-D Converter
The microcomputer contains one A-D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107, P95,
_________
P96, P00 to P07, and P20 to P27. Similarly, ADTRG input shares the pin with P97. Therefore, when using these
inputs, make sure the corresponding port direction bits are set to “0” (input mode).
When not using the A-D converter, set the VCUT bit to “0” (VREF unconnected), so that no current will flow
from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A-D conversion result is stored in the ADi register bits for ANi, AN0i, and AN2i pins (i = 0 to 7).
Table 1.16.1 shows the performance of the A-D converter. Figure 1.16.1 shows the block diagram of the A-D
converter, and Figures 1.16.2 and 1.16.3 show the A-D converter-related registers.
Table 1.16.1 A-D Converter Performance
Rev.1.00 2003.05.30 page 188
M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
Figure 1.16.1 A-D Converter Block Diagram
ANEX
0
ANEX
1
OPA0=1
OPA1=1
PM01 to PM00=00
2
ADGSEL1 to ADGSEL0=10
2
OPA1 to OPA0=11
2
ADGSEL1 to ADGSEL0=00
2
OPA1 to OPA0=11
2
=000
2
=001
2
=010
2
=011
2
=100
2
=101
2
=110
2
=111
2
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
AN
00
AN
01
AN
02
AN
03
AN
04
AN
05
AN
06
AN
07
V
REF
V
IN
CH2 to CH0
PM00
PM01
Decoder
for channel
selection
Data bus low-order
V
REF
AV
SS
VCUT=0
VCUT=1
Data bus high-order
OPA1=1
Port P10 group
Port P0 group
PM01 to PM00=00
2
ADGSEL1 to ADGSEL0=10
2
OPA1 to OPA0=00
2
ADGSEL1 to ADGSEL0=00
2
OPA1 to OPA0=00
2
OPA1 to OPA0
=01
2
AN
20
AN
21
AN
22
AN
23
AN
24
AN
25
AN
26
AN
27
PM01 to PM00=00
2
ADGSEL1 to ADGSEL0=11
2
OPA1 to OPA0=11
2
PM01 to PM00=00
2
ADGSEL1 to ADGSEL0=11
2
OPA1 to OPA0=00
2
f
AD
CKS0=1
CKS0=0
CKS1=1
CKS1=0
1/3
CKS2=0
CKS2=1
1/21/2
φ
AD
A-D conversion rate selection
Resistor ladder
Successive conversion register
Comparator
Decoder
for A-D register
Port P2 group
AD
TRG
TRG=0
TRG=1
A-D trigger
Software trigger
=000
2
=001
2
=010
2
=011
2
=100
2
=101
2
=110
2
=111
2
=000
2
=001
2
=010
2
=011
2
=100
2
=101
2
=110
2
=111
2
CH2 to CH0
CH2 to CH0
(Note)
Note: Port P0 group (AN
00
to AN
07
) can be used as analog input pins even when the PM01
to PM00 bits are set to "01
2
" (memory expansion mode) and the PM05 to PM04 bits are
set to "11
2
" (multiplexed bus allocated to the entire CS space).
AD register 0 (16)
AD register 1 (16)
AD register 2 (16)
AD register 3 (16)
AD register 4 (16)
AD register 5 (16)
AD register 6 (16)
AD register 7 (16)
ADCON0 register
ADCON1 register
ADCON2 register
(Note)
(Note)
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M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
Figure 1.16.2 ADCON0 Register and ADCON1 Register
CH0
CH1
CH2
MD0
MD1
TRG
ADST
CKS0
RW
RW
RW
RW
RW
RW
RW
RW
SCAN0
SCAN1
MD2
BITS
VCUT
OPA0
OPA1
CKS1
Function varies
with each operation mode
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
0 : Software trigger
1 : AD
TRG
trigger
0 : A-D conversion disabled
1 : A-D conversion started
See Note 2 for the ADCON2
register
Trigger select bit
A-D conversion start flag
Frequency select bit 0
Analog input pin select bit
A-D operation mode
select bit 0
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function RW
RW
RW
RW
RW
RW
RW
RW
RW
Bit name Function
Bit symbol RW
Symbol Address After reset
ADCON1 03D7
16 0016
0 : 8-bit mode
1 : 10-bit mode
0 : Any mode other than repeat
sweep mode 1
1 : Repeat sweep mode 1
0 : VREF not connected
1 : VREF connected
See Note 2 for the ADCON2
register
Function varies
with each operation mode
A-D sweep pin select bit
8/10-bit mode select bit
VREF connect bit (Note 2)
A-D operation mode
select bit 1
External op-amp
connection mode bit
Frequency select bit 1
Function varies
with each operation mode
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (Note 1)
Symbol Address After reset
ADCON0 03D6
16 00000XXX2
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A-D conversion.
b4 b3
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M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
Figure 1.16.3 ADCON2 Register, and AD0 to AD7 Registers
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: The φAD frequency must be 10 MHz or less. The selected φAD frequency is determined by a combination of the
ADCON0 register’s CKS0 bit, ADCON1 register’s CKS1 bit, and ADCON2 register’s CKS2 bit.
Divide-by-4 of fAD
Divide-by-2 of fAD
fAD
Divide-by-12 of fAD
Divide-by-6 of fAD
Divide-by-3 of fAD
b7 b6 b5 b4 b3 b2 b1 b0
0Symbol Address After reset
ADCON2 03D4
16
00
16
A-D control register 2 (Note 1)
Bit symbol Bit name Function RW
RW
RW
RW
RW
RW
-
SMP
CKS2
ADGSEL0
ADGSEL1
-
(b3)
-
(b7-b5)
(Note 2)
b2 b1
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
A-D input group select bit
A-D conversion method
select bit
Reserved bit
Frequency select bit 2
0 : Without sample and hold
1 : With sample and hold
0 0 : Port P10 group is selected
0 1 : Must not be set
1 0 : Port P0 group is selected
1 1 : Port P2 group is selected
Set to "0"
0 : Selects fAD, divide-by-2 of fAD, or
divide-by-4 of fAD.
1 : Selects divide-by-3 of fAD, divide-by-6
of fAD, or divide-by-12 of fAD.
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
1
0
1
0
0
1
0
1
1
CKS0 CKS1 CKS2 φ
AD
(b15)
b7b7 b0 b0
(b8)
A-D register i (i = 0 to 7)
Low-order 8 bits of
A-D conversion result
Function
When the ADCON1 register’s
BITS bit is "1" (10-bit mode)
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
When read, the content is
indeterminate.
RW
-
RO
RO
High-order 2 bits of
A-D conversion result
When the ADCON1 register’s
BITS bit is "0" (8-bit mode)
A-D conversion result
Symbol Address After reset
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
03C116 to 03C016
03C316 to 03C216
03C516 to 03C416
03C716 to 03C616
03C916 to 03C816
03CB16 to 03CA16
03CD16 to 03CC16
03CF16 to 03CE16
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Rev.1.00 2003.05.30 page 191
M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
Item Specification
Function The input voltage on one pin selected by the ADCON0 register's CH2 to CH0
bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits or the ADCON1
register's OPA1 to OPA0 bits is A-D converted once.
A-D conversion start condition
• When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
_________
• When the TRG bit is “1” (ADTRG trigger)
_________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condition
• Completion of A-D conversion (If a software trigger is selected, the ADST bit
is set to “0” (A-D conversion halted).)
• Set the ADST bit to “0”
Interrupt request generation timing
Completion of A-D conversion
Analog input pin
Select one pin from AN
0
to AN
7
, AN
00
to AN
07
, AN
20
to AN
27
, ANEX0 to ANEX1
Reading of result of A-D converter
Read one of the AD0 to AD7 registers that corresponds to the selected pin
(1) One-shot Mode
In this mode, the input voltage on one selected pin is A-D converted once. Table 1.16.2 lists the specifications
of one-shot mode. Figure 1.16.4 shows the ADCON0 and ADCON1 registers in one-shot mode.
Table 1.16.2 One-shot Mode Specifications
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M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
Figure 1.16.4 ADCON0 Register and ADCON1 Register in One-shot Mode
CH0
CH1
CH2
MD0
MD1
TRG
ADST
CKS0
RW
RW
RW
RW
RW
RW
RW
RW
SCAN0
SCAN1
MD2
BITS
VCUT
OPA0
OPA1
CKS1
0 0 : One-shot mode (Note 3)
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
See Note 2 for the ADCON2
register
Trigger select bit
A-D conversion start flag
Frequency select bit 0
Analog input pin select bit
A-D operation mode
select bit 0
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function RW
RW
RW
RW
RW
RW
RW
RW
RW
Bit name Function
Bit symbol RW
Symbol Address After reset
ADCON1 03D716 0016
0 : 8-bit mode
1 : 10-bit mode
Set to "0" when one-shot mode
is selected
1 : VREF connected
See Note 2 for the ADCON2
register
Invalid in one-shot modeA-D sweep pin select bit
8/10-bit mode select bit
VREF connect bit (Note 2)
A-D operation mode
select bit 1
External op-amp
connection mode bit
Frequency select bit 1
0 0 :
ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 :
External op-amp connection mode
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (Note 1)
Symbol Address After reset
ADCON0 03D616 00000XXX2
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A-D conversion.
b4 b3
b7 b6
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected (Note 2)
1 1 1 : AN7 is selected (Note 3)
b2 b1 b0
0
10
0
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in same way as AN0 to AN7. Use the ADCON2 register’s
ADGSEL1 to ADGSEL0 bits to select the desired pin.
Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
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M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
(2) Repeat Mode
I
n this mode, the input voltage on one selected pin is A-D converted repeatedly. Table 1.16.3 lists the
specifications of repeat mode. Figure 1.16.5 shows the ADCON0 and ADCON1 registers in repeat mode.
Table 1.16.3 Repeat Mode Specifications
Item Specification
Function The input voltage on one pin selected by the ADCON0 register's CH2 to CH0
bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits or the ADCON1
register's OPA1 to OPA0 bits is A-D converted repeatedly.
A-D conversion start condition
• When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condition
Set the ADST bit to “0” (A-D conversion halted)
Interrupt request generation timing
None generated
Analog input pin
Select one pin from AN
0
to AN
7
, AN
00
to AN
07
, AN
20
to AN
27
, ANEX0 to ANEX1
Reading of result of A-D converter
Read one of the AD0 to AD7 registers that corresponds to the selected pin
Rev.1.00 2003.05.30 page 194
M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
Figure 1.16.5 ADCON0 Register and ADCON1 Register in Repeat Mode
CH0
CH1
CH2
MD0
MD1
TRG
ADST
CKS0
RW
RW
RW
RW
RW
RW
RW
RW
SCAN0
SCAN1
MD2
BITS
VCUT
OPA0
OPA1
CKS1
0 1 : Repeat mode (Note 3)
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
See Note 2 for the ADCON2
register
Trigger select bit
A-D conversion start flag
Frequency select bit 0
Analog input pin select bit
A-D operation mode
select bit 0
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function RW
RW
RW
RW
RW
RW
RW
RW
RW
Bit name Function
Bit symbol RW
Symbol Address After reset
ADCON1 03D716 0016
0 : 8-bit mode
1 : 10-bit mode
Set to "0" when repeat mode is
selected
1 : VREF connected
See Note 2 for the ADCON2
register
Invalid in repeat modeA-D sweep pin select bit
8/10-bit mode select bit
VREF connect bit (Note 2)
A-D operation mode
select bit 1
External op-amp
connection mode bit
Frequency select bit 1
0 0 :
ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 :
External op-amp connection mode
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (Note 1)
Symbol Address After reset
ADCON0 03D616 00000XXX2
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A-D conversion.
b4 b3
b7 b6
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected (Note 2)
1 1 1 : AN7 is selected (Note 3)
b2 b1 b0
0
10
1
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in same way as AN0 to AN7. Use the ADCON2 register’s
ADGSEL1 to ADGSEL0 bits to select the desired pin.
Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
Rev.1.00 2003.05.30 page 195
M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
(3) Single Sweep Mode
I
n this mode, the input voltages on selected pins are A-D converted, one pin at a time. Table 1.16.4 lists
the specifications of single sweep mode. Figure 1.16.6 shows the ADCON0 and ADCON1 registers in
single sweep mode.
Table 1.16.4 Single Sweep Mode Specifications
Item Specification
Function The input voltages on pins selected by the ADCON1 register's SCAN1 to
SCAN0 bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits are A-D
converted, one pin at a time.
A-D conversion start condition
• When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condition
• Completion of A-D conversion (If a software trigger is selected, the ADST bit
is set to “0” (A-D conversion halted).)
• Set the ADST bit to “0”
Interrupt request generation timing
Completion of A-D conversion
Analog input pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0
to AN7 (8 pins) (Note)
Reading of result of A-D converter
Read one of the AD0 to AD7 registers that corresponds to the selected pin
Note: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7.
Rev.1.00 2003.05.30 page 196
M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
Figure 1.16.6 ADCON0 Register and ADCON1 Register in Single Sweep Mode
CH0
CH1
CH2
MD0
MD1
TRG
ADST
CKS0
1 0 : Single sweep mode
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
See Note 2 for the ADCON2
register
Trigger select bit
A-D conversion start flag
Frequency select bit 0
Analog input pin select bit
A-D operation mode
select bit 0
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function RW
RW
RW
RW
RW
RW
RW
RW
RW
Invalid in single sweep mode
Symbol Address After reset
ADCON0 03D616 00000XXX2
b4 b3
1
RW
RW
RW
RW
RW
RW
RW
RW
SCAN0
SCAN1
MD2
BITS
VCUT
OPA0
OPA1
CKS1
Bit name Function
Bit symbol RW
Symbol Address After reset
ADCON1 03D716 0016
0 : 8-bit mode
1 : 10-bit mode
Set to "0" when single sweep mode
is selected
1 : VREF connected
See Note 2 for the ADCON2
register
When single sweep mode is selected
A-D sweep pin select bit
8/10-bit mode select bit
VREF connect bit (Note 3)
A-D operation mode
select bit 1
External op-amp
connection mode bit
Frequency select bit 1
0 0 :
ANEX0 and ANEX1 are not used
0 1 : Must not be set
1 0 : Must not be set
1 1 :
External op-amp connection mode
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (Note 1)
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in same way as AN0 to AN7. Use the ADCON2 register’s
ADGSEL1 to ADGSEL0 bits to select the desired pin.
Note 3: If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A-D conversion.
b7 b6
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins) (Note 2)
b1 b0
10
0
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Rev.1.00 2003.05.30 page 197
M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
(4) Repeat Sweep Mode 0
In this mode, the input voltages on selected pins are A-D converted repeatedly. Table 1.16.5 lists the
specifications of repeat sweep mode 0. Figure 1.16.7 shows the ADCON0 and ADCON1 registers in
repeat sweep mode 0.
Table 1.16.5 Repeat Sweep Mode 0 Specifications
Item Specification
Function The input voltages on pins selected by the ADCON1 register's SCAN1 to
SCAN0 bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits are A-D
converted repeatedly.
A-D conversion start condition
• When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condition
Set the ADST bit to “0” (A-D conversion halted)
Interrupt request generation timing
None generated
Analog input pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0
to AN7 (8 pins) (Note)
Reading of result of A-D converter
Read one of the AD0 to AD7 registers that corresponds to the selected pin
Note: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7.
Rev.1.00 2003.05.30 page 198
M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
Figure 1.16.7 ADCON0 Register and ADCON1 Register in Repeat Sweep Mode 0
CH0
CH1
CH2
MD0
MD1
TRG
ADST
CKS0
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
See Note 2 for the ADCON2
register
Trigger select bit
A-D conversion start flag
Frequency select bit 0
Analog input pin select bit
A-D operation mode
select bit 0
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function RW
RW
RW
RW
RW
RW
RW
RW
RW
Invalid in repeat sweep mode 0
Symbol Address After reset
ADCON0 03D616 00000XXX2
b4 b3
1
RW
RW
RW
RW
RW
RW
RW
RW
SCAN0
SCAN1
MD2
BITS
VCUT
OPA0
OPA1
CKS1
Bit name Function
Bit symbol RW
Symbol Address After reset
ADCON1 03D716 0016
0 : 8-bit mode
1 : 10-bit mode
Set to "0" when repeat sweep
mode 0 is selected
1 : VREF connected
See Note 2 for the ADCON2
register
When repeat sweep mode 0 is selected
A-D sweep pin select bit
8/10-bit mode select bit
VREF connect bit (Note 3)
A-D operation mode
select bit 1
External op-amp
connection mode bit
Frequency select bit 1
0 0 :
ANEX0 and ANEX1 are not used
0 1 : Must not be set
1 0 : Must not be set
1 1 :
External op-amp connection mode
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (Note 1)
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in same way as AN0 to AN7. Use the ADCON2 register’s
ADGSEL1 to ADGSEL0 bits to select the desired pin.
Note 3: If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A-D conversion.
b7 b6
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins) (Note 2)
b1 b0
10
1
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Rev.1.00 2003.05.30 page 199
M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
Item Specification
Function The input voltages on all pins selected by the ADCON2 register's ADGSEL1 to
ADGSEL0 bits are A-D converted repeatedly, with priority given to pins se-
lected by the ADCON1 register's SCAN1 to SCAN0 bits and ADGSEL1 to
ADGSEL0 bits.
Example : If AN0 selected, input voltages are A-D converted in order of
AN0 AN1 AN0 AN2 AN0 AN3, and so on.
A-D conversion start condition
• When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
_________
• When the TRG bit is “1” (ADTRG trigger)
_________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condition
Set the ADST bit to “0” (A-D conversion halted)
Interrupt request generation timing
None generated
Select from AN0 (1 pin), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4
pins) (Note)
Reading of result of A-D converter
Read one of the AD0 to AD7 registers that corresponds to the selected pin
(5) Repeat Sweep Mode 1
In this mode, the input voltages on all pins are A-D converted repeatedly, with priority given to the
selected pins. Table 1.16.6 lists the specifications of repeat sweep mode 1. Figure 1.16.8 shows the
ADCON0 and ADCON1 registers in repeat sweep mode 1.
Table 1.16.6 Repeat Sweep Mode 1 Specifications
Analog input pins to be given
priority when A-D converted
Note: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7.
Rev.1.00 2003.05.30 page 200
M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
Figure 1.16.8 ADCON0 Register and ADCON1 Register in Repeat Sweep Mode 1
CH0
CH1
CH2
MD0
MD1
TRG
ADST
CKS0
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
See Note 2 for the ADCON2
register
Trigger select bit
A-D conversion start flag
Frequency select bit 0
Analog input pin select bit
A-D operation mode
select bit 0
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function RW
RW
RW
RW
RW
RW
RW
RW
RW
Invalid in repeat sweep mode 1
Symbol Address After reset
ADCON0 03D616 00000XXX2
b4 b3
1
RW
RW
RW
RW
RW
RW
RW
RW
SCAN0
SCAN1
MD2
BITS
VCUT
OPA0
OPA1
CKS1
Bit name Function
Bit symbol RW
Symbol Address After reset
ADCON1 03D716 0016
0 : 8-bit mode
1 : 10-bit mode
Set to "1" when repeat sweep
mode 1 is selected
1 : VREF connected
See Note 2 for the ADCON2
register
When repeat sweep mode 1 is selected
A-D sweep pin select bit
8/10-bit mode select bit
VREF connect bit (Note 3)
A-D operation mode
select bit 1
External op-amp
connection mode bit
Frequency select bit 1
0 0 :
ANEX0 and ANEX1 are not used
0 1 : Must not be set
1 0 : Must not be set
1 1 :
External op-amp connection mode
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (Note 1)
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in same way as AN0 to AN7. Use the ADCON2 register’s
ADGSEL1 to ADGSEL0 bits to select the desired pin.
Note 3: If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A-D conversion.
b7 b6
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins) (Note 2)
b1 b0
11
1
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Rev.1.00 2003.05.30 page 201
M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
(a) Resolution Select Function
The desired resolution can be selected using the ADCON1 register’s BITS bit. If the BITS bit is set to “1”
(10-bit conversion accuracy), the A-D conversion result is stored in the ADi register (i = 0 to 7)'s bit 0 to bit 9.
If the BITS bit is set to “0” (8-bit conversion accuracy), the A-D conversion result is stored in the ADi
register's bit 0 to bit 7.
(b) Sample and Hold
If the ADCON2 register’s SMP bit is set to “1” (with sample-and-hold), the conversion speed per pin is
increased to 28 φAD cycles for 8-bit resolution or 33 φAD cycles for 10-bit resolution. Sample-and-hold is
effective in all operation modes. Select whether or not to use the sample-and-hold function before starting
A-D conversion.
(c) Extended Analog Input Pins
In one-shot and repeat modes, the ANEX0 and ANEX1 pins can be used as analog input pins. Use the
ADCON1 register’s OPA1 to OPA0 bits to select whether or not use ANEX0 and ANEX1.
The A-D conversion results of ANEX0 and ANEX1 inputs are stored in the AD0 and AD1 registers,
respectively.
(d) External Operation Amp Connection Mode
Multiple analog inputs can be amplified using a single external op-amp via the ANXE0 and ANEX1 pins.
Set the ADCON1 register’s OPA1 to OPA0 bits to “112” (external op-amp connection mode). The inputs
from ANi (i = 0 to 7) (Note) are output from the ANEX0 pin. Amplify this output with an external op-amp
before sending it back to the ANEX1 pin. The A-D conversion result is stored in the corresponding ADi
register. The A-D conversion speed depends on the response characteristics of the external op-amp.
Note that the ANXE0 and ANEX1 pins cannot be directly connected to each other. Figure 1.16.9 shows
an example of how to connect the pins in external operation amp.
Note: AN0i and AN2i can be used the same as ANi.
Figure 1.16.9 External Op-amp Connection
ADCON2 register’s ADGSEL1 to ADGSEL0 bits=00
2
Successive conversion
register
Comparator
External op-amp
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ANEX0
ANEX1
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
ADGSEL1 to ADGSEL0 bits=10
2
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
ADGSEL1 to ADGSEL0 bits=11
2
Resistor ladder
Microcomputer
Rev.1.00 2003.05.30 page 202
M16C/6N4 Group A-D Converter
Under development
This document is under development and its contents are subject to change.
(e) Current Consumption Reducing Function
When not using the A-D converter, its resistor ladder and reference voltage input pin (VREF) can be separated
using the ADCON1 register’s VCUT bit. When separated, no current will flow from the VREF pin into the
resistor ladder, helping to reduce the power consumption of the chip.
To use the A-D converter, set the VCUT bit to “1” (VREF connected) and then set the ADCON0 register’s
ADST bit to “1” (A-D conversion start). The VCUT and ADST bits cannot be set to “1” at the same time.
Nor can the VCUT bit be set to “0” (VREF unconnected) during A-D conversion.
Note that this does not affect VREF for the D-A converter (irrelevant).
(f) Analog Input Pin and External Sensor Equivalent Circuit Example
Figure 1.16.10 shows analog input pin and external sensor equivalent circuit example.
Figure 1.16.10 Analog Input Pin and External Sensor Equivalent Circuit
R
0
R
C
VIN
Microcomputer
Sensor equivalent
circuit
VC
Sampling time
Sample-and-hold function enabled:
Sample-and-hold function disabled:
3
f
AD
2
f
AD
Rev.1.00 2003.05.30 page 203
M16C/6N4 Group D-A Converter
Under development
This document is under development and its contents are subject to change.
D-A Converter
This is an 8-bit, R-2R type D-A converter. These are two independent D-A converters.
D-A conversion is performed by writing to the DAi register (i = 0, 1). To output the result of conversion, set
the DACON register’s DAiE bit to “1” (output enabled). Before D-A conversion can be used, the corresponding
port direction bit must be set to “0” (input mode). Setting the DAiE bit to “1” removes a pull-up from the
corresponding port.
Output analog voltage (V) is determined by a set value (n : decimal) in the DAi register.
V = VREF ✕ n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 1.17.1 lists the performance of the D-A converter. Figure 1.17.1 shows the block diagram of the D-A
converter. Figure 1.17.2 shows the D-A converter-related registers. Figure 1.17.3 shows the D-A converter
equivalent circuit.
Item Performance
D-A conversion method R-2R method
Resolution 8 bits
Analog output pin 2 (DA0 and DA1)
Table 1.17.1 D-A Converter Performance
Figure 1.17.1 D-A Converter Block Diagram
DA0E bit
DA
0
Data bus low-order
DA1E bit
DA
1
DA0 register
R-2R ladder resistor
DA1 register
R-2R ladder resistor
Rev.1.00 2003.05.30 page 204
M16C/6N4 Group D-A Converter
Under development
This document is under development and its contents are subject to change.
Figure 1.17.2 DACON Register, DA0 Register and DA1 Register
Figure 1.17.3 D-A Converter Equivalent Circuit
D-A control register (Note)
Symbol Address After reset
Symbol Address After reset
DACON 03DC16
03D816
03DA16
0016
b7 b6 b5 b4 b3 b2 b1 b0
D-A0 output enable bit
Bit symbol Bit name Function RW
D-A1 output enable bit
DA0
DA1
Indeterminate
Indeterminate
b7 b0
Function
Output value of D-A conversion
RW
RW
-
RW
RW
DA0E
DA1E
-
(b7-b2)
0 : Output disabled
1 : Output enabled
0 : Output disabled
1 : Output enabled
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
Note: When not using the D-A converter, set the DAiE bit (i = 0, 1) to "0" (output disabled) to reduce the unnecessary
current consumption in the chip and set the DAi register to "0016" to prevent current from flowing into the R-2R
resistor ladder.
Note: When not using the D-A converter, set the DAiE bit (i = 0, 1) to "0" (output disabled) to reduce the unnecessary
current consumption in the chip and set the DAi register to "0016" to prevent current from flowing into the R-2R
resistor ladder.
D-Ai register (Note) (i = 0, 1)
VREF
AVSS
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
2R
DAiE bit
DAi
"1""0"
MSB LSB
DAi register
R
i = 0, 1
Note: The above diagram shows an instance in which the DAi register is assigned "2A
16
".
"1"
"0"
Rev.1.00 2003.05.30 page 205
M16C/6N4 Group CRC Calculation
Under development
This document is under development and its contents are subject to change.
CRC Calculation
The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a
generator polynomial of CRC-CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8-bit
unit. After the initial value is set in the CRCD register, the CRC code is set in that register each time one
byte of data is written to the CRCIN register. CRC code generation for one-byte data is finished in two
cycles.
Figure 1.18.1 shows the block diagram of the CRC circuit. Figure 1.18.2 shows the CRC-related registers.
Figure 1.18.3 shows the calculation example using the CRC operation.
Figure 1.18.2 CRCD Register and CRCIN Register
Figure 1.18.1 CRC Circuit Block Diagram
High-order 8 bitsLow-order 8 bits
CRCIN register
x
16
+x
12
+x
5
+1
Data bus high-order
Data bus low-order
CRCD register
CRC code generating circuit
When data is written to the CRCIN register after setting
the initial value in the CRCD register, the CRC code can
be read out from the CRCD register.
000016 to FFFF16
Function Setting range
RW
RW
CRCD
Symbol After reset
Indeterminate
03BD16-03BC16
Address
b7 b0 b7 b0
(b15) (b8)
CRC data register
Data input 00
16 to FF16
Function Setting range
RW
RW
CRCIN
Symbol After reset
Indeterminate
03BE
16
Address
b7 b0
CRC input register
Rev.1.00 2003.05.30 page 206
M16C/6N4 Group CRC Calculation
Under development
This document is under development and its contents are subject to change.
Figure 1.18.3 CRC Calculation
→ →
(2) Write 0000
16
(initial value)
b15 b0
CRCD register
1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
1000 1000
Generator polynomial
Data
CRC code
Modulo-2 operation is
operation that complies
with the law given below.
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
Setup procedure and CRC operation when generating CRC code "80C4
16
"
(a) CRC operation performed by the M16C
CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is
divided by the generator polynomial
(1) Reverse the bit positions of the value "80C4
16
" bytewise in a program.
(3) Write 01
16
b0b7
b15 b0
CRCIN register
CRCD register
1189
16
Two cycles later, the CRC code for "80
16
," i.e.,
9188
16
, has its bit positions reversed to become
"1189
16
" which is stored in the CRCD register.
(c) Details of CRC operation
In the case of (3) above, the value written to the CRCIN register "01
16
(00000001
2
)" has its bit positions reversed to
become "10000000
2
". The value "1000 0000 0000 0000 0000 0000
2
" derived from that by adding 16 digits and the
CRCD register s initial value "0000
16
" are added, the result of which is divided by the generator polynomial using
modulo-2 arithmetic.
The value "0001 0001 1000 1001
2
(1189
16
)" derived from the remainder "1001 0001 1000 1000
2
(9188
16
)" by
reversing its bit positions may be read from the CRCD register.
If operation (4) above is performed subsequently, the value written to the CRCIN register "23
16
(00100011
2
)" has its bit
positions reversed to become "11000100
2
". The value "1100 0100 0000 0000 0000 0000
2
" derived from that by adding
16 digits and the remainder in (3) "1001 0001 1000 1000
2
" which is left in the CRCD register are added, the result of
which is divided by the generator polynomial using modulo-2 arithmetic.
The value "0000 1010 0100 0001
2
(0A41
16
)" derived from the remainder by reversing its bit positions may be read from
the CRCD register.
(b) Setting procedure
Generator polynomial: X
16
+ X
12
+ X
5
+ 1 (1 0001 0000 0010 0001
2
)
"80
16
" "01
16
", "C4
16
" "23
16
"
(4) Write 23
16
b0b7
b15 b0
0A41
16
CRCIN register
CRCD register
Two cycles later, the CRC code for "80C4
16
," i.e.,
8250
16
, has its bit positions reversed to become
"0A41
16
" which is stored in the CRCD register.
Rev.1.00 2003.05.30 page 207
M16C/6N4 Group CAN Module
Under development
This document is under development and its contents are subject to change.
CAN Module
The CAN (Controller Area Network) module for the M16C/6N4 group of microcomputers is a communication
controller implementing the CAN 2.0B protocol as defined in the BOSCH specification. The M16C/6N4
group contains two CAN modules which can transmit and receive messages in both standard (11-bit) ID
and extended (29-bit) ID formats.
Figure 1.19.1 shows a block diagram of the CAN module.
External CAN bus driver and receiver are required.
Figure 1.19.1 Block Diagram of CAN Module
CTx/CRx: CAN I/O pins.
Protocol controller: This controller handles the bus arbitration and the CAN protocol services, i.e. bit
timing, stuffing, error status etc.
Message box: This memory block consists of 16 slots that can be configured either as transmitter
or receiver. Each slot contains an individual ID, data length code, a data field
(8 bytes) and a time stamp.
Acceptance filter: This block performs filtering operation for received messages. For the filtering
operation, the CiGMR register (i = 0, 1), the CiLMAR register, or the CiLMBR
register is used.
16 bit timer: Used for the time stamp function. When the received message is stored in the
message memory, the timer value is stored as a time stamp.
Wake up function: CAN0/1 wake up interrupt is generated by a message from the CAN bus.
Interrupt generation function
: The interrupt events are provided by the CAN module. CANi successful reception
interrupt, CANi successful transmission interrupt, CAN0/1 error interrupt, and
CAN0/1 wake up interrupt.
CiCONR Register CiCTLR Register CiIDR Register
i = 0, 1
j = 0 to 15
Interrupt
Generation
Function
Message Box
slots 0 to 15
Message ID
DLC
Message Data
Time Stamp
CTX
CRX
CiGMR Register
CiLMAR Register
CiLMBR Register
CANi Error Int
CANi Wake Up Int
Data Bus
Data Bus
CiMCTLj Register
CiTSR Register
16 Bit Timer
Acceptance Filter
slots 0 to 15
Protocol
Controller
Wake Up
Function
CiSSTR Register CiICR Register
CiSTR Register
CiRECR Register
CiTECR Register
CANi Successful Reception Int
CANi Successful Transmission Int
Rev.1.00 2003.05.30 page 208
M16C/6N4 Group CAN Module
Under development
This document is under development and its contents are subject to change.
CAN Module-Related Registers
The CANi (i = 0, 1) modules have the following registers.
(1) CAN Message Box
A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as Basic CAN.
• Priority of the slots: The smaller the number of the slot, the higher the priority, in both transmission and
reception.
• A program can define whether a slot is defined as transmitter or receiver.
(2) Acceptance Mask Registers
A CAN module is equipped with 3 masks for the acceptance filter.
• CANi global mask register (CiGMR register: 6 bytes)
Configuration of the masking condition for acceptance filtering processing to slots 0 to 13
• CANi local mask A register (CiLMAR register: 6 bytes)
Configuration of the masking condition for acceptance filtering processing to slot 14
• CANi local mask B register (CiLMBR register: 6 bytes)
Configuration of the masking condition for acceptance filtering processing to slot 15
(3) CAN SFR Registers
• CANi message control register j (CiMCTLj register: 8 bits ✕ 16) (j = 0 to 15)
Control of transmission and reception of a corresponding slot
• CANi control register (CiCTLR register: 16 bits)
Control of the CAN protocol
• CANi status register (CiSTR register: 16 bits)
Indication of the protocol status
• CANi slot status register (CiSSTR register: 16 bits)
Indication of the status of contents of each slot
• CANi interrupt control register (CiICR register: 16 bits)
Selection of “interrupt enabled or disabled” for each slot
• CANi extended ID register (CiIDR register: 16 bits)
Selection of ID format (standard or extended) for each slot
• CANi configuration register (CiCONR register: 16 bits)
Configuration of the bus timing
• CANi receive error count register (CiRECR register: 8 bits)
Indication of the error status of the CAN module in reception: the counter value is incremented or
decremented according to the error occurrence.
• CANi transmit error count register (CiTECR register: 8 bits)
Indication of the error status of the CAN module in transmission: the counter value is incremented or
decremented according to the error occurrence.
• CANi time stamp register (CiTSR register: 16 bits)
Indication of the value of the time stamp counter
• CANi acceptance filter support register (CiAFS register: 16 bits)
Decoding the received ID for use by the acceptance filter support unit
Explanation of each register is given below.
Rev.1.00 2003.05.30 page 209
M16C/6N4 Group CAN Module
Under development
This document is under development and its contents are subject to change.
CANi Message Box (i = 0, 1)
Table 1.19.1 shows the memory mapping of the CANi message box.
It is possible to access to the message box in byte or word.
Mapping of the message contents differs from byte access to word access. Byte access or word access can
be selected by the MsgOrder bit of the CiCTLR register.
Table 1.19.1 Memory Mapping of CANi Message Box (n = 0 to 15: the number of the slot)
CAN0 CAN1 Byte access (8 bits) Word access (16 bits)
Address Message content (Memory mapping)
0060
16
+ n •16 + 0 0260
16
+ n •16 + 0 SID
10
to SID
6
SID
5
to SID
0
0060
16
+ n •16 + 1 0260
16
+ n •16 + 1 SID
5
to SID
0
SID
10
to SID
6
0060
16
+ n •16 + 2 0260
16
+ n •16 + 2 EID
17
to EID
14
EID
13
to EID
6
0060
16
+ n •16 + 3 0260
16
+ n •16 + 3 EID
13
to EID
6
EID
17
to EID
14
0060
16
+ n •16 + 4 0260
16
+ n •16 + 4 EID
5
to EID
0
Data Length Code (DLC)
0060
16
+ n •16 + 5 0260
16
+ n •16 + 5 Data Length Code (DLC) EID
5
to EID
0
0060
16
+ n •16 + 14 0260
16
+ n •16 + 14
0060
16
+ n •16 + 15 0260
16
+ n •16 + 15
Time stamp high-order byte
Time stamp low-order byte Time stamp high-order byte
Time stamp low-order byte
0060
16
+ n •16 + 6 0260
16
+ n •16 + 6 Data byte 0
0060
16
+ n •16 + 7 0260
16
+ n •16 + 7 Data byte 1
Data byte 1
Data byte 0
0060
16
+ n •16 + 13 0260
16
+ n •16 + 13 Data byte 7 Data byte 6
i = 0, 1
Rev.1.00 2003.05.30 page 210
M16C/6N4 Group CAN Module
Under development
This document is under development and its contents are subject to change.
Figures 1.19.2 and 1.19.3 show the bit mapping in each slot in byte access and word access. The content
of each slot remains unchanged unless transmission or reception of a new message is performed.
Figure 1.19.2 Bit Mapping in Byte Access
Figure 1.19.3 Bit Mapping in Word Access
Bit 7 Bit 0
SID10 SID9SID8SID7SID6
SID5SID4SID3SID2SID1SID0
EID17 EID16 EID15 EID14
EID13 EID12 EID11 EID10 EID9EID8EID7EID6
EID5EID4EID3EID2EID1EID0
DLC3DLC2DLC1DLC0
Data Byte 0
Data Byte 1
Data Byte 7
Note: When
The value is "0" when read on the reception slot configuration.
is read, the value is the one written upon the transmission slot configuration.
CAN Data Frame:
Time Stamp high-order byte
Time Stamp low-order byte
SID10 to 6 SID5 to 0 EID17 to 14 EID13 to 6 EID5 to 0 DLC3 to 0 Data Byte 0 Data Byte 1 Data Byte 7
Bit 15 Bit 0
SID10 SID9SID8SID7SID6SID5SID4SID3SID2SID1SID0
Bit 8 Bit 7
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9EID8EID7EID6
EID5EID4EID3EID2EID1EID0DLC3DLC2DLC1DLC0
Data Byte 0 Data Byte 1
Time Stamp high-order byte Time Stamp low-order byte
CAN Data Frame:
Data Byte 2 Data Byte 3
Data Byte 4 Data Byte 5
Data Byte 6 Data Byte 7
Note: When
The value is "0" when read on the reception slot configuration.
is read, the value is the one written upon the transmission slot configuration.
SID
10 to 6
SID
5 to 0
EID
17 to 14
EID
13 to 6
EID
5 to 0
DLC
3 to 0
Data Byte 0 Data Byte 1 Data Byte 7
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Figure 1.19.4 Bit Mapping of Mask Registers in Byte Access
Acceptance Mask Registers
Figures 1.19.4 and 1.19.5 show the CiGMR register (i = 0, 1), the CiLMAR register, and the CiLMBR
register, in which bit mapping in byte access and word access are shown.
Figure 1.19.5 Bit Mapping of Mask Registers in Word Access
Bit 7 Bit 0
SID10 SID9SID8SID7SID6
SID5SID4SID3SID2SID1SID0
EID17 EID16 EID15 EID14
EID13 EID12 EID11 EID10 EID9EID8EID7EID6
EID5EID4EID3EID2EID1EID0
SID10 SID9SID8SID7SID6
SID5SID4SID3SID2SID1SID0
EID17 EID16 EID15 EID14
EID13 EID12 EID11 EID10 EID9EID8EID7EID6
EID5EID4EID3EID2EID1EID0
SID10 SID9SID8SID7SID6
SID5SID4SID3SID2SID1SID0
EID17 EID16 EID15 EID14
EID13 EID12 EID11 EID10 EID9EID8EID7EID6
EID5EID4EID3EID2EID1EID0
i = 0, 1
CiGMR register
CiLMAR register
CiLMBR register
016016 036016
016116 036116
016216 036216
016316 036316
016416 036416
016616 036616
016716 036716
016816 036816
016916 036916
016A16 036A16
016C16 036C16
016D16 036D16
016E16 036E16
016F16 036F16
017016 037016
Addresses
CAN0 CAN1
Bit 15 Bit 0
SID
10
SID
9
SID
8
SID
7
SID
6
SID
5
SID
4
SID
3
SID
2
SID
1
SID
0
Bit 8 Bit 7
EID
17
EID
16
EID
15
EID
14
EID
13
EID
12
EID
11
EID
10
EID
9
EID
8
EID
7
EID
6
EID
5
EID
4
EID
3
EID
2
EID
1
EID
0
SID
10
SID
9
SID
8
SID
7
SID
6
SID
5
SID
4
SID
3
SID
2
SID
1
SID
0
EID
17
EID
16
EID
15
EID
14
EID
13
EID
12
EID
11
EID
10
EID
9
EID
8
EID
7
EID
6
EID
5
EID
4
EID
3
EID
2
EID
1
EID
0
SID
10
SID
9
SID
8
SID
7
SID
6
SID
5
SID
4
SID
3
SID
2
SID
1
SID
0
EID
17
EID
16
EID
15
EID
14
EID
13
EID
12
EID
11
EID
10
EID
9
EID
8
EID
7
EID
6
EID
5
EID
4
EID
3
EID
2
EID
1
EID
0
i = 0, 1
CiGMR register
CiLMAR register
CiLMBR register
0160
16
0360
16
0162
16
0362
16
0164
16
0364
16
0166
16
0366
16
0168
16
0368
16
016A
16
036A
16
016C
16
036C
16
016E
16
036E
16
0170
16
0370
16
Addresses
CAN0 CAN1
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CAN SFR Registers
CiMCTLj Register (i = 0, 1, j = 0 to 15)
Figure 1.19.6 shows the CiMCTLj register.
Figure 1.19.6 CiMCTLj Register
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function (Note 4) RW
RO
(Note 1)
RO
(Note 1)
RO
RO
RO
(Note 1)
NewData Successful
reception flag
SentData Successful
transmission flag
When set to reception slot
0: The content of the slot is read or still under
processing by the CPU.
1 The CAN module has stored new data in the slot.
When set to reception slot
0: The message is valid.
1: The message is invalid.
(The message is being updated.)
When set to reception slot
0: No message has been overwritten in this slot.
1: This slot already contained a message, but it has
been overwritten by a new one.
When set to transmission slot
0: Transmission is not started or completed yet.
1: Transmission is successfully completed.
When set to transmission slot
0: Waiting for bus idle or completion of arbitration.
1: Transmitting
InvalData
TrmActive
"Under reception"
flag
"Under
transmission" flag
MsgLost Overwrite flag
Remote frame
transmission/
reception status
flag (Note 2)
0: Data frame transmission/reception status
1: Remote frame automatic transfer status
RemActive
RspLock Transmission/
reception auto
response lock
mode select bit
Remote frame
corresponding
slot select bit
When set to reception remote frame slot
0: After a remote frame is received, it will be
answered automatically.
1: After a remote frame is received, no transmission
will be started as long as this bit is set to "1".
(Not responding)
0: Slot not corresponding to remote frame
1: Slot corresponding to remote frame
Remote
0: Not reception slot
1: Reception slot
RecReq Reception slot
request bit
(Note 3)
0: Not transmission slot
1: Transmission slot
TrmReq Transmission
slot request bit
(Note 3)
Note 1: As for write, only writing "0" is possible. The value of each bit is written when the CAN module enters the respective state.
Note 2: In Basic CAN mode, they serve as data format identification flag. Refer to "Basic CAN Mode" for more details.
Note 3: One slot cannot be defined as reception slot and transmission slot at the same time.
Note 4: This register can not be set in CAN reset/initialization mode of the CAN module.
CANi message control register j (i = 0, 1, j = 0 to 15) (Note 4)
Symbol
C0MCTL0 to C0MCTL15
to 020F
16
0200
16
to 022F
16
0220
16
00
16
00
16
C1MCTL0 to C1MCTL15
After reset
Address
RW
RW
RW
RW
RW
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Figure 1.19.7 CiCTLR Register
CiCTLR Register (i = 0, 1)
Figure 1.19.7 shows the CiCTLR register.
Bit symbol Bit name Function
Reset CAN module
reset bit
LoopBack Loop back mode
select bit
MsgOrder Message order
BasicCAN Basic CAN mode
select bit
select bit
BusErrEn Bus error interrupt
enable bit
Sleep Sleep mode
select bit
PortEn CAN port enable bit
-
(b7)
CANi control register (i = 0, 1)
Symbol Address After reset
C0CTLR X0000001
2
C1CTLR 0230
16
0210
16
X0000001
2
b7 b6 b5 b4 b3 b2 b1 b0
Note: CTx/CRx function regardless of configuration of PD7 and PD9 registers.
RW
RW
RW
RW
RW
RW
RW
RW
-
0: Operation mode
1: Reset/initialization mode
0: Word access
1: Byte access
0: Normal operation mode
1: Basic CAN mode
0: Normal operation mode
1: Loop back mode
0: Bus error interrupt disabled
1: Bus error interrupt enabled
0: Sleep mode disabled
1: Sleep mode enabled; clock supply stopped
0: I/O port function
1: CTx/CRx function (Note)
(b15) (b8)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function
TSPreScale
Bit1, Bit0
TSReset
RXOnly
RetBusOff
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
XX0X0000
2
XX0X0000
2
Symbol Address After reset
C0CTLR 0211
16
C1CTLR 0231
16
b1 b0
Note 1: When the TSReset bit = 1, the CiTSR register is set to "0000
16
". After this, the bit is automatically set to "0".
Note 2: When the RetBusOff bit = 1, the CiRECR register and the CiTECR register are set to "00
16
". After this, the bit is automatically set to "0".
RW
RW
RW
RW
-
RW
-
0 0: Period of 1 bit time
0 1: Period of 1/2 bit time
1 0: Period of 1/4 bit time
1 1: Period of 1/8 bit time
0: Normal operation mode
1: Force reset of the time stamp counter
0: Normal operation mode
1: Listen-only mode
0: Normal operation mode
1: Force return from bus off
Time stamp
prescaler
Time stamp counter
reset bit
(Note 1)
Return from bus off
command bit
(Note 2)
Listen-only mode
select bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
-
(b4)
-
(b7-b6)
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Figure 1.19.8 CiSTR Register
CiSTR Register (i = 0, 1)
Figure 1.19.8 shows the CiSTR register.
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function
State_Reset Reset state flag
State_
LoopBack
Loop back state flag
State_
MsgOrder
Message order
state flag
State_
BasicCAN
Basic CAN mode
state flag
State_
BusError
Bus error
state flag
State_
ErrPass
Error passive
state flag
State_
BusOff
-
(b7)
Error bus off
state flag
0: Operation mode
1: Reset mode
0:Word access
1: Byte access
0: Normal operation mode
1: Basic CAN mode
0: No error has occurred.
1: A CAN bus error has occurred.
0: Normal operation mode
1: Loop back mode
0: The CAN module is not in error passive state.
1: The CAN module is in error passive state.
0: The CAN module is not in error bus off state.
1: The CAN module is in error bus off state.
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
RW
RO
RO
RO
RO
RO
RO
RO
-
Symbol Address
C0STR 0213
16
X0000001
2
C1STR 0233
16
X0000001
2
After reset
CANi status register (i = 0, 1) (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function
MBOX Active slot bits
b3 b2 b1 b0
RW
RO
RO
RO
RO
RO
Successful
reception flag
Transmission flag
(Transmitter)
Reception flag
(Receiver)
0 0 0 0 : Slot 0
0 0 0 1 : Slot 1
0 0 1 0 : Slot 2
.
.
.
1 1 1 0 : Slot 14
1 1 1 1 : Slot 15
0: No [successful] reception
1: CAN module received a message successfully.
0: CAN module is idle or receiver.
1: CAN module is transmitter.
0: CAN module is idle or transmitter.
1: CAN module is receiver.
TrmSucc Successful
transmission flag
0: No [successful] transmission
1: The CAN module has transmitted a message
successfully.
RecSucc
TrmState
RecState
Symbol Address
C0STR 0212
16
00
16
C1STR 0232
16
00
16
After reset
Note: This register can not be set in CAN reset/initialization mode of the CAN module.
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Figure 1.19.9 CiSSTR Register
CiSSTR Register (i = 0, 1)
Figure 1.19.9 shows the CiSSTR register.
(b15) (b8)
b7 b0 b7 b0
Function
Slot status bits
Each bit corresponds to the slot with the
same number.
0: Reception slot
The message has been read.
Transmission slot
Transmission is not completed.
1: Reception slot
The message has not been read.
Transmission slot
Transmission is completed.
CANi slot status register (i = 0, 1)
RW
RO
Symbol Address After reset
C0SSTR 0215
16
, 0214
16
0000
16
C1SSTR 0235
16
, 0234
16
0000
16
Setting values
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Figure 1.19.10 CiICR Register
CiIDR Register
Figure 1.19.11 shows the CiIDR register.
CiICR Register (i = 0, 1)
Figure 1.19.10 shows the CiICR register.
Figure 1.19.11 CiIDR Register
CANi interrupt control register (i = 0, 1) (Note)
(b15) (b8)
b0b0 b7b7
Function
Setting values
Interrupt enable bits:
Each bit corresponds with a slot with the same
number.
Enabled/disabled of successful transmission inter-
rupt or successful reception interrupt can be selected.
0: Interrupt disabled
1: Interrupt enabled
RW
RW
Symbol Address After reset
C0ICR 021716, 021616 000016
C1ICR 023716, 023616 000016
Note: This register can not be set in CAN reset/initialization mode of the CAN module.
CANi extended ID register (i = 0, 1) (Note)
Symbol Address After reset
C0IDR 0219
16
, 0218
16
0000
16
C1IDR 0239
16
, 0238
16
0000
16
(b15) (b8)
Function
Setting values
b0b0 b7b7
RW
RW
Extended ID bits:
Each bit corresponds with a slot with the same
number.
Selection of the ID format that each slot handles.
0: Standard ID
1: Extended ID
Note: This bit can not be set in CAN reset/initialization mode of the CAN module.
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Figure 1.19.12 CiCONR Register
CiCONR Register (i = 0, 1)
Figure 1.19.12 shows the CiCONR register.
C0CONR
C1CONR 023A
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function
BRP
SAM
PTS
0 : One time sampling
1 : Three times sampling
0 0 0 0 : Divide-by-1 of f
CAN
0 0 0 1 : Divide-by-2 of f
CAN
0 0 1 0 : Divide-by-3 of f
CAN
1 1 1 0 : Divide-by-15 of f
CAN
1 1 1 1 : Divide-by-16 of f
CAN
(Note)
.....
0 0 0 : 1Tq
0 0 1 : 2Tq
0 1 0 : 2Tq
1 1 0 : 7Tq
1 1 1 : 8Tq
(b15) (b8)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function RW
RW
RW
RW
PBS1 Phase buffer
segment 1
control bits
PBS2 Phase buffer
segment 2
control bits
SJW Resynchronization
jump width
control bits
.....
CANi configuration register (i = 0, 1)
C0CONR
C1CONR
b3 b2 b1 b0
b7 b6 b5
b2 b1b0
b5 b4 b3
b7 b6
021A
16
Note: f
CAN
serves for the CAN clock. The period is decided by configuration of the CCLKi bits (i = 0 to 2 and 4 to 6) of CCLKR register.
Symbol Address
Symbol Address
Sampling control
bit
Prescaler division
ratio select bits
Propagation time
segment control bits
RW
RW
RW
RW
..... .....
021B
16
023B
16
0 0 0 : Inhibited
0 0 1 : 2Tq
0 1 0 : 3Tq
1 1 0 : 7Tq
1 1 1 : 8Tq
0 0 0 : Inhibited
0 0 1 : 2Tq
0 1 0 : 3Tq
1 1 0 : 7Tq
1 1 1 : 8Tq
0 0 : 1Tq
0 1 : 2Tq
1 0 : 3Tq
1 1 : 4Tq
After reset
After reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
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Figure 1.19.13 CiRECR Register
CiTECR Register (i = 0, 1)
Figure 1.19.14 shows the CiTECR register.
Figure 1.19.14 CiTECR Register
CiRECR Register (i = 0, 1)
Figure 1.19.13 shows the CiRECR register.
Reception error counting function
The value is incremented or decremented
according to the CAN module’s error status.
00
16
to FF
16
(Note 1)
CANi receive error count register (i = 0, 1) (Note 2)
Address
Symbol After reset
C0RECR 021C
16
00
16
C1RECR 023C
16
00
16
b7 b0
Function Counter value
Note 1: The value is indeterminate in bus off state.
Note 2: This register can not be set in CAN reset/initialization mode of the CAN module.
RW
RO
C0TECR 021D16
0016
023D16
0016
C1TECR
CANi transmit error count register (i = 0, 1) (Note)
b7 b0
Function
0016 to FF16
Counter value
RW
RO
Symbol Address After reset
Transmission error counting function
The value is incremented or decremented
according to the CAN module’s error status.
Note: This register can not be set in CAN reset/initialization mode of the CAN module.
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Figure 1.19.15 CiTSR Register
CiAFS Register (i = 0, 1)
Figure 1.19.16 shows the CiAFS register.
CiTSR Register (i = 0, 1)
Figure 1.19.15 shows the CiTSR register.
0000
16
to FFFF
16
CANi time stamp register (i = 0, 1) (Note)
C0TSR 021F
16
, 021E
16
0000
16
C1TSR 023F
16
, 023E
16
0000
16
(b15) (b8)
Function
Setting range
b0b0 b7b7
Time stamp function
Symbol Address After reset
RW
RO
Note: This register can not be set in CAN reset/initialization mode of the CAN module.
Figure 1.19.16 CiAFS Register
(b15)
b7
(b8)
b0 b7 b0
Function
Setting values
CANi acceptance filter support register (i = 0, 1)
C0AFS , 0242
16
C1AFS
0243
16
0245
16
, 0244
16
RW
RW
Symbol Address
Write the content equivalent to the standard frame
ID of the received message.
The value is "converted standard frame ID" when
read.
Standard frame ID
Indeterminate
Indeterminate
After reset
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Operational Modes
The CAN module has the following three operational modes.
• CAN Reset/Initialization Mode
• CAN Sleep Mode
• CAN Operation Mode
Figure 1.19.17 shows transition between operational modes.
Figure 1.19.17 Transition Between Operational Modes
CAN Reset/Initialization Mode
The CAN reset/initialization mode is activated upon MCU reset or by setting the Reset bit of the CiCTLR
register (i = 0, 1). It can be observed by reading the State_Reset bit of the CiSTR register. Entering the
CAN reset/initialization mode initiates the following functions by the module:
•Suspend all communication functions. When the CAN reset/initialization mode is activated during an
ongoing transmission in operation mode, the module suspends the mode transition until completion
of the transmission (successful, arbitration loss, or error detection) and then sets the State_Reset bit.
•Initialization of CiMCTLj (j = 0 to 15), CiSTR, CiICR, CiIDR,CiRECR, CiTECR and CiTSR registers to
their reset values. All these registers are locked to prevent CPU modification.
•The CiCTLR and CiCONR registers and the message box retain their contents and are available for
CPU access.
MCU Reset
Reset/initialization
mode
(State_Reset = 1)
Operation mode
(State_Reset = 0)
Sleep mode Bus off state
(State_BusOff = 1)
Reset = 0
Reset = 1
Reset = 1
Sleep = 1
RetBusOff = 1
Sleep = 0
TEC > 255
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CAN Operation Mode
The CAN operation mode is activated by clearing the Reset bit of the CiCTLR register. Entering the
operation mode initiates the following functions by the module:
•The module's communication functions are released and it becomes an active node on the network
and may transmit and receive CAN messages.
• Release the internal fault confinement logic including receive and transmit error counters. The module
may leave the CAN operation mode depending on the error counts.
Within the CAN operation mode the module may be in three different sub modes, depending on which
type of communication functions are performed:
• Module idle: The modules receive and transmit sections are inactive.
• Module receives: The module receives a CAN message sent by another node.
• Module transmits: The module transmits a CAN message. The module may receive its own message
simultaneously when the loopback function is enabled.
Figure 1.19.18 shows sub modes of the CAN operation mode.
Figure 1.19.18 Sub Modes of CAN Operation Mode
CAN Sleep Mode
The CAN sleep mode is activated by setting the Sleep bit of the CiCTLR register. It should never be
activated from the CAN operation mode but only via the CAN reset/initialization mode. Entering the CAN
sleep mode instantly stops the modules clock supply and thereby reduces power dissipation.
Bus off State
The bus off state is entered according to the fault confinement rules of the CAN specification. It can be
quit instantly to error active state by setting the RetBusOff bit of the CiCTLR register to “1” (force return from
buss off) and CAN communication becomes possible again. This does not alter any CAN registers, except
CiRECR and CiTECR registers.
Lost in arbitration
Start
transmission
Detect
an SOF
Finish
transmission
Finish
reception
Module idle
TrmState = 0
RecState = 0
Module transmits
TrmState = 1
RecState = 0
Module receives
TrmState = 0
RecState = 1
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Configuration of the CAN Module System Clock
The M16C/6N4 group has a CAN module system clock select circuit dedicated to each channel.
Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the
BRP bits of the CiCONR registers (i = 0, 1).
For the CCLKR register, refer to “Clock Generation Circuit”.
Figure 1.19.19 shows a block diagram of the clock generation circuit of the CAN module system.
Figure 1.19.19 Block Diagram of CAN Module System Clock Generation Circuit
CAN Bus Timing Control
Bit Timing Configuration
The bit time consists of the following four segments:
• Synchronization segment (SS)
This serves for monitoring a falling edge for synchronization.
• Propagation time segment (PTS)
This segment absorbs physical delay on the CAN network which amounts to double the total sum of
delay on the CAN bus, the input comparator delay, and the output driver delay.
• Phase buffer segment 1 (PBS1)
This serves for compensating the phase error. When the falling edge of the bit falls later than expected,
the segment can become longer by the maximum of the value defined in SJW.
• Phase buffer segment 2 (PBS2)
This segment has the same function as the phase buffer segment 1. When the falling edge of the bit
falls earlier than expected, the segment can become shorter by the maximum of the value defined in
SJW.
Figure 1.19.20 shows the bit timing.
Figure 1.19.20. Bit Timing
1/2
Divide-by-1 of X
IN
(undivided)
Divide-by-2 of X
IN
Divide-by-4 of X
IN
Divide-by-8 of X
IN
Divide-by-16 of X
IN
Prescaler
CAN module
Prescaler
for baud rate
Division by (P + 1)
fCAN
fCANCLK
i = 0, 1
fCAN: CAN module system clock
P: The value written in the BRP bit of the CiCONR register. P = 0 to 15
fCANCLK: CAN communication clock fCANCLK = fCAN/2(P + 1)
XIN Divider
CCLKR register
Value: 1, 2, 4, 8, 16
The range of each segment: Bit time = 8 to 25Tq
SS = 1Tq
PTS = 1Tq to 8Tq
PBS1 = 2Tq to 8Tq
PBS2 = 2Tq to 8Tq
SJW = 1Tq to 4Tq
Configuration of PBS1 and PBS2: PBS1 ≥ PBS2
PBS1 ≥ SJW
PBS2 ≥ 2 when SJW = 1
PBS2 ≥ SJW when 2 ≤ SJW ≤ 4
Bit time
SS PTS PBS1
SJW
Sampling point
PBS2
SJW
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Baud Rate
Baud rate depends on XIN, the division value of the CAN module system clock, the division value of the
prescaler for baud rate, and the number of Tq of one bit.
Table 1.19.2 shows the examples of baud rate.
Table 1.19.2 Examples of Baud Rate
Calculation of Baud Rate
Note 1: fCAN division value = 1, 2, 4, 8, 16
fCAN division value: a value selected in the CCLKR register
Note 2: Division value of prescaler for baud rate = P + 1 (P: 0 to 15)
P: a value selected in the BRP bit of the CiCONR register (i = 0, 1)
2 ✕ "fCAN division value (Note 1)" ✕ "division value of prescaler for baud rate (Note 2)" ✕ "number of Tq of one bit"
XIN
Baud rate 20 MHz 16 MHz 10 MHz 8 MHz
1 Mbps 10Tq (1) 8Tq (1)
--
500 kbps 10Tq (2) 8Tq (2) 10Tq (1) 8Tq (1)
20Tq (1) 16Tq (1)
--
125 kbps 10Tq (8) 8Tq (8) 10Tq (4) 8Tq (4)
20Tq (4) 16Tq (4) 20Tq (2) 16Tq (2)
83.3 kbps 10Tq (12) 8Tq (12) 10Tq (6) 8Tq (6)
20Tq (6) 16Tq (6) 20Tq (3) 16Tq (3)
33.3 kbps 10Tq (30) 8Tq (30) 10Tq (15) 8Tq (15)
20Tq (15) 16Tq (15)
--
Note: The number in ( ) indicates a value of “fCAN division value” multiplied by “division value of the prescaler
for baud rate”.
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Figure 1.19.21 Correspondence of Mask Registers to Slots
Figure 1.19.22 Acceptance Function
When using the acceptance function, note the following points.
(1) When one ID is defined in two slots, the one with a smaller number alone is valid.
(2) When it is configured that slots 14 and 15 receive all IDs with Basic CAN mode, slots 14 and 15
receive all IDs which are not stored into slots 0 to 13.
Acceptance Filtering Function and Masking Function
These functions serve the users to select and receive a facultative message. The CiGMR register (i =0, 1),
the CiLMAR register, and the CiLMBR register can perform masking to the standard ID and the extended ID
of 29 bits. The CiGMR register corresponds to slots 0 to 13, the CiLMAR register corresponds to slot 14,
and the CiLMBR register corresponds to slot 15. The masking function becomes valid to 11 bits or 29 bits
of a received ID according to the value in the corresponding slot of the CiIDR register upon acceptance
filtering operation. When the masking function is employed, it is possible to receive a certain range of IDs.
Figure 1.19.21 shows correspondence of the mask registers and slots, Figure 1.19.22 shows the acceptance
function.
Slot #0
Slot #1
Slot #2
Slot #3
Slot #4
Slot #5
Slot #6
Slot #7
Slot #8
Slot #9
Slot #10
Slot #11
Slot #12
Slot #14
Slot #15
CiGMR register
Slot #13
CiLMAR register
CiLMBR register
i = 0, 1
ID of the
received message
ID stored in
the slot
The value of the
mask register
Acceptance Signal
Mask Bit Values
Acceptance judge signal
0: The CAN module ignores the
current incoming message.
(Not stored in any slot)
1: The CAN module stores the
current incoming message in
a slot of which ID matches.
0: ID (to which the received message
corresponds) match is handled as
"Don’t care".
1: ID (to which the received message
corresponds) match is checked.
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Acceptance Filter Support Unit (ASU)
The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search.
The IDs to receive are registered in the data table; a received ID is stored in the CiAFS register (i = 0, 1),
and table search is performed with a decoded received ID. The acceptance filter support unit can be used
for the IDs of the standard frame only.
The acceptance filter support unit is valid in the following cases.
• When the ID to receive cannot be masked by the acceptance filter.
(Example) IDs to receive: 07816, 08716, 11116
• When there are too many IDs to receive; it would take too much time to filter them by software.
Figure 1.19.23 shows the write and read of CiAFS register in word access.
Figure 1.19.23 Write/read of CiAFS Register in Word Access
Bit 15 Bit 0
Bit 8 Bit 7
When read
SID10 SID9SID8SID7SID6SID5SID4SID3
Bit 15 Bit 0
SID10 SID9SID8SID7SID6SID5SID4SID3SID2SID1SID0
Bit 8 Bit 7
When write
3/8 Decoder
24216 24416
24216 24416
Addresses
CAN0 CAN1
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Basic CAN Mode
When the BasicCAN bit of the CiCTLR register (i = 0, 1) is set to "1", slots 14 and 15 correspond to Basic
CAN mode. When slots 14 and 15 are defined as reception slots in Basic CAN mode, received messages
are stored in slots 14 and 15 alternately.
Figure 1.19.24 shows the operation of slots 14 and 15 in Basic CAN mode.
Figure 1.19.24 Operation of Slots 14 and 15 in Basic CAN Mode
When configuring Basic CAN mode, note the following points.
(1) Selection of Basic CAN mode has to be done in reset/initialization mode.
(2) Select the same ID for slots 14 and 15. Also, configuration of the CiLMAR register and that of the
CiLMBR register has to be the same.
(3) Define slots 14 and 15 as reception slot only.
(4) There is no protection available against message overwrite. A message can be overwritten by a new
message.
(5) Slots 0 to 13 can be used in the same way as in normal CAN operation mode.
Slot 14
Slot 15
Msg n Msg n+1 Msg n+2
Empty
Locked (empty) Locked (empty)
Msg n Locked
Msg n + 1
Msg n+2 (Msg n lost)
Locked (Msg n+1)
(Msg n)
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Return from Bus off Function
When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by
the return from bus off function of the CiCTLR register (i = 0, 1). At this time, the error state changes from
bus off state to error active state. Implementation of this function initializes the protocol controller. However,
registers of the CAN module such as CiCONR register and the content of each slot are not initialized.
Time Stamp Counter and Time Stamp Function
When the CiTSR register is read, the value of the time stamp counter at the moment is read. The period of
the time stamp counter reference clock is the same as that of 1 bit time that is configured by the CiCONR
register. The time stamp counter functions as a free run counter.
The 1 bit time period can be divided by 1 (undivided), 2, 4 or 8 to produce the time stamp counter reference
clock. Use the TSPreScale bits 1 and 0 of the CiCTLR register to select the divide-by-n value.
The time stamp counter is equipped with a register that captures the counter value when the protocol
controller regards it as a successful reception. The captured value is stored when a time stamp value is
stored in a reception slot.
Listen-Only Mode
When the RXOnly bit of the CiCTLR register is set to "1", the module enters listen-only mode.
In listen-only mode, no transmission -- data frames, error frames, and ACK response -- is performed to bus.
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Reception and Transmission
Configuration of CAN Reception and Transmission Mode
Table 1.19.3 shows configuration of CAN reception and transmission mode.
Table 1.19.3 Configuration of CAN Reception and Transmission Mode
RemActive bit, RspLock bit: CiMCTLj register’s bits (i = 0, 1, j = 0 to 15)
When configuring a slot as a reception slot, note the following points.
(1) Before configuring a slot as a reception slot, be sure to set the CiMCTLj registers (i = 0, 1, j = 0 to 15)
to “0016”.
(2) A received message is stored in a slot that matches the condition first according to the result of
reception mode configuration and acceptance filtering operation. Upon deciding in which slot to
store, the smaller the number of the slot is, the higher priority it has.
(3) In normal CAN operation mode, when a CAN module transmits a message of which ID matches, the
CAN module never receives the transmitted data. In loop back mode, however, the CAN module
receives back the transmitted data. In this case, the module does not return ACK.
When configuring a slot as a transmission slot, note the following points.
(1) Before configuring a slot as a transmission slot, be sure to set the CiMCTLj registers to “0016”.
(2) Set the TrmReq bit in the CiMCTLj register to “0” (not transmission slot) before rewriting a transmission
slot.
(3) A transmission slot should not be rewritten when the TrmActive bit in the CiMCTLj register is “1”
(transmitting).
If it is rewritten, an indeterminate data will be transmitted.
TrmReq
0 0 Communication environment configuration mode: configure the commu-
nication mode of the slot.
RecReq Remote RspLock Communication mode of the slot
0 1 0 0 Configured as a reception slot for a data frame.
1 0 1 0 Configured as a transmission slot for a remote frame. (At this time the
RemActive bit is "1".)
After completion of transmission, this functions as a reception slot for a
data frame. (At this time the RemActive bit is "0".)
However, when an ID that matches on the CAN bus is detected before
remote frame transmission, this immediately functions as a reception
slot for a data frame.
1 0 0 0 Configured as a transmission slot for a data frame.
0 1 1 1/0 Configured as a reception slot for a remote frame. (At this time the
RemActive bit is "1".)
After completion of reception, this functions as a transmission slot for a
data frame. (At this time the RemActive bit is "0".)
However, transmission does not start as long as RspLock bit remains "1";
thus no automatic remote frame response.
Response (transmission) starts when RspLock bit is set to "0".
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Reception
Figure 1.19.25 shows the behavior of the module when receiving two consecutive CAN messages, that fit
into the slot of the shown CiMCTLj register (i =0, 1, j = 0 to 15) and leads to losing/overwriting of the first
message.
Figure 1.19.25 Timing of Receive Data Frame Sequence
1) On monitoring a SOF on the CAN bus the RecState bit in the CiSTR register (i = 0, 1) becomes “1”
(CAN module is receiver) immediately, given the module has no transmission pending (refer to
“Transmission”).
2) After successful reception of the message the NewData bit in the CiMCTLj register (j = 0 to 15) of the
receiving slot becomes “1” (stored new data in slot). The InvalData bit in the CiMCTLj register
becomes “1” (message is being updated) at the same time and the InvalData bit becomes “0” (message
is valid) again after the complete message was transferred to the slot.
3) When the interrupt enable bit in the CiICR register of the receiving slot = 1 (interrupt enabled), the
successful reception interrupt request is occurred and the MBOX bit in the CiSTR register changes.
It shows the slot number where the message was stored and the RecSucc bit in the CiSTR register
is active.
4) After reading out the message out of the slot, the CPU should set the New Data bit to “0” (the content
of the slot is read or still under processing by the CPU).
5) If the NewData bit is not set to “0” by the CPU and the Receive request for the slot is not disabled
before the next successful reception of a CAN message that is fitting in this slot the MsgLost bit in the
CiMCTLj register becomes “1” (message has been overwritten). The new received message is transferred
to the slot. The interrupt request and change of the CiSTR register is same as in 3).
CANbus
RecReq bit
InvalData bit
CANi Successful
Reception Interrupt
RecState bit
RecSucc bit
MBOX bit
NewData bit
SOF ACK EOF EOFIF IF
SOF
Receive slot No.
MsgLost bit
CiMCTLj register
CiSTR register
(1)
(2)
(2)
(3)
(4)
(5)
(5)
(5)
i = 0, 1
j = 0 to 15
ACK
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Transmission
Figure 1.19.26 shows the timing of the transmit sequence.
CTx
TrmReq bit
TrmActive bit
CANi Successful
Transmission Interrupt
TrmState bit
TrmSucc bit
MBOX bit
SentData bit
SOF SOF
Transmission slot No.
B
CiMCTLj register
CiSTR register
EOF IF
(1) (4)
(2)
A
(2)
A
(3b)
(2)
(2)
(3b)
(3b)
(3b)
i = 0, 1
j = 0 to 15
ACK
Figure 1.19.26 Timing of Transmit Sequence
1) If one or more of the slots of a module has a request for transmission, the module attempts to start the
transmission at the next possible time (depending on the bus condition).
2) The TrmActive bit in the CiMCTLj register (i = 0, 1, j = 0 to 15) of the lowest slot with transmit request
is set to “1” (transmitting). Also the TrmState bit in the CiSTR register is set to “1” (transmitter). If the
arbitration is lost against another CAN node both bits are set to “0” (idle) again (A).
3a) When the arbitration was won, but the transmission was not successful;
The module will attempt to re-transmit.
3b) When the arbitration was won and the transmission has been successful;
The SentData bit in the CiMCTLj register is set to “1” (transmission is successfully completed) and
TrmSucc bit in the CiSTR register is set to “1” (transmitted a message successfully). If the according
interrupt enable bit in the CiICR register is “1”, the successful transmission interrupt request is occurred.
The number of the slot that was transmitted can be found in MBOX bit in the CiSTR register.
4) After a successful transmission, the module will not attempt to send the slot again until it is reactivated.
To reactivate a slot for transmission, first the TrmReq bit in the CiMCTLj register has to be set to “0”
(not transmission slot). Then the Sent Data bit in the CiMCTLj register can be set to “0” (transmission
is not started or completed yet) and the TrmReq bit is can be set to “1” (transmission slot) again (B).
Note that the SentData bit is locked and cannot be set to “0” as long as TrmReq bit =1.
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CAN Interrupts
The CAN module provides the following CAN interrupts.
• CAN0 Successful Reception Interrupt
• CAN0 Successful Transmission Interrupt
• CAN1 Successful Reception Interrupt
• CAN1 Successful Transmission Interrupt
• CAN0/1 Error Interrupt
Error Passive State
Error BusOff State
Bus Error (this feature can be disabled separately)
• CAN0/1 Wake Up Interrupt
When the CPU detects a successful reception/transmission interrupt request, the MBOX bit in the CiSTR
register (i = 0, 1) must be read to determine which slot has generated the interrupt request.
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Programmable I/O Ports
The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 87 lines P0 to
P10 (except P85). Each port can be set for input or output every line by using a direction register, and can
also be chosen to be or not be pulled high every 4 lines. P85 is an input-only port and does not have a pull-
_______ ______
up resistor. Port P85 shares the pin with NMI, so that the NMI input level can be read from the P8 register
P8_5 bit.
Figures 1.20.1 to 1.20.5 show the I/O ports. Figure 1.20.6 shows the I/O pins.
Each pin functions as an I/O port, a peripheral function input/output, or a bus control pin.
For details on how to set peripheral functions, refer to each functional description in this manual. If any pin
is used as a peripheral function input or D-A converter output pin, set the direction bit for that pin to “0” (input
mode). Any pin used as an output pin for peripheral functions other than the D-A converter is directed for
output no matter how the corresponding direction bit is set.
When using any pin as a bus control pin, refer to “Bus Control.”
(1) Port Pi Direction Register (PDi Register, i = 0 to 10)
Figure 1.20.7 shows the PDi register.
This register selects whether the I/O port is to be used for input or output. The bits in this register correspond
one for one to each port.
During memory expansion and microprocessor modes, the PDi registers for the pins functioning as bus
_______ _________ ______ __________________ _________ _________ _________
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
No direction register bit for P85 is available.
(2) Port Pi Register (Pi Register, i = 0 to 10)
Figure 1.20.8 shows the Pi register.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For
ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register,
and data can be written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register. The data written to the port latch is output
from the pin. The bits in the Pi register correspond one for one to each port.
During memory expansion and microprocessor modes, the PDi registers for the pins functioning as bus
_______ _________ ______ __________________ _________ _________ _________
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
(3) Pull-up Control Register j (PURj Register, j = 0 to 2)
Figure 1.20.9 shows the PURj register.
The PURj register bits can be used to select whether or not to pull the corresponding port high in 4 bit
units. The port selected to be pulled high has a pull-up resistor connected to it when the direction bit is set
for input mode.
However, the pull-up control register has no effect on P0 to P3, P40 to P43, and P5 during memory
expansion and microprocessor modes. Although the register contents can be modified, no pull-up resistors
are connected.
(4) Port Control Register (PCR Register)
Figure 1.20.10 shows the PCR register.
When the P1 register is read after setting the PCR register’s PCR0 bit to “1”, the corresponding port latch
can be read no matter how the PD1 register is set.
Tables 1.20.1 and 1.20.2 list an example connection of unused pins. Figure 1.20.11 shows an example
connection of unused pins.
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Figure 1.20.1 I/O Ports (1)
Note: symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Data bus
(Note)
Analog input
P0
0
to P0
7
, P2
0
to P2
7
P3
0
to P3
7
, P4
0
to P4
7
,
P5
0
to P5
4
, P5
6
(inside dotted-line
included)
(inside dotted-line
not included)
Pull-up selection
Direction register
Port latch
P1
0
to P1
4
Data bus
Direction register
Port latch
Pull-up selection
(Note)
Port P1 control register
P1
5
to P1
7
Data bus
Direction register
Port latch
Pull-up selection
(Note)
Port P1 control register
Input to respective peripheral functions
P5
7
, P6
0
, P6
4
, P7
0
7
3
, P to P7
6
,
P8
0
, P8
1
, P9
0
, P9
2
"1"
Output
Data bus
Direction
register
Port latch
Pull-up selection
(Note)
Input to respective peripheral functions
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Figure 1.20.2 I/O Ports (2)
P61, P65, P72
"1"
Output
Data bus
Direction
register
Port latch
Pull-up selection
(Note)
Input to respective peripheral functions
Switching
between
CMOS and
Nch
P82 to P84
(Note)
Data bus
Pull-up selection
Direction register
Port latch
Input to respective peripheral functions
P55, P77, P97
Data bus
Pull-up selection
Direction register
Port latch
Input to respective peripheral functions
(Note)
Note: symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
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Figure 1.20.3 I/O Ports (3)
P62, P66
Data bus
Pull-up selection
Direction register
Port latch
Input to respective peripheral functions
(Note 1)
Switching
between
CMOS and Nch
P63, P67
Output
"1"
Data bus
Pull-up selection
Direction register
Port latch
(Note 1)
Switching between CMOS and Nch
P85Data bus
(Note 1)
NMI interrupt input
P71, P91
Data bus
Direction register
Port latch
Input to respective peripheral functions
(Note 2)
Output
"1"
Note 2: symbolizes a parasitic diode.
Note 1: symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
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Note: symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Data bus
Direction register
Pull-up selection
Port latch
Analog input
Input to respective peripheral functions
P10
0
to P10
3
(inside dotted-line
not included)
P10
4
to P10
7
(inside dotted-line
included)
(Note)
P9
3
, P9
4
D-A output enabled
Analog output
Direction register
Data bus Port latch
Pull-up selection
Input to respective peripheral functions
D-A output enabled
(Note)
P9
6
"1"
Output
Direction register
Data bus Port latch
Analog input
Pull-up selection
(Note)
P9
5
Direction register
Data bus Port latch
Analog input
Pull-up selection
Input to respective peripheral functions
(Note)
"1"
Output
Figure 1.20.4 I/O Ports (4)
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Figure 1.20.5 I/O Ports (5)
Figure 1.20.6 I/O Pins
P8
7
P8
6
fc
Rf
Rd
Data bus
Direction register
Pull-up selection
Port latch
"1"
Output
Direction register
Pull-up selection
Port latch
Data bus
(Note)
(Note)
Note: symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
BYTE
BYTE signal input
CNVSS
CNVSS signal input
RESET
RESET signal input
(Note 1)
(Note 2)
(Note 1)
(Note 2)
(Note 2)
Note 2: symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Note 1: A parasitic diode on the VCC side is added to the mask ROM version.
Make sure the input voltage on each port will not exceed Vcc.
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Figure 1.20.7 PD0 to PD10 Registers
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Port Pi direction register (i = 0 to 7, 9, 10) (Notes 1, 2)
Bit nameBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0 PD0 to PD3
PD4 to PD7
PD9, PD10
03E216, 03E316, 03E616, 03E716
03EA16, 03EB16, 03EE16, 03EF16
03F316, 03F616
0016
0016
0016
Symbol Address After reset
Note 1: Make sure the PD7 and PD9 registers are written to by the next instruction after setting the PRCR
register’s PRC2 bit to "1" (write enabled).
Note 2: During memory expansion and microprocessor modes, the PD register for the pins functioning
as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY,
HOLD, HLDA and BCLK) cannot be modified.
PDi_0
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
PDi_7
Port Pi0 direction bit
Port Pi1 direction bit
Port Pi2 direction bit
Port Pi3 direction bit
Port Pi4 direction bit
Port Pi5 direction bit
Port Pi6 direction bit
Port Pi7 direction bit
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 7, 9, 10)
RW
RW
RW
RW
RW
RW
RW
RW
Function
Port P8 direction register
Bit nameBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
PD8 03F216 00X000002
Symbol Address After reset
PD8_0
PD8_1
PD8_2
PD8_3
PD8_4
-
(b5)
PD8_6
PD8_7
Port P80 direction bit
Port P81 direction bit
Port P82 direction bit
Port P83 direction bit
Port P84 direction bit
Port P86 direction bit
Port P87 direction bit
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
RW
RW
RW
RW
RW
-
RW
RW
Function
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Figure 1.20.8 P0 to P10 Registers
Port Pi register (i = 0 to 7, 9, 10) (Note 1)
Bit nameBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0 P0 to P3
P4 to P7
P9, P10
03E016, 03E116, 03E416, 03E516
03E816, 03E916, 03EC16, 03ED16
03F116, 03F416
Indeterminate
Indeterminate
Indeterminate
Symbol Address After reset
Note 1: During memory expansion and microprocessor modes, the Pi register for the pins functioning
as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY,
HOLD, HLDA and BCLK) cannot be modified.
Note 2: Since P71 and P91 are N channel open-drain ports, the data is high-impedance.
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Pi_5
Pi_6
Pi_7
Port Pi0 bit
Port Pi1 bit
Port Pi2 bit
Port Pi3 bit
Port Pi4 bit
Port Pi5 bit
Port Pi6 bit
Port Pi7 bit
The pin level on any I/O port which is set
for input mode can be read by reading
the corresponding bit in this register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register.
0 : "L" level
1 : "H" level (Note 2)
(i = 0 to 7, 9, 10)
RW
RW
RW
RW
RW
RW
RW
RW
Function
Port P8 register
Bit nameBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
P8 03F016 Indeterminate
Symbol Address After reset
P8_0
P8_1
Pi8_2
P8_3
P8_4
P8_5
P8_6
P8_7
Port P80 bit
Port P81 bit
Port P82 bit
Port P83 bit
Port P84 bit
Port P85 bit
Port P86 bit
Port P87 bit
The pin level on any I/O port which is set
for input mode can be read by reading
the corresponding bit in this register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register. (Except for P85.)
0 : "L" level
1 : "H" level
RW
RW
RW
RW
RW
RO
RW
RW
Function
Rev.1.00 2003.05.30 page 240
M16C/6N4 Group Programmable I/O Ports
Under development
This document is under development and its contents are subject to change.
Pull-up control register 0 (Note 1)
Bit nameBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
PUR0 03FC16 0016
Symbol Address After reset
Note 1: During memory expansion and microprocessor modes, the pins are not pulled high although
their corresponding register contents can be modified.
Note 2: The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
PU00
PU01
PU02
PU03
PU04
PU05
PU06
PU07
P0
0
to P0
3
pull-up
P0
4
to P0
7
pull-up
P1
0
to P1
3
pull-up
P1
4
to P1
7
pull-up
P2
0
to P2
3
pull-up
P2
4
to P2
7
pull-up
P3
0
to P3
3
pull-up
P3
4
to P3
7
pull-up
0 : Not pulled high
1 : Pulled high (Note 2)
RW
RW
RW
RW
RW
RW
RW
RW
Function
Pull-up control register 1
Bit nameBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
PUR1 03FD16 000000002
000000102
Symbol Address After reset (Note 1)
Note 1: The values after hardware reset is as follows:
000000002 when input on CNVss pin is "L".
000000102 when input on CNVss pin is "H".
The values after software reset, watchdog timer reset and oscillation stop detection reset are
as follows:
000000002 when PM 01 to PM00 bits of PM0 register are "002" (single-chip mode).
000000102 when PM 01 to PM00 bits of PM0 register are "012" (memory expansion mode) or
"112" (microprocessor mode).
Note 2: During memory expansion and microprocessor modes, the pins are not pulled high although
their corresponding register contents can be modified.
Note 3: If the PM01 to PM00 bits are set to "012" (memory expansion mode) or "112" (microprocessor mode)
in a program during single-chip mode, the PU11 bit becomes "1".
Note 4: The P71 pin does not have pull-up.
Note 5: The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
PU10
PU11
PU12
PU13
PU14
PU15
PU16
PU17
P4
0
to P4
3
pull-up (Note 2)
P4
4
to P4
7
pull-up (Note 3)
P5
0
to P5
3
pull-up (Note 2)
P5
4
to P5
7
pull-up (Note 2)
P6
0
to P6
3
pull-up
P6
4
to P6
7
pull-up
P7
0
, P7
2
and P7
3
pull-up (Note 4)
P7
4
to P7
7
pull-up
0 : Not pulled high
1 : Pulled high (Note 5)
RW
RW
RW
RW
RW
RW
RW
RW
Function
Pull-up control register 2
Bit nameBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
PUR2 03FE16 0016
Symbol Address After reset
Note 1: The P85 pin does not have pull-up.
Note 2: The P91 pin does not have pull-up.
Note 3: The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
PU20
PU21
PU22
PU23
PU24
PU25
-
(b7-b6)
P8
0
to P8
3
pull-up
P8
4
to P8
7
pull-up (Note 1)
P9
0
, P9
2
and P9
3
pull-up (Note 2)
P9
4
to P9
7
pull-up
P10
0
to P10
3
pull-up
P10
4
to P10
7
pull-up
0 : Not pulled high
1 : Pulled high (Note 3)
RW
RW
RW
RW
RW
RW
-
Function
Nothing is assigned. When write, set to "0".
When read, its content is "0".
Figure 1.20.9 PUR0 to PUR2 Registers
Rev.1.00 2003.05.30 page 241
M16C/6N4 Group Programmable I/O Ports
Under development
This document is under development and its contents are subject to change.
Figure 1.20.10 PCR Register
Port control register
Bit nameBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
PCR 03FF16 0016
Symbol Address After reset
PCR0
-
(b7-b1)
Port P1 control bit
Operation performed when the P1
register is read
0 : When the port is set for input, the
input levels of P10 to P17 pins are
read. When set for output, the port
latch is read.
1 : The port latch is read regardless of
whether the port is set for input or
output.
RW
-
Function
Nothing is assigned. When write, set to "0".
When read, its content is "0".
Rev.1.00 2003.05.30 page 242
M16C/6N4 Group Programmable I/O Ports
Under development
This document is under development and its contents are subject to change.
Table 1.20.1 Unassigned Pin Handling in Single-chip Mode
Pin name Connection
Ports P0 to P7, P80 to P84,
P86, P87, P9, P10
XOUT (Note 4)
_______
NMI(P85)
AVCC
AVSS, VREF, BYTE
After setting for input mode, connect every pin to VSS via a resistor (pull-down);
or after setting for output mode, leave these pins open. (Notes 1, 2, 3)
Open
Connect via resistor to VCC (pull-up)
Connect to VCC
Connect to VSS
Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input mode
until it is switched to output mode in a program after reset. For this reason, the voltage level on the pin
becomes indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be
changed by noise or noise-induced runaway, it is recommended that the contents of the direction
registers be periodically reset in software, for the increased reliability of the program.
Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer
pins (within 2 cm).
Note 3: When the ports P71 and P91 are set for output mode, make sure a low-level signal is output from the pins.
The ports P71 and P91 are N-channel open-drain outputs.
Note 4: With external clock input to XIN pin.
Table 1.20.2 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode
Pin name Connection
Ports P0 to P7, P80 to P84,
P86, P87, P9, P10
______ ______
P45/CS1 to P47/CS3
________ __________
BHE, ALE, HLDA,
XOUT (Note 5), BCLK (Note 6)
___________ ________ _______
HOLD, RDY, NMI(P85)
AVCC
AVSS, VREF
After setting for input mode, connect every pin to VSS via a resistor (pull-down);
or after setting for output mode, leave these pins open. (Notes 1, 2, 3, 4)
Connect to VCC via a resistor (pulled high) by setting the PD4 register’s
_____
corresponding direction bit for CSi (i = 1 to 3) to “0” (input mode) and
_____
the CSR register’s CSi bit to “0” (chip select disabled).
Open
Connect via resistor to VCC (pull-up)
Connect to VCC
Connect to VSS
Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input mode
until it is switched to output mode in a program after reset. For this reason, the voltage level on the pin
becomes indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be
changed by noise or noise-induced runaway, it is recommended that the contents of the direction
registers be periodically reset in software, for the increased reliability of the program.
Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer
pins (within 2 cm).
Note 3: If the CNVSS pin has the VSS level applied to it, these pins are set for input ports until the processor
mode is switched over in a program after reset. For this reason, the voltage levels on these pins
become indeterminate, causing the power supply current to increase while they remain set for input ports.
Note 4: When the ports P71 and P91 are set for output mode, make sure a low-level signal is output from the pins.
The ports P71 and P91 are N-channel open-drain outputs.
Note 5: With external clock input to XIN pin.
Note 6: If the PM0 register’s PM07 bit is set to “1” (BCLK not output), connect this pin to VCC via a resistor.
(pulled high).
Rev.1.00 2003.05.30 page 243
M16C/6N4 Group Programmable I/O Ports
Under development
This document is under development and its contents are subject to change.
Figure 1.20.11 Unassigned Pins Handling
Open
Open
Port P4
5
/CS
1
to P4
7
/CS
3
(Input mode)
(Input mode)
(Output mode)
Microcomputer Microcomputer
Port
P0 to P10
(except for P8
5
)
AV
CC
BYTE
AV
SS
V
REF
X
OUT
NMI
(Input mode)
(Input mode)
(Output mode)
Port P6 to P10
(except for P8
5
)
AV
CC
BYTE
AV
SS
V
REF
X
OUT
NMI
BHE
V
CC
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
Open
Open
In single-chip mode In memory expansion mode or
in microprocessor mode
HLDA
BCLK (Note)
HOLD
ALE
RDY
Note: If the PM0 register’s PM07 bit is set to "1" (BCLK not output), connect this pin to V
CC
via a resistor (pulled high).
Rev.1.00 2003.05.30 page 244
M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
V
V
V
V
V
V
V
V
V
mW
°C
°C
Unit
Supply voltage
Supply voltage
Analog supply voltage
Input
voltage
Output
voltage
Power dissipation
Operating ambient temperature
Storage temperature
Symbol Parameter
____________
RESET, CNVSS, BYTE,
P60~P67, P70, P72~P77, P80~P87,
P90, P92~P97, P100~P107,
VREF, XIN
P00~P07, P10~P17, P20~P27,
P30~P37, P40~P47, P50~P57
P71, P91
P60~P67, P70, P72~P77, P80~P84,
P86, P87, P90, P92~P97, P100~P107,
XOUT
P00~P07, P10~P17, P20~P27,
P30~P37, P40~P47, P50~P57
P71, P91
Rated value
VCC1
VCC2
AVCC
VI
VO
Pd
Topr
Tstg
–0.3 to 6.5
–0.3<VCC2=VCC1
–0.3 to 6.5
–0.3 to VCC1+0.3
–0.3 to VCC2+0.3
–0.3 to 6.5
–0.3 to VCC1+0.3
–0.3 to VCC2+0.3
–0.3 to 6.5
700
–40 to 85/–40 to 125 (option)
–65 to 150
Condition
VCC1=AVCC
VCC2
VCC1=AVCC
Topr=25°C
Electrical Characteristics
Table 1.21.1 Absolute Maximum Ratings
option: If you desire this option, please so specify.
Rev.1.00 2003.05.30 page 245
M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
5.0
VCC
0
0
32.768
1
Note 1: Referenced to VCC = 4.2 to 5.5 V at Topr = –40 to 85 °C unless otherwise specified.
Note 2: The mean output current is the mean value within 100 ms.
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
MHz
kHz
MHz
MHz
MHz
ms
Supply voltage (VCC1=VCC2)
Analog supply voltage
Supply voltage
Analog supply voltage
HIGH input
voltage
LOW input
voltage
HIGH peak output
current
HIGH average
output current
LOW peak output
current
LOW average
output current
Main clock input No wait Mask ROM version VCC=4.2 to 5.5V
oscillation frequency Flash memory version
(Notes 4, 5 and 6)
Sub clock oscillation frequency
Ring oscillation frequency
PLL clock oscillation frequency
CPU operation clock VCC=4.2 to 5.5V
PLL frequency synthesizer stabilization wait time
4.2
0.8VCC
0.8VCC
0.8VCC
0.5VCC
0
0
0
0
0
5.5
VCC
6.5
VCC
VCC
0.2VCC
0.2VCC
0.16VCC
–10.0
–5.0
10.0
5.0
16
50
20
20
20
VCC1, VCC2
AVCC
VSS
AVSS
VIH
VIL
IOH (peak)
IOH (avg)
IOL (peak)
IOL (avg)
f(XIN)
f(XCIN)
f(Ring)
f(PLL)
f(BCLK)
tsu(PLL)
P31~P37, P40~P47, P50~P57, P60~P67,
P70, P72~P77, P80~P87, P90, P92~P97, P100~P107,
____________
XIN, RESET, CNVSS, BYTE
P71, P91
P00~P07, P10~P17, P20~P27, P30
(During single-chip mode)
P00~P07, P10~P17, P20~P27, P30
(Data input during memory expansion and microprocessor modes)
P31~P37, P40~P47, P50~P57, P60~P67,
P70~P77, P80~P87, P90~P97, P100~P107,
____________
XIN, RESET, CNVSS, BYTE
P00~P07, P10~P17, P20~P27, P30
(During single-chip mode)
P00~P07, P10~P17, P20~P27, P30
(Data input during memory expansion and microprocessor modes)
P00~P07, P10~P17, P20~P27, P30~P37,
P40~P47, P50~P57, P60~P67, P70, P72~P77,
P80~P84, P86, P87, P90, P92~P97, P100~P107
P00~P07, P10~P17, P20~P27, P30~P37,
P40~P47, P50~P57, P60~P67, P70, P72~P77,
P80~P84, P86, P87, P90, P92~P97, P100~P107
P00~P07, P10~P17, P20~P27, P30~P37,
P40~P47, P50~P57, P60~P67, P70~P77,
P80~P84, P86, P87, P90~P97, P100~P107
P00~P07, P10~P17, P20~P27, P30~P37,
P40~P47, P50~P57, P60~P67, P70~P77,
P80~P84, P86, P87, P90~P97, P100~P107
ParameterSymbol Typ.Min.
Standard Unit
Max.
Table 1.21.2 Recommended Operating Conditions (Note 1)
0.0
16.0
5.54.2
V
CC
[V] (main clock: no division)
Main clock input oscillation frequency
(Mask ROM, flash memory version: no wait)
f(X
IN
) operating maximum frequency [MHz]
Note 3: The total IOL (peak) for ports P0, P1, P2, P86, P87,
P9 and P10 must be 80mA max. The total IOL
(peak) for ports P3, P4, P5, P6, P7 and P80 to P84
must be 80mA max. The total IOH (peak) for ports
P0, P1, and P2 must be –40mA max. The total IOH
(peak) for ports P3, P4 and P5 must be –40mA
max. The total IOH (peak) for ports P6, P7 and P80
to P84 must be –40mA max. The total IOH (peak)
for ports P86, P87, P9 and P10 must be –40mA max.
Note 4: Relationship between main clock oscillation
frequency and supply voltage is shown right.
Note 5: Execute program /erase of flash memory by
VCC = 5.0 ± 0.5 V.
Note 6: When using 16 MHz or more, use PLL clock.
Rev.1.00 2003.05.30 page 246
M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
Table 1.21.3 Electrical Characteristics (Note 1)
Note 1: Referenced to VCC = 4.2 to 5.5 V, Vss = 0 V at Topr = –40 to 85 °C, f(BCLK) = 20 MHz unless otherwise specified.
Note 2: This indicates the memory in which the program to be executed exists.
Note 3: With one timer operated using fC32.
2.5
1.6
0
0
50
1.5
15
18
1
20
1.8
15
25
25
25
420
50
8.5
3.0
0.8
HIGH output
voltage
HIGH output
voltage
HIGH output
voltage
HIGH output
voltage
LOW output
voltage
LOW output
voltage
LOW output
voltage
LOW output
voltage
Hysteresis
Hysteresis
HIGH input
current
LOW input
current
Pull-up
resistance
Feedback resistance
Feedback resistance
RAM retention voltage
Power supply current
(VCC = 4.2 to 5.5V)
VOH
VOH
VOH
VOL
VOL
VOL
VT+–VT-
VT+–VT-
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
ICC
IOH=–5mA
IOH=–200µA
IOH=–1mA
IOH=–0.5mA
With no load applied
With no load applied
IOL=5mA
IOL=200µA
IOL=1mA
IOL=0.5mA
With no load applied
With no load applied
VI=5V
VI=0V
VI=0V
At stop mode
Mask ROM f(BCLK)=20MHz,
No division, PLL operation
No division, Ring oscillation
Flash memory
f(BCLK)=20MHz,
No division, PLL operation
No division, Ring oscillation
Flash memory
f(BCLK)=10MHz,
Program VCC=5V
Flash memory
f(BCLK)=10MHz,
Erase VCC=5V
Mask ROM
f(XCIN)=32kHz, Low power
dissipation mode, ROM (Note 2)
Flash memory
f(BCLK)=32kHz, Low power
dissipation mode, RAM (Note 2)
f(BCLK)=32kHz, Low power dissipation
mode, Flash memory (Note 2)
Mask ROM
Ring oscillation, Wait mode
Flash memory
f(BCLK)=32kHz, Wait mode (Note
3), Oscillation capacity High
f(BCLK)=32kHz, Wait mode (Note
3), Oscillation capacity Low
Stop mode,
T
opr
= 25 °C
V
V
V
V
V
V
V
V
V
V
µA
µA
kΩ
MΩ
MΩ
V
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
Measuring condition Standard
Min. Unit
VCC
VCC
VCC
VCC
2.0
0.45
2.0
2.0
1.0
2.2
5.0
–5.0
170
32
34
3.0
ParameterSymbol
P00~P07, P10~P17, P20~P27, P30~P37,
P4
0
~P4
7
, P5
0
~P5
7
, P6
0
~P6
7
, P7
0
, P7
2
~P7
7
,
P8
0
~P8
4
, P8
6
, P8
7
, P9
0
, P9
2
~P9
7
, P10
0
~P10
7
P00~P07, P10~P17, P20~P27, P30~P37,
P4
0
~P4
7
, P5
0
~P5
7
, P6
0
~P6
7
, P7
0
, P7
2
~P7
7
,
P8
0
~P8
4
, P8
6
, P8
7
, P9
0
, P9
2
~P9
7
, P10
0
~P10
7
XOUT HIGHPOWER
LOWPOWER
XCOUT HIGHPOWER
LOWPOWER
P00~P07, P10~P17, P20~P27, P30~P37,
P40~P47, P50~P57, P60~P67, P70~P77,
P80~P84, P86, P87, P90~P97, P100~P107
P00~P07, P10~P17, P20~P27, P30~P37,
P40~P47, P50~P57, P60~P67, P70~P77,
P80~P84, P86, P87, P90~P97, P100~P107
XOUT HIGHPOWER
LOWPOWER
XCOUT HIGHPOWER
LOWPOWER
__________ ________
HOLD, RDY, TA0IN~TA4IN,
_______ _______ ______ __________
TB0IN~TB5IN, INT0~INT5, NMI, ADTRG,
________ ________
CTS0~CTS2, SCL, SDA, CLK0~CLK4,
_____ _____
TA2OUT~TA4OUT, KI0~KI3, RxD0~RxD2, SIN3
____________
RESET
P00~P07, P10~P17, P20~P27, P30~P33,
P40~P47, P50~P57, P60~P67, P70~P77,
P80~P87, P90~P97, P100~P107,
____________
XIN, RESET, CNVSS, BYTE
P00~P07, P10~P17, P20~P27, P30~P33,
P40~P47, P50~P57, P60~P67, P70~P77,
P80~P87, P90~P97, P100~P107,
____________
XIN, RESET, CNVSS, BYTE
P00~P07, P10~P17, P20~P27, P30~P37,
P4
0
~P4
7
, P5
0
~P5
7
, P6
0
~P6
7
, P7
0
, P7
2
~P7
7
,
P8
0
~P8
4
, P8
6
, P8
7
, P9
0
, P9
2
~P9
7
, P10
0
~P10
7
XIN
XCIN
In single-chip mode,
the output pins are
open and other pins
are VSS.
Typ. Max.
VCC-2.0
VCC-0.3
3.0
3.0
0.2
0.2
30
2.0
Rev.1.00 2003.05.30 page 247
M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
–
INL
–
DNL
–
–
RLADDER
tCONV
tSAMP
VREF
VIA
Resolution
Integral 10 bits
non-linearity
error
8 bits
Absolute 10 bits
accuracy
8 bits
Differential non-linearity error
Offset error
Gain error
Ladder resistance
Conversion time (10 bits), Sample & hold function available
Conversion time (8 bits), Sample & hold function available
Sampling time
Reference voltage
Analog input voltage
10
±3
±7
±2
±3
±7
±2
±1
±3
±3
40
VCC
VREF
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
kΩ
µs
µs
µs
V
V
10
3.3
2.8
0.3
2.0
0
VREF=VCC
VREF=VCC
=5V
VREF=AVCC=VCC=5V
VREF=VCC
=5V
VREF=AVCC=VCC=5V
VREF=VCC
VREF=VCC=5V, φAD=10MHz
VREF=VCC=5V, φAD=10MHz
Note 1: Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, –40 to 85 °C unless otherwise specified.
Note 2: This applies when using one D-A converter, with the DAi register (i = 0, 1) for the unused D-A converter set to
“0016”. The A-D converter’s ladder resistance is not included. Also, the current IVREF always flows even though
VREF may have been set to be unconnected by the ADCON1 register.
Table 1.21.6 Power Supply Circuit Timing Characteristics
Note 1: Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, –40 to 85 °C unless otherwise specified.
Note 2: AD operation clock frequency (φAD frequency) must be 10 MHz or less.
Note 3: A case without sample & hold function turn φAD frequency into 250 kHz or more in addition to a limit of Note 2.
A case with sample & hold function turn φAD frequency into 1 MHz or more in addition to a limit of Note 2.
Table 1.21.5 D-A conversion Characteristics (Note 1)
ANEX0, ANEX1 input,
AN0 to AN7 input,
AN00 to AN07 input,
AN20 to AN27 input
External operation amp
connection mode
Symbol Parameter Min.
Standard Unit
Measuring condition Max.
Typ.
(Note 2)
8
1.0
3
20
1.5
Bits
%
µs
kΩ
mA
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
–
–
tsu
RO
IVREF
Symbol Parameter Min.
Standard Unit
Measuring condition
4
Max.
Typ.
10
Table 1.21.4 A-D Conversion Characteristics (Note 1)
2
150
150
50
ms
µs
µs
µs
Time for internal power supply stabilization during
powering-on
STOP release time
Low power dissipation mode wait mode release time
Time for internal power supply stabilization when main
clock oscillation status
td(P-R)
td(R-S)
td(W-S)
td(M-L)
Symbol Parameter Min.
Standard Unit
Measuring
condition Max.Typ.
td(R-S)
Interrupt for stop
mode releaser
CPU clock
VCC = 4.2 to 5.5 V
ANEX0, ANEX1 input,
AN0 to AN7 input,
AN00 to AN07 input,
AN20 to AN27 input
External operation amp
connection mode
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M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
15
15
ns
ns
ns
ns
ns
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
Symbol Parameter Min.
Standard Unit
Max.
62.5
25
25
Table 1.21.8 Memory Expansion Mode and Microprocessor Mode
tC
tw(H)
tw(L)
tr
tf
Timing Requirements
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 1.21.7 External Clock Input (XIN Input)
(Note 1)
(Note 2)
(Note 3)
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input access time (for setting with no wait)
Data input access time (for setting with wait)
Data input access time (when accessing multiplexed bus area)
Data input setup time
________
RDY input setup time
__________
HOLD input setup time
Data input hold time
________
RDY input hold time
__________
HOLD input hold time
__________
HLDA output delay time
Symbol Parameter Min.
Standard Unit
Max.
40
30
40
0
0
0
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
td(BCLK-HLDA)
Note 1: Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 45 [ns]
Note 2: Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
f(BCLK) – 45 [ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
Note 3: Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
f(BCLK) – 45 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.
Rev.1.00 2003.05.30 page 249
M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
ns
ns
ns
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
100
40
40
Table 1.21.10 Timer A Input (Gating Input in Timer Mode)
tc(TA)
tw(TAH)
tw(TAL)
Timing Requirements
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 1.21.9 Timer A Input (Counter Input in Event Counter Mode)
Table 1.21.11 Timer A Input (External Trigger Input in One-shot Timer Mode)
Table 1.21.12 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Table 1.21.13 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
ns
ns
ns
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
400
200
200
tc(TA)
tw(TAH)
tw(TAL)
ns
ns
ns
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
200
100
100
tc(TA)
tw(TAH)
tw(TAL)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
100
100
tw(TAH)
tw(TAL)
ns
ns
ns
ns
ns
TAiOUT input cycle time
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
Symbol Parameter Min.
Standard Unit
Max.
2000
1000
1000
400
400
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
Table 1.21.14 Timer A Input (Two-phase Pulse Input in Event Counter Mode)
ns
ns
ns
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
Symbol Parameter Min.
Standard Unit
Max.
800
200
200
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
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Under development
This document is under development and its contents are subject to change.
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
Symbol Parameter Min.
Standard Unit
Max.
100
40
40
200
80
80
Table 1.21.16 Timer B Input (Pulse Period Measurement Mode)
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Timing Requirements
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 1.21.15 Timer B Input (Counter Input in Event Counter Mode)
Table 1.21.17 Timer B Input (Pulse Width Measurement Mode)
Table 1.21.18 A-D Trigger Input
Table 1.21.19 Serial I/O
ns
ns
ns
TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
400
200
200
tc(TB)
tw(TBH)
tw(TBL)
ns
ns
ns
TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
400
200
200
tc(TB)
tw(TBH)
tw(TBL)
ns
ns
__________
ADTRG input cycle time (trigger able minimum)
__________
ADTRG input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
1000
125
tC(AD)
tw(ADL)
80
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
RxDi input setup time
RxDi input hold time
Symbol Parameter Min.
Standard Unit
Max.
200
100
100
0
30
90
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
_______
Table 1.21.20 External Interrupt INTi Input
ns
ns
_______
INTi input HIGH pulse width
_______
INTi input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
250
250
tw(INH)
tw(INL)
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M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output delay time
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
Address output hold time (refers to WR)
Chip select output delay time
Chip select output hold time (refers to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK) (Note 3)
Data output delay time (refers to WR)
Data output hold time (refers to WR) (Note 3)
Symbol Parameter Min.
Standard Unit
Max.
4
0
(Note 1)
4
–4
0
0
4
(Note 2)
(Note 1)
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 1.21.21 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
25
25
25
25
25
40
Note 1: Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 10 [ns]
Note 2: Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 40 [ns]
Note 3: This standard value shows the timing when the output is off, and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
Figure 1.21.1. Port P0 to P10 Measurement Circuit
DBi
R
C
30pF
P6
P7
P8
P10
P9
P0
P1
P2
P3
P4
P5
Measuring
condition
Figure 1.21.1
f(BCLK) is 12.5 MHz or less.
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M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output delay time
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
Address output hold time (refers to WR)
Chip select output delay time
Chip select output hold time (refers to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK) (Note 3)
Data output delay time (refers to WR)
Data output hold time (refers to WR) (Note 3)
Symbol Parameter Min.
Standard Unit
Max.
4
0
(Note 1)
4
–4
0
0
4
(Note 2)
(Note 1)
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 1.21.22
Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
25
25
25
25
25
40
Note 1: Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 10 [ns]
Note 2: Calculated according to the BCLK frequency as follows:
(n – 0.5) ✕ 109n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
f(BCLK) – 40 [ns] When n = 1, f(BCLK) is 12.5 MHz or less.
Note 3: This standard value shows the timing when the output is off, and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR ✕ ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
DBi
R
C
Measuring
condition
Figure 1.21.1
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M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
4
(Note 1)
(Note 1)
4
(Note 1)
(Note 1)
0
0
4
(Note 2)
(Note 1)
–4
(Note 3)
(Note 4)
0
0
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
td(AD-WR)
tdZ(RD-AD)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output delay time
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
Address output hold time (refers to WR)
Chip select output delay time
Chip select output hold time (refers to BCLK)
Chip select output hold time (refers to RD)
Chip select output hold time (refers to WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK)
Data output delay time (refers to WR)
Data output hold time (refers to WR)
ALE signal output delay time (refers to BCLK)
ALE signal output hold time (refers to BCLK)
ALE signal output delay time (refers to Address)
ALE signal output hold time (refers to Address)
RD signal output delay from the end of Address
WR signal output delay from the end of Address
Address output floating start time
Symbol Parameter Min.
Standard Unit
Max.
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 1.21.23 Memory Expansion Mode and Microprocessor Mode
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
25
25
25
25
40
25
8
Measuring
condition
Figure 1.21.1
Note 1: Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 10 [ns]
Note 2: Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
f(BCLK) – 40 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.
Note 3: Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 25 [ns]
Note 4: Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 15 [ns]
Rev.1.00 2003.05.30 page 254
M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
Figure 1.21.2 Timing Diagram (1)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
TAiOUT input
(Up/down input)
tsu(D—C)
CLKi
TxDi
RxDi
tc(CK)
tw(CKH)
tw(CKL)
tw(INL)
tw(INH)
td(C—Q) th(C—D)
th(C—Q)
INTi input
iIN input
tc(TB)
tw(TBH)
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
TB
Two-phase pulse input in event counter mode
tsu(TAOUT—TAIN)
tsu(TAOUT—TAIN)
tsu(TAIN—TAOUT)
tC(TA)
tsu(TAIN—TAOUT)
TAiIN input
TAiOUT input
tc(TA)
tw(TAH)
tw(TAL)
tc(UP)
tw(UPH)
tw(UPL)
TAiIN input
TAiOUT input
th(TIN—UP) tsu(UP—TIN)
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M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
Figure 1.21.3 Timing Diagram (2)
Measuring conditions :
V
CC
= 5 V
Input timing voltage : Determined with V
IL
= 1.0 V, V
IH
= 4.0 V
Output timing voltage: Determined with V
OL
= 2.5 V, V
OH
= 2.5 V
Memory Expansion Mode and Microprocessor Mode
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P50 to P52
(Common to setting with wait and setting without wait)
Note:
The above pins are set to high-impedance regardless of the input level of the BYTE pin,
PM06 bit of PM0 register and PM11 bit of PM1 register.
(Effective for setting with wait)
Hi—Z
RDY input
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
td(BCLK—HLDA)td(BCLK—HLDA)
th(BCLK—HOLD)tsu(HOLD—BCLK)
tsu(RDY—BCLK) th(BCLK—RDY)
Rev.1.00 2003.05.30 page 256
M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
Figure 1.21.4 Timing Diagram (3)
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
25ns.max
ALE
25ns.max -4ns.min
RD
25ns.max
t
h(BCLK-RD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
Hi-Z
DB
t
h(RD-DB)
0ns.min
0ns.min
t
h(RD-AD)
BHE
tcyc
Read timing
t
d(BCLK-AD)
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
SU(DB-RD)
t
d(BCLK-RD)
40ns.min
t
ac1(RD-DB)
Memory Expansion Mode and Microprocessor Mode
(For setting with no wait)
WR,WRL,
WRH
25ns.max
t
h(BCLK-WR)
0ns.min
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
t
d(BCLK-AD)
25ns.max
ALE
25ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-4ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
t
h(WR-AD)
BHE
t
d(BCLK-DB)
40ns.max 4ns.min
t
h(BCLK-DB)
t
d(DB-WR)
(0.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
DBi
Write timing
t
d(BCLK-WR)
Hi-Z
(0.5 ✕ tcyc-45)ns.max
(0.5 ✕ tcyc-10)ns.min
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
(0.5 ✕ tcyc-10)ns.min
Rev.1.00 2003.05.30 page 257
M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
Figure 1.21.5 Timing Diagram (4)
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
t
d(BCLK-AD)
25ns.max
ALE
25ns.max
t
h(BCLK-ALE)
-4ns.min
RD
25ns.max
t
h(BCLK-RD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
Hi-Z
DB
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
tcyc
BHE
Read timing
WR,WRL,
WRH
25ns.max
t
h(BCLK-WR)
0ns.min
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
t
d(BCLK-AD)
25ns.max
ALE
25ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-4ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
t
h(WR-AD)
BHE
t
d(BCLK-DB)
40ns.max 4ns.min
t
h(BCLK-DB)
t
d(DB-WR)
(0.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min
t
h(WR-DB)
DBi
Write timing
t
d(BCLK-ALE)
t
d(BCLK-RD)
t
d(BCLK-WR)
0ns.min
t
h(RD-AD)
t
ac2(RD-DB)
Hi-Z
Memory Expansion Mode and Microprocessor Mode
(For 1-wait setting and external area access)
(1.5 ✕ tcyc-45)ns.max
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
(0.5 ✕ tcyc-10)ns.min
Rev.1.00 2003.05.30 page 258
M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
Figure 1.21.6 Timing Diagram (5)
Read timing
Write timing
BCLK
CSi
ALE
DB
ADi
BHE
WR, WRL
WRH
Memory Expansion Mode and Microprocessor Mode
(
For 2-wait setting and external area access
)
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
25ns.max
Hi-Z
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-RD)
0ns.min
t
h(RD-AD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
Hi-Z
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-WR)
25ns.max
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min
t
d(BCLK-DB)
40ns.max
t
d(DB-WR)
(1.5 ✕ tcyc-40)ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t
ac2(RD-DB)
(2.5 ✕ tcyc-45)ns.max
tcyc = 1
f(BCLK)
Measuring conditions :
V
CC
= 5 V
Input timing voltage : V
IL
= 0.8 V, V
IH
= 2.0 V
Output timing voltage : V
OL
= 0.4 V, V
OH
= 2.4 V
Rev.1.00 2003.05.30 page 259
M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
Figure 1.21.7 Timing Diagram (6)
Read timing
Write timing
BCLK
CSi
ALE
DB
ADi
BHE
WR, WRL
WRH
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting and external area access)
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
25ns.max
Hi-Z
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-RD)
0ns.min
t
h(RD-AD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
Hi-Z
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-WR)
25ns.max
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min
t
d(BCLK-DB)
40ns.max
t
d(DB-WR)
(2.5 ✕ tcyc-40)ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t
ac2(RD-DB)
(3.5 ✕ tcyc-45)ns.max
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Rev.1.00 2003.05.30 page 260
M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
Figure 1.21.8 Timing Diagram (7)
Memory Expansion Mode and Microprocessor Mode
(
For 1- or 2-wait setting, external area access and multiplexed bus selection)
BCLK
CSi
td(BCLK-CS)
25ns.max
ADi
td(BCLK-AD)
25ns.max
ALE
th(BCLK-ALE)
-4ns.min
RD
25ns.max
th(BCLK-RD)
0ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc th(RD-CS)
th(RD-AD)
BHE
ADi
/DBi th(RD-DB)
0ns.min
td(AD-ALE)
Read timing
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
BCLK
CSi
td(BCLK-CS)
25ns.max
ADi
td(BCLK-AD)
25ns.max
ALE
25ns.max
th(BCLK-ALE)
-4ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
th(WR-AD)
BHE
td(BCLK-DB)
40ns.max 4ns.min
th(BCLK-DB)
td(DB-WR) th(WR-DB)
ADi
/DBi
Data output
WR,WRL,
WRH
Write timing
Address
Address
Data input
40ns.min
(0.5 ✕ tcyc-10)ns.min
td(BCLK-ALE)
td(BCLK-RD)
th(WR-CS)
Address
td(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
(1.5 ✕ tcyc-40)ns.min
(0.5 ✕ tcyc-10)ns.min
td(BCLK-ALE)
(0.5 ✕ tcyc-25)ns.min
Address
25ns.max
tSU(DB-RD)
tac3(RD-DB)
(0.5 ✕ tcyc-10)ns.min
td(AD-RD)
0ns.min
tdZ(RD-AD)
8ns.max
td(AD-WR)
0ns.min
th(ALE-AD)
tcyc = 1
f(BCLK)
Measuring conditions :
V
CC
= 5 V
Input timing voltage : V
IL
= 0.8 V, V
IH
= 2.0 V
Output timing voltage : V
OL
= 0.4 V, V
OH
= 2.4 V
(1.5 ✕ tcyc-45)ns.max
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-15)ns.min
Rev.1.00 2003.05.30 page 261
M16C/6N4 Group Electrical Characteristics
Under development
This document is under development and its contents are subject to change.
Figure 1.21.9 Timing Diagram (8)
Read timing
Write timing
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
BCLK
CSi
ALE
RD
ADi
/DB
ADi
BHE
BCLK
CSi
ALE
ADi
/DB
tcyc
t
d(BCLK-AD)
25ns.max
tcyc
Data output
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
25ns.max
t
h(BCLK-RD)
0ns.min
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
t
h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-AD)
4ns.min
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
h(BCLK-DB)
4ns.min
t
h(BCLK-WR)
0ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
t
d(BCLK-ALE)
25ns.max
t
d(BCLK-WR)
25ns.max
t
-4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
Data input
Address
Address
ADi
BHE
WR, WRL
WRH
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
t
d(AD-RD)
0ns.min
t
dZ(RD-AD)
8ns.max
t
ac3(RD-DB)
t
d(BCLK-DB)
40ns.max
(0.5 ✕ tcyc-10)ns.min
t
h(WR-CS)
t
d(AD-WR)
0ns.min
t
h(RD-CS)
(0.5 ✕ tcyc-10)ns.min
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
(2.5 ✕ tcyc-45)ns.max
(no multiplex)
(no multiplex)
tcyc = 1
f(BCLK)
Measuring conditions :
V
CC
= 5 V
Input timing voltage : V
IL
= 0.8 V, V
IH
= 2.0 V
Output timing voltage : V
OL
= 0.4 V, V
OH
= 2.4 V
td(DB-WR)
(2.5 ✕ tcyc-40)ns.min
h(BCLK-ALE)
(0.5 ✕ tcyc-15)ns.min
th(ALE-AD)
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M16C/6N4 Group Flash Memory
Under development
This document is under development and its contents are subject to change.
Flash Memory
Flash Memory Performance
The flash memory version is functionally the same as the mask ROM version except that it internally
contains flash memory.
The flash memory version has four modes — CPU rewrite mode, standard serial I/O mode, parallel I/O
mode and CAN I/O mode — in which its internal flash memory can be operated on.
Table 1.22.1 shows the outline performance of flash memory version (refer to “Table 1.1.1 Performance
outline of M16C/6N4 Group” for the items not listed in Table 1.22.1). Table 1.22.2 shows the outline of
flash memory rewrite mode.
Table 1.22.1 Flash Memory Version Specifications
Item Specifications
Flash memory operating mode 4 modes (CPU rewrite, standard serial I/O, parallel I/O, CAN I/O)
Erase block User ROM area Refer to “Figure 1.22.1 Flash Memory Block Diagram”
division Boot ROM area 1 block (4 Kbytes) (Note 1)
Method for program In units of word, in units of byte (Note 2)
Method for erasure Collective erase, block erase
Program, erase control method Program and erase controlled by software command
Protect method Protected for each block by lock bit
Number of commands 8 commands
Number of program and erasure (Note 3)
100 times
ROM code protect ion Parallel I/O , standard serial I/O and CAN I/O modes are supported.
Note 1: The boot ROM area contains a standard serial I/O mode and CAN I/O mode rewrite control program which is stored in
it when shipped from the factory. This area can only be rewritten in parallel I/O mode.
Note 2: Can be programmed in byte units in only parallel I/O mode.
Note 3: Definition of programming and erasure times
The programming and erasure times are defined to be per-block erasure times. For example, assume a case where a
4K-byte block A is programmed in 2,048 operations by writing one word at a time and erased thereafter. In this case, the
block is reckoned as having been programmed and erased once.
If a product is guaranteed of 100 times of programming and erasure, each block in it can be erased up to 100 times.
Table 1.22.2 Flash Memory Rewrite Modes Overview
Flash memory CPU rewrite mode Standard serial I/O Parallel I/O mode CAN I/O mode
rewrite mode (Note 1) mode
Function
Areas which User ROM area User ROM area User ROM area User ROM area
can be rewritten
Boot ROM area
Operation Single chip mode Boot mode Parallel I/O mode Boot mode
mode Memory expansion mode
(EW0 mode)
Boot mode (EW0 mode)
ROM None Serial programmer Parallel programmer CAN programmer
programmer
The user ROM area is
rewritten by executing
software commands
from the CPU.
EW0 mode:
Can be rewritten in any
area other than the flash
memory (Note 2)
EW1 mode:
Can be rewritten in the
flash memory
The user ROM area is
rewritten by using a
dedicated serial pro-
grammer.
Standard serial I/O mode 1:
Clock synchronous
serial I/O
Standard serial I/O mode 2:
UART (Note 3)
The boot ROM and user
ROM areas are rewrit-
ten by using a dedicated
parallel programmer.
The user ROM area is
rewritten by using a
dedicated CAN pro-
grammer.
Note 1: The PM13 bit remains set to “1” while the FMR01 bit in the FMR0 register = 1 (CPU rewrite mode enabled). The PM13
bit is reverted to its original value by setting the FMR01 bit to “0” (CPU rewrite mode disabled). However, if the PM13 bit
is changed during CPU rewrite mode, its changed value is not reflected until after the FMR01 bit is set to “0”.
Note 2: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite control program can
only be executed in the internal RAM or in an external area that is enabled for use when the PM13 bit = 1.
Note 3: When using the standard serial I/O mode 2, make sure a main clock input oscillation frequency is set to 5 MHz, 10 MHz
or 16 MHz .
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M16C/6N4 Group Flash Memory
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Memory Map
The ROM in the flash memory version is separated between a user ROM area and a boot ROM area.
Figure 1.22.1 shows the block diagram of flash memory. The user ROM area has a 4-Kbyte block A, in
addition to the area that stores a program for microcomputer operation during singe-chip or memory
expansion mode.
The user ROM area is divided into several blocks, each of which can individually be protected (locked)
against programming or erasure. The user ROM area can be rewritten in all of CPU rewrite, standard
serial I/O mode, parallel I/O mode and CAN I/O mode. Block A is enabled for use by setting the PM1
______
register’s PM10 bit to “1” (block A enabled, CS2 area at addresses 1000016 to 26FFF16).
The boot ROM area is located at addresses that overlap the user ROM area, and can only be rewritten in
parallel I/O mode. After a hardware reset that is performed by applying a high-level signal to the CNVSS
and P50 pins and a low-level signal to the P55 pin, the program in the boot ROM area is executed. After a
hardware reset that is performed by applying a low-level signal to the CNVSS pin, the program in the user
ROM area is executed (but the boot ROM area cannot be read).
Figure 1.22.1 Flash Memory Block Diagram
Data ROM area
Reserved area
Boot ROM area (Note 2)
4 Kbytes
* Shown here is a block diagram during single-chip mode.
Note 1: Block A can be made usable by setting the PM1 register’s PM10 bit to "1" (block A enabled, CS2 area
allocated at addresses 1000016 to 26FFF16).
Block A cannot be erased by the Erase All Unlocked Block command. Use the Block Erase command to
erase it.
Note 2: The boot ROM area can only be rewritten in parallel input/output mode.
Note 3: To specify a block, use an even address in that block.
0FF000
16
0FFFFF
16
Block 5: 32 Kbytes
Block 4: 8 Kbytes
Block 3: 8 Kbytes
Block 2: 8 Kbytes
Block 1: 4 Kbytes
Block 0: 4 Kbytes
0F0000
16
0F7FFF
16
0F8000
16
0F9FFF
16
0FA000
16
0FBFFF
16
0FC000
16
0FDFFF
16
0FE000
16
0FEFFF
16
0FF000
16
0FFFFF
16
Block 8: 64 Kbytes
Block 7: 64 Kbytes
Block 6: 64 Kbytes
Block 5 to 0
(32+8+8+8+4+4) Kbytes
0C0000
16
0CFFFF
16
0D0000
16
0DFFFF
16
0E0000
16
0EFFFF
16
0F0000
16
0FFFFF
16
User ROM area
Block A: 4 Kbytes (Note 1)
00F000
16
00FFFF
16
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M16C/6N4 Group Flash Memory
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This document is under development and its contents are subject to change.
Boot Mode
After a hardware reset which is performed by applying a low-level signal to the P55 pin and a high-level
signal to the CNVSS and P50 pins, the microcomputer is placed in boot mode, thereby executing the program in
the boot ROM area.
During boot mode, the boot ROM and user ROM areas are switched over by the FMR05 bit in the FMR0 register.
The boot ROM area contains a standard serial I/O mode and CAN I/O mode based rewrite control program
which was stored in it when shipped from the factory.
The boot ROM area can be rewritten in parallel input/output mode. Prepare an EW0 mode based rewrite
control program and write it in the boot ROM area, and the flash memory can be rewritten as suitable for the
system.
Functions to Prevent Flash Memory from Rewriting
To prevent the flash memory from being read or rewritten easily, parallel I/O mode has a ROM code protect
and standard serial I/O mode and CAN I/O mode have an ID code check function.
• ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel I/O
mode. Figure 1.22.2 shows the ROMCP register.
The ROMCP register is located in the user ROM area. The ROMCP1 bit consists of two bits. The ROM
code protect function is enabled by setting one or both of two ROMCP1 bits to “0” when the ROMCR bits
are not “002”, with the flash memory thereby protected against reading or rewriting. Conversely, when the
ROMCR bits are “002” (ROM code protect removed), the flash memory can be read or rewritten. Once the
ROM code protect function is enabled, the ROMCR bits cannot be changed during parallel I/O mode.
Therefore, use standard serial I/O mode or other modes to rewrite the flash memory.
• ID Code Check Function
Use this function in standard serial I/O mode and CAN I/O mode. Unless the flash memory is blank, the ID
codes sent from the programmer and the ID codes written in the flash memory are compared to see if
they match. If the ID codes do not match, the commands sent from the programmer are not accepted.
The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16,
0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Prepare a program in which the ID
codes are preset at these addresses and write it in the flash memory.
Figure 1.22.3 shows the ID code store addresses.
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M16C/6N4 Group Flash Memory
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This document is under development and its contents are subject to change.
Figure 1.22.2 ROMCP Register
Figure 1.22.3 Address for ID Code Stored
ROM code protect control address
Symbol Address Value when shipped
ROMCP 0FFFFF
16
FF
16
(Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
Bit symbol Bit name Function
Reserved bit
ROM code protect
reset bit (Notes 1, 2)
ROM code protect level
1 set bit (Notes 1, 3, 4)
Set to "1" RW
RW
RW
RW
RW
RW
-
(b3-b0)
ROMCR
ROMCP1
111
b5 b4
0 0 : Removes protect
0 1 :
1 0 :
Enables ROOMCP1 bit
1 1 :
b7 b6
0 0 :
0 1 : Protect enabled
1 0 :
1 1 : Protect disabled
Note 1: Once any of these bits is set to "0", it cannot be set back to "1". If a memory block that contains the
ROMCP register is erased, the ROMCP register is set to "FF
16
".
Note 2: If the ROMCR bits are set to "00
2
", ROM code protect level 1 is removed. However, because the ROMCR
bits cannot be modified during parallel I/O mode, they need to be modified in standard serial I/O or other
modes.
Note 3: If the ROMCR bits are set to other than "00
2
" and the ROMCP1 bits are set to other than "11
2
" (ROM
code protect enabled), the flash memory is disabled against reading and rewriting in parallel input/output
mode.
Note 4: The ROMCP1 bits are effective when the ROMCR bits are "01
2
", "10
2
" or "11
2
".
0FFFDF
16
to 0FFFDC
16
0FFFE3
16
to 0FFFE0
16
0FFFE7
16
to 0FFFE4
16
0FFFEB
16
to 0FFFE8
16
0FFFEF
16
to 0FFFEC
16
0FFFF3
16
to 0FFFF0
16
0FFFF7
16
to 0FFFF4
16
0FFFFB
16
to 0FFFF8
16
0FFFFF
16
to 0FFFFC
16
Reset vector
Oscillation stop and re-oscillation detection/Watchdog timer vector
Single step vector
Address match vector
BRK instruction vector
Overflow vector
Undefined instruction vector
NMI vector
DBC vector
ID7
ROMCP
ID6
ID5
ID4
ID3
ID2
ID1
Address
4 bytes
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M16C/6N4 Group Flash Memory
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This document is under development and its contents are subject to change.
Item EW0 mode EW1 mode
Operation mode • Single chip mode Single chip mode
• Memory expansion mode
• Boot mode
Areas in which a • User ROM area User ROM area
rewrite control • Boot ROM area
program can be located
Areas in which a Must be transferred to any area other Can be executed directly in the user
rewrite control than the flash memory (e.g., RAM) ROM area
program can be executed before being executed (Note 2)
Areas which can be User ROM area User ROM area
rewritten However, this does not include the area
in which a rewrite control program exists
Software command None •Program, Block Erase command
limitations Cannot be executed on any block in
which a rewrite control program exists
•Erase All Unlocked Block command
Cannot be executed when the lock bit
for any block in which a rewrite control
program exists is set to “1” (unlocked)
or the FMR0 register’s FMR02 bit is set
to “1” (lock bit disabled)
•Read Status Register command
Cannot be executed
Modes after Program or Read Status Register mode Read Array mode
Erase
CPU status during Auto Operating Hold state (I/O ports retain the state in
Write and Auto Erase which they were before the command
was executed) (Note 1)
Flash memory status •Read the FMR0 register's FMR00, Read the FMR0 register's FMR00,
detection FMR06, and FMR07 bits in a program FMR06, and FMR07 bits in a program
•Execute the Read Status Register
command to read the status register's
SR7, SR5, and SR4 flags.
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board
without having to use a ROM programmer, etc.
In CPU rewrite mode, only the user ROM area shown in Figure 1.22.1 can be rewritten and the boot ROM
area cannot be rewritten. Make sure the Program and the Block Erase commands are executed only on
each block in the user ROM area.
During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase
Write 1 (EW1) mode. Table 1.22.3 lists the differences between EW0 and EW1 modes.
Table 1.22.3 EW0 Mode and EW1 Mode
Note 1:
_______
Make sure no interrupts (except NMI and watchdog timer interrupts) and DMA transfers will occur.
Note 2: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite
control program can only be executed in the internal RAM or in an external area that is enabled for
use when the PM13 bit = 1.
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M16C/6N4 Group Flash Memory
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• EW0 Mode
The microcomputer is placed in CPU rewrite mode by setting the FMR0 register’s FMR01 bit to “1” (CPU
rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register’s FMR11 bit
= 0, EW0 mode is selected. The FMR01 bit can be set to “1” by writing “0” and then “1” in succession.
Use software commands to control program and erase operations. Read the FMR0 register or status
register to check the status of program or erase operation at completion.
• EW1 Mode
EW1 mode is selected by setting FMR11 bit to “1” (by writing “0” and then “1” in succession) after setting
the FMR01 bit to “1” (by writing “0” and then “1” in succession).
Read the FMR0 register to check the status of program or erase operation at completion. The status
register cannot be read during EW1 mode.
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Figure 1.22.4 shows the FMR0 register and FMR1 register.
FMR00 Bit
This bit indicates the operating status of the flash memory. The bit is “0” when the Program, Erase, or
Lock Bit program is running; otherwise, the bit is “1”.
FMR01 Bit
The microcomputer is made ready to accept commands by setting the FMR01 bit to “1” (CPU rewrite
mode). During boot mode, make sure the FMR05 bit also is “1” (user ROM area access).
FMR02 Bit
The lock bit set for each block can be disabled by setting the FMR02 bit to “1” (lock bit disabled). (Refer to
“Data Protect Function”.) The lock bits set are enabled by setting the FMR02 bit to “0”.
The FMR02 bit only disables the lock bit function and does not modify the lock bit data (lock bit status
flag). However, if the Erase command is executed while the FMR02 bit is set to “1”, the lock bit data
changes state from “0” (locked) to “1” (unlocked) after Erase is completed.
FMSTP Bit
This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of
current consumed in the flash memory. Setting the FMSTP bit to “1” makes the internal flash memory
inaccessible. Therefore, make sure the FMSTP bit is modified in other than the flash memory area.
In the following cases, set the FMSTP bit to “1”:
• When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00
bit not reset to “1” (ready))
• When entering low power dissipation mode or ring oscillator low power dissipation mode
Figure 1.22.7 shows a flow chart to be followed before and after entering low power dissipation mode.
Note that when going to stop or wait mode, the FMR0 register does not need to be set because the power
for the internal flash memory is automatically turned off and is turned back on again after returning from
stop or wait mode.
FMR05 Bit
This bit switches between the boot ROM and user ROM areas during boot mode. Set this bit to “0” when
accessing the boot ROM area (for read) or “1” (user ROM access) when accessing the user ROM area
(for read, write, or erase).
FMR06 Bit
This is a read-only bit indicating the status of auto program operation. The bit is set to “1” when a program
error occurs; otherwise, it is set to “0”. For details, refer to “Full Status Check”.
FMR07 Bit
This is a read-only bit indicating the status of auto erase operation. The bit is set to “1” when an erase
error occurs; otherwise, it is set to “0”. For details, refer to “Full Status Check”.
FMR11 Bit
Setting this bit to “1” (EW1 mode) places the microcomputer in EW1 mode.
FMR16 Bit
This is a read-only bit indicating the execution result of the Read Lock Bit Status command.
Figures 1.22.5 and 1.22.6 show the setting and resetting of EW0 mode and EW1 mode, respectively.
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M16C/6N4 Group Flash Memory
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Figure 1.22.4 FMR0 Register and FMR1 Register
Flash memory control register 0
Symbol Address After reset
FMR0 01B716 XX0000012
b7 b6 b5 b4 b3 b2 b1 b0
0
RY/BY status flag
FMR00 0 : Busy (being written or erased) (Note 1)
1 : Ready
CPU rewrite mode
select bit (Note 2)
0 : Disables CPU rewrite mode
1 : Enables CPU rewrite mode
FMR01
0 : Boot ROM area is accessed
1 : User ROM area is accessed
Lock bit disable select bit
(Note 3)
0: Enables lock bit
1: Disables lock bit
Flash memory stop bit
(Notes 4, 5)
0 Enables flash memory operation
1: Stops flash memory operation
(placed in low power dissipation mode,
flash memory initialized)
User ROM area select bit
(Effective in only boot mode)
(Note 4)
FMR02
FMSTP
FMR05
Set to "0"Reserved bit
Program status flag
(Note 6)
FMR06
Erase status flag (Note 6)
FMR07 0 : Terminated normally
1 : Terminated in error
0 : Terminated normally
1 : Terminated in error
RW
RW
RW
RW
RW
RO
RO
-
(b4)
RW
RO
Note 1: This status includes writing or reading with the Lock Bit Program or Read Lock Bit Status command.
Note 2: To set this bit to "1", write "0" and then "1" in succession. Make sure no interrupts or no DMA transfers will occur
before writing "1" after writing "0".
Write to this bit when the NMI pin is in the high state. Also, while in EW0 mode, make sure this bit is modified in
other than the flash memory area.
To set this bit to "0", in a read array mode.
Note 3: To set this bit to "1", write "0" and then "1" in succession when the FMR01 bit = 1. Make sure no interrupts or no
DMA transfers will occur before writing "1" after writing "0".
Note 4: Make sure this bit is modified in other than the flash memory area.
Note 5: Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMSTP bit can be set
to "1" by writing "1" in a program, the flash memory is neither placed in low power mode nor initialized.
Note 6: This flag is set to "0" by executing the Clear Status command.
Bit symbol Bit name Function
Flash memory control register 1
Symbol Address After reset
FMR1 01B516 0X00XX0X2
b7 b6 b5 b4 b3 b2 b1 b0
000
EW1 mode select bit (Note) 0 : EW0 mode
1 : EW1 mode
FMR11
Lock bit status flag
FMR16 0 : Lock
1 : Unlock
RW
RO
Set to "0"Reserved bit RW
-
(b7)
Set to "0"Reserved bit RW
-
(b5-b4)
The value in this bit when read is
indeterminate.
Reserved bit RO
-
(b3-b2)
The value in this bit when read is
indeterminate.
Reserved bit
-
(b0)
RW
RO
Note: To set this bit to "1", write "0" and then "1" in succession when the FMR01 bit = 1. Make sure no interrupts or no DMA
transfers will occur before writing "1" after writing "0".
Write to this bit when the NMI pin is in the high state.
Note that the FMR01 and FMR11 bits both are set to "0" by setting the FMR01 bit to "0".
Bit symbol Bit name Function
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Figure 1.22.6 Setting and Resetting of EW1 Mode
Figure 1.22.5 Setting and Resetting of EW0 Mode
EW0 mode operation procedure
Set CM0, CM1, and PM1 registers (Note 1)
Transfer the rewrite control program to any area
other than the flash memory (Note 5)
Single-chip mode, memory expansion
mode, or boot mode
For only boot mode
set the FMR05 bit to "1" (user ROM area access)
Set the FMR01 bit by writing "0" and then "1"
(CPU rewrite mode enabled) (Note 2)
Execute software commands
Execute the Read Array command
Write "0" to the FMR01 bit
(CPU rewrite mode disabled)
For only boot mode
Write "0" to the FMR05 bit (Boot ROM area accessed)
(Note 4)
Jump to a specified address in the flash memory
Jump to the rewrite control program which has been
transferred to any area other than the flash memory
(The subsequent processing is executed by the
rewrite control program in any area other than the
flash memory.)
Rewrite control program
Note 1: Select 10 MHz or less for CPU clock using the CM0
register’s CM06 bit and CM1 register’s CM17 to
CM16 bits. Also, set the PM1 register’s PM17 bit
to "1" (with wait state).
Note 2: To set the FMR01 bit to "1", write "0" and then "1"
in succession. Make sure no interrupts or no DMA
transfers will occur before writing "1" after writing "0".
Write to the FMR01 bit from a program in other
than the flash memory. Also write only when the
NMI pin is "H" level.
Note 3: Disables the CPU rewrite mode after executing
the Read Array command.
Note 4: User ROM area is accessed when the FMR05 bit
is set to "1".
Note 5: When in CPU rewrite mode, the PM10 and PM13
bits in the PM1 register are set to "1".
The rewrite control program can only be executed
in the internal RAM or in an external area that is
enabled for use when the PM13 bit = 1.
EW1 mode operation procedure
Set CM0, CM1, and PM1 registers (Note 2)
Set the FMR01 bit by writing "0" and then "1"
(CPU rewrite mode enabled)
Set the FMR11 bit by writing "0" and then "1"
(EW1 mode) (Note 3)
Single-chip mode (Note 1)
Execute software commands
Write "0" to the FMR01 bit
(CPU rewrite mode disabled)
Note 1: In EW1 mode, do not set the microcomputer in memory expansion or boot mode.
Note 2: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1 register’s
CM17 to CM16 bits. Also, set the PM1 register’s PM17 bit to "1" (with wait state).
Note 3: To set the FMR01 bit to "1", write "0" and then "1" in succession. Make sure no interrupts or
no DMA transfers will occur before writing "1" after writing "0".
Also write only when the NMI pin is "H" level.
Program in ROM
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Figure 1.22.7 Processing Before and After Low Power Dissipation Mode
Transfer a low power dissipation mode program
to any area other the flash memory
Set FMSTP bit to "1"
(flash memory stopped. Low power state) (Note 1)
Set the FMR01 bit by writing "0" and then "1"
(CPU rewrite mode enabled)
Switch the clock source for CPU clock.
Turn main clock off. (Note 2)
Process of low power dissipation mode or
ring oscillator low power dissipation mode
Turn main clock on
-
>
wait until oscillation stabilizes
-
>
switch the clock source for CPU clock (Note 2)
Set the FMSTP bit to "0" (flash memory operation)
Write "0" to the FMR01 bit
(CPU rewrite mode disabled)
Wait until the flash memory circuit stabilizes (tps)
(Note 3)
Jump to a specified address in the flash memory
Jump to the low power dissipation mode program
which has been transferred to any area other than
the flash memory
(The subsequent processing is executed by a program
in any area other than the flash memory.)
Low power dissipation
mode program
Note 1: Set the FMSTP bit to "1" after setting the FMR01 bit to "1" (CPU rewrite mode).
Note 2: Before the clock source for CPU clock can be changed to main clock or sub clock, the clock to which to be changed
must be stable.
Note 3: Insert tps wait time in a program. The flash memory cannot be accessed during this wait time.
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Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
(1) Operation Speed
Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for CPU clock using
the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register. Also, set the PM17
bit in the PM1 register to “1” (with wait state).
(2) Instructions to Prevent from Using
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts
EW0 Mode
• Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
_______
• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register
are initialized when one of those interrupts occurs. The jump addresses for those interrupt
service routines should be set in the fixed vector table.
_______
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory’s internal data is referenced.
EW1 Mode
• Make sure that any interrupt which has a vector in the variable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
_______
• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when
this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed
vector table.
_______
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be
executed again after exiting the interrupt service routine.
(4) How to Access
To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary
to ensure that no interrupts or no DMA transfers will occur before writing “1” after writing “0”. Also only
_______
when NMI pin is “H” level.
(5) Writing in User ROM Space
EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse-
quently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial
I/O, parallel I/O or CAN I/O mode should be used.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.
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(6) DMA Transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0
(during the auto program or auto erase period).
(7) Writing Command and Data
Write the command code and data at even addresses.
(8) Wait Mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing
the WAIT instruction.
(9) Stop Mode
When shifting to stop mode, the following settings are required:
•Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the
CM10 bit to “1” (stop mode).
•Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop mode)
Example program BSET 0, CM1 ; Stop mode
JMP.B L1
L1:
Program after returning from stop mode
(10) Low Power Dissipation Mode and Ring Oscillator Low Power Dissipation Mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
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Software Commands
Software commands are described below. The command code and data must be read and written in 16-bit
unit, to and from even addresses in the user ROM area. When writing command code, the high-order 8
bits (D15 to D8) are ignored. Table 1.22.4 lists the software commands.
Table 1.22.4 Software Commands
Read Array Command (FF16)
This command reads the flash memory.
Writing “xxFF16” in the first bus cycle places the microcomputer in read array mode. Enter the read
address in the next or subsequent bus cycles, and the content of the specified address can be read in
16-bit unit.
Because the microcomputer remains in read array mode until another command is written, the contents
of multiple addresses can be read in succession.
Read Status Register Command (7016)
This command reads the status register.
Write “xx7016” in the first bus cycle, and the status register can be read in the second bus cycle. (Refer
to “Status Register.”) When reading the status register too, specify an even address in the user ROM
area.
Do not execute this command in EW1 mode.
Read array
Read status register
Clear status register
Program
Block erase
Erase all unlocked block (Note 1)
Lock bit program
Read lock bit status
Write
Write
Write
Write
Write
Write
Write
Write
✕
✕
✕
WA
✕
✕
BA
✕
xxFF16
xx7016
xx5016
xx4016
xx2016
xxA716
xx7716
xx7116
-
Read
-
Write
Write
Write
Write
Write
-
SRD
-
WD
xxD016
xxD016
xxD016
xxD016
-
✕
-
WA
BA
✕
BA
BA
Mode Address Data
(D15 to D0)Mode Address
First bus cycle Second bus cycle
Software command Data
(D15 to D0)
(Note 2)
Note 1: It is only blocks 0 to 8 that can be erased by the Erase All Unlocked Block command.
Block A cannot be erased. Use the Block Erase command to erase block A.
Note 2: Note that the commands in the second bus cycle are different from those of the existing M16C/6N0 group.
The lock bit status is output to the FMR16 bit of the FMR1 register. Read this bit: “0” (locked), “1” (unlocked)
SRD: Status register data (D7 to D0)
WA: Write address (Make sure the address value specified in the first bus cycle is the same even address as the
write address specified in the second bus cycle.)
WD: Write data (16 bits)
BA: Uppermost block address (even address, however)
✕: Any even address in the user ROM area
x: High-order 8 bits of command (ignored)
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Figure 1.22.8 Program Command
Clear Status Register Command (5016)
This command clears the status register to “0”.
Write “xx5016” in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to
SR5 in the status register will be set to “0”.
Program Command (4016)
This command writes data to the flash memory in 1-word (2-byte) unit.
Write “xx4016” in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in
the first bus cycle is the same even address as the write address specified in the second bus cycle.
Check the FMR00 bit in the FMR0 register to see if auto programming has finished. The FMR00 bit is
“0” during auto programming and set to “1” when auto programming is completed.
Check the FMR06 bit in the FMR0 register after auto programming has finished, and the result of auto
programming can be known. (Refer to “Full Status Check”.)
Figure 1.22.8 shows an example of program flowchart.
Note that each block can be disabled from being programmed by a lock bit. (Refer to “Data Protect Function”.)
Be careful not to write over already programmed addresses.
In EW1 mode, do not execute this command on any address at which the rewrite control program is
located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto programming
starts, making it possible to read the status register. The status register bit 7 (SR7) is set to “0” at the
same time auto programming starts, and set back to “1” when auto programming finishes. In this case,
the microcomputer remains in read status register mode until a read command is written next. The
result of auto programming can be known by reading the status register after auto programming has
finished.
Start
YES
NO
Write the command code "xx4016"
to the write address
FMR00=1?
Program
completed
Note: Write the command code and data at even number.
Full status check
Write data to the write address
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Figure 1.22.9 Block Erase Command
Block Erase
Write “xx2016” in the first bus cycle and write “xxD016” to the uppermost address of a block (even
address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start.
Check the FMR0 register’s FMR00 bit to see if auto erasing has finished.
The FMR00 bit is “0” during auto erasing and set to “1” when auto erasing is completed.
Check the FMR0 register’s FMR07 bit after auto erasing has finished, and the result of auto erasing
can be known. (Refer to “Full Status Check”.)
Figure 1.22.9 shows an example of a block erase flowchart.
Each block can be protected against erasing by a lock bit. (Refer to “Data Protect Function”.)
In EW1 mode, do not execute this command on any address at which the rewrite control program is
located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing
starts, making it possible to read the status register. The status register bit 7 (SR7) is set to “0” at the
same time auto erasing starts, and set back to “1” when auto erasing finishes. In this case, the micro-
computer remains in read status register mode until the Read Array or Read Lock Bit Status command
is written next.
Write "xxD016" to the uppermost
block address
Start
YES
NO
FMR00=1?
Full status check
Note: Write the command code and data at even number.
Block erase completed
Write the command code "xx2016"
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Erase All Unlocked Block
Write “xxA716” in the first bus cycle and write “xxD016” in the second bus cycle, and all blocks except
block A will be erased successively, one block at a time.
Check the FMR0 register’s FMR00 bit to see if auto erasing has finished. The result of the auto erase
operation can be known by inspecting the FMR0 register’s FMR07 bit.
Each block can be protected against erasing by a lock bit. (Refer to “Data Protect Function”.)
In EW1 mode, do not execute this command when the lock bit for any block = 1 (unlocked) in which the
rewrite control program is stored, or when the FMR0 register’s FMR02 bit = 1 (lock bit disabled).
In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing
starts, making it possible to read the status register. The status register bit 7 (SR7) is set to “0” at the
same time auto erasing starts, and set back to “1” when auto erasing finishes. In this case, the
microcomputer remains in read status register mode until the Read Array or Read Lock Bit Status
command is written next.
Note that only blocks 0 to 8 can be erased by the Erase All Unlocked Block command. Block A cannot
be erased. Use the Block Erase command to erase block A.
Lock Bit Program Command (7716/D016)
This command sets the lock bit for a specified block to “0” (locked).
Write “xx7716” in the first bus cycle and write “xxD016” to the uppermost address of a block (even
address, however) in the second bus cycle, and the lock bit for the specified block is set to “0”. Make
sure the address value specified in the first bus cycle is the same uppermost block address that is
specified in the second bus cycle.
Figure 1.22.10 shows an example of a lock bit program flowchart.
The lock bit status (lock bit data) can be read using the Read Lock Bit Status command.
Check the FMR0 register’s FMR00 bit to see if writing has finished.
For details about the lock bit function, and on how to set the lock bit to “1”, refer to “Data Protect
Function”.
Figure 1.22.10 Lock Bit Program Command
Start
YES
NO
FMR00=1?
Full status check
Note: Write the command code and data at even number.
Write "xxD016" to the uppermost
block address
Write command code "xx7716" to
the uppermost block address
Lock bit program completed
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Read Lock Bit Status Command (7116)
This command reads the lock bit status of a specified block.
Write “xx7116” in the first bus cycle and write “xxD016” to the uppermost address of a block (even
address, however) in the second bus cycle, and the lock bit status of the specified block is stored in the
FMR1 register’s FMR16 bit. Read the FMR16 bit after the FMR0 register’s FMR00 bit is set to “1”
(ready).
Figure 1.22.11 shows an example of a read lock bit status flowchart.
Figure 1.22.11 Read Lock Bit Status Command
.Note: Write the command code and data at even number
Start
YES
NO
FMR00=1?
YES
NO
FMR16=0?
Write the command code "xx71
16
"
Write "xxD0
16
" to the uppermost
block address
Not locked
Locked
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Data Protect Function
Each block in the flash memory has a nonvolatile lock bit. The lock bit is effective when the FMR02 bit =
0 (lock bit enabled). The lock bit allows each block to be individually protected (locked) against program-
ming and erasure. This helps to prevent data from inadvertently written to or erased from the flash
memory. The following shows the relationship between the lock bit and the block status.
• When the lock bit = 0, the block is locked (protected against programming and erasure).
• When the lock bit = 1, the block is not locked (can be programmed or erased).
The lock bit is set to “0” (locked) by executing the Lock Bit Program command, and is set to “1” (unlocked)
by erasing the block. The lock bit cannot be set to “1” by a command.
The lock bit status can be read using the Read Lock Bit Status command
The lock bit function is disabled by setting the FMR02 bit to “1”, with all blocks placed in an unlocked state.
(The lock bit data itself does not change state.) Setting the FMR02 bit to “0” enables the lock bit function
(lock bit data retained).
If the Block Erase or Erase All Unlocked Block command is executed while the FMR02 bit = 1, the target
block or all blocks are erased irrespective of how the lock bit is set. The lock bit for each block is set to “1”
after completion of erasure.
For details about the commands, refer to “Software Commands.”
Status Register
The status register indicates the operating status of the flash memory and whether an erase or program-
ming operation terminated normally or in error. The status of the status register can be known by reading
the FMR0 register’s FMR00, FMR06, and FMR07 bits.
Table 1.22.5 shows the status register.
In EW0 mode, the status register can be read in the following cases:
(1) When a given even address in the user ROM area is read after writing the Read Status Register
command
(2) When a given even address in the user ROM area is read after executing the Program, Block Erase,
Erase All Unlocked Block, or Lock Bit Program command but before executing the Read Array
command.
Sequencer Status (SR7 and FMR00 Bits)
The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto
programming, auto erase, and lock bit write, and is set to “1” (ready) at the same time the operation
finishes.
Erase Status (SR5 and FMR07 Bits)
Refer to “Full Status Check”.
Program Status (SR4 and FMR06 Bits)
Refer to “Full Status Check”.
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Table 1.22.5 Status Register
SR7 (D7)
SR6 (D6)
SR5 (D5)
SR4 (D4)
SR3 (D3)
SR2 (D2)
SR1 (D1)
SR0 (D0)
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
Busy
-
Terminated normally
Terminated normally
-
-
-
-
Ready
-
Terminated in error
Terminated in error
-
-
-
-
“0”
Status name Contents
Status register
bit “1”
FMR00
-
FMR07
FMR06
-
-
-
-
FMR0 register
bit Value after reset
1
-
0
0
-
-
-
-
Note: The FMR07 bit (SR5) and FMR06 bit (SR4) are set to “0” by executing the Clear Status Register command.
When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program, Block Erase, Erase All Unlocked
Block, and Lock Bit Program commands are not accepted.
D7 to D0: Indicates the data bus which is read out when the Read Status Register command is executed.
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FRM00 register
(status register)
status Error Error occurrence condition
FMR07 FMR06
(SR5) (SR4)
1 1 Command •When any command is not written correctly
sequence error •When invalid data was written other than those that can be written
in the second bus cycle of the Lock Bit Program, Block Erase, or
Erase All Unlocked Block command (i.e., other than “xxD016” or
“xxFF16”) (Note 1)
1 0 Erase error •When the Block Erase command was executed on locked blocks
(Note 2)
•When the Block Erase or Erase All Unlocked Block command
was executed on unlocked blocks but the blocks were not
automatically erased correctly
0 1 Program error •When the Block Erase command was executed on locked blocks
(Note 2)
•When the Program command was executed on unlocked blocks
but the blocks were not automatically programmed correctly.
•When the Lock Bit Program command was executed but not
programmed correctly
Full Status Check
When an error occurs, the FMR0 register’s FMR06 or FMR07 bits are set to “1”, indicating occurrence
of each specific error. Therefore, execution results can be verified by checking these status bits (full
status check). Table 1.22.6 lists errors and FMR0 register status. Figure 1.22.12 shows a full status
check flowchart and the action to be taken when each error occurs.
Table 1.22.6 Errors and FMR0 Register Status
Note 1: Writing “xxFF16” in the second bus cycle of these commands places the microcomputer in read array
mode, and the command code written in the first bus cycle is nullified.
Note 2: When the FMR02 bit of FMR0 register = 1 (lock bit disabled), no error will occur under this condition.
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Figure 1.22.12 Full Status Check and Handling Procedure for Each Error
Full status check
FMR06 = 1
and
FMR07 = 1?
NO
Command
sequence error
YES
FMR07 = 0?
YES
Erase error
NO
(1) Execute the Clear Status Register command to set
status flags to "0".
(2) Reexecute the command after checking that it is
entered correctly.
(1) Execute the Clear Status Register command to set
the erase status flag to "0".
(2) Execute the Read Lock Bit Status command to see
if the lock bit for the block in error is "0". If so, set
the FMR0 register s FMR02 bit to "1".
(3) Reexecute the Block Erase Command or Erase All
Unlocked Block command.
Note 4: If FMR06 or FMR07 = 1, any of the Program, Block Erase, Erase All Unlocked
Block, Lock Bit Program, or Read Lock Bit Status command is not accepted.
Execute the Clear Status Register command before executing those commands.
FMR06 = 0?
YES
Program error
NO
Full status check completed
Note 1: If the error still occurs, the block in error cannot
be used.
Furthermore, if the lock bit = 1 in (2) above,
the block in error cannot be used either.
(1) Execute the Clear Status Register command to set
the erase status flag to "0" .
(2) Execute the Read Lock Bit Status command to see
if the lock bit for the block in error is "0". If so, set
the FMR0 register s FMR02 bit to "1".
(3) Reexecute the Program command.
Note 2: If the error still occurs, the block in error cannot
be used.
Furthermore, if the lock bit = 1 in (2) above,
the block in error cannot be used either.
[During programming]
(1) Execute the Clear Status Register command to set
the erase status flag to "0" .
(2) Set the FMR0 register s FMR02 bit to "1".
(3) Execute the Block Erase command to erase the block
in error.
(4) Reexecute the Lock Bit command.
Note 3: If the error still occurs, the block in error cannot
be used.
[During lock bit programming]
Rev.1.00 2003.05.30 page 283
M16C/6N4 Group Flash Memory
Under development
This document is under development and its contents are subject to change.
Standard Serial I/O Mode
In standard serial I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on-
board by using a serial programmer suitable for the M16C/6N4 group. For more information about serial
programmers, contact the manufacturer of your serial programmer. For details on how to use, refer to the
user’s manual included with your serial programmer.
Table 1.22.7 lists pin functions for standard serial I/O mode. Figures 1.22.13 shows pin connections for
standard serial I/O mode.
ID Code Check Function
This function determines whether the ID codes sent from the serial programmer and those written in the
flash memory match. (Refer to “Functions to Prevent Flash Memory from Rewriting”.)
Rev.1.00 2003.05.30 page 284
M16C/6N4 Group Flash Memory
Under development
This document is under development and its contents are subject to change.
Table 1.22.7 Pin Functions for Standard Serial I/O Mode
___________
Note: When using standard serial input/output mode 1, the TxD pin must be held high while the RESET pin
is pulled low. Therefore, connect this pin to VCC via a resistor. Because this pin is directed for data
output after reset, adjust the pull-up resistance value in the system so that data transfers will not be
affected.
Apply the voltage guaranteed for Program and Erase to VCC pin and 0 V
to VSS pin.
Connect to VCC pin.
____________
Reset input pin. While RESET pin is "L" level, input 20 cycles or longer
clock to XIN pin.
Connect a ceramic resonator or crystal oscillator between XIN and XOUT
pins. To input an externally generated clock, input it to XIN pin and open
XOUT pin.
Connect this pin to VCC or VSS.
Connect AVSS to VSS and AVCC to VCC, respectively.
Enter the reference voltage for A-D and D-A converters from this pin.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” level signal.
Input “H” or “L” level signal or open.
Input “L” level signal.
Input “H” or “L” level signal or open.
Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitors the boot program operation
check signal output pin.
Standard serial I/O mode 1: Serial clock input pin.
Standard serial I/O mode 2: Input “L”.
Serial data input pin
Serial data output pin (Note)
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Connect this pin to VCC.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or connect to a CAN transceiver.
Input “H” level signal, open or connect to a CAN transceiver.
Input “H” or “L” level signal or open.
VCC, VSS
CNVSS
_____________
RESET
XIN
XOUT
BYTE
AVCC, AVSS
VREF
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50
P51 to P54,
P56, P57
P55
P60 to P63
________
P64/RTS1
P65/CLK1
P66/RxD1
P67/TxD1
P70 to P77
P80 to P84,
P86, P87
_______
P85/NMI
P90 to P94, P97
P95/CRx0
P96/CTx0
P100 to P107
I
I
I
O
I
I
I
I
I
I
I
I
I
I
I
O
I
I
O
I
I
I
I
I
O
I
Pin Name I/O Description
Power input
CNVSS
Reset input
Clock input
Clock output
BYTE
Analog power
supply input
Reference
voltage input
Input port P0
Input port P1
Input port P2
Input port P3
Input port P4
_____
CE input
Input port P5
________
EPM input
Input port P6
BUSY output
SCLK input
RxD input
TxD output
Input port P7
Input port P8
________
NMI input
Input port P9
CRx input
CTx output
Input port P10
Rev.1.00 2003.05.30 page 285
M16C/6N4 Group Flash Memory
Under development
This document is under development and its contents are subject to change.
Figure 1.22.13 Pin Connections for Serial I/O Mode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
CNV
SS
RESET
V
SS
V
CC1
V
CC2
T
X
D
SCLK
EPM
CE
R
X
D
BUSY
CNVss
EPM
RESET
CE
Signal
Mode setup method
Value
V
CC1
V
SS
V
SS
to V
CC1
V
CC2
M16C/6N4 Group
(Flash memory version)
Package: 100P6S-A
Connect
oscillator
circuit
Rev.1.00 2003.05.30 page 286
M16C/6N4 Group Flash Memory
Under development
This document is under development and its contents are subject to change.
Example of Circuit Application in Standard Serial I/O Mode
Figures 1.22.14 and 1.22.15 show example of circuit application in standard serial I/O mode 1 and mode 2,
respectively. Refer to the user’s manual for serial writer to handle pins controlled by a serial writer.
Note that when using the standard serial I/O mode 2, make sure a main clock input oscillation frequency
is set to 5 MHz, 10 MHz or 16 MHz .
Figure 1.22.14 Circuit Application in Standard Serial I/O Mode 1
Figure 1.22.15 Circuit Application in Standard Serial I/O Mode 2
Microcomputer
Control pins and external circuitry will vary according to programmer.
For more information, refer to the programmer manual.
In this example, modes are switched between single-chip mode and standard serial
input/output mode by controlling the CNVss input with a switch.
If in standard serial input/output mode 1 there is a possibility that the user reset signal
will go low during serial input/output mode, break the connection between the user
reset signal and RESET pin by using, for example, a jumper switch.
SCLK input
BUSY output
TxD output
RxD input
Reset input
P64/RTS
1
P66/CLK
1
P67/TxD
1
RESET
P66/RxD
1
CNVss
P5
0
(CE)
P5
5
(EPM)
P8
5
/NMI
User reset
signal
Microcomputer
P64/RTS1
P65/CLK1
P67/TxD1
P66/RxD1CNVss
P50(CE)
P55(EPM)
P85/NMI
Monitor output
TxD output
RxD input
In this example, modes are switched between single-chip mode and standard serial
input/output mode by controlling the CNVss input with a switch.
Rev.1.00 2003.05.30 page 287
M16C/6N4 Group Flash Memory
Under development
This document is under development and its contents are subject to change.
Parallel I/O Mode
In parallel I/O mode, the user ROM and boot ROM areas can be rewritten by using a parallel programmer
suitable for the M16C/6N4 group. For more information about parallel programmers, contact the manufac-
turer of your parallel programmer. For details on how to use, refer to the user’s manual included with your
parallel programmer.
User ROM and Boot ROM Areas
In the boot ROM area, an erase block operation is applied to only one 4-Kbyte block. The boot ROM area
contains a standard serial I/O and CAN I/O modes based rewrite control program which was written in it
when shipped from the factory. Therefore, when using a serial programmer or a CAN programmer, be
careful not to rewrite the boot ROM area.
When in parallel I/O mode, the boot ROM area is located at addresses 0FF00016 to 0FFFFF16. When
rewriting the boot ROM area, make sure that only this address range is rewritten. (Do not access other
than the addresses 0FF00016 to 0FFFFF16.)
ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten. (Refer to “Functions
to Prevent Flash Memory from Rewriting”.)
Rev.1.00 2003.05.30 page 288
M16C/6N4 Group Flash Memory
Under development
This document is under development and its contents are subject to change.
CAN I/O Mode
In CAN I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by
using a CAN programmer suitable for the M16C/6N4 group. For more information about CAN program-
mers, contact the manufacturer of your CAN programmer. For details on how to use, refer to the user’s
manual included with your CAN programmer.
Table 1.22.8 lists pin functions for CAN I/O mode. Figures 1.22.16 shows pin connections for CAN I/O
mode.
ID code check function
This function determines whether the ID codes sent from the CAN programmer and those written in the
flash memory match. (Refer to ”Functions to Prevent Flash Memory from Rewriting”.)
Table 1.22.8 Pin Functions for CAN I/O Mode
Apply the voltage guaranteed for Program and Erase to VCC pin and 0 V
to VSS pin.
Connect to VCC pin.
____________
Reset input pin. While RESET pin is “L” level, input 20 cycles or longer
clock to XIN pin.
Connect a ceramic resonator or crystal oscillator between XIN and XOUT
pins. To input an externally generated clock, input it to XIN pin and open
XOUT pin.
Connect this pin to VCC or VSS.
Connect AVSS to VSS and AVCC to VCC, respectively.
Enter the reference voltage for A-D and D-A converters from this pin.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” level signal.
Input “H” or “L” level signal or open.
Input “L” level signal.
Input “H” or “L” level signal or open.
Input “L” level signal.
Input “H” level signal.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Connect this pin to VCC.
Input “H” or “L” level signal or open.
Connect to a CAN transceiver.
Connect to a CAN transceiver.
Input “H” or “L” level signal or open.
VCC, VSS
CNVSS
_____________
RESET
XIN
XOUT
BYTE
AVCC, AVSS
VREF
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50
P51 to P54,
P56, P57
P55
P60 to P64, P66
P65/CLK1
P67/TxD1
P70 to P77
P80 to P84,
P86, P87
_______
P85/NMI
P90 to P94, P97
P95/CRx0
P96/CTx0
P100 to P107
I
I
I
O
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
O
I
Pin Name I/O Description
Power input
CNVSS
Reset input
Clock input
Clock output
BYTE
Analog power
supply input
Reference
voltage input
Input port P0
Input port P1
Input port P2
Input port P3
Input port P4
_____
CE input
Input port P5
________
EPM input
Input port P6
SCLK input
TxD output
Input port P7
Input port P8
________
NMI input
Input port P9
CRx input
CTx output
Input port P10
Rev.1.00 2003.05.30 page 289
M16C/6N4 Group Flash Memory
Under development
This document is under development and its contents are subject to change.
Figure 1.22.16 Pin Connections for CAN I/O Mode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
CNV
SS
RESET
V
SS
V
CC1
V
CC2
T
X
D
SCLK
EPM
CE
CNVss
EPM
RESET
CE
SCLK
TxD
Mode setup method
ValueSignal
V
CC
V
SS
V
SS
to V
CC
V
CC
V
SS
V
CC
CTx
CRx
M16C/6N4 Group
(Flash memory version)
Package: 100P6S-A
Connect
oscillator
circuit
Rev.1.00 2003.05.30 page 290
M16C/6N4 Group Flash Memory
Under development
This document is under development and its contents are subject to change.
Example of Circuit Application in CAN I/O Mode
Figure 1.22.17 shows example of circuit application in CAN I/O mode. Refer to the user’s manual for CAN
writer to handle pins controlled by a CAN writer.
CNVss
P50(CE)
P55(EPM)
Microcomputer
CAN_L
CAN_H
CAN_L
CAN_H
CAN transceiver
P67/TXD1
P96/CTx0
P95/CRx0
P65/CLK1
RESET
Control pins and external circuitry will vary according to programmer.
For more information, refer to the programmer manual.
In this example, modes are switched between single-chip mode and CAN input/output
mode by controlling the CNVss input with a switch.
P85/NMI
Figure 1.22.17 Circuit Application in CAN I/O Mode
Rev.1.00 2003.05.30 page 291
M16C/6N4 Group Flash Memory
Under development
This document is under development and its contents are subject to change.
Note 1: Referenced to VCC = 4.5 to 5.5 V, Topr = 0 to 60 °C unless otherwise specified.
Note 2: n denotes the number of blocks to erase.
Table 1.22.10 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics
(at Topr = 0 to 60 °C)
200
4
4 ✕ n
200
15
µs
s
s
µs
µs
Word program time
Block erase time
Erase all unlocked blocks time
Lock bit program time
Flash memory circuit stabilization wait time
Parameter Min.
Standard Unit
Max.Typ.
30
1
1 ✕ n
(Note 2)
30
Electrical Characteristics
Table 1.22.9 lists the flash memory electrical characteristics. Table 1.22.10 lists the flash memory version
program/erase voltage and read operation voltage characteristics.
Table 1.22.9 Flash Memory Electrical Characteristics (Note 1)
Symbol
-
-
-
-
tps
VCC = 5.0 ± 0.5 V
Flash read operation voltageFlash program, erase voltage
VCC = 4.2 to 5.5 V
Rev.1.00 2003.05.30 page 292
M16C/6N4 Group Package Dimension
Under development
This document is under development and its contents are subject to change.
Package Dimension
QFP100-P-1420-0.65 1.58
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
100P6S-A Plastic 100pin 14✕20mm body QFP
–
0.1
–
––
0.2
–
–
––
–
–
––
–
Symbol Min Nom Max
A
A2
b
c
D
E
HE
L
L1
y
b2
Dimension in Millimeters
HD
A1
0.35
––
I21.3
––
MD14.6
––
ME20.6
10°0°
0.1
1.4
0.80.60.4
23.122.822.5
17.116.816.5
0.65
20.220.019.8
14.214.013.8
0.20.150.13
0.40.30.25
2.8
0
3.05
e
e
e
E
c
HE
1
30
31
81
50
80
51
HD
D
MD
ME
A
F
A1A2
L1
L
y
b2
I2
Recommended Mount Pad
Detail F
100
x – – 0.13
b
xM
MMP
Rev.1.00 2003.05.30 page 293
M16C/6N4 Group Register Index
Under development
This document is under development and its contents are subject to change.
Register Index
A
AD0 ............................................... 190
AD1 ............................................... 190
AD2 ............................................... 190
AD3 ............................................... 190
AD4 ............................................... 190
AD5 ............................................... 190
AD6 ............................................... 190
AD7 ............................................... 190
ADCON0 .... 189,192,194,196,198,200
ADCON1 .... 189,192,194,196,198,200
ADCON2 ....................................... 190
ADIC................................................ 77
AIER ................................................ 89
AIER2 .............................................. 89
C
C01ERRIC ...................................... 77
C01WKIC ........................................ 77
C0AFS........................................... 219
C0CONR ....................................... 217
C0CTLR ........................................ 213
C0GMR .......................................... 211
C0ICR ........................................... 216
C0IDR ........................................... 216
C0LMAR......................................... 211
C0LMBR......................................... 211
C0MCTL0 ...................................... 212
C0MCTL1 ...................................... 212
C0MCTL2 ...................................... 212
C0MCTL3 ...................................... 212
C0MCTL4 ...................................... 212
C0MCTL5 ...................................... 212
C0MCTL6 ...................................... 212
C0MCTL7 ...................................... 212
C0MCTL8 ...................................... 212
C0MCTL9 ...................................... 212
C0MCTL10 .................................... 212
C0MCTL11 .................................... 212
C0MCTL12 .................................... 212
C0MCTL13 .................................... 212
C0MCTL14 .................................... 212
C0MCTL15 .................................... 212
C0RECIC ........................................ 77
C0RECR ....................................... 218
C0SSTR ........................................ 215
C0STR .......................................... 214
C0TECR ........................................ 218
C0TRMIC ........................................ 77
C0TSR .......................................... 219
C1AFS........................................... 219
C1CONR ....................................... 217
C1CTLR ........................................ 213
C1GMR .......................................... 211
C1ICR ........................................... 216
C1IDR ........................................... 216
C1LMAR......................................... 211
C1LMBR......................................... 211
C1MCTL0 ...................................... 212
C1MCTL1 ...................................... 212
C1MCTL2 ...................................... 212
C1MCTL3 ...................................... 212
C1MCTL4 ...................................... 212
C1MCTL5 ...................................... 212
C1MCTL6 ...................................... 212
C1MCTL7 ...................................... 212
C1MCTL8 ...................................... 212
C1MCTL9 ...................................... 212
C1MCTL10 .................................... 212
C1MCTL11 .................................... 212
C1MCTL12 .................................... 212
C1MCTL13 .................................... 212
C1MCTL14 .................................... 212
C1MCTL15 .................................... 212
C1RECIC ........................................ 78
C1RECR ....................................... 218
C1SSTR ........................................ 215
C1STR .......................................... 214
C1TECR ........................................ 218
C1TRMIC ........................................ 78
C1TSR .......................................... 219
CAN0/1 SLOT 0 to 15
: Time Stamp ....................... 209,210
: Data Field .......................... 209,210
: Message Box .................... 209,210
CCLKR ............................................ 52
CM0................................................. 49
CM1................................................. 50
CM2................................................. 51
CPSRF ................................... 107,121
CRCD ............................................ 205
CRCIN ........................................... 205
CSE ................................................. 43
CSR................................................. 37
D
DA0 ............................................... 204
DA1 ............................................... 204
DACON ......................................... 204
DAR0............................................... 96
DAR1............................................... 96
DM0CON......................................... 95
DM0IC ............................................. 77
DM0SL ............................................ 94
DM1CON......................................... 95
CM1IC ............................................. 77
DM1SL ............................................ 95
DTT ............................................... 131
F
FMR0 ............................................ 269
FMR1 ............................................ 269
I
ICTB2 ............................................ 133
IDB0 .............................................. 131
IDB1 .............................................. 131
IFSR0 .............................................. 86
IFSR1 .............................................. 86
INT0IC ............................................. 78
INT1IC ............................................. 78
INT2IC ............................................. 78
INT3IC ............................................. 78
INT4IC ............................................. 78
INT5IC ............................................. 78
INVC0............................................ 129
INVC1............................................ 130
K
KUPIC ............................................. 77
O
ONSF ............................................ 107
P
P0 .................................................. 239
P1 .................................................. 239
P2 .................................................. 239
P3 .................................................. 239
P4 .................................................. 239
P5 .................................................. 239
P6 .................................................. 239
P7 .................................................. 239
Rev.1.00 2003.05.30 page 294
M16C/6N4 Group Register Index
Under development
This document is under development and its contents are subject to change.
P8 .................................................. 239
P9 .................................................. 239
P10 ................................................ 239
PCLKR ............................................ 52
PCR............................................... 241
PD0 ............................................... 238
PD1 ............................................... 238
PD2 ............................................... 238
PD3 ............................................... 238
PD4 ............................................... 238
PD5 ............................................... 238
PD6 ............................................... 238
PD7 ............................................... 238
PD8 ............................................... 238
PD9 ............................................... 238
PD10 ............................................. 238
PLC0 ............................................... 54
PM0 ................................................. 31
PM1 ................................................. 32
PM2 ................................................. 53
PRCR .............................................. 71
PUR0 ............................................. 240
PUR1 ............................................. 240
PUR2 ............................................. 240
R
RMAD0............................................ 89
RMAD1............................................ 89
RMAD2............................................ 89
RMAD3............................................ 89
ROMCP ......................................... 265
S
S0RIC.............................................. 77
S0TIC .............................................. 77
S1RIC.............................................. 77
S1TIC .............................................. 77
S2RIC.............................................. 77
S2TIC .............................................. 77
S3BRG .......................................... 183
S3C ............................................... 183
S3IC ................................................ 78
S3TRR .......................................... 183
SAR0 ............................................... 96
SAR1 ............................................... 96
T
TA0 ................................................ 105
TA0IC .............................................. 77
TA0MR ............... 105,108,110,115,117
TA1 ......................................... 105,132
TA11 .............................................. 132
TA1IC .............................................. 77
TA1MR ........ 105,108,110,115,117,135
TA2 ......................................... 105,132
TA21 .............................................. 132
TA2IC .............................................. 77
TA2MR ... 105,108,110,112,115,117,135
TA3 ................................................ 105
TA3IC .............................................. 77
TA3MR ........ 105,108,110,112,115,117
TA4 ......................................... 105,132
TA41 .............................................. 132
TA4IC .............................................. 77
TA4MR ... 105,108,110,112,115,117,135
TABSR ............................ 106,121,134
TB0................................................ 120
TB0IC .............................................. 77
TB0MR ..................... 120,122,123,125
TB1................................................ 120
TB1IC .............................................. 77
TB1MR ..................... 120,122,123,125
TB2......................................... 120,132
TB2IC .............................................. 77
TB2MR .............. 120,122,123,125,135
TB2SC........................................... 133
TB3................................................ 120
TB3IC .............................................. 77
TB3MR ..................... 120,122,123,125
TB4................................................ 120
TB4IC .............................................. 77
TB4MR ..................... 120,122,123,125
TB5................................................ 120
TB5IC .............................................. 77
TB5MR ..................... 120,122,123,125
TBSR............................................. 121
TCR0 ............................................... 96
TCR1 ............................................... 96
TRGSR................................... 107,134
U
U0BCNIC ........................................ 77
U0BRG .......................................... 141
U0C0 ............................................. 142
U0C1 ............................................. 143
U0MR ............................................ 142
U0RB ............................................. 141
U0SMR.......................................... 144
U0SMR2........................................ 145
U0SMR3........................................ 145
U0SMR4........................................ 146
U0TB ............................................. 141
U1BCNIC ........................................ 77
U1BRG .......................................... 141
U1C0 ............................................. 142
U1C1 ............................................. 143
U1MR ............................................ 142
U1RB ............................................. 141
U1SMR.......................................... 144
U1SMR2........................................ 145
U1SMR3........................................ 145
U1SMR4........................................ 146
U1TB ............................................. 141
U2BCNIC ........................................ 77
U2BRG .......................................... 141
U2C0 ............................................. 142
U2C1 ............................................. 143
U2MR ............................................ 142
U2RB ............................................. 141
U2SMR.......................................... 144
U2SMR2........................................ 145
U2SMR3........................................ 145
U2SMR4........................................ 146
U2TB ............................................. 141
UCON............................................ 144
UDF ............................................... 106
W
WDC................................................ 91
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REVISION HISTORY M16C/6N4 Group Hardware Manual
Rev. Date Description
Page Summary
C-1
1.00
May 30, 2003
– First edition issued
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RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
HARDWARE MANUAL
M16C/6N4 Group Rev.1.00
Editioned by
Committee of editing of RENESAS Semiconductor Hardware Manual
This book, or parts thereof, may not be reproduced in any form without permission
of Renesas Technology Corporation.
Copyright © 2003. Renesas Technology Corporation, All rights reserved.
M16C/6N4 Group
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY / M16C/60 SERIES
M16C/6N4 Group
16
Rev. 1.00
Revision date: May 30, 2003
Usage Notes Reference Book
www.renesas.com
Before using this material, please visit our website to confirm that this is the most
current document available.
REJ09B0010-0100Z
For the most current Usage Notes Reference Book, please visit our website.
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Preface
The “Usage Notes Reference Book” is a
compilation of usage notes from the
Hardware Manual as well as technical
news related to this product.
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A-1
Table of Contents
1. Usage Precaution
1.1 Precautions for External Bus ....................................................................................................................... 1
1.2 Precautions for PLL Frequency Synthesizer ................................................................................................ 2
1.3 Precautions for Power Control ..................................................................................................................... 3
1.4 Precautions for Protection ............................................................................................................................ 4
1.5 Precautions for Interrupts ............................................................................................................................. 5
1.5.1 Reading Address 0000016 .................................................................................................................................................................................................. 5
1.5.2 SP Setting ............................................................................................................................................ 5
_______
1.5.3 NMI Interrupt ........................................................................................................................................ 5
1.5.4 Changing the Interrupt Generate Factor .............................................................................................. 6
_____
1.5.5 INT Interrupt ......................................................................................................................................... 6
1.5.6 Rewrite the Interrupt Control Register ................................................................................................. 7
1.5.7 Watchdog Timer Interrupt .................................................................................................................... 7
1.6 Precautions for DMAC ................................................................................................................................. 8
1.6.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) ................................................................................ 8
1.7 Precautions for Timers ................................................................................................................................. 9
1.7.1 Timer A ................................................................................................................................................. 9
1.7.2 Timer B ............................................................................................................................................... 12
1.8 Precautions for Serial I/O (Clock Synchronous Serial I/O Mode) ..............................................................14
1.8.1 Transmission/reception ...................................................................................................................... 14
1.8.2 Transmission ...................................................................................................................................... 14
1.8.3 Reception ........................................................................................................................................... 14
1.9 Precaution for Serial I/O (Special Modes) .................................................................................................. 15
1.9.1 Special Mode 2 ................................................................................................................................. 15
1.9.2 Special Mode 4 (SIM Mode) ............................................................................................................. 15
1.10 Precautions for A-D Converter ................................................................................................................. 16
1.11 Precautions for CAN Module .................................................................................................................... 18
1.11.1 Reading CiSTR Register (i = 0, 1).................................................................................................... 18
1.11.2 CAN Transceiver in Boot Mode ........................................................................................................ 20
1.12 Precautions for Programmable I/O Ports ................................................................................................. 21
1.13
Precautions for Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers ...
22
1.14 Precautions for Flash Memory Version .................................................................................................... 23
1.14.1 Precautions for Functions to Prevent Flash Memory from Rewriting ............................................... 23
1.14.2 Precautions for Stop Mode .............................................................................................................. 23
1.14.3 Precautions for Wait Mode ............................................................................................................... 23
1.14.4 Precautions for Low Power Dissipation Mode and Ring Oscillator Low Power Dissipation Mode... 23
1.14.5 Writing command and data .............................................................................................................. 23
1.14.6 Precautions for Program Command ................................................................................................ 23
1.14.7 Precautions for Lock Bit Program Command................................................................................... 23
1.14.8 Operation speed .............................................................................................................................. 24
1.14.9 Instructions to prevent from using .................................................................................................... 24
1.14.10 Interrupts ........................................................................................................................................ 24
1.14.11 How to access ................................................................................................................................ 24
1.14.12 Writing in user ROM area .............................................................................................................. 24
1.14.13 DMA transfer .................................................................................................................................. 24
Blank page
Rev.1.00 2003.05.30 page 1
M16C/6N4 Group 1.1 Precautions for External Bus
Under development
This document is under development and its contents are subject to change.
1. Usage Precaution
1.1 Precautions for External Bus
1. The external ROM version can operate only in the microprocessor mode, connect the CNVSS pin to VCC.
2. When resetting CNVSS pin with "H" input, contents of internal ROM cannot be read out.
Rev.1.00 2003.05.30 page 2
M16C/6N4 Group 1.2 Precautions for PLL Frequency Synthesizer
Under development
This document is under development and its contents are subject to change.
1.2 Precautions for PLL Frequency Synthesizer
Make the supply voltage stable to use the PLL frequency synthesizer.
For ripple with the supply voltage 5 V, keep below 10 kHz as frequency, below 0.5 V (peak to peak) as
voltage fluctuation band and below 1 V/mS as voltage fluctuation rate.
Rev.1.00 2003.05.30 page 3
M16C/6N4 Group 1.3 Precautions for Power Control
Under development
This document is under development and its contents are subject to change.
1.3 Precautions for Power Control
1.
____________
When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is
stabilized.
2. Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit of
the CM1 register to “1” (all clock stopped). When shifting to wait mode or stop mode, an instruction
queue reads ahead to the next instruction to halt a program by an WAIT instruction and an instruction
to set the CM10 bit to “1”. The next instruction may be executed before entering wait mode or stop
mode, depending on a combination of instruction and an execution timing.
3. Wait until the td(M-L) elapses or main clock oscillation stabilization time, whichever is longer, before
switching the clock source for CPU clock to the main clock.
Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to
the sub clock.
4. Suggestions to reduce power consumption
(a) Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode.
A current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When
entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
(b) A-D converter
When A-D conversion is not performed, set the VCUT bit of the ADCON1 register to “0” (VREF not
connection). When A-D conversion is performed, start the A-D conversion at least 1 µs or longer after
setting the VCUT bit to “1” (VREF connection).
(c) D-A converter
When not performing D-A conversion, set the DAiE bit (i = 0, 1) of the DACON register to “0” (input
inhibited) and DAi register to “0016”.
(d) Stopping peripheral functions
Use the CM02 bit of the CM0 register to stop the unnecessary peripheral functions during wait
mode. However, because the peripheral function clock (fC32) generated from the sub clock does not
stop, this measure is not conducive to reducing the power consumption of the chip. If low speed mode
or low power dissipation mode is to be changed to wait mode, set the CM02 bit to “0” (do not peripheral
function clock stopped when in wait mode), before changing wait mode.
(e) Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
(f) External clock
When using an external clock input for the CPU clock, set the CM05 bit of the CM0 register to “1”
(stop). Setting the CM05 bit to “1” disables the XOUT pin from functioning, which helps to reduce the
amount of current drawn in the chip. (When using an external clock input, note that the clock remains
fed into the chip regardless of how the CM05 bit is set.)
Rev.1.00 2003.05.30 page 4
M16C/6N4 Group 1.4 Precautions for Protection
Under development
This document is under development and its contents are subject to change.
1.4 Precautions for Protection
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be set to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or no DMA transfers will occur between the instruction
in which the PRC2 bit is set to “1” and the next instruction.
Rev.1.00 2003.05.30 page 5
M16C/6N4 Group 1.5 Precautions for Interrupts
Under development
This document is under development and its contents are subject to change.
1.5 Precautions for Interrupts
1.5.1 Reading Address 0000016
Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the
CPU reads interrupt information (interrupt number and interrupt request priority level) from the
address 0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is set to “0”.
If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is set to “0”. This causes a problem that the interrupt is canceled, or an
unexpected interrupt is generated.
1.5.2 SP Setting
Set any value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is set to “000016”
after reset. Therefore, if an interrupt is accepted before setting any value in the SP (USP, ISP), the
program may go out of control.
_______
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the
_______
first and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
_______
1.5.3 NMI Interrupt
1.
_______ _______
The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC via a
resistor (pull-up).
2.
_______
The input level of the NMI pin can be read by accessing the P8_5 bit of the P8 register. Note that the
_______
P8_5 bit can only be read when determining the pin level in NMI interrupt routine.
3.
_______
Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on
_______
the NMI pin is low the CM10 bit of the CM1 register is fixed to “0”.
4.
_______ _______
Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin
goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the
chip does not drop. In this case, normal condition is restored by an interrupt generated thereafter.
5.
_______
The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles
+ 300 ns or more.
Rev.1.00 2003.05.30 page 6
M16C/6N4 Group 1.5 Precautions for Interrupts
Under development
This document is under development and its contents are subject to change.
1.5.4 Changing the Interrupt Generate Factor
If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate
factor for an interrupt that needs to be used, be sure to set the IR bit for that interrupt to “0” (interrupt
not requested).
“Changing the interrupt generate factor” referred to here means any act of changing the source, polar-
ity or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change
of any peripheral function involves changing the generate factor, polarity or timing of an interrupt, be
sure to set the IR bit for that interrupt to “0” (interrupt not requested) after making such changes. Refer
to the description of each peripheral function for details about the interrupts from peripheral functions.
Figure 1.5.1 shows the procedure for changing the interrupt generate factor.
Figure 1.5.1 Procedure for Changing Interrupt Generate Factor
_____
1.5.5 INT Interrupt
1. Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal
_______ _______
input to pins INT0 through INT5 regardless of the CPU operation clock.
2. If the POL bit in the INT0IC to INT5IC registers or the IFSR17 to IFSR10 bits in the IFSR1 register
are changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to “0”
(interrupt not requested) after changing any of those register bits.
Changing the interrupt source
Disable interrupts (Notes 2, 3)
Use the MOV instruction to set the IR bit to "0"
(interrupt not requested) (Note 3)
Change the interrupt generate factor
(including a mode change of peripheral function)
Enable interrupts (Notes 2, 3)
End of change
R bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
be changed
Note 1: The above settings must be executed individually. Do not execute two or more settings
simultaneously (using one instruction).
Note 2: Use the I flag for the INTi interrupt (i = 0 to 5).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the
peripheral function that is the source of the interrupt in order not to generate an interrupt
request before changing the interrupt generate factor. In this case, if the maskable
interrupts can all be disabled without causing a problem, use the I flag. Otherwise, use
the corresponding
ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is to be changed.
Note 3: Refer to "Rewrite the Interrupt Control Register" for details about the instructions to use
and the notes to be taken for instruction execution.
Rev.1.00 2003.05.30 page 7
M16C/6N4 Group 1.5 Precautions for Interrupts
Under development
This document is under development and its contents are subject to change.
1.5.6 Rewrite the Interrupt Control Register
(1) The interrupt control register for any interrupt should be modified in places where no requests for
that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with
the instruction to be used.
Changing any bit other than the IR bit
If while executing an instruction, a request for an interrupt controlled by the register being modified
occurs, the IR bit in the register may not be set to “1” (interrupt requested), with the result that the
interrupt request is ignored. If such a situation presents a problem, use the instructions shown
below to modify the register.
Usable instructions: AND, OR, BCLR, BSET
Changing the IR bit
Depending on the instruction used, the IR bit may not always be set to “0” (interrupt not requested).
Therefore, be sure to use the MOV instruction to set the IR bit to “0”.
(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below
as you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample
program fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before
the interrupt control register is rewrited, owing to the effects of the internal bus and the instruction
queue buffer.
Example 1: Using the NOP instruction to keep the program waiting until the interrupt control register is modified
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00H, 0055H ; Set the TA0IC register to “0016”.
NOP ;
NOP
FSET I ; Enable interrupts.
The number of NOP instruction is as follows.
• PM20 of the PM2 register = 1 (1 wait) : 2
• PM20 = 0 (2 waits) : 3
• When using HOLD function : 4.
Example 2: Using the dummy read to keep the FSET instruction waiting
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h,0055h ; Set the TA0IC register to “0016”.
MOV.W MEM,R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3: Using the POPC instruction to changing the I flag
INT_SWITCH3:
PUSHC FLG
FCLR I ;Disable interrupts.
AND.B #00h,0055h ;Set the TA0IC register to “0016 ”.
POPC FLG ;Enable interrupts.
1.5.7 Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt occurs.
Rev.1.00 2003.05.30 page 8
M16C/6N4 Group 1.6 Precautions for DMAC
Under development
This document is under development and its contents are subject to change.
1.6 Precautions for DMAC
1.6.1 Write to DMAE Bit in DMiCON Register (i = 0, 1)
When both of the conditions below are met, follow the steps below.
Conditions
• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
• A DMA request may occur simultaneously when the DMAE bit is being written.
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously (Note 1) .
Step 2: Make sure that the DMAi is in an initial state (Note 2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
Note 1: The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it
is set to “0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0,
“1” should be written to the DMAS bit when “1” is written to the DMAE bit. In this way the state
of the DMAS bit immediately before being written can be maintained.
Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be
written to the DMAS bit in order to maintain a DMA request which is generated during execution.
Note 2: Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is
equal to a value which was written to the TCRi register before DMA transfer start, the DMAi is in an
initial state. (If a DMA request occurs after writing to the DMAE bit, the value written to the
TCRi register is “1”.) If the read value is a value in the middle of transfer, the DMAi is not in an
initial state.
Rev.1.00 2003.05.30 page 9
M16C/6N4 Group 1.7 Precautions for Timers
Under development
This document is under development and its contents are subject to change.
1.7 Precautions for Timers
1.7.1 Timer A
1.7.1.1 Timer A (Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the
TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to
“1” (count starts).
Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, if the counter is read at the same time it is reloaded, the value “FFFF16” is read.
Also, if the counter is read before it starts counting after a value is set in the TAi register while not
counting, the set value is read.
3.
______
If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible
______
cutoff by input on NMI pin enabled) of the TB2SC register, the TA1OUT, TA2OUT and TA4OUT pins go
to a high-impedance state.
1.7.1.2 Timer A (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the
TAiMR (i = 0 to 4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL
and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1”
(count starts).
Always make sure the TAiMR register, the UDF register, the ONSF register TAZIE, TA0TGL and
TA0TGH bits and the TRGSR register are modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, “FFFF16” can be read in underflow, while reloading, and “000016” in overflow.
When setting TAi register to a value during a counter stop, the setting value can be read before a
counter starts counting. Also, if the counter is read before it starts counting after a value is set in
the TAi register while not counting, the set value is read.
______
3. If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible
______
cutoff by input on NMI pin enabled) of the TB2SC register, the TA1OUT, TA2OUT and TA4OUT pins go
to a high-impedance state.
Rev.1.00 2003.05.30 page 10
M16C/6N4 Group 1.7 Precautions for Timers
Under development
This document is under development and its contents are subject to change.
1.7.1.3 Timer A (One-shot Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the
TAiMR (i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after
reset or not.
2. When setting the TAiS bit of the TABSR register to “0” (count stop), the followings occur:
• A counter stops counting and a content of reload register is reloaded.
• TAiOUT pin outputs “L”.
• After one cycle of the CPU clock, the IR bit of the TAiIC register is set to “1” (interrupt request).
3. Output in one-shot timer mode synchronizes with a count source internally generated. When an
external trigger has been selected, one-cycle delay of a count source as maximum occurs
between a trigger input to TAiIN pin and output in one-shot timer mode.
4. The IR bit is set to “1” when timer operation mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
•Change an operation mode from timer mode to one-shot timer mode.
• Change an operation mode from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have
been made.
5. When a trigger occurs, while counting, a counter reloads the reload register to continue counting
after generating a re-trigger and counting down once. To generate a trigger while counting, generate
a second trigger between occurring the previous trigger and operating longer than one cycle of a
timer count source.
6.
______
If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible
______
cutoff by input on NMI pin enabled) of the TB2SC register, the TA1OUT, TA2OUT and TA4OUT pins go
to a high-impedance state.
Rev.1.00 2003.05.30 page 11
M16C/6N4 Group 1.7 Precautions for Timers
Under development
This document is under development and its contents are subject to change.
1.7.1.4 Timer A (Pulse Width Modulation Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the
TAiMR (i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after
reset or not.
2. The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
• Select the PWM mode after reset.
•Change an operation mode from timer mode to PWM mode.
•Change an operation mode from event counter mode to PWM mode.
To use the timer Ai interrupt (the IR bit), set the IR bit to “0” by program after the above listed
changes have been made.
3. When setting TAiS bit to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remain unchanged.
4.
______
If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible
______
cutoff by input on NMI pin enabled) of the TB2SC register, the TA1OUT, TA2OUT and TA4OUT pins go
to a high-impedance state.
Rev.1.00 2003.05.30 page 12
M16C/6N4 Group 1.7 Precautions for Timers
Under development
This document is under development and its contents are subject to change.
1.7.2 Timer B
1.7.2.1 Timer B (Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the
TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR
register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
The TB0S to TB2S bits are the bits 5 to 7 of the TABSR register, the TB3S to TB5S bits are the bits
5 to 7 of the TBSR register.
2. A value of a counter, while counting, can be read in the TBi register at any time. “FFFF16” is read
while reloading. Setting value is read between setting values in TBi register at count stop and
starting a counter.
1.7.2.2 Timer B (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the
TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR
register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
The TB0S to TB2S bits are the bits 5 to 7 of the TABSR register, the TB3S to TB5S bits are the bits
5 to 7 of the TBSR register.
2. A value of a counter, while counting, can be read in the TBi register at any time. “FFFF16” is read
while reloading. Setting value is read between setting values in TBi register at count stop and
starting a counter.
Rev.1.00 2003.05.30 page 13
M16C/6N4 Group 1.7 Precautions for Timers
Under development
This document is under development and its contents are subject to change.
1.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode)
1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5)
register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register
while the TBiS bit = “1” (count starts), be sure to write the same value as previously written to the
TM0D0, TM0D1, MR0, MR1, TCK0 and TCK1 bits and a 0 to the MR2 bit.
2. The IR bit of TBiIC register (i = 0 to 5) goes to “1” (interrupt request), when an effective edge of a
measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be deter-
mined by use of the MR3 bit of TBiMR register within the interrupt routine.
3. If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse
input and a timer overflow occur at the same time, use another timer to count the number of times
timer B has overflowed.
4. To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and
counting the next count source after setting the MR3 bit to “1” (overflow).
5. Use the IR bit of the TBiIC register to detect only overflows. Use the MR3 bit only to determine the
interrupt factor within the interrupt routine.
6. When a count is started and the first effective edge is input, an indeterminate value is transferred
to the reload register. At this time, timer Bi interrupt request is not generated.
7. A value of the counter is indeterminate at the beginning of a count. The MR3 bit may be set to “1”
and timer Bi interrupt request may be generated between a count start and an effective edge input.
8. For pulse width measurement, pulse widths are successively measured. Use program to check
whether the measurement result is an “H” level width or an “L” level width.
Rev.1.00 2003.05.30 page 14
M16C/6N4 Group 1.8 Precautions for Serial I/O (Clock Synchronous Serial I/O Mode)
Under development
This document is under development and its contents are subject to change.
1.8 Precautions for Serial I/O (Clock Synchronous Serial I/O Mode)
1.8.1 Transmission/reception
1.
_______
With an external clock selected, and choosing the RTS function, the output level of the RTSi pin
goes to “L” when the data-receivable status becomes ready, which informs the transmission side
that the reception has become ready. The output level of the RTSi pin goes to “H” when reception
________
starts. So if the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can
_______
transmission and reception data with consistent timing. With the internal clock, the RTS function
has no effect.
2.
_______
If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible
_______ ________
cutoff by input on NMI pin enabled) of the TB2SC register, the RTS2 and CLK2 pins go to a high-
impedance state.
1.8.2 Transmission
When an external clock is selected, the conditions must be met while if the CKPOL bit of the UiC0
register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of
the transfer clock), the external clock is in the high state; if the CKPOL bit of the UiC0 register = 1
(transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer
clock), the external clock is in the low state.
• The TE bit of the UiC1 register = 1 (transmission enabled)
• The TI bit of the UiC1 register = 0 (data present in UiTB register)
_______ _______
• If CTS function is selected, input on the CTSi pin = L
1.8.3 Reception
1. In operating the clock synchronous serial I/O, operating a transmitter generates a shift clock.
Fix settings for transmission even when using the device only for reception. Dummy data is output
to the outside from the TxDi (i = 0 to 2) pin when receiving data.
2. When an internal clock is selected, set the TE bit of the UiC1 register to “1” (transmission enabled)
and write dummy data to the UiTB register, and the shift clock will thereby be generated. When an
external clock is selected, set the TE bit to “1” and write dummy data to the UiTB register, and the
shift clock will be generated when the external clock is fed to the CLKi input pin.
3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi
receive register while the RI bit of the UiC1 register = 1 (data present in the UiRB register), an
overrun error occurs and the OER bit of the UiRB register is set to “1” (overrun error occurred). In
this case, because the content of the UiRB register is indeterminate, a corrective measure must be
taken by programs on the transmit and receive sides so that the valid data before the overrun error
occurred will be retransmitted. Note that when an overrun error occurred, the IR bit of the SiRIC
register does not change state.
4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every
time reception is made.
5. When an external clock is selected, the conditions must be met while if the CKPOL bit = 0, the
external clock is in the high state; if the CKPOL bit = 1, the external clock is in the low state.
• The RE bit of the UiC1 register = 1 (reception enabled)
• The TE bit of the UiC1 register = 1 (transmission enabled)
• The TI bit of the UiC1 register = 0 (data present in the UiTB register)
Rev.1.00 2003.05.30 page 15
M16C/6N4 Group 1.9 Precautions for Serial I/O (Special Modes)
Under development
This document is under development and its contents are subject to change.
1.9 Precaution for Serial I/O (Special Modes)
1.9.1 Special Mode 2
_______
If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = 1 (three-phase
_______
output forcible cutoff by input on NMI pin enabled), the RTS2 and CLK2 pins go to a high-impedance state.
1.9.2 Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmission
complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode, be
sure to set the IR bit to “0” (no interrupt request) after setting these bits.
Rev.1.00 2003.05.30 page 16
M16C/6N4 Group 1.10 Precautions for A-D Converter
Under development
This document is under development and its contents are subject to change.
1.10 Precautions for A-D Converter
1. Set the ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A-D conversion is stopped
(before a trigger occurs).
2. When the VCUT bit of the ADCON1 register is changed from “0” (VREF not connected) to “1” (VREF
connected), start A-D conversion after passing 1 µs or longer.
3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi (i = 0 to 7), AN0i, and AN2i) each and the
AVSS pin. Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 1.10.1 is an example
connection of each pin.
4. Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input
mode). Also, if the TGR bit of the ADCON0 register = 1 (external trigger), make sure the port direction
__________
bit for the ADTRG pin is set to “0” (input mode).
5. When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key
input interrupt request is generated when the A-D input voltage goes low.)
6. The φAD frequency must be 10 MHz or less. Without sample-and-hold function, limit the φAD frequency
to 250 kHz or more. With the sample and hold function, limit the φAD frequency to 1 MHz or more.
7. When changing an A-D operation mode, select analog input pin again in the CH2 to CH0 bits of the
ADCON0 register and the SCAN1 to SCAN0 bits of the ADCON1 register.
Figure 1.10.1 Use of capacitors to reduce noise
VCC
VSS
AVCC
AVSS
VREF
ANi
C4
C1 C2
C3
Microcomputer
ANi: ANi, AN0i, and AN2i (i =0 to 7)
Note 1: C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF, C4 ≥ 0.1 µF (reference).
Note 2: Use thick and shortest possible wiring to connect capacitors.
Rev.1.00 2003.05.30 page 17
M16C/6N4 Group 1.10 Precautions for A-D Converter
Under development
This document is under development and its contents are subject to change.
8. If the CPU reads the ADi register at the same time the conversion result is stored in the ADi register
after completion of A-D conversion, an incorrect value may be stored in the ADi register. This problem
occurs when a divide-by-n clock derived from the main clock or a sub clock is selected for CPU clock.
•When operating in one-shot or single-sweep mode
Check to see that A-D conversion is completed before reading the target ADi register. (Check the IR
bit of the ADIC register to see if A-D conversion is completed.)
•When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
9. If A-D conversion is forcibly terminated while in progress by setting the ADST bit of the ADCON0
register to “0” (A-D conversion halted), the conversion result of the A-D converter is indeterminate. The
contents of ADi registers irrelevant to A-D conversion may also become indeterminate. If while A-D
conversion is underway the ADST bit is set to “0” in a program, ignore the values of all ADi registers.
Rev.1.00 2003.05.30 page 18
M16C/6N4 Group 1.11 Precautions for CAN Module
Under development
This document is under development and its contents are subject to change.
1.11 Precautions for CAN Module
1.11.1 Reading CiSTR Register (i = 0, 1)
The CAN module on the M16C/6N4 group updates the status of the CiSTR register in a certain period.
When the CPU and the CAN module access to the CiSTR register at the same time, the CPU has the
access priority; the access from the CAN module is disabled. Consequently, when the updating period
of the CAN module matches the access period from the CPU, the status of the CAN module cannot be
updated. (Refer to Figure 1.11.1.)
Accordingly, be careful about the following points so that the access period from the CPU should not
match the updating period of the CAN module:
(1) There should be a wait time of 3fCAN or longer (refer to Table 1.11.1) before the CPU reads the
CiSTR register. (Refer to Figure 1.11.2.)
(2) When the CPU polls the CiSTR register, the polling period must be 3fCAN or longer. (Refer to Figure
1.11.3.)
Table 1.11.1 CAN Module Status Updating Period
3fCAN period = 3 ✕ XIN (Original oscillation period) ✕ Division value of the CAN clock (CCLK)
(Example 1) Condition XIN 16 MHz CCLK: Divided by 1 3fCAN period = 3 ✕ 62.5 ns ✕ 1 = 187.5 ns
(Example 2) Condition XIN 16 MHz CCLK: Divided by 2 3fCAN period = 3 ✕ 62.5 ns ✕ 2 = 375 ns
(Example 3) Condition XIN 16 MHz CCLK: Divided by 4 3fCAN period = 3 ✕ 62.5 ns ✕ 4 = 750 ns
(Example 4) Condition XIN 16 MHz CCLK: Divided by 8 3fCAN period = 3 ✕ 62.5 ns ✕ 8 = 1.5 µs
(Example 5) Condition XIN 16 MHz CCLK: Divided by 16 3fCAN period = 3 ✕ 62.5 ns ✕ 16 = 3 µs
Rev.1.00 2003.05.30 page 19
M16C/6N4 Group 1.11 Precautions for CAN Module
Under development
This document is under development and its contents are subject to change.
Figure 1.11.1 When Updating Period of CAN Module Matches Access Period from CPU
f
CAN
✕✕✕ ✕✕
CPU read signal
CPU reset signal
Updating period of
CAN module
CiSTR register
b8: State_Reset bit
i = 0, 1
0: CAN operation
mode
1: CAN reset/initial-
ization mode
✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read
period, it does not enter reset mode, for the CPU read has the higher priority.
Figure 1.11.2 With a Wait Time of 3fCAN Before CPU Read
Figure 1.11.3 When Polling Period of CPU is 3fCAN or Longer
: Updated without fail in period of 3f
CAN
CPU read signal
CPU reset signal
Updating period of
the CAN module
CiSTR register
b8: Reset state flag
Wait time
i = 0, 1
0: CAN operation
mode
1: CAN reset/initial-
ization mode
: Updated without fail in period of 4f
CAN
CPU read signal
CPU reset signal
Updating period of
the CAN module
CiSTR register
b8: State_Reset bit
✕
4fCAN
i = 0, 1
0: CAN operation
mode
1: CAN reset/initial-
ization mode
✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read
period, it does not enter reset mode, for the CPU read has the higher priority.
Rev.1.00 2003.05.30 page 20
M16C/6N4 Group 1.11 Precautions for CAN Module
Under development
This document is under development and its contents are subject to change.
1.11.2 CAN Transceiver in Boot Mode
When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver
should be set to “high-speed mode” or “normal operation mode”. If the operation mode is controlled by
the microcomputer, CAN transceiver must be set the operation mode to “high-speed mode” or “normal
operation mode” before programming the flash memory by changing the switch etc. Table 1.11.2 and
1.11.3 show pin connections of CAN transceiver.
Table 1.11.2 Pin Connections of CAN Transceiver (In case of PCA82C250: Philips product)
Table 1.11.3 Pin Connections of CAN Transceiver (In case of PCA82C252: Philips product)
Standby mode High-speed mode
Rs pin
(Note 1)
“H” “L”
CAN communication
impossible possible
Connection
i = 0, 1
Note 1: The pin which controls the operation mode of CAN transceiver.
Note 2: Connect to enabled port to control CAN transceiver.
Table 1.11.3 Pin Connections of CAN Transceiver (In case of PCA82C252: Philips product)
M16C/6N4 PCA82C250
CTx
i
CRx
i
Port (Note 2)
TxD
RxD
Rs
CANH
CANL
Switch OFF
M16C/6N4 PCA82C250
CTx
i
CRx
i
TxD
RxD
Rs
CANH
CANL
Port (Note 2)
Switch ON
Sleep mode Normal operation mode
_______
STB pin (Note 1)
“L”“H”
EN pin
(Note 1)
“L”“H”
CAN communication
impossible possible
Connection
i = 0, 1
Note 1: The pin which controls the operation mode of CAN transceiver.
Note 2: Connect to enabled port to control CAN transceiver.
M16C/6N4 PCA82C252
CTxi
CRxi
TxD
RxD
STB
CANH
CANL
EN
Switch OFF
Por
t (Note 2)
Por
t (Note 2)
M16C/6N4 PCA82C252
CTx
i
CRx
i
TxD
RxD
STB
CANH
CANL
EN
Por
t (Note 2)
Por
t (Note 2)
Switch ON
Rev.1.00 2003.05.30 page 21
M16C/6N4 Group 1.12 Precautions for Programmable I/O Ports
Under development
This document is under development and its contents are subject to change.
1.12 Precautions for Programmable I/O Ports
1.
_______
If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
_______
output forcible cutoff by input on NMI pin enabled), the P72 to P75, P80 and P81 pins go to a high-
impedance state.
2. Setting the SM32 bit in the S3C register to “1” causes the P92 pin to go to a high-impedance state.
3. The input threshold voltage of pins differs between programmable input/output ports and peripheral
functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the
input level at this pin is outside the range of recommended operating conditions VIH and VIL (neither
“high” nor “low”), the input level may be determined differently depending on which side—the programmable
input/output port or the peripheral function—is currently selected.
Rev.1.00 2003.05.30 page 22
M16C/6N4 Group
1.13 Precautions for Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers
Under development
This document is under development and its contents are subject to change.
1.13 Precautions for Electrical Characteristic Differences Between Mask ROM
and Flash Memory Version Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin,
noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout
pattern, etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation
tests conducted in the flash memory version.
Rev.1.00 2003.05.30 page 23
M16C/6N4 Group 1.14 Precautions for Flash Memory Version
Under development
This document is under development and its contents are subject to change.
1.14 Precautions for Flash Memory Version
1.14.1 Precautions for Functions to Prevent Flash Memory from Rewriting
ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716,
and 0FFFFB16. If wrong data are written to theses addresses, the flash memory cannot be read or
written in standard serial I/O mode and CAN I/O mode.
The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash
memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses
(H) of fixed vectors.
1.14.2 Precautions for Stop Mode
When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the
CM10 bit to “1” (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop
mode)
Example program BSET 0, CM1 ; Stop mode
JMP.B L1
L1:
Program after returning from stop mode
1.14.3 Precautions for Wait Mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing
the WAIT instruction.
1.14.4 Precautions for Low Power Dissipation Mode and Ring Oscillator Low Power Dissipation Mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
1.14.5 Writing command and data
Write the command code and data at even addresses.
1.14.6 Precautions for Program Command
Write “xx4016” in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in
the first bus cycle is the same even address as the write address specified in the second bus cycle.
1.14.7 Precautions for Lock Bit Program Command
Write “xx7716” in the first bus cycle and write “xxD016” to the uppermost address of a block (even
address, however) in the second bus cycle, and the lock bit for the specified block is set to “0”.
Make sure the address value specified in the first bus cycle is the same uppermost block address that
is specified in the second bus cycle.
Rev.1.00 2003.05.30 page 24
M16C/6N4 Group 1.14 Precautions for Flash Memory Version
Under development
This document is under development and its contents are subject to change.
1.14.8 Operation speed
Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for BCLK using the
CM06 bit of the CM0 register and the CM17 to CM16 bits of the CM1 register. Also, set the PM17 bit
of the PM1 register to “1” (with wait state).
1.14.9 Instructions to prevent from using
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
1.14.10 Interrupts
EW0 Mode
•Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
•
_______
The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register
are initialized when one of those interrupts occurs. The jump addresses for those interrupt service
routines should be set in the fixed vector table._______
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
•The address match interrupt cannot be used because the flash memory’s internal data is
referenced.
EW1 Mode
•Make sure that any interrupt which has a vector in the variable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
•Avoid using watchdog timer interrupts.
•
_______
The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when
this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed
vector table. _______
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be
executed again after exiting the interrupt service routine.
1.14.11 How to access
To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary
to ensure that no interrupts or no DMA transfers will occur before writing “1” after writing “0”. Also only
_______
when NMI pin is “H” level.
1.14.12 Writing in user ROM area
EW0 Mode
•If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and,
consequently, the flash memory becomes unable to be rewritten thereafter. In this case, standard
serial I/O, parallel I/O or CAN I/O mode should be used.
EW1 Mode
•Avoid rewriting any block in which the rewrite control program is stored.
1.14.13 DMA transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR00 bit of the FMR0 register
= 0 (during the auto program or auto erase period).
REVISION HISTORY M16C/6N4 Group Usage Notes
Rev. Date Description
Page Summary
B-1
1.00
May 30, 2003
– First edition issued
Blank page
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
USAGE NOTES REFERENCE BOOK
M16C/6N4 Group Rev.1.00
Editioned by
Committee of editing of RENESAS Semiconductor Usage Notes Reference
Book
This book, or parts thereof, may not be reproduced in any form without permission
of Renesas Technology Corporation.
Copyright © 2003. Renesas Technology Corporation, All rights reserved.
M16C/6N4 Group
Usage Notes Reference Book
2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan
