MF1045-03 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C60N03 Technical Manual S1C60N03 Technical Hardware NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2001 All rights reserved. The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number Devices S1 C 60N01 F 0A01 00 Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor) Development tools C 60R08 S5U1 D1 1 00 Packing specification Version (1: Version 1 2) Tool type (D1: Development Tool 1) Corresponding model number (60R08: for S1C60R08) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products) 1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.) 2: Actual versions are not written in the manuals. Comparison table between new and previous number S1C60 Family processors Previous No. E0C6001 E0C6002 E0C6003 E0C6004 E0C6005 E0C6006 E0C6007 E0C6008 E0C6009 E0C6011 E0C6013 E0C6014 E0C60R08 New No. S1C60N01 S1C60N02 S1C60N03 S1C60N04 S1C60N05 S1C60N06 S1C60N07 S1C60N08 S1C60N09 S1C60N11 S1C60N13 S1C60140 S1C60R08 S1C62 Family processors Previous No. E0C621A E0C6215 E0C621C E0C6S27 E0C6S37 E0C623A E0C623E E0C6S32 E0C6233 E0C6235 E0C623B E0C6244 E0C624A E0C6S46 New No. S1C621A0 S1C62150 S1C621C0 S1C6S2N7 S1C6S3N7 S1C6N3A0 S1C6N3E0 S1C6S3N2 S1C62N33 S1C62N35 S1C6N3B0 S1C62440 S1C624A0 S1C6S460 Previous No. E0C6247 E0C6248 E0C6S48 E0C624C E0C6251 E0C6256 E0C6292 E0C6262 E0C6266 E0C6274 E0C6281 E0C6282 E0C62M2 E0C62T3 New No. S1C62470 S1C62480 S1C6S480 S1C624C0 S1C62N51 S1C62560 S1C62920 S1C62N62 S1C62660 S1C62740 S1C62N81 S1C62N82 S1C62M20 S1C62T30 Comparison table between new and previous number of development tools Development tools for the S1C60/62 Family Previous No. ASM62 DEV6001 DEV6002 DEV6003 DEV6004 DEV6005 DEV6006 DEV6007 DEV6008 DEV6009 DEV6011 DEV60R08 DEV621A DEV621C DEV623B DEV6244 DEV624A DEV624C DEV6248 DEV6247 New No. S5U1C62000A S5U1C60N01D S5U1C60N02D S5U1C60N03D S5U1C60N04D S5U1C60N05D S5U1C60N06D S5U1C60N07D S5U1C60N08D S5U1C60N09D S5U1C60N11D S5U1C60R08D S5U1C621A0D S5U1C621C0D S5U1C623B0D S5U1C62440D S5U1C624A0D S5U1C624C0D S5U1C62480D S5U1C62470D Previous No. DEV6262 DEV6266 DEV6274 DEV6292 DEV62M2 DEV6233 DEV6235 DEV6251 DEV6256 DEV6281 DEV6282 DEV6S27 DEV6S32 DEV6S37 EVA6008 EVA6011 EVA621AR EVA621C EVA6237 EVA623A New No. S5U1C62620D S5U1C62660D S5U1C62740D S5U1C62920D S5U1C62M20D S5U1C62N33D S5U1C62N35D S5U1C62N51D S5U1C62560D S5U1C62N81D S5U1C62N82D S5U1C6S2N7D S5U1C6S3N2D S5U1C6S3N7D S5U1C60N08E S5U1C60N11E S5U1C621A0E2 S5U1C621C0E S5U1C62N37E S5U1C623A0E Previous No. EVA623B EVA623E EVA6247 EVA6248 EVA6251R EVA6256 EVA6262 EVA6266 EVA6274 EVA6281 EVA6282 EVA62M1 EVA62T3 EVA6S27 EVA6S32R ICE62R KIT6003 KIT6004 KIT6007 New No. S5U1C623B0E S5U1C623E0E S5U1C62470E S5U1C62480E S5U1C62N51E1 S5U1C62N56E S5U1C62620E S5U1C62660E S5U1C62740E S5U1C62N81E S5U1C62N82E S5U1C62M10E S5U1C62T30E S5U1C6S2N7E S5U1C6S3N2E2 S5U1C62000H S5U1C60N03K S5U1C60N04K S5U1C60N07K CONTENTS CONTENTS CHAPTER 1 INTRODUCTION ____________________________________________ 1 1.1 1.2 1.3 Features ......................................................................................................... 1 Block Diagram .............................................................................................. 2 Pad Layout .................................................................................................... 3 1.3.1 Pad layout diagram .................................................................................... 3 1.3.2 Pad coordinates .......................................................................................... 3 1.4 CHAPTER Pad Description ............................................................................................ 3 2 POWER SUPPLY AND INITIAL RESET _____________________________ 4 2.1 2.2 Power Supply ................................................................................................ 4 Initial Reset ................................................................................................... 6 2.2.1 Oscillation detection circuit ....................................................................... 6 2.2.2 Reset terminal (RESET) ............................................................................. 6 2.2.3 Simultaneous high input to input ports (K00-K03) .................................. 6 2.2.4 Internal register following initialization ................................................... 7 2.3 CHAPTER 3 CPU, ROM, RAM________________________________________ 8 3.1 3.2 3.3 CHAPTER Test Terminal (TEST) .................................................................................... 7 CPU ............................................................................................................... 8 ROM .............................................................................................................. 8 RAM .............................................................................................................. 8 4 PERIPHERAL CIRCUITS AND OPERATION __________________________ 9 4.1 4.2 Memory Map ................................................................................................. 9 Oscillation Circuit ....................................................................................... 11 4.2.1 Crystal oscillation circuit .......................................................................... 11 4.2.2 CR oscillation circuit ................................................................................ 11 4.3 Input Ports (K00-K03) ................................................................................ 12 4.3.1 Configuration of input port ....................................................................... 12 4.3.2 Interrupt function ...................................................................................... 12 4.3.3 Mask option ............................................................................................... 13 4.3.4 I/O memory of input port .......................................................................... 14 4.3.5 Programming note ..................................................................................... 14 4.4 Output Ports (R00-R03) .............................................................................. 15 4.4.1 Configuration of output port ..................................................................... 15 4.4.2 Mask option ............................................................................................... 15 4.4.3 I/O memory of output port ........................................................................ 17 4.4.4 Programming note ..................................................................................... 18 4.5 LCD Driver (COM0-COM3, SEG0-SEG14) ............................................. 19 4.5.1 Configuration of LCD driver .................................................................... 19 4.5.2 Cadence adjustment of oscillation frequency ........................................... 24 4.5.3 Mask option ............................................................................................... 25 4.5.4 I/O memory of LCD driver ........................................................................ 26 4.5.5 Programming note ..................................................................................... 26 S1C60N03 TECHNICAL MANUAL EPSON i CONTENTS 4.6 Clock Timer .................................................................................................. 27 4.6.1 Configuration of clock timer ..................................................................... 27 4.6.2 Interrupt function ...................................................................................... 27 4.6.3 Mask option ............................................................................................... 28 4.6.4 I/O memory of clock timer ........................................................................ 28 4.6.5 Programming notes ................................................................................... 29 4.7 Interrupt and HALT ..................................................................................... 30 4.7.1 Interrupt factors ........................................................................................ 31 4.7.2 Specific masks for interrupt ...................................................................... 31 4.7.3 Interrupt vectors ........................................................................................ 32 4.7.4 I/O memory of interrupt ............................................................................ 32 4.7.5 Programming notes ................................................................................... 33 CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM ____________________________ 34 CHAPTER 6 ELECTRICAL CHARACTERISTICS ________________________________ 36 6.1 6.2 6.3 6.4 6.5 ii Absolute Maximum Rating ........................................................................... 36 Recommended Operating Conditions .......................................................... 36 DC Characteristics ...................................................................................... 37 Analog Circuit Characteristics and Current Consumption ........................ 38 Oscillation Characteristics .......................................................................... 40 CHAPTER 7 CERAMIC PACKAGE FOR TEST SAMPLES _________________________ 41 CHAPTER 8 PRECAUTIONS ON MOUNTING _________________________________ 42 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 1: INTRODUCTION CHAPTER 1 INTRODUCTION The S1C60N03 Series single-chip microcomputer features an S1C6200B CMOS 4-bit CPU as the core. It contains a 768 (words) x 12 (bits) ROM, 64 (words) x 4 (bits) RAM, LCD driver , 4-bit input port (K00- K03), 4-bit output port (R00-R03) and a timer. The S1C60N03 Series is configured as follows, depending on the supply voltage. S1C60N03: 3.0 V (1.8 to 3.6 V) S1C60L03: 1.5 V (1.2 to 2.0 V) 1.1 Features Core CPU ........................................... S1C6200B Built-in oscillation circuit ............. Crystal 32.768 kHz (Typ.) or CR oscillation circuit 65 kHz (Typ.) Instruction set .................................. 100 instructions ROM capacity ................................... 768 words x 12 bits RAM capacity ................................... 64 words x 4 bits Input port .......................................... 4 bits (pull-down resistors are available by mask option) Output ports ..................................... 4 bits (clock and buzzer outputs are possible by mask option) LCD driver ........................................ 15 segments x 4, 3 or 2 commons (1/4, 1/3 or 1/2 duty are selectable by mask option) Timer .................................................. 1 system (clock timer) built-in Interrupt ............................................ External: Input port interrupt Internal: Timer interrupt 1 system 1 system Supply voltage ................................. 1.5 V (1.2 to 2.0 V) S1C60L03 3.0 V (1.8 to 3.6 V) S1C60N03 Current consumption (Typ.) ......... During HALT: 1.0 A (32 kHz crystal, with power divider OFF) During execution: 2.5 A (32 kHz crystal, with power divider OFF) 15 A (32 kHz crystal, with power divider ON) Supply form ..................................... Chip S1C60N03 TECHNICAL MANUAL EPSON 1 CHAPTER 1: INTRODUCTION 1.2 Block Diagram ROM System Reset Control 768 words x 12 bits RESET Core CPU S1C6200B OSC1 OSC2 OSC Interrupt Generator RAM Input Port K00-K03 64 words x 4 bits COM0-3 SEG0-14 TEST R00 (FOUT, BUZZER)1 R01 (BUZZER)1 R02, R03 Output Port LCD Driver 15 SEG x 4 COM FOUT & Buzzer VDD CA, CB VS2 VSS Power Controller Clock Timer 1: Terminal specifications can be selected by mask option. Fig. 1.2.1 S1C60N03 block diagram 2 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 1: INTRODUCTION 1.3 Pad Layout 1.3.1 Pad layout diagram 15 10 5 1 2.03 mm Y 35 X (0, 0) 30 Die No. 20 25 Chip thickness: 400 m Pad opening: 95 m 2.32 mm Fig. 1.3.1.1 Pad layout 1.3.2 Pad coordinates Table 1.3.2.1 Pad coordinates (unit: m) No. 1 2 3 4 5 6 7 8 9 10 11 12 Pad name TEST SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 X 980 850 720 590 460 330 200 70 -60 -190 -320 -450 Y 849 849 849 849 849 849 849 849 849 849 849 849 No. 13 14 15 16 17 18 19 20 21 22 23 24 Pad name SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 CA CB VS2 VSS X -580 -710 -840 -970 -983 -853 -723 -593 -463 -333 -203 -50 Y 849 849 849 849 -849 -849 -849 -849 -849 -849 -849 -849 No. 25 26 27 28 29 30 31 32 33 34 35 36 Pad name OSC2 OSC1 VDD RESET R00 R01 R02 R03 K00 K01 K02 K03 X 80 210 340 470 994 994 994 994 994 994 994 994 Y -849 -849 -849 -849 -760 -542 -403 -269 -120 10 140 270 1.4 Pad Description Table 1.4.1 Pan description Pad name Pad No. I/O Function VDD 27 (I) Power supply terminal (+) 24 (I) Power supply terminal (-) VSS 23 O LCD system voltage doubler (2*VSS)/halver (VSS/2) output VS2 21, 22 - Booster capacitor connecting terminal CA, CB 26 I Crystal or CR oscillation input terminal * OSC1 25 O Crystal or CR oscillation output terminal * OSC2 33-36 I Input port terminal K00-03 29 O Output port terminal, BUZZER or FOUT output terminal * R00 30 O Output port terminal or BUZZER output terminal * R01 31, 32 O Output port terminal R02, R03 2-16 O LCD segment output or DC output terminal * SEG0-14 17-20 O LCD common output terminal (1/4, 1/3 or 1/2 duty are selectable *) COM0-3 28 I Initial reset input terminal RESET 1 I Test input terminal TEST Can be selected by mask option S1C60N03 TECHNICAL MANUAL EPSON 3 CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply () supplied to VDD through VSS, the S1C60N03 Series generates the necessary internal voltages with the voltage doubler/halver and power divider. Supply voltage: S1C60N03 ... 3.0 V S1C60L03 ... 1.5 V Figure 2.1.1 shows the basic configuration of the power divider and voltage doubler/halver. VDD VDD Power divider VL1 VS2 Voltage halver (S1C60N03) VS2 CA Voltage doubler (S1C60L03) VL2 CB VL3 LON VSS Mask option Fig. 2.1.1 Basic configuration of the power divider and voltage doubler/halver The power divider and voltage doubler/halver generate the LCD drive voltage (VL1, VL2, VL3). The circuit is configured according to the model and the LCD drive bias selected by mask option. The LCD drive bias can be selected from 1/3 bias, 1/2 bias (A) and 1/2 bias (B). For S1C60N03 When 1/3 bias or 1/2 bias (A) is selected, the power divider is used to generate VL1 and VL2 by dividing the source voltage with the resistors. The voltage doubler/halver is not used. In the S1C60N03, this selection can reduce the external component count. When 1/2 bias (B) is selected in the S1C60N03, the voltage halver is used to generate VL1 and VL2 and the power divider is disconnected. This selection can reduce current consumption, but two external capacitors are necessary for the voltage halver. In the S1C60N03, the voltage doubler is not used. Figure 2.1.2 shows the power circuit configuration of the S1C60N03 according to the selected mask option. For S1C60L03 The S1C60L03 always uses the voltage doubler to generate the LCD drive voltage from 1.5 V source voltage. The voltage halver is not used. When 1/3 bias or 1/2 bias (A) is selected, the power divider is used to generate VL1 and VL2 by dividing the VS2 voltage generated by the voltage doubler. When 1/2 bias (B) is selected in the S1C60L03, the power divider is not used. Figure 2.1.3 shows the power circuit configuration of the S1C60L03 according to the selected mask option. 4 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 2: POWER SUPPLY AND INITIAL RESET S1C60N03 3 V LCD Panel 1/4, 1/3 or 1/2 duty, 1/3 bias VDD VDD VL1 = 1/3*VSS VL2 = 2/3*VSS VL3 = VSS VS2 NC CA NC CB NC 3.0 V VSS Note: VL3 is shorted to VSS internally. 3 V LCD Panel 1/4, 1/3 or 1/2 duty, 1/2 bias (A) 3 V LCD Panel 1/4, 1/3 or 1/2 duty, 1/2 bias (B) VDD VDD VS2 VL1 = 1/2*VSS VL2 = 1/2*VSS VL3 = VSS VDD VDD NC CA NC CB NC VL1 = 1/2*VSS 3.0 V VL2 = 1/2*VSS VS2 VS2 Voltage halver Note: VL3-VSS and VL1-VL2 are shorted internally. 3.0 V CB VL3 = VSS VSS CA VSS Note: VL3-VSS and VL1-VL2 are shorted internally. Fig. 2.1.2 Power circuit configuration of S1C60N03 S1C60L03 3 V LCD Panel 1/4, 1/3 or 1/2 duty, 1/3 bias VDD VDD VL1 = 1/3*VS2 VL2 = 2/3*VS2 VS2 VS2 Voltage doubler CA 1.5 V CB VL3 = 2*VSS VSS Note: VL3 is shorted to VS2 internally. 3 V LCD Panel 1/4, 1/3 or 1/2 duty, 1/2 bias (A) VDD VDD VL1 = 1/2*VS2 VL2 = 1/2*VS2 3 V LCD Panel 1/4, 1/3 or 1/2 duty, 1/2 bias (B) VS2 Voltage doubler VL3 = 2*VSS CA CB VSS Note: VL3-VS2 and VL1-VL2 are shorted internally. VDD VDD VS2 VS2 VL1 = VSS Voltage doubler 1.5 V VL2 = VSS VS2 VL3 = 2*VSS CA 1.5 V CB VSS Note: VL3-VS2 and VL1-VL2 are shorted internally. Fig. 2.1.3 Power circuit configuration of S1C60L03 S1C60N03 TECHNICAL MANUAL EPSON 5 CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C60N03 Series circuits, an initial reset must be executed. There are three ways of doing this. (1) Initial reset by the oscillation detection circuit (Note) (2) External initial reset via the RESET terminal (3) External initial reset by simultaneous high input to K00-K03 (depending on mask option) Figure 2.2.1 shows the configuration of the initial reset circuit. OSC1 OSC1 OSC2 Oscillation circuit K00 Oscillation detection circuit Vss K01 Noise rejection circuit K02 Noise rejection circuit Initial reset K03 RESET Vss Fig. 2.2.1 Configuration of initial reset circuit Note: Be sure to use reset function (2) or (3) at power-on because the initial reset function by the oscillation detection circuit (1) may not operate normally depending on the power-on procedure. 2.2.1 Oscillation detection circuit The oscillation detection circuit outputs the initial reset signal at power-on until the oscillation circuit starts oscillating, or when the oscillation circuit stops oscillating for some reason. However, use the following reset functions at power-on because the initial reset function by the oscillation detection circuit may not operate normally depending on the power-on procedure. 2.2.2 Reset terminal (RESET) An initial reset can be invoked externally by making the reset terminal high. This high level must be maintained for at least 5 msec (when oscillating frequency fosc = 32 kHz), because the initial reset circuit contains a noise rejection circuit. When the reset terminal goes low the CPU begins to operate. 2.2.3 Simultaneous high input to input ports (K00-K03) Another way of invoking an initial reset externally is to input a high signal simultaneously to the input ports (K00-K03) selected with the mask option. The specified input port terminals must be kept high for at least 4 sec (when oscillating frequency fosc = 32 kHz), because of the noise rejection circuit. Table 2.2.3.1 shows the combinations of input ports (K00-K03) that can be selected with the mask option. Table 2.2.3.1 Input port combinations A Not used B K00*K01 C K00*K01*K02 D K00*K01*K02*K03 When, for instance, mask option D (K00*K01*K02*K03) is selected, an initial reset is executed when the signals input to the four ports K00-K03 are all high at the same time. When this function is used, make sure that the specified ports do not go high at the same time during normal operation. 6 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2.4 Internal register following initialization An initial reset initializes the CPU as shown in the table below. Table 2.2.4.1 Initial values CPU Core Name Symbol Bit size Program counter step PCS 8 Program counter page PCP 4 New page pointer NPP 4 Stack pointer SP 8 Index register X X 8 Index register Y Y 8 Register pointer RP 4 General-purpose register A A 4 General-purpose register B B 4 Interrupt flag I 1 Decimal flag D 1 Zero flag Z 1 Carry flag C 1 Initial value 00H 1H 1H Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined Peripheral Circuits Bit size Initial value RAM 64 x 4 Undefined Display memory 16 x 4 Undefined Other peripheral circuits - See Section 4.1, "Memory Map". Name 2.3 Test Terminal (TEST) This terminal is used when IC is inspected for shipment. During normal operation connect it to VSS. S1C60N03 TECHNICAL MANUAL EPSON 7 CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C60N03 Series employs the S1C6200B core CPU, so that register configuration, instructions, and so forth are virtually identical to those in other processors in the family using the S1C6200/6200A/6200B. Refer to the "S1C6200/6200A Core CPU Manual" for details of the S1C6200B. Note the following points with regard to the S1C60N03 Series: (1) Since the S1C60N03 Series don't provides the SLEEP function, the SLP instruction can not be used. (2) Because the ROM capacity is 768 words, 12 bits per word, bank bits are unnecessary, and PCB and NBP are not used. (3) The RAM page is set to 0 only, so the page part (XP, YP) of the index register that specifies addresses is invalid. PUSH XP POP XP LD XP,r LD r,XP PUSH YP POP YP LD YP,r LD r,YP 3.2 ROM The built-in ROM, a mask ROM for the program, has a capacity of 768 x 12-bit steps. The program area is 3 pages (0-2), each consisting of 256 steps (00H-FFH). After an initial reset, the program start address is set to page 1, step 00H. The interrupt vectors are allocated to page l, steps 01H-07H. Bank 0 Step 00H Page 0 Step 01H Interrupt vector area Page 1 Page 2 Program start address Step 07H Step 08H Program area Step FFH 12 bits Fig. 3.2.1 ROM configuration 3.3 RAM The RAM, a data memory for storing a variety of data, has a capacity of 64 words, 4-bit words. When programming, keep the following points in mind: (1) Part of the data memory is used as stack area when saving subroutine return addresses and registers, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words on the stack. (3) Data memory 000H-00FH is the memory area pointed by the register pointer (RP). 8 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C60N03 Series are memory mapped. Thus, all the peripheral circuits can be controlled by using memory operations to access the I/O memory. The following sections describe how the peripheral circuits operate. 4.1 Memory Map The data memory of the S1C60N03 Series has an address space of 89 words, of which 16 words are allocated to display memory and 9 words, to I/O memory. Figure 4.1.1 show the overall memory map for the S1C60N03 Series, and Table 4.1.1, the memory maps for the peripheral circuits (I/O space). Address Low 0 Page 1 2 3 4 5 6 7 8 9 A B C D E F High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 RAM area (000H-03FH) 64 words x 4 bits (R/W) 2 3 4 5 6 0 7 8 9 A B C D E Display memory ares (0E0H-0EFH) 16 words x 4 bits (W only) F I/O memory See Table 4.1.1 Unused area Fig. 4.1.1 Memory map Note: Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. S1C60N03 TECHNICAL MANUAL EPSON 9 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1 I/O memory map Address Register Comment 1 0 Name Init 1 2 High K03 Low - K03 K02 K01 K00 - 2 High K02 Low 0F0H K0 input port data - 2 High K01 Low R - 2 High K00 Low R03 0 High Low R03 output port data R00 R01 R02 0 High Low R02 output port data R03 R02 FOUT 0 High Low R01 output port data BUZZER BUZZER R01 0F1H BUZZER Buzzer output On/Off control 0 On Off R00 0 High Low R00 output port data R/W FOUT FOUT output On/Off control 0 On Off Buzzer inverted output On/Off control BUZZER 0 On Off Clock timer data (2 Hz) TM3 - 2 TM3 TM2 TM1 TM0 - 2 Clock timer data (4 Hz) TM2 0F2H - 2 Clock timer data (8 Hz) TM1 R - 2 Clock timer data (16 Hz) TM0 EIK03 0 Enable Mask Interrupt mask register (K03) EIK03 EIK02 EIK01 EIK00 EIK02 0 Enable Mask Interrupt mask register (K02) 0F3H EIK01 0 Enable Mask Interrupt mask register (K01) R/W EIK00 0 Enable Mask Interrupt mask register (K00) TMRST3 Reset Reset Clock timer reset - TMRST EIT2 EIT16 EIT32 EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) 0F4H EIT16 0 Enable Mask Interrupt mask register (clock timer 16 Hz) W R/W EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 - 2 Unused - - 0 0 0 IK0 0 3 - 2 Unused - - 0F5H 0 3 - 2 Unused - - R IK0 4 0 Interrupt factor flag (K00-K03) Yes No 0 3 - 2 Unused - - 0 IT2 IT16 IT32 IT2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No 0F6H IT16 4 0 Interrupt factor flag (clock timer 16 Hz) Yes No R IT32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No XBZR 0 2 kHz 4 kHz Buzzer frequency control XBZR 0 XFOUT1 XFOUT0 0 3 Unused - 2 - - 0F7H XFOUT1 0 FOUT frequency control R/W R R/W XFOUT0 0 0: F1, 1: F2, 2: F3, 3: F4 LON LCD power and display On/Off conrol 0 On Off LON 0 0 CSDC 0 3 Unused - 2 - - 0F8H 0 3 - 2 Unused - - R/W R R/W CSDC 0 Static Dynamic LCD drive switch 1 Initial value at initial reset 3 Always "0" being read 2 Not set in the circuit 4 Reset (0) immediately after being read 10 D3 D2 D1 D0 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.2 Oscillation Circuit The S1C60N03 Series has a built-in oscillation circuit that generates the operating clock of the CPU and the peripheral circuit. Either crystal oscillation or CR oscillation can be selected for the oscillation circuit by mask option. 4.2.1 Crystal oscillation circuit The crystal oscillation circuit can be selected by mask option. The oscillation frequency (fosc) is 32.768 kHz (Typ.). Figure 4.2.1.1 shows the configuration of the crystal oscillation circuit. VDD OSC1 CPU and peripheral circuits X'tal RD RF CG CD VDD OSC2 Fig. 4.2.1.1 Configuration of crystal oscillation circuit As Figure 4.2.1.1 indicates, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator X'tal (Typ. 32.768 kHz) between the OSC1 and OSC2 terminals and the trimmer capacitor CG (5-25 pF) between the OSC1 and VDD terminals. Note: The OSC1 and OSC2 terminals on the board should be shielded with the VDD (+ side). 4.2.2 CR oscillation circuit The CR oscillation circuit can also be selected by mask option. The oscillation frequency (fosc) is 65 kHz (Typ.). Figure 4.2.2.1 shows the configuration of the CR oscillation circuit. OSC1 RCR CPU and peripheral circuits CCR OSC2 Fig. 4.2.2.1 Configuration of CR oscillation circuit As Figure 4.2.2.1 indicates, the CR oscillation circuit can be configured simply by connecting the resistor RCR between terminals OSC1 and OSC2 since capacity (CCR) is built-in. See Chapter 6, "Electrical Characteristics" for RCR value. S1C60N03 TECHNICAL MANUAL EPSON 11 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.3 Input Ports (K00-K03) 4.3.1 Configuration of input port The S1C60N03 Series has a 4-bit general-purpose input port. Each of the input port terminals (K00-K03) has an internal pull-down resistor. The pull-down resistor can be selected for each bit with the mask option. Figure 4.3.1.1 shows the configuration of input port. VDD Data bus Interrupt request Kxx Address VSS Mask option Fig. 4.3.1.1 Configuration of input port Selecting "pull-down resistor enabled" with the mask option allows input from a push button, key matrix, and so forth. When "pull-down resistor disabled" is selected, the port can be used for slide switch input and interfacing with other LSIs. 4.3.2 Interrupt function All four input port bits (K00-K03) provide the interrupt function. The conditions for issuing an interrupt can be set by the software for the four bits. Also, whether to mask the interrupt function can be selected individually for all four bits by the software. Figure 4.3.2.1 shows the configuration of K00-K03. Data bus Kxx Noise rejector Address Interrupt factor flag (IK0) Interrupt request Address Interrupt mask register (EIK) Mask option (K00-K03) Address Fig. 4.3.2.1 Input interrupt circuit configuration (K00-K03) The interrupt mask registers (EIK00-EIK03) enable the interrupt mask to be selected individually for K00-K03. An interrupt occurs when the input value which are not masked change and the interrupt factor flag (IK0) is set to 1. 12 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Input interrupt programming related precautions Port K input Active status Mask register Factor flag set Not set When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flag is set at . Fig. 4.3.2.2 Input interrupt timing When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status (input terminal = high status), the factor flag for input interrupt may be set. For example, a factor flag is set with the timing of shown in Figure 4.3.2.2. However, when clearing the content of the mask register with the input terminal kept in the high status and then setting it, the factor flag of the input ir 5rrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (high status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the rising edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (low status). 4.3.3 Mask option The contents that can be selected with the input port mask option are as follows: (1) An internal pull-down resistor can be selected for each of the four bits of the input ports (K00-K03). Having selected "pull-down resistor disabled", take care that the input does not float. Select "pulldown resistor enabled" for input ports that are not being used. (2) The input interrupt circuit contains a noise rejection circuit to prevent interrupts form occurring through noise. The mask option enables selection of the noise rejection circuit for each separate terminal series. When "use" is selected, a maximum delay of 0.5 msec (fosc = 32 kHz) occurs from the time an interrupt condition is established until the interrupt factor flag (IK0) is set to 1. S1C60N03 TECHNICAL MANUAL EPSON 13 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.3.4 I/O memory of input port Table 4.3.4.1 list the input port control bits and their addresses. Table 4.3.4.1 Input port control bits Address Register D3 D2 D1 D0 K03 K02 K01 K00 EIK01 EIK00 0F0H R EIK03 EIK02 0F3H R/W 0 0 0 IK0 0F5H R Name K03 K02 K01 K00 EIK03 EIK02 EIK01 EIK00 0 3 0 3 0 3 IK0 4 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Init 1 - 2 High Low - 2 High Low K0 input port data - 2 High Low - 2 High Low 0 Enable Mask Interrupt mask register (K03) 0 Enable Mask Interrupt mask register (K02) 0 Enable Mask Interrupt mask register (K01) 0 Enable Mask Interrupt mask register (K00) - 2 Unused - - - 2 Unused - - - 2 Unused - - 0 Interrupt factor flag (K00-K03) Yes No 3 Always "0" being read 4 Reset (0) immediately after being read K00-K03: Input port data (0F0H) The input data of the input port terminals can be read with these registers. When 1 is read: High level When 0 is read: Low level Writing: Invalid The value read is 1 when the terminal voltage of the input port (K00-K03) goes high (VDD), and 0 when the voltage goes low (VSS). These are read only bits, so writing cannot be done. EIK00-EIK03: Interrupt mask registers (0F3H) Masking the interrupt of the input port terminals can be done with these registers. When 1 is written: Enable When 0 is written: Mask Reading: Valid With these registers, masking of the input port bits can be done for each of the four bits. After an initial reset, these registers are all set to 0. IK0: Interrupt factor flag (0F5H*D0) This flag indicates the occurrence of an input interrupt. When 1 is read: Interrupt has occurred When 0 is read: Interrupt has not occurred Writing: Invalid The interrupt factor flag IK0 is associated with K00-K03. From the status of this flag, the software can decide whether an input interrupt has occurred. This flag is reset when the software has read it. Reading of interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. After an initial reset, this flag is set to 0. 4.3.5 Programming note When modifying the input port from high level to low level with pull-down resistor, a delay will occur at the fall of the waveform due to time constant of the pull-down resistor and input gate capacities. Provide appropriate waiting time in the program when performing input port reading. 14 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.4 Output Ports (R00-R03) 4.4.1 Configuration of output port Data bus The S1C60N03 Series has a 4-bit general output port (R00-R03). Output specification of the output port can be selected in a bit units with the mask option. Two kinds of output specifications are available: complementary output and Pch open drain output. Also, the mask option enables the output ports R00 and R01 to be used as special output ports. Figure 4.4.1.1 shows the configuration of the output port. VDD Register Rxx Complementary Pch open drain Address VSS Mask option Fig. 4.4.1.1 Configuration of output port 4.4.2 Mask option The mask option enables the following output port selection. (1) Output specification of output port The output specifications for the output port (R00-R03) may be either complementary output or Pch open drain output for each of the two bits. However, even when Pch open drain output is selected, a voltage exceeding the source voltage must not be applied to the output port. (2) Special output In addition to the regular DC output, special output can be selected for output ports R00 and R01, as shown in Table 4.4.2.1. Figure 4.4.2.1 shows the structure of output ports R00-R03. Table 4.4.2.1 Special output Data bus Output port R00 R01 Special output FOUT or BUZZER output BUZZER output Register R03 R03 Register R02 R02 BUZZER Register R01 R01 BUZZER Register R00 R00 FOUT Address 0F1H Mask option Fig. 4.4.2.1 Structire of output ports R00-R03 S1C60N03 TECHNICAL MANUAL EPSON 15 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) FOUT (R00) When the output port R00 is set as the FOUT output port, the R00 will output the fosc (CPU operating clock frequency) clock or the clock that is generated by dividing the fosc clock. The clock frequency can be selected individually for F1-F4, from among 5 types by mask option; one among F1-F4 is selected by software (XFOUT register) and used. The types of frequency which can be selected are shown in Table 4.4.2.2. Table 4.4.2.2 FOUT clock frequency Mask option Clock frequency (Hz) set F1 (XFOUT)=(0, 0) F2 (XFOUT)=(0, 1) F3 (XFOUT)=(1, 0) F4 (XFOUT)=(1, 1) Set 1 256 (fosc/128) 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) Set 2 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) Set 3 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) Set 4 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) Set 5 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) 32,768 (fosc/1) fosc = 32.768 kHz Note: A hazard may occur when the FOUT signal is turned on or off. BUZZER, BUZZER (R01, R00) Output ports R01 and R00 may be set to BUZZER output and BUZZER output (BUZZER reverse output), respectively, allowing for direct driving of the piezo-electric buzzer. The BUZZER signal is controlled by the R00 register and the BUZZER signal is controlled by the R01 register. The frequency of buzzer output may be selected by software to be either 2 kHz or 4 kHz. 16 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.4.3 I/O memory of output port Table 4.4.3.1 lists the output port control bits and their addresses. Table 4.4.3.1 Control bits of output port Address Register Comment Name Init 1 1 0 R03 0 High Low R03 output port data R00 R01 R02 0 High Low R02 output port data R03 R02 FOUT 0 High Low R01 output port data BUZZER BUZZER R01 0F1H Buzzer output On/Off control BUZZER 0 On Off R00 0 High Low R00 output port data R/W FOUT output On/Off control FOUT 0 On Off Buzzer inverted output On/Off control BUZZER 0 On Off XBZR 0 2 kHz 4 kHz Buzzer frequency control XBZR 0 XFOUT1 XFOUT0 0 3 Unused - 2 - - 0F7H XFOUT1 0 FOUT frequency control R/W R R/W XFOUT0 0 0: F1, 1: F2, 2: F3, 3: F4 1 Initial value at initial reset 3 Always "0" being read 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 R00-R03: Output port data (0F1H) Sets the output data for the output ports. When 1 is written: High output When 0 is written: Low output Reading: Valid The output port terminals output the data written to the corresponding registers (R00-R03) without changing it. When 1 is written to the register, the output port terminal goes high (VDD), and when 0 is written, the output port terminal goes low (VSS). After an initial reset, all the registers are set to 0. R00 (when FOUT is selected): Special output port data (0F1H*D0) Controls the FOUT (fosc clock) output. When 1 is written: Clock output When 0 is written: Low level (DC) output Reading: Valid FOUT output can be controlled by writing data to R00. After an initial reset, this register is set to 0. Figure 4.4.3.1 shows the output waveform for FOUT output. R00 register 0 1 FOUT output waveform Fig. 4.4.3.1 FOUT output waveform XFOUT0, XFOUT1: FOUT frequency control (0F7H*D0, D1) Selects the output frequency when the R00 port is set for FOUT output. Table 4.4.3.2 FOUT frequency selection XFOUT1 XFOUT0 0 0 0 1 1 0 1 Frequency selected F1 F2 F3 1 F4 After an initial reset, these registers are set to 0. S1C60N03 TECHNICAL MANUAL EPSON 17 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00, R01 (when buzzer output is selected): Special output port data (0F1H*D0, D1) Controls the buzzer output. When 1 is written: Buzzer output When 0 is written: Low level (DC) output Reading: Valid BUZZER and BUZZER output can be controlled by writing data to R00 and R01. After an initial reset, these registers are set to 0. Figure 4.4.3.2 shows the output waveform for buzzer output. R01 (R00) register 0 1 BUZZER output waveform BUZZER output waveform Fig. 4.4.3.2 Buzzer output waveform XBZR: Buzzer frequency control (0F7H*D3) Selects the frequency of the buzzer signal. When 1 is written: 2 kHz When 0 is written: 4 kHz Reading: Valid When R00 and R01 port is set to buzzer output, the frequency of the buzzer signal can be selected by this register. When 1 is written to this register, the frequency is set in 2 kHz, and in 4 kHz when 0 is written. After an initial reset, this register is set to 0. 4.4.4 Programming note The buzzer or FOUT signal may produce hazards when the output ports R00 and R01 are turned on or off. 18 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.5 LCD Driver (COM0-COM3, SEG0-SEG14) 4.5.1 Configuration of LCD driver The S1C60N03 Series has four common terminals and 15 (SEG0-SEG14) segment terminals, so that an LCD with a maximum of 60 (15 x 4) segments can be driven. The power for driving the LCD is generated by the CPU internal circuit, so there is no need to supply power externally. The driving method is 1/4 duty (or 1/3, 1/2 duty by mask option) dynamic drive, adopting the four types of potential (1/3 bias), VDD, VL1, VL2 and VL3. Moreover, the 1/2 bias dynamic drive that uses three types of potential, VDD, VL1 = VL2 and VL3, can be selected by setting the mask option (drive duty can also be selected from 1/4, 1/3 or 1/2). The LCD drive voltages VL1 to VL3 are generated by the power divider and/or voltage doubler/halver as shown in Table 4.5.1.1. Table 4.5.1.1 LCD drive voltage Bias Model selection S1C60N03 1/3 bias 1/2 bias (A) 1/2 bias (B) S1C60L03 1/3 bias 1/2 bias (A) 1/2 bias (B) VL1 1/3 VSS 1/2 VSS VS2 1/3 VS2 1/2 VS2 VSS Drive voltage VL2 VL3 2/3 VSS VSS 1/2 VSS VSS VS2 VSS 2/3 VS2 VS2 1/2 VS2 VS2 VSS VS2 VS2 - - 1/2 VSS 2 VSS 2 VSS 2 VSS Refer to Section 2.1, "Power Supply", for details of the power supply circuit. The frame frequency is 32 Hz for 1/4 duty and 1/2 duty, and 42.7 Hz for 1/3 duty (in the case of fosc = 32 kHz). Figures 4.5.1.1 to 4.5.1.6 show the drive waveform for each duty and bias. Note: "fosc" indicates the oscillation frequency of the oscillation circuit. S1C60N03 TECHNICAL MANUAL EPSON 19 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VDD VL1 VL2 VL3 COM0 COM1 LCD status COM0 COM1 COM2 COM3 COM2 SEG0-14 COM3 Off On VDD VL1 VL2 VL3 SEG0 -SEG14 Frame frequency Fig. 4.5.1.1 Drive waveform for 1/4 duty (1/3 bias) 20 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VDD VL1 VL2 VL3 COM0 COM1 LCD status COM0 COM1 COM2 SEG0-14 COM2 Off On COM3 VDD VL1 VL2 VL3 SEG0 -SEG14 Frame frequency Fig. 4.5.1.2 Drive waveform for 1/3 duty (1/3 bias) VDD VL1 VL2 VL3 COM0 COM1 LCD status COM0 COM1 SEG0-14 COM2 COM3 VDD VL1 VL2 VL3 Off On SEG0 -SEG14 Frame frequency Fig. 4.5.1.3 Drive waveform for 1/2 duty (1/3 bias) S1C60N03 TECHNICAL MANUAL EPSON 21 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 COM2 COM3 SEG0-14 COM2 Off On COM3 -VDD -VL1, L2 -VL3 SEG 0-14 Frame frequency Fig. 4.5.1.4 Drive waveform for 1/4 duty (1/2 bias) 22 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0-14 COM2 Off On COM3 -VDD -VL1, L2 -VL3 SEG 0-14 Frame frequency Fig. 4.5.1.5 Drive waveform for 1/3 duty (1/2 bias) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 SEG0-14 COM2 Off On COM3 -VDD -VL1, L2 -VL3 SEG 0-14 Frame frequency Fig. 4.5.1.6 Drive waveform for 1/2 duty (1/2 bias) S1C60N03 TECHNICAL MANUAL EPSON 23 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.5.2 Cadence adjustment of oscillation frequency In the S1C60N03 Series, the LCD drive duty can be set to 1/1 duty by software. This function enables easy adjustment (cadence adjustment) of the oscillation frequency of the oscillation circuit. The procedure to set to 1/1 duty drive is as follows: Write 1 to the CSDC register at address 0F8H*D0. Write the same value to all registers corresponding to COMs 0 through 3 of the display memory. The frame frequency is 32 Hz (fosc/1024, when fosc = 32.768 kHz). Note: * Even when l/3 or 1/2 duty is selected by the mask option, the display data corresponding to all COM are valid during 1/1 duty driving. Hence, for 1/1 duty drive, set the same value for all display memory corresponding to COMs 0 through 3. * For cadence adjustment, set the display data corresponding to COMs 0 through 3, so that all the LCD segments go on. Figures 4.5.2.1 and 4.5.2.2 show the 1/1 duty drive waveform in 1/3 bias and 1/2 bias driving. LCD lighting status -VDD -VL1 -VL2 -VL3 COM 0-3 COM0 COM1 COM2 COM3 Frame frequency SEG0-14 Off On -VDD -VL1 -VL2 -VL3 SEG 0-14 -VDD -VL1 -VL2 -VL3 Fig. 4.5.2.1 Drive waveform for 1/1 duty (1/3 bias) LCD lighting status -VDD -VL1, VL2 COM 0-3 -VL3 COM0 COM1 COM2 COM3 Frame frequency Off SEG0-14 On -VDD -VL1, VL2 -VL3 SEG 0-14 -VDD -VL1, VL2 -VL3 Fig. 4.5.2.2 Drive waveform for 1/1 duty (1/2 bias) 24 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.5.3 Mask option (1) Segment allocation As shown in Figure 4.l.1, display data is decided by the data written to the display memory (writeonly) at address 0E0H-0EFH. The address and bits of the display memory can be made to correspond to the segment terminals (SEG0-SEG14) in any combination through mask option. This simplifies design by increasing the degree of freedom with which the liquid crystal panel can be designed. Figure 4.5.3.1 shows an example of the relationship between the LCD segments (on the panel) and the display memory in the case of 1/3 duty. Address Common 0 Common 1 Common 2 EA, D0 EB, D1 EB, D0 (a) (f) (e) SEG11 EA, D1 EB, D2 EA, D3 (b) (g) (d) SEG12 ED, D1 EA, D2 EB, D3 (f') (c) (p) Data D3 D2 D1 D0 0EAH d c b a 0EBH p g f e 0ECH d' c' b' a' 0EDH p' g' f' e' SEG10 Display data memory allocation Pin address allocation a a' b f e g' c c' e' p d SEG10 b' f' g SEG11 p' d' SEG12 Common 0 Common 1 Common 2 Fig. 4.5.3.1 Segment allocation (2) Drive duty According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty. Table 4.5.3.1 shows the differences in the number of segments according to the selected duty. Table 4.5.3.1 Differences according to selected duty Duty COM used 1/4 COM0-COM3 1/3 COM0-COM2 1/2 COM0-COM1 Max. number of segments Frame frequency * 60 (15 x 4) 32 Hz 45 (15 x 3) 42.7 Hz 30 (15 x 2) 32 Hz When fOSC = 32 kHz (3) Output specification The segment terminals (SEG0-SEG14) are selected by mask option in pairs for either segment signal output or DC output (VDD and VSS binary output). When DC output is selected, the data corresponding to COM0 of each segment terminal is output. When DC output is selected, either complementary output or Pch open drain output can be selected for each terminal by mask option. Note: The terminal pairs are the combination of SEG (2n) and SEG (2n + 1) (where n is an integer from 0 to 6). (4) Drive bias For the drive bias, either 1/3 bias or 1/2 bias can be selected by the mask option. S1C60N03 TECHNICAL MANUAL EPSON 25 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.5.4 I/O memory of LCD driver Table 4.5.4.1 shows the control bits of the LCD driver and their addresses. Figure 4.5.4.1 shows the display memory map. Table 4.5.4.1 Control bits of LCD driver Address Register D3 D2 D1 D0 LON 0 0 CSDC 0F8H R/W R R/W Name LON 0 3 0 3 CSDC 1 Initial value at initial reset 2 Not set in the circuit Address 0 1 2 Comment Init 1 1 0 LCD power and display On/Off conrol 0 On Off Unused - 2 - - - 2 Unused - - 0 Static Dynamic LCD drive switch 3 Always "0" being read 4 Reset (0) immediately after being read 3 4 5 6 7 8 9 A B C D E F Display memory (Write only) 16 words x 4 bits 0E0 Fig. 4.5.4.1 Display memory map LON: LCD display and power divider On/Off control (0F8H*D3) The LCD display can be turned on or off with this switch. It also controls the power divider on or off if the power divider is selected for the LCD power generator. When 1 is written: LCD displayed When 0 is written: LCD is all off Reading: Valid When the power divider is selected for the LCD power generator, power current consumption will increase if this switch is turned on. Keep this switch off (LON = 0) when LCD display is not necessary. After an initial reset, LCD and the power divider is turned off. CSDC: LCD drive switch (0F8H*D0) The LCD drive format can be selected with this switch. When 1 is written: Static drive When 0 is written: Dynamic drive Reading: Valid After an initial reset, dynamic drive (CSDC = 0) is selected. Display memory (0E0H-0EFH) The LCD segments are turned on or off according to this data. When 1 is written: On When 0 is written: Off Reading: Invalid By writing data into the display memory allocated to the LCD segment (on the panel), the segment can be turned on or off. After an initial reset, the contents of the display memory are undefined. 4.5.5 Programming note Because the display memory is for writing only, re-writing the contents with computing instructions (e.g., AND, OR, etc.) which come with read-out operations is not possible. To perform bit operations, a buffer to hold the display data is required on the RAM. 26 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.6 Clock Timer 4.6.1 Configuration of clock timer The S1C60N03 Series has a built-in clock timer that uses the oscillation circuit as the clock source. The clock timer is configured as a 7-bit binary counter that counts with a 256 Hz source clock from the divider. The high-order 4 bits of the counter (16 Hz-2 Hz) can be read by the software. Figure 4.6.1.1 is the block diagram of the clock timer. Data bus Oscillation circuit Divider 256 Hz 128 Hz-32 Hz 16 Hz-2 Hz 64 Hz 32 Hz 16 Hz 2 Hz Clock timer reset signal Mask option Interrupt control Interrupt request Fig. 4.6.1.1 Block diagram of clock timer Normally, this clock timer is used for all kinds of timing purpose, such as clocks. 4.6.2 Interrupt function The clock timer can generate interrupts at the falling edge of the 32 Hz (or 64 Hz), 16 Hz, and 2 Hz signals. The software can mask any of these interrupt signals. Figure 4.6.2.1 is the timing chart of the clock timer. Address 0F2H Register Frequency bits D0 16 Hz D1 8 Hz D2 4 Hz D3 2 Hz Clock timer timing chart Occurrence of 32 Hz interrupt request Occurrence of 16 Hz interrupt request Occurrence of 2 Hz interrupt request Fig. 4.6.2.1 Timing chart of the clock timer As shown in Figure 4.6.2.1, an interrupt is generated at the falling edge of the 32 Hz, 16 Hz, and 2 Hz signals. At this point, the corresponding interrupt factor flag (IT32, IT16, IT2) is set to 1. The interrupts can be masked individually with the interrupt mask register (EIT32, EIT16, EIT2). However, regardless of the interrupt mask register setting, the interrupt factor flags will be set to 1 at the falling edge of their corresponding signal (e.g. the falling edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to 1). Note: Write to the interrupt mask registers (EIT32, EIT16, EIT2) and read the interrupt factor flags (IT32, IT16, IT2) only in the DI status (interrupt flag = 0). Otherwise, it causes malfunction. S1C60N03 TECHNICAL MANUAL EPSON 27 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.6.3 Mask option The 32 Hz timer interrupt can be changed to 64 Hz by mask option. When 64 Hz is selected by mask option, the falling edge of the 64 Hz signal sets the IT32 interrupt factor flag (0F6H*D0) and the interrupt is controlled with the EIT32 interrupt mask register (0F4H*D0). 4.6.4 I/O memory of clock timer Table 4.6.4.1 shows the clock timer control bits and their addresses. Table 4.6.4.1 Control bits of clock timer Address Register D3 D2 D1 TM3 TM2 TM1 0F2H R TMRST EIT2 EIT16 0F4H W 0 R/W IT2 IT16 0F6H R 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Name Init 1 2 Clock timer data (2 Hz) TM3 - TM0 - 2 Clock timer data (4 Hz) TM2 - 2 Clock timer data (8 Hz) TM1 - 2 Clock timer data (16 Hz) TM0 TMRST3 Reset Reset Clock timer reset - EIT32 EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT16 0 Enable Mask Interrupt mask register (clock timer 16 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 - 2 Unused - - IT32 IT2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No IT16 4 0 Interrupt factor flag (clock timer 16 Hz) Yes No IT32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No 3 Always "0" being read 4 Reset (0) immediately after being read D0 TM0-TM3: Timer data (0F2H) The l6 Hz to 2 Hz timer data of the clock timer can be read from this register. These four bits are readonly, and write operations are invalid. After an initial reset, the timer data is initialized to "0H". EIT32, EIT16, EIT2: Interrupt mask registers (0F4H*D0-D2) These registers are used to mask the clock timer interrupt. When 1 is written: Enabled When 0 is written: Masked Reading: Valid The interrupt mask registers (EIT32, EIT16, EIT2) mask the corresponding interrupt frequencies (32 Hz/ 64 Hz, 16 Hz, 2 Hz). At initial reset, these registers are all set to 0. IT32, IT16, IT2: Interrupt factor flags (0F6H*D0-D2) These flags indicate the status of the clock timer interrupt. When 1 is read: Interrupt has occurred When 0 is read: Interrupt has not occurred Writing: Invalid The interrupt factor flags (IT32, IT16, IT2) correspond to the clock timer interrupts (32 Hz/64 Hz, 16 Hz, 2 Hz). The software can determine from these flags whether there is a clock timer interrupt. However, even if the interrupt is masked, the flags are set to 1 at the falling edge of the signal. These flags can be reset when the register is read by the software. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. At initial reset, these flags are set to 0. 28 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) TMRST: Clock timer reset (0F4H*D3) This bit resets the clock timer. When 1 is written: Clock timer reset When 0 is written: No operation Reading: Always 0 The clock timer is reset by writing 1 to TMRST. The clock timer starts immediately after this. No operation results when 0 is written to TMRST. This bit is write-only, and so is always 0 when read. 4.6.5 Programming notes (1) Note that the frequencies and times differ from the description in this section when the oscillation frequency is not 32.768 kHz. (2) Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. S1C60N03 TECHNICAL MANUAL EPSON 29 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.7 Interrupt and HALT The S1C60N03 Series provides the following interrupt settings, each of which is maskable. External interrupt: Internal interrupt: Input port interrupt (one) Timer interrupt (one) To enable interrupts, the interrupt flag must be set to 1 (EI) and the necessary related interrupt mask registers must be set to 1 (enable). When an interrupt occurs, the interrupt flag is automatically reset to 0 (DI) and interrupts after that are inhibited. Figure 4.7.1 shows the configuration of the interrupt circuit. K00 Interrupt vector EIK00 (MSB) K01 EIK01 IK0 : K02 Program counter of CPU (three low-order bits) : EIK02 K03 (LSB) EIK03 IT2 EIT2 IT16 INT (Interrupt request) IT32 EIT32 Interrupt factor flag Interrupt mask register Interrupt flag EIT16 Fig. 4.7.1 Configuration of interrupt circuit HALT mode When the HALT instruction is executed, the CPU stops operating and enters the HALT mode. The oscillation circuit and the peripheral circuits operate in the HALT mode. By an interrupt, the CPU exits the HALT mode and resumes operating. 30 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.7.1 Interrupt factors Table 4.7.1.1 shows the factors that generate interrupt requests. The interrupt factor flags are set to 1 depending on the corresponding interrupt factors. The CPU is interrupted when the following two conditions occur and an interrupt factor flag is set to 1. * The corresponding mask register is 1 (enabled) * The interrupt flag is 1 (EI) The interrupt factor flag is a read-only register, but can be reset to 0 when the register data is read. At initial reset, the interrupt factor flags are reset to 0. Note: Reading of interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. Table 4.7.1.1 Interrupt factors Interrupt factor Clock timer 2 Hz falling edge Clock timer 16 Hz falling edge Clock timer 32 (or 64) Hz falling edge Input (K00-K03) port rising edge Interrupt factor flag IT2 (0F6H*D2) IT16 (0F6H*D1) IT32 (0F6H*D0) IK0 (0F5H*D0) 4.7.2 Specific masks for interrupt The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. The interrupts are enabled when 1 is written to them, and masked (interrupt disabled) when 0 is written to them. At initial reset, the interrupt mask register is set to 0. Table 4.7.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags. Table 4.7.2.1 Interrupt mask registers and interrupt factor flags Interrupt mask register EIT2 (0F4H*D2) EIT16 (0F4H*D1) EIT32 (0F4H*D0) EIK03* (0F3H*D3) EIK02* (0F3H*D2) EIK01* (0F3H*D1) EIK00* (0F3H*D0) Interrupt factor flag IT2 (0F6H*D2) IT16 (0F6H*D1) IT32 (0F6H*D0) IK0 (0F5H*D0) There is an interrupt mask register for each input port terminal. S1C60N03 TECHNICAL MANUAL EPSON 31 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.7.3 Interrupt vectors When an interrupt request is input to the CPU, the CPU starts interrupt processing. After the program being executed is suspended, interrupt processing is executed in the following order: The address data (value of the program counter) of the program step to be executed next is saved on the stack (RAM). The interrupt request causes the value of the interrupt vector (page 1, 01H-07H) to be loaded into the program counter. The program at the specified address is executed (execution of interrupt processing routine). Note: The processing in steps 1 and 2, above, takes 12 cycles of the CPU system clock. Table 4.7.3.1 Interrupt vector addresses Page 1 Step Interrupt vector 00H Initial reset 01H Clock timer interrupt 04H Input (K00-K03) interrupt 4.7.4 I/O memory of interrupt Table 4.7.4.1 shows the interrupt control bits and their addresses. Table 4.7.4.1 Control bits of interrupt Address Register D3 D2 D1 EIK03 EIK02 EIK01 0F3H R/W TMRST EIT2 EIT16 0F4H W 0 R/W 0 0 0F5H R 0 IT2 IT16 0F6H R 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Name Init 1 EIK03 0 Enable Mask Interrupt mask register (K03) EIK00 EIK02 0 Enable Mask Interrupt mask register (K02) EIK01 0 Enable Mask Interrupt mask register (K01) EIK00 0 Enable Mask Interrupt mask register (K00) TMRST3 Reset Reset Clock timer reset - EIT32 EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT16 0 Enable Mask Interrupt mask register (clock timer 16 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 - 2 Unused - - IK0 0 3 - 2 Unused - - 0 3 - 2 Unused - - IK0 4 0 Interrupt factor flag (K00-K03) Yes No 0 3 - 2 Unused - - IT32 IT2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No IT16 4 0 Interrupt factor flag (clock timer 16 Hz) Yes No IT32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No 3 Always "0" being read 4 Reset (0) immediately after being read D0 EIT32, EIT16, EIT2: Interrupt mask registers (0F4H*D0-D2) IT32, IT16, IT2: Interrupt factor flags (0F6H*D0-D2) ...See Section 4.6, "Clock Timer". EIK00-EIK03: Interrupt mask registers (0F3H) IK0: Interrupt factor flag (0F5H*D0) ...See Section 4.3, "Input Ports". 32 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.7.5 Programming notes (1) Restart from the HALT mode is performed by an interrupt. The return address after completion of the interrupt processing will be the address following the HALT instruction. (2) When an interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI status. After completion of the interrupt processing, set to the EI status through the software as needed. Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning of the interrupt processing routine. (3) The interrupt factor flags must always be reset before setting the EI status. When the interrupt mask register has been set to 1, the same interrupt will occur again if the EI status is set unless of resetting the interrupt factor flag. (4) The interrupt factor flag will be reset by reading through the software. Because of this, when multiple interrupt factor flags are to be assigned to the same address, perform the flag check after the contents of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the interrupt factor flag to be reset. (5) Reading of interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. S1C60N03 TECHNICAL MANUAL EPSON 33 CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM Piezo Buzzer Single Terminal Driving COM3 COM0 SEG14 SEG0 LCD PANEL K00 CA CB C1 VDD I VS2 C2 K03 OSC1 S1C60N03 S1C60L03 OSC2 R00 O CG X'tal 1 RCR 2 RESET 1.5 V (S1C60L03) R02 Cp R03 3.0 V (S1C60N03) R01 TEST VSS Piezo Buzzer Coil 1 Crystal oscillation 2 CR oscillation X'tal CG RCR C1, C2 Cp Crystal oscillator Trimmer capacitor Resistor for CR oscillation Capacitor Capacitor 32.768 kHz, CI (Max.) = 35 k 5-25 pF 470 k (65 kHz) 1 F (see Note) 3.3 F Note: Use a 1 F capacitor for C1 and C2 when "S1C60L03 1/3 bias" is selected, or a 0.1 F capacitor when "S1C60N03 1/2 bias" or "S1C60L03 1/2 bias (A), (B)" is selected. No capacitor is required for C1 and C2 when another specification is selected. 34 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM Piezo Buzzer Direct Driving COM3 COM0 SEG14 SEG0 LCD PANEL K00 CA CB C1 VDD I VS2 C2 K03 OSC1 S1C60N03 S1C60L03 OSC2 R02 CG X'tal 1 RESET O 1.5 V (S1C60L03) Cp R03 RCR 2 3.0 V (S1C60N03) R00 R01 TEST VSS Piezo Buzzer X'tal CG RCR C1, C2 Cp 1 Crystal oscillation 2 CR oscillation Crystal oscillator Trimmer capacitor Resistor for CR oscillation Capacitor Capacitor 32.768 kHz, CI (Max.) = 35 k 5-25 pF 470 k (65 kHz) 1 F (see Note) 3.3 F Note: Use a 1 F capacitor for C1 and C2 when "S1C60L03 1/3 bias" is selected, or a 0.1 F capacitor when "S1C60N03 1/2 bias" or "S1C60L03 1/2 bias (A), (B)" is selected. No capacitor is required for C1 and C2 when another specification is selected. S1C60N03 TECHNICAL MANUAL EPSON 35 CHAPTER 6: ELECTRICAL CHARACTERISTICS CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Rating (VDD=0V) Item Rated value Unit Symbol Supply voltage -5.0 to 0.5 V VSS Input voltage (1) VI VSS - 0.3 to 0.5 V Input voltage (2) VIOSC VSS - 0.3 to 0.5 V Permissible total output current 1 IVSS 10 mA Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Soldering temperature / time Tsol 260C, 10sec (lead section) - Permissible dissipation PD 250 mW 1 The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pin (or is drawn in). 6.2 Recommended Operating Conditions S1C60N03 Item Supply voltage Oscillation frequency Booster capacitor Capacitor betwen VDD and VS2 Condition Symbol VDD=0V VSS fOSC Crystal oscillation CR oscillation, RCR=470k C1 C2 Min. -3.6 Condition Symbol VDD=0V VSS fOSC Crystal oscillation CR oscillation, RCR=470k C1 C2 Min. -2.0 50 0.1 0.1 S1C60L03 Item Supply voltage Oscillation frequency Booster capacitor Capacitor betwen VDD and VS2 36 EPSON 50 0.1 0.1 (Ta=-20 to 70C) Typ. Max. Unit -3.0 -1.8 V 32.768 kHz 65 80 kHz F F (Ta=-20 to 70C) Typ. Max. Unit -1.5 -1.2 V 32.768 kHz 65 80 kHz F F S1C60N03 TECHNICAL MANUAL CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.3 DC Characteristics S1C60N03 Unless otherwise specified: VDD=0V, VSS=-3.0V, fosc=32.768kHz, Ta=25C, VS2 is internal voltage, C1=C2=0.1F Item Condition Symbol High level input voltage (1) VIH1 K00-03 High level input voltage (2) VIH2 RESET Low level input voltage (1) VIL1 K00-03 Low level input voltage (2) VIL2 RESET High level input current (1) IIH1 VIH1=0V, No pull-down K00-03 High level input current (2) IIH2 VIH2=0V, Pull-down K00-03 High level input current (3) IIH3 VIH3=0V, Pull-down RESET Low level input current IIL VIL=VSS K00-03 RESET, TEST High level output current (1) IOH1 VOH1=0.1*VSS R02, R03 High level output current (2) IOH2 VOH2=0.1*VSS R00, R01 (with protection resistor) Low level output current (1) IOL1 VOL1=0.9*VSS R02, R03 Low level output current (2) IOL2 VOL2=0.9*VSS R00, R01 (with protection resistor) Common output current IOH3 VOH3=-0.05V COM0-3 IOL3 VOL3=VL3+0.05V Segment output current IOH4 VOH4=-0.05V SEG0-14 (during LCD output) IOL4 VOL4=VL3+0.05V Segment output current IOH5 VOH5=0.1*VSS SEG0-14 (during DC output) IOL5 VOL5=0.9*VSS Min. 0.2*VSS 0.15*VSS VSS VSS 0 10 30 -0.5 Typ. Max. 0 0 0.8*VSS 0.85*VSS 0.5 40 100 0 Unit V V V V A A A A -1.0 -1.0 mA mA 3.0 3.0 mA mA -3 3 -3 3 -300 300 A A A A A A S1C60L03 Unless otherwise specified: VDD=0V, VSS=-1.5V, fosc=32.768kHz, Ta=25C, VS2 is internal voltage, C1=C2=0.1F Item Condition Symbol High level input voltage (1) VIH1 K00-03 High level input voltage (2) VIH2 RESET Low level input voltage (1) VIL1 K00-03 VIL2 Low level input voltage (2) RESET High level input current (1) IIH1 VIH1=0V, No pull-down K00-03 High level input current (2) IIH2 VIH2=0V, Pull-down K00-03 IIH3 RESET High level input current (3) VIH3=0V, Pull-down VIL=VSS Low level input current IIL K00-03 RESET, TEST R02, R03 High level output current (1) IOH1 VOH1=0.1*VSS VOH2=0.1*VSS High level output current (2) IOH2 R00, R01 (with protection resistor) R02, R03 Low level output current (1) IOL1 VOL1=0.9*VSS VOL2=0.9*VSS Low level output current (2) IOL2 R00, R01 (with protection resistor) Common output current IOH3 VOH3=-0.05V COM0-3 IOL3 VOL3=VL3+0.05V IOH4 SEG0-14 Segment output current VOH4=-0.05V VOL4=VL3+0.05V (during LCD output) IOL4 Segment output current IOH5 VOH5=0.1*VSS SEG0-14 IOL5 (during DC output) VOL5=0.9*VSS S1C60N03 TECHNICAL MANUAL EPSON Min. 0.2*VSS 0.15*VSS VSS VSS 0 5.0 9.0 -0.5 Typ. Max. 0 0 0.8*VSS 0.85*VSS 0.5 20 100 0 Unit V V V V A A A A -200 -200 A A A A 700 700 -3 3 -3 3 -100 130 A A A A A A 37 CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.4 Analog Circuit Characteristics and Current Consumption S1C60N03 (Crystal Oscillation) Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC=32.768kHz, Ta=25C, CG=25pF, VS2 is internal voltage, C1=C2=0.1F Item Max. Symbol Condition Typ. Min. LCD drive voltage VL1 Connect 1 M load resistor between VDD and 1/3*VSS 1/3*VSS 1/3*VSS segment driver (SEG0-SEG14) when segment - 0.1 x0.9 driver's level is VL1 2/3*VSS 2/3*VSS 2/3*VSS VL2 Connect 1 M load resistor between VDD and segment driver (SEG0-SEG14) when segment - 0.1 x0.9 driver's level is VL2 VL3 Connect 1 M load resistor between VDD and VSS segment driver (SEG0-SEG14) when segment driver's level is VL3 Current consumption 2.5 IHLT During HALT with LCD OFF No panel 1.0 5.0 During operation with LCD OFF load 2.0 IEXE1 20 During operation with power divider ON 15 IEXE2 Unit V V V A A A S1C60L03 (Crystal Oscillation) Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Ta=25C, CG=25pF, VS2 is internal voltage, C1=C2=0.1F Min. Condition Typ. Item Max. Symbol 1/3*VS2 1/3*VS2 1/3*VS2 Connect 1 M load resistor between VDD and LCD drive voltage VL1 - 0.1 x0.9 segment driver (SEG0-SEG14) when segment driver's level is VL1 VL2 Connect 1 M load resistor between VDD and 2/3*VS2 2/3*VS2 2/3*VS2 segment driver (SEG0-SEG14) when segment - 0.1 x0.9 driver's level is VL2 VL3 Connect 1 M load resistor between VDD and VS2 VS2 VS2 segment driver (SEG0-SEG14) when segment - 0.1 x0.9 driver's level is VL3 IHLT During HALT with LCD OFF No panel 1.0 2.5 Current consumption During operation with LCD OFF load 2.0 IEXE1 5.0 During operation with power divider ON 15 IEXE2 20 38 EPSON Unit V V V A A A S1C60N03 TECHNICAL MANUAL CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C60N03 (CR Oscillation) Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC=65kHz, Ta=25C, RCR=470k, VS2 is internal voltage, C1=C2=0.1F Item Max. Symbol Condition Typ. Min. LCD drive voltage VL1 Connect 1 M load resistor between VDD and 1/3*VSS 1/3*VSS 1/3*VSS segment driver (SEG0-SEG14) when segment - 0.1 x0.9 driver's level is VL1 2/3*VSS 2/3*VSS 2/3*VSS VL2 Connect 1 M load resistor between VDD and segment driver (SEG0-SEG14) when segment - 0.1 x0.9 driver's level is VL2 VL3 Connect 1 M load resistor between VDD and VSS segment driver (SEG0-SEG14) when segment driver's level is VL3 Current consumption 15 IHLT During HALT with LCD OFF No panel 8 20 During operation with LCD OFF load 15 IEXE1 30 During operation with power divider ON 25 IEXE2 Unit V V V A A A S1C60L03 (CR Oscillation) Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC=65kHz, Ta=25C, RCR=470k, VS2 is internal voltage, C1=C2=0.1F Min. Condition Typ. Item Max. Symbol 1/3*VS2 1/3*VS2 1/3*VS2 Connect 1 M load resistor between VDD and LCD drive voltage VL1 - 0.1 x0.9 segment driver (SEG0-SEG14) when segment driver's level is VL1 VL2 Connect 1 M load resistor between VDD and 2/3*VS2 2/3*VS2 2/3*VS2 segment driver (SEG0-SEG14) when segment - 0.1 x0.9 driver's level is VL2 VL3 Connect 1 M load resistor between VDD and VS2 VS2 VS2 segment driver (SEG0-SEG14) when segment - 0.1 x0.9 driver's level is VL3 IHLT During HALT with LCD OFF No panel 8 15 Current consumption During operation with LCD OFF load 15 IEXE1 20 During operation with power divider ON 25 IEXE2 30 S1C60N03 TECHNICAL MANUAL EPSON Unit V V V A A A 39 CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.5 Oscillation Characteristics Oscillation characteristics will vary according to different conditions (elements used, board pattern). Use the following characteristics are as reference values. S1C60N03 Crystal Oscillation Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC=32.768kHz, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C Symbol Item Condition Vsta tsta5sec (VSS) Oscillation start voltage Vstp tstp10sec (VSS) Oscillation stop voltage CD Including the parasitic capacitance inside the IC (in chip) Built-in capacitance (drain) Frequency/voltage deviation f/V VSS=-1.8 to -3.6V f/IC Frequency/IC deviation Frequency adjustment range f/CG CG=5 to 25pF Harmonic oscillation start voltage Vhho CG=5pF (VSS) Permitted leak resistance Rleak Between OSC1 and VDD Min. -1.8 -1.8 Typ. Max. 20 5 10 -10 40 -3.6 200 Unit V V pF ppm ppm ppm V M S1C60L03 Crystal Oscillation Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C Symbol Item Condition Vsta tsta5sec (VSS) Oscillation start voltage Vstp tstp10sec (VSS) Oscillation stop voltage CD Including the parasitic capacitance inside the IC (in chip) Built-in capacitance (drain) Frequency/voltage deviation f/V VSS=-1.2 to -2.0V f/IC Frequency/IC deviation Frequency adjustment range f/CG CG=5 to 25pF Harmonic oscillation start voltage Vhho CG=5pF (VSS) Between OSC1 and VDD Permitted leak resistance Rleak Min. -1.2 -1.2 Typ. Max. 20 5 10 -10 40 -2.0 200 Unit V V pF ppm ppm ppm V M S1C60N03 CR Oscillation Unless otherwise specified: VDD=0V, VSS=-3.0V, RCR=470k, Ta=25C Item Symbol Oscillation frequency dispersion fOSC Oscillation start voltage Vsta (VSS) Oscillation start time tsta VSS=-1.8 to -3.6V Oscillation stop voltage Vstp (VSS) Condition Min. -20 -1.8 Typ. 65kHz Max. 20 Unit % V mS V Max. 20 Unit % V mS V 3 -1.8 S1C60L03 CR Oscillation Unless otherwise specified: VDD=0V, VSS=-1.5V, RCR=470k, Ta=25C Item Symbol Oscillation frequency dispersion fOSC Oscillation start voltage Vsta (VSS) Oscillation start time tsta VSS=-1.2 to -2.0V Oscillation stop voltage Vstp (VSS) 40 Condition Min. -20 -1.2 Typ. 65kHz 3 -1.2 EPSON S1C60N03 TECHNICAL MANUAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 N.C. N.C. N.C. SEG0 N.C. N.C. N.C. N.C. N.C. SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 N.C. N.C. N.C. N.C. N.C. TEST K03 K02 K01 CHAPTER 7 64 63 PIN NO. 1 2 S1C60N03 TECHNICAL MANUAL EPSON 23.1 22.8 N.C. N.C. N.C. N.C. COM0 N.C. N.C. N.C. N.C. N.C. COM1 COM2 COM3 CA CB VS2 VSS OSC2 OSC1 VDD RESET N.C. N.C. N.C. N.C. N.C. N.C. R00 R01 R02 R03 K00 CHAPTER 7: CERAMIC PACKAGE FOR TEST SAMPLES CERAMIC PACKAGE FOR TEST SAMPLES 81.3 34 33 INDEX MARK 31 32 2.54 78.7 (Unit: mm) 41 CHAPTER 8: PRECAUTIONS ON MOUNTING CHAPTER 8 PRECAUTIONS ON MOUNTING <Oscillation Circuit> Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when using a crystal oscillator, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: (1) Components which are connected to the OSC1 and OSC2 terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. Sample VDD pattern (2) As shown in the right hand figure, make a VDD pattern as large as possible at circumscription of the OSC1 and OSC2 terminals and the components connected to these terminals. Furthermore, do not use this VDD pattern for any purpose other than the oscillation system. OSC2 OSC1 VDD In order to prevent unstable operation of the oscillation circuit due to current leak between OSC1 and VSS, please keep enough distance between OSC1 and VSS or other signals on the board pattern. <Reset Circuit> The power-on reset signal which is input to the RESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. When the built-in pull-down resistor is added to the RESET terminal by mask option, take into consideration dispersion of the resistance for setting the constant. In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the RESET terminal in the shortest line. <Power Supply Circuit> Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the VDD and VSS terminal with patterns as short and large as possible. (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. Bypass capacitor connection example VDD VDD VSS VSS (3) Components which are connected to the VS2 terminal, such as a capacitor, should be connected in the shortest line. 42 EPSON S1C60N03 TECHNICAL MANUAL CHAPTER 8: PRECAUTIONS ON MOUNTING <Arrangement of Signal Lines> In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit. When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit. Prohibited pattern OSC2 OSC1 VDD Large current signal line High-speed signal line <Precautions for Visible Radiation (when bare chip is mounted)> Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to malfunction. When developing products which use this IC, consider the following precautions to prevent malfunctions caused by visible radiations. (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. S1C60N03 TECHNICAL MANUAL EPSON 43 International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. - HEADQUARTERS - 28F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: 64106655 Fax: 64107319 1960 E. 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No. 1 Temasek Avenue, #36-00 Millenia Tower, SINGAPORE 039192 Phone: +65-337-7911 Fax: +65-334-2716 EUROPE EPSON EUROPE ELECTRONICS GmbH SEIKO EPSON CORPORATION KOREA OFFICE - HEADQUARTERS Riesstrasse 15 80992 Munich, GERMANY Phone: +49-(0)89-14005-0 Fax: +49-(0)89-14005-110 SALES OFFICE Altstadtstrasse 176 51379 Leverkusen, GERMANY Phone: +49-(0)2171-5045-0 Fax: +49-(0)2171-5045-10 UK BRANCH OFFICE Unit 2.4, Doncastle House, Doncastle Road Bracknell, Berkshire RG12 8PE, ENGLAND Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: 02-784-6027 Fax: 02-767-3677 SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION Electronic Device Marketing Department IC Marketing & Engineering Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624 ED International Marketing Department Europe & U.S.A. FRENCH BRANCH OFFICE 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Prima Sant Cugat Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 Fax: +34-93-544-2491 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110 In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. S1C60N03 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue December, 1997 Printed February, 2001 in Japan M A