Small Form Factor Copyright © 2011 by Silicon Laboratories 1.10.2011
Port 0
Latch
UART
8 kB
FLASH
256 Byte
SRAM
POR
SFR Bus
8
0
5
1
C
o
r
e
Timer
0, 1, 2 /
RTC
PCA/
WDT
8-bit
500 ksps
ADC
A
M
U
X
AIN0-AIN7
P
0
D
r
v
VREF
X
B
A
R
Reset
XTAL1
XTAL2
External
Oscillator
Circuit System Clock
2%
Internal
Oscillator
Analog/Digital
Power
Debug HW
VDD
SMBus
C2D
C2D
CP0 +
-
Temp
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7/C2D
VDD
GND
RST/C2CK
Brown-
Out
PGA
C8051F300
25 MIPS, 8 kB Flash, 8-Bit ADC, 11-Pin Mixed-Signal MCU
Analog Peripherals
8-Bit ADC
-±1 LSB INL; no missing codes
-Programmable throughput up to 500 ksps
-Up to 8 external input s; programmable as single-ended or differential
-Programmable amplifier gain: 4, 2, 1, 0.5
-VREF from exter nal pin or VDD
-Internal or external start of conversion sources
-Data-dependent windowed interrupt generator
-Built-in temperature sensor (±3 °C)
Comparator
-Programmable hysteresis and response time
-Configurable to generate int errupts or reset
-Low current (0.4 µA)
POR/Brown-Out Detector
On-Chip Debug
-On-chip debug circuitry facilitates full speed, non- intrusive in-system
debug (no emulator required)
-Provides breakpoint s, single stepping, watchpoints
-Inspect/modify memory, registers, and stack
-Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Supply Voltage: 2.7 to 3.6 V
-Typical operating current: 5.8 mA at 25 MHz
11 µA at 32 kHz
-Typical stop mode current: <0.1 µA
Temperature Range: –40 to +85 °C
High-Speed 8051 µC Core
-Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
-Up to 25 MIPS throughput with 25 MHz clock
-Expanded interrupt handler
Memory
-256 bytes data RAM
-8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
reserved)
Digita l Peripherals
-8 port I/O; all are 5 V tolera nt
-Enhanced Hardware SMBus™ (I2C™ compatible) and UART serial
ports
-Programmable 16-bit counter/timer array with three capture/compare
modules, WDT
-3 general-purpose 16-bit counter/timers
-Dedicated watchdog timer; bidirectional reset
-Real-time clock mode using PCA or timer and external clock source
Clock Sources
-Internal oscillator: 25 MHz, 2% accuracy supports UART operation
-External oscillator: Crystal, RC, C, or Clock (1 or 2 Pin Modes)
-Can switch between clock sources on-the-fly
Package
-11-pin QFN
-14-pin SOIC
Ordering Part Numbers
-Lead-free package: C8051F300-GM (QFN)
-Lead-free package: C8051F300-GS (SOIC)
Small Form Factor Copyright © 2011 by Silicon Laboratories 1.10.2011
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of the ir respective holders
C8051F300
25 MIPS, 8 kB Flash, 8-Bit ADC, 11-Pin Mixed-Signal MCU
Selected Electrical Specifications
(TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified)
PARAMETER CONDITIONS MIN TYP MAX UNITS
GLOBAL CHARACTERISTICS
Supply Voltage 2.7 3.6 V
Supply Curr ent with
CPU active Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz; VDD Monitor Disabled
5.8
0.34
11
mA
mA
µA
Supply Current (shutdown) Oscillator off; VDD Monitor Enabled
Oscillator off; VDD Monitor Disabled 10
<0.1 µA
µA
CPU & DIGITAL I/O PORTS
Clock Frequency Range DC 25 MHz
Port Output High Voltage IOH = -3 mA, Port I/O push-pull VDD – 0.7 V
Port Output Low V oltage IOL = 8.5 mA 0.6 V
Input High Voltage 0.7 x VDD V
Input Lo w Voltage 0.3 x VDD V
INTERNAL OSCILLATOR
Frequency 24.0 24.5 25.0 MHz
A/D CONVERTER
Resolution 8 bits
Integral Nonlinearity ½ 1 LSB
Differential Nonlinearity Guaranteed Monotonic ½ 1 LSB
Signal-to-Noise Plus
Distortion 49 dB
Throughput Rate 500 ksps
Input Voltage Range 0 VREF V
COMPARA TOR
Response Time M ode0 (CP+) – (CP-) = 100 mV 0.1 µs
Current Consumption Mode0 7.6 µA
Response Time Mode1 (CP+) – (CP-) = 100 mV 0.18 µs
Current Consumption Mode1 3.2 µA
Response Time Mode2 (CP+) – (CP-) = 100 mV 0.32 µs
Current Consumption Mode2 1.3 µA
Response Time Mode3 (CP+) – (CP-) = 100 mV 1 µs
Current Consumption Mode3 0.4 µA
Package Information
A1
e
A3
A2
A
Side D View
Side E View
L
be
E
D
e
E2
D2
LT
LB
k
b
D4
Bottom View
R
e
A1
A
A3
A2
b
A3
A2
A1
A
k
L
LB
LT
R
D
D2
D3
E
E2
D4
e
0.18 0.23 0.30
0.25
00.65 1.00
00.02 0.05
0.80 0.90 1.00
MIN TYP MAX
0.27
0.45 0.55 0.65
0.36
0.37
0.09
3.00
02.20 2.25
2.27
3.00
1.36
0.386
0.5
MM
D3
C8051F300DK Development Kit
