ATXMEGA256A1-AU - Atmel Corporation

Features

•High-performance, Low-power 8/16-bit Atmel® AVR® XMEGATM Microcontroller

•Non-Volatile Program and Data Memories

– 64K - 384K Bytes of In-System Self-Programmable Flash

– 4K - 8K Bytes Boot Section with Independent Lock Bits

– 2 KB - 4 KB EEPROM

– 4 KB - 32 KB Internal SRAM

External Bus Interface for up to 16M bytes SRAM

External Bus Interface for up to 128M bit SDRAM

•Peripheral Features

– Four-channel DMA Controller with support for external requests

– Eight-channel Event System

– Eight 16-bit Timer/Counters

Four Timer/Counters with 4 Output Compare or Input Capture channels

Four Timer/Counters with 2 Output Compare or Input Capture channels

High-Resolution Extension on all Timer/Counters

Advanced Waveform Extension on two Timer/Counters

– Eight USARTs

IrDA modulation/demodulation for one USART

– Four Two-Wire Interfaces with dual address match (I2C and SMBus compatible)

– Four SPI (Serial Peripheral Interface) peripherals

– AES and DES Crypto Engine

– 16-bit Real Time Counter with separate Oscillator

– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters

– Two Two-channel, 12-bit, 1 Msps Digital to Analog Converters

– Four Analog Comparators with Window compare function

– External Interrupts on all General Purpose I/O pins

– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator

•Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal and External Clock Options with PLL and Prescaler

– Programmable Multi-level Interrupt Controller

– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby

– Advanced Programming, Test and Debugging Interfaces

JTAG (IEEE 1149.1 Compliant) Interface for programming, test and debugging

PDI (Program and Debug Interface) for programming and debugging

•I/O and Packages

– 78 Programmable I/O Lines

– 100 - lead TQFP

– 100 - ball CBGA

– 100 - ball VFBGA

•Operating Voltage

– 1.6 – 3.6V

•Speed performance

– 0 – 12 MHz @ 1.6 – 3.6V

– 0 – 32 MHz @ 2.7 – 3.6V

Typical Applications

•Industrial control •Climate control •Hand-held battery applications

•Factory automation •ZigBee •Power tools

•Building control •Motor control •HVAC

•Board control •Networking •Metering

•White Goods •Optical •Medical Applications

8/16-bit

XMEGA A1

Microcontroller

ATxmega384A1

ATxmega256A1

ATxmega192A1

ATxmega128A1

ATxmega64A1

Preliminary

8067M–AVR–09/10

XMEGA A1

‘

1. Ordering Information

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

3. For packaging information, see “Packaging information” on page 64.

Ordering Code Flash (B) E2SRAM Speed (MHz) Power Supply Package(1)(2)(3) Temp

ATxmega384A1-AU 384K + 8K 4 KB 32 KB 32 1.6 - 3.6V

100A

-40°C - 85°C

ATxmega256A1-AU 256K + 8K 4 KB 16 KB 32 1.6 - 3.6V

ATxmega192A1-AU 192K + 8K 2 KB 16 KB 32 1.6 - 3.6V

ATxmega128A1-AU 128K + 8K 2 KB 8 KB 32 1.6 - 3.6V

ATxmega64A1-AU 64K + 4K 2 KB 4 KB 32 1.6 - 3.6V

ATxmega384A1-CU 384K + 8K 4 KB 32 KB 32 1.6 - 3.6V

100C1

ATxmega256A1-CU 256K + 8K 4 KB 16 KB 32 1.6 - 3.6V

ATxmega192A1-CU 192K + 8K 2 KB 16 KB 32 1.6 - 3.6V

ATxmega128A1-CU 128K + 8K 2 KB 8 KB 32 1.6 - 3.6V

ATxmega64A1-CU 64K + 4K 2 KB 4 KB 32 1.6 - 3.6V

ATxmega128A1-C7U 128K + 8K 2 KB 8 KB 32 1.6 - 3.6V 100C2

ATxmega64A1-C7U 64K + 4K 2 KB 4 KB 32 1.6 - 3.6V

Package Type

100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

100C1 100-ball, 9 x 9 x 1.2 mm Body, Ball Pitch 0.88 mm, Chip Ball Grid Array (CBGA)

100C2 100-ball, 7 x 7 x 1.0 mm Body, Ball Pitch 0.65 mm, Very Thin Fine-Pitch Ball Grid Array (VFBGA)

8067M–AVR–09/10

XMEGA A1

2. Pinout/Block Diagram

Figure 2-1. Block diagram and pinout

Notes: 1. For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 49.

2. VCC/GND on pin 83/84 are swapped compared to other VCC/GND to allow easier routing of GND to 32 kHz crystal.

INDEX CORNER

PA6

PA7

GND

AVCC

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

GND

VCC

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

GND

VCC

PD0

100

PD1

PD2

PD3

PD4

PD5

PD6

PD7

GND

VCC

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

GND

VCC

PF0

PF1

PF2

PF3

PF4

PF5

PK0

VCC

GND

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

VCC

GND

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

VCC

GND

PF7

PF6

PA5

PA4

PA3

PA2

PA1

PA0

AVCC

GND

PR1

PR0

RESET/PDI

PDI

PQ3

PQ2

PQ1

PQ0

GND

VCC

PK7

PK6

PK5

PK4

PK3

PK2

PK1

FLASH

RAM

E2PROM

DMA

Interrupt Controlle r

OCD

External Bus Interface

ADC A

ADC B

DAC B

DAC A

AC A0

AC A1

AC B0

AC B1

Port A

Port B

Event System ctrl

Port K

Port J

Port H

Port Q

Port R

Power

Contro l

Reset

Contro l

Watchdog

OSC/CLK

Contro l BOD POR

RTC

EVENT ROUTING NETWORK

DATA BU S

VREF

TEMP

Port C

CPU

T/C0:1

USART0:1

TWI

SPI

Port FPort EPort D

T/C0:1

USART0/1

TWI

SPI

T/C0:1

USART0:1

TWI

SPI

T/C0:1

USART0:1

TWI

SPI

8067M–AVR–09/10

XMEGA A1

Figure 2-2. CBGA-pinout

12345678910

10987654321

Top view Bottom view

Table 2-1. CBGA-pinout

1 2 3 4 5 6 78910

APK0 VCC GND PJ3 VCC GND PH1 GND VCC PF7

BPK3 PK2 PK1 PJ4 PH7 PH4 PH2 PH0 PF6 PF5

CVCC PK5 PK4 PJ5 PJ0 PH5 PH3 PF2 PF3 VCC

DGND PK6 PK7 PJ6 PJ1 PH6 PF0 PF1 PF4 GND

EPQ0 PQ1 PQ2 PJ7 PJ2 PE7 PE6 PE5 PE4 PE3

FPR1 PR0 RESET/

PDI PDI PQ3 PC2 PE2 PE1 PE0 VCC

GGND PA1 PA4 PB3 PB4 PC1 PC6 PD7 PD6 GND

HAVCC PA2 PA5 PB2 PB5 PC0 PC5 PD5 PD4 PD3

JPA0 PA3 PB0 PB1 PB6 PC3 PC4 PC7 PD2 PD1

KPA6 PA7 GND AVCC PB7 VCC GND VCC GND PD0

8067M–AVR–09/10

XMEGA A1

3. Overview

The Atmel® AVR® XMEGA™ A1 is a family of low power, high performance and peripheral rich

CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing

powerful instructions in a single clock cycle, the XMEGA A1 achieves throughputs approaching

1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize

power consumption versus processing speed.

The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction, executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs many times faster than conven-

tional single-accumulator or CISC based microcontrollers.

The XMEGA A1 devices provides the following features: In-System Programmable Flash with

Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,

eight-channel Event System, Programmable Multi-level Interrupt Controller, 78 general purpose

I/O lines, 16-bit Real Time Counter (RTC), eight flexible 16-bit Timer/Counters with compare

modes and PWM, eight USARTs, four Two Wire Serial Interfaces (TWIs), four Serial Peripheral

Interfaces (SPIs), AES and DES crypto engine, two 8-channel, 12-bit ADCs with optional differ-

ential input with programmable gain, two 2-channel, 12-bit DACs, four analog comparators with

window mode, programmable Watchdog Timer with seperate Internal Oscillator, accurate inter-

nal oscillators with PLL and prescaler and programmable Brown-Out Detection.

The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,

is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this

can also be used for On-chip Debug and programming.

The XMEGA A1 devices have five software selectable power saving modes. The Idle mode

stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and

all peripherals to continue functioning. The Power-down mode saves the SRAM and register

contents but stops the oscillators, disabling all other functions until the next TWI or pin-change

interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run,

allowing the application to maintain a timer base while the rest of the device is sleeping. In

Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is

sleeping. This allows very fast start-up from external crystal combined with low power consump-

tion. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue

to run. To further reduce power consumption, the peripheral clock to each individual peripheral

can optionally be stopped in Active mode and Idle sleep mode.

The device is manufactured using Atmel's high-density nonvolatile memory technology. The pro-

gram Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader

running in the device can use any interface to download the application program to the Flash

memory. The Bootloader software in the Boot Flash section will continue to run while the Appli-

cation Flash section is updated, providing true Read-While-Write operation. By combining an

8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A1 is a power-

ful microcontroller family that provides a highly flexible and cost effective solution for many

embedded applications.

The XMEGA A1 devices are supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, programmers,

and evaluation kits.

8067M–AVR–09/10

XMEGA A1

3.1 Block Diagram

Figure 3-1. XMEGA A1 Block Diagram

Power

Supervision

POR/BOD &

RESET

PORT A (8)

PORT B (8)

EVENT ROUTING NETWORK

DMA

Controller

BUS

Controller

SRAM

EBI

ADCA

DACA

ACA

DACB

ADCB

ACB

OCD

Int. Ref.

PORT K (8)

PORT J (8)

PORT H (8)

PDI

CPU

PH[0..7]

PJ[0..7]

PK[0..7]

PA[0..7]

PB[0..7]/

JTAG

Watchdog

Timer

Watchdog

Oscillator

Interrupt

Controller

DATA BUS

Prog/Debug

Controller

VCC

GND

Oscillator

Circuits/

Clock

Generation

Oscillator

Control

Real Time

Counter

Event System

Controller

JTAG

AREFA

AREFB

PDI_DATA

RESET/

PDI_CLK

PORT B

Sleep

Controller

Flash EEPROM

NVM Controller

DES

AES

IRCOM

PORT C (8)

PC[0..7]

TCC0:1

USARTC0:1

TWIC

SPIC

PD[0..7] PE[0..7] PF[0..7]

PORT R (2)

XTAL1

XTAL2

PR[0..1]

TOSC1

TOSC2

PQ[0..3]

PORT Q (4)

PORT D (8)

TCD0:1

USARTD0:1

TWID

SPID

TCF0:1

USARTF0:1

TWIF

SPIF

TCE0:1

USARTE0:1

TWIE

SPIE

PORT E (8) PORT F (8)

Tempref

VCC/10

8067M–AVR–09/10

XMEGA A1

4. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

4.1 Recommended reading

• XMEGA A Manual

• XMEGA A Application Notes

This device data sheet only contains part specific information and a short description of each

peripheral and module. The XMEGA A Manual describes the modules and peripherals in depth.

The XMEGA A application notes contain example code and show applied use of the modules

and peripherals.

The XMEGA A Manual and Application Notes are available from http://www.atmel.com/avr.

5. Disclaimer

For devices that are not available yet, typical values contained in this datasheet are based on

simulations and characterization of other AVR XMEGA microcontrollers manufactured on the

same process technology. Min. and Max values will be available after the device is

characterized.

8067M–AVR–09/10

XMEGA A1

6. AVR CPU

6.1 Features

•8/16-bit high performance AVR RISC Architecture

– 138 instructions

– Hardware multiplier

•32x8-bit registers directly connected to the ALU

•Stack in SRAM

•Stack Pointer accessible in I/O memory space

•Direct addressing of up to 16M Bytes of program and data memory

•True 16/24-bit access to 16/24-bit I/O registers

•Support for 8-, 16- and 32-bit Arithmetic

•Configuration Change Protection of system critical features

6.2 Overview

The XMEGA A1 uses the 8/16-bit AVR CPU. The main function of the CPU is program execu-

tion. The CPU must therefore be able to access memories, perform calculations and control

peripherals. Interrupt handling is described in a separate section. Figure 6-1 on page 8 shows

the CPU block diagram.

Figure 6-1. CPU block diagram

The AVR uses a Harvard architecture - with separate memories and buses for program and

data. Instructions in the program memory are executed with a single level pipeline. While one

instruction is being executed, the next instruction is pre-fetched from the program memory. This

Flash

Program

Memory

Instruction

Decode

Program

Counter

OCD

32 x 8 General

Purpose

Registers

ALU Multiplier/

DES

Instruction

STATUS/

CONTROL

Peripheral

Module 1

Peripheral

Module 2 EEPROM PMICSRAM

DATA BUS

8067M–AVR–09/10

XMEGA A1

concept enables instructions to be executed in every clock cycle. The program memory is In-

System Self-Programmable Flash memory.

6.3 Register File

The fast-access Register File contains 32 x 8-bit general purpose working registers with single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU cycle, the operation is performed on two Register File operands, and the result is stored

back in the Register File.

Six of the 32 registers can be used as three 16-bit address register pointers for data space

addressing - enabling efficient address calculations. One of these address pointers can also be

used as an address pointer for look up tables in Flash program memory.

6.4 ALU - Arithmetic Logic Unit

The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations

between registers or between a constant and a register. Single register operations can also be

executed. Within a single clock cycle, arithmetic operations between general purpose registers

or between a register and an immediate are executed. After an arithmetic or logic operation, the

Status Register is updated to reflect information about the result of the operation.

The ALU operations are divided into three main categories – arithmetic, logical, and bit-func-

tions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient

implementation of 32-bit aritmetic. The ALU also provides a powerful multiplier supporting both

signed and unsigned multiplication and fractional format.

6.5 Program Flow

When the device is powered on, the CPU starts to execute instructions from the lowest address

in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to

be fetched. After a reset, the PC is set to location ‘0’.

Program flow is provided by conditional and unconditional jump and call instructions, capable of

addressing the whole address space directly. Most AVR instructions use a 16-bit word format,

while a limited number uses a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack

is effectively allocated in the general data SRAM, and consequently the Stack size is only limited

by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to

the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory

space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can

easily be accessed through the five different addressing modes supported in the AVR CPU.

8067M–AVR–09/10

XMEGA A1

7. Memories

7.1 Features

•Flash Program Memory

– One linear address space

– In-System Programmable

– Self-Programming and Bootloader support

– Application Section for application code

– Application Table Section for application code or data storage

– Boot Section for application code or bootloader code

– Separate lock bits and protection for all sections

– Built in fast CRC check of a selectable flash program memory section

•Data Memory

– One linear address space

– Single cycle access from CPU

– SRAM

– EEPROM

Byte and page accessible

Optional memory mapping for direct load and store

– I/O Memory

Configuration and Status registers for all peripherals and modules

16 bit-accessible General Purpose Register for global variables or flags

– External Memory support

SRAM

SDRAM

Memory mapped external hardware

– Bus arbitration

Safe and deterministic handling of CPU and DMA Controller priority

– Separate buses for SRAM, EEPROM, I/O Memory and External Memory access

Simultaneous bus access for CPU and DMA Controller

•Production Signature Row Memory for factory programmed data

Device ID for each microcontroller device type

Serial number for each device

Oscillator calibration bytes

ADC, DAC and temperature sensor calibration data

•User Signature Row

One flash page in size

Can be read and written from software

Content is kept after chip erase

7.2 Overview

The AVR architecture has two main memory spaces, the Program Memory and the Data Mem-

ory. In addition, the XMEGA A1 features an EEPROM Memory for non-volatile data storage. All

three memory spaces are linear and require no paging. The available memory size configura-

tions are shown in “Ordering Information” on page 2. In addition each device has a Flash

memory signature row for calibration data, device identification, serial number etc.

Non-volatile memory spaces can be locked for further write or read/write operations. This pre-

vents unrestricted access to the application software.

8067M–AVR–09/10

XMEGA A1

7.3 In-System Programmable Flash Program Memory

The XMEGA A1 devices contain On-chip In-System Programmable Flash memory for program

storage, see Figure 7-1 on page 11. Since all AVR instructions are 16- or 32-bits wide, each

Flash address location is 16 bits.

The Program Flash memory space is divided into Application and Boot sections. Both sections

have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Pro-

gram Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash

memory.

A third section inside the Application section is referred to as the Application Table section which

has separate Lock bits for storage of write or read/write protection. The Application Table sec-

tion can be used for storing non-volatile data or application software.

The Application Table Section and Boot Section can also be used for general application

software.

7.4 Data Memory

The Data Memory consists of the I/O Memory, EEPROM and SRAM memories, all within one

linear address space, see Figure 7-2 on page 11. To simplify development, the memory map for

all devices in the family is identical and with empty, reserved memory space for smaller devices.

Figure 7-1. Flash Program Memory (Hexadecimal address)

Word Address

0Application Section (Bytes)

(384K/256K/192K/128K/64K)

...

2EFFF / 1EFFF / 16FFF / EFFF / 77FF

2F000 / 1F000 / 17000 / F000 / 7800 Application Table Section (Bytes)

(8K/8K/8K/8K/4K)

2FFFF / 1FFFF / 17FFF / FFFF / 7FFF

30000 / 20000 / 18000 / 10000 / 8000 Boot Section (Bytes)

(8K/8K/8K/8K/4K)

30FFF / 20FFF / 18FFF / 10FFF / 87FF

Figure 7-2. Data Memory Map (Hexadecimal address)

Byte Address ATxmega192A1 Byte Address ATxmega128A1 Byte Address ATxmega64A1

0I/O Registers

(4 KB)

0I/O Registers

(4 KB)

0I/O Registers

(4 KB)

FFF FFF FFF

1000 EEPROM

(2 KB)

1000 EEPROM

(2 KB)

1000 EEPROM

(2 KB)

17FF 17FF 17FF

RESERVED RESERVED RESERVED

8067M–AVR–09/10

XMEGA A1

7.4.1 I/O Memory

All peripherals and modules are addressable through I/O memory locations in the data memory

space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store

(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the

CPU and the I/O Memory.

The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F

directly.

I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and

CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-

tions on these registers.

The I/O memory address for all peripherals and modules in XMEGA A1 is shown in the “Periph-

eral Module Address Map” on page 58.

7.4.2 SRAM Data Memory

The XMEGA A1 devices has internal SRAM memory for data storage.

7.4.3 EEPROM Data Memory

The XMEGA A1 devices have internal EEPROM memory for non-volatile data storage. It is

addressable either in a separate data space or it can be memory mapped into the normal data

memory space. The EEPROM memory supports both byte and page access.

2000 Internal SRAM

(16 KB)

2000 Internal SRAM

(8 KB)

2000 Internal SRAM

(4 KB)

5FFF 3FFF 2FFF

6000 External Memory

(0 to 16 MB)

4000 External Memory

(0 to 16 MB)

3000 External Memory

(0 to 16 MB)

FFFFFF FFFFFF FFFFFF

Byte Address ATxmega384A1 Byte Address ATxmega256A1

0I/O Registers

(4 KB)

0I/O Registers

(4 KB)

FFF FFF

1000

EEPROM

(4 KB)

1000

EEPROM

(4 KB)

1FFF 1FFF

2000 Internal SRAM

(32 KB)

2000 Internal SRAM

(16 KB)

9FFF 5FFF

10000 External Memory

(0 to 16 MB)

6000 External Memory

(0 to 16 MB)

FFFFFF FFFFFF

Figure 7-2. Data Memory Map (Hexadecimal address)

8067M–AVR–09/10

XMEGA A1

7.4.4 EBI - External Bus Interface

•Supports SRAM up to

– 512K Bytes using 2-port EBI

– 16M Bytes using 3-port EBI

•Supports SDRAM up to

– 128M bit using 3-port EBI

•Four software configurable Chip Selects

•Software configurable Wait State insertion

•Clocked from the Peripheral 2x Clock at up to two times the CPU clock speed

The External Bus Interface (EBI) is the interface for connecting external peripheral and memory

to the data memory space. The XMEGA A1 has 3 ports that can be used for the EBI. It can inter-

face external SRAM, SDRAM, and/or peripherals such as LCD displays and other memory

mapped devices.

The address space, and the number of pins used, for the external memory is selectable from

256 bytes (8-bit) and up to 16M bytes (24-bit). Various multiplexing modes for address and data

lines can be selected for optimal use of pins when more or less pins is available for the EBI.

Each of the four chip selects has seperate configuration, and can be configured for SRAM,

SRAM Low Pin Count (LPC) or SDRAM. The data memory address space associated for each

chip select is decided by a configurable base address and address size for each chip celect.

For SDRAM both 4-bit SDRAM is supported, and SDRAM configurations such as CAS Latency

and Refresh rate is configurable in software.

The EBI is clocked from the Peripheral 2x Clock, running up to two times faster than the CPU

and supporting speeds of up to 64 MHz.

8067M–AVR–09/10

XMEGA A1

7.5 Production Signature Row

The Production Signature Row is a separate memory section for factory programmed data. It

contains calibration data for functions such as oscillators and analog modules.

The production signature row also contains a device ID that identify each microcontroller device

type, and a serial number that is unique for each manufactured device. The device ID for the

available XMEGA A1 devices is shown in Table 7-1 on page 14. The serial number consist of

the production LOT number, wafer number, and wafer coordinates for the device.

The production signature row can not be written or erased, but it can be read from both applica-

tion software and external programming.

Table 7-1. Device ID bytes for XMEGA A1 devices.

7.6 User Signature Row

The User Signature Row is a separate memory section that is fully accessible (read and write)

from application software and external programming. The user signature row is one flash page

in size, and is meant for static user parameter storage, such as calibration data, custom serial

numbers or identification numbers, random number seeds etc. This section is not erased by

Chip Erase commands that erase the Flash, and requires a dedicated erase command. This

ensures parameter storage during multiple program/erase session and on-chip debug sessions.

Device Device ID bytes

Byte 2 Byte 1 Byte 0

ATxmega64A1 4E 96 1E

ATxmega128A1 4C 97 1E

ATxmega192A1 4E 97 1E

ATxmega256A1 46 98 1E

ATxmega384A1 TBD TBD TBD

8067M–AVR–09/10

XMEGA A1

7.7 Flash and EEPROM Page Size

The Flash Program Memory and EEPROM data memory is organized in pages. The pages are

word accessible for the Flash and byte accessible for the EEPROM.

Table 7-2 on page 15 shows the Flash Program Memory organization. Flash write and erase

operations are performed on one page at a time, while reading the Flash is done one byte at a

time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in

the address (FPAGE) gives the page number and the least significant address bits (FWORD)

gives the word in the page.

Table 7-2. Number of words and Pages in the Flash.

Table 7-3 on page 15 shows EEPROM memory organization for the XMEGA A1 devices.

EEPROM write and erase operations can be performed one page or one byte at a time, while

reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Regis-

ter (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) gives

the page number and the least significant address bits (E2BYTE) gives the byte in the page.

Table 7-3. Number of Bytes and Pages in the EEPROM.

Devices Flash Page Size FWORD FPAGE Application Boot

Size (Bytes) (words) Size (Bytes) No of Pages Size (Bytes) No of Pages

ATxmega64A1 64K + 4K 128 Z[7:1] Z[16:8] 64K 256 4K 16

ATxmega128A1 128K + 8K 256 Z[8:1] Z[17:9] 128K 256 8K 16

ATxmega192A1 192K + 8K 256 Z[8:1] Z[18:9] 192K 384 8K 16

ATxmega256A1 256K + 8K 256 Z[8:1] Z[18:9] 256K 512 8K 16

ATxmega384A1 384K + 8K 256 Z[8:1] Z[19:9] 384K 768 8K 16

Devices EEPROM Page Size E2BYTE E2PAGE No of Pages

Size (Bytes)

ATxmega64A1 2 KB 32 ADDR[4:0] ADDR[10:5] 64

ATxmega128A1 2 KB 32 ADDR[4:0] ADDR[10:5] 64

ATxmega192A1 2 KB 32 ADDR[4:0] ADDR[10:5] 64

ATxmega256A1 4 KB 32 ADDR[4:0] ADDR[11:5] 128

ATxmega384A1 4 KB 32 ADDR[4:0] ADDR[11:5] 128

8067M–AVR–09/10

XMEGA A1

8. DMAC - Direct Memory Access Controller

8.1 Features

•Allows High-speed data transfer

– From memory to peripheral

– From memory to memory

– From peripheral to memory

– From peripheral to peripheral

•4 Channels

•From 1 byte and up to 16M bytes transfers in a single transaction

•Multiple addressing modes for source and destination address

–Increment

– Decrement

– Static

•1, 2, 4, or 8 byte Burst Transfers

•Programmable priority between channels

8.2 Overview

The XMEGA A1 has a Direct Memory Access (DMA) Controller to move data between memories

and peripherals in the data space. The DMA controller uses the same data bus as the CPU to

transfer data.

It has 4 channels that can be configured independently. Each DMA channel can perform data

transfers in blocks of configurable size from 1 to 64K bytes. A repeat counter can be used to

repeat each block transfer for single transactions up to 16M bytes. Each DMA channel can be

configured to access the source and destination memory address with incrementing, decrement-

ing or static addressing. The addressing is independent for source and destination address.

When the transaction is complete the original source and destination address can automatically

be reloaded to be ready for the next transaction.

The DMAC can access all the peripherals through their I/O memory registers, and the DMA may

be used for automatic transfer of data to/from communication modules, as well as automatic

data retrieval from ADC conversions, data transfer to DAC conversions, or data transfer to or

from port pins. A wide range of transfer triggers is available from the peripherals, Event System

and software. Each DMA channel has different transfer triggers.

To allow for continuous transfers, two channels can be interlinked so that the second takes over

the transfer when the first is finished and vice versa.

The DMA controller can read from memory mapped EEPROM, but it cannot write to the

EEPROM or access the Flash.

8067M–AVR–09/10

XMEGA A1

9. Event System

9.1 Features

•Inter-peripheral communication and signalling with minimum latency

•CPU and DMA independent operation

•8 Event Channels allows for up to 8 signals to be routed at the same time

•Events can be generated by

– Timer/Counters (TCxn)

– Real Time Counter (RTC)

– Analog to Digital Converters (ADCx)

– Analog Comparators (ACx)

– Ports (PORTx)

– System Clock (ClkSYS)

– Software (CPU)

•Events can be used by

– Timer/Counters (TCxn)

– Analog to Digital Converters (ADCx)

– Digital to Analog Converters (DACx)

– Ports (PORTx)

– DMA Controller (DMAC)

– IR Communication Module (IRCOM)

•The same event can be used by multiple peripherals for synchronized timing

•Advanced Features

– Manual Event Generation from software (CPU)

– Quadrature Decoding

– Digital Filtering

•Functions in Active and Idle mode

9.2 Overview

The Event System is a set of features for inter-peripheral communication. It enables the possibil-

ity for a change of state in one peripheral to automatically trigger actions in one or more

peripherals. These changes in a peripheral that will trigger actions in other peripherals are con-

figurable by software. It is a simple, but powerful system as it allows for autonomous control of

peripherals without any use of interrupts, CPU or DMA resources.

The indication of a change in a peripheral is referred to as an event, and is usually the same as

the interrupt conditions for that peripheral. Events are passed between peripherals using a dedi-

cated routing network called the Event Routing Network. Figure 9-1 on page 18 shows a basic

block diagram of the Event System with the Event Routing Network and the peripherals to which

it is connected. This highly flexible system can be used for simple routing of signals, pin func-

tions or for sequencing of events.

The maximum latency is two CPU clock cycles from when an event is generated in one periph-

eral, until the actions are triggered in one or more other peripherals.

The Event System is functional in both Active and Idle modes.

8067M–AVR–09/10

XMEGA A1

Figure 9-1. Event system block diagram.

The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators

(ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Com-

munication Module (IRCOM). Events can also be generated from software (CPU).

All events from all peripherals are always routed into the Event Routing Network. This consist of

eight multiplexers where each can be configured in software to select which event to be routed

into that event channel. All eight event channels are connected to the peripherals that can use

events, and each of these peripherals can be configured to use events from one or more event

channels to automatically trigger a software selectable action.

ADCx

DACx

Event Routing

Network

PORTx CPU

ACx

RTC

T/Cxn DMACIRCOM

ClkSYS

8067M–AVR–09/10

XMEGA A1

10. System Clock and Clock options

10.1 Features

•Fast start-up time

•Safe run-time clock switching

•Internal Oscillators:

– 32 MHz run-time calibrated RC oscillator

– 2 MHz run-time calibrated RC oscillator

– 32.768 kHz calibrated RC oscillator

– 32 kHz Ultra Low Power (ULP) oscillator with 1 kHz ouput

•External clock options

– 0.4 - 16 MHz Crystal Oscillator

– 32 kHz Crystal Oscillator

– External clock

•PLL with internal and external clock options with 1 to 31x multiplication

•Clock Prescalers with 1 to 2048x division

•Fast peripheral clock running at 2 and 4 times the CPU clock speed

•Automatic Run-Time Calibration of internal oscillators

•Crystal Oscillator failure detection

10.2 Overview

XMEGA A1 has an advanced clock system, supporting a large number of clock sources. It incor-

porates both integrated oscillators, external crystal oscillators and resonators. A high frequency

Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a

wide range of clock frequencies from the clock source input.

It is possible to switch between clock sources from software during run-time. After reset the

device will always start up running from the 2 Mhz internal oscillator.

A calibration feature is available, and can be used for automatic run-time calibration of the inter-

nal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature.

A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and

switch to internal oscillator if the external oscillator fails. Figure 10-1 on page 20 shows the prin-

cipal clock system in XMEGA A1.

8067M–AVR–09/10

XMEGA A1

Figure 10-1. Clock system overview

Each clock source is briefly described in the following sub-sections.

10.3 Clock Options

10.3.1 32 kHz Ultra Low Power Internal Oscillator

The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock

source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock

source for the Real Time Counter. This oscillator cannot be used as the system clock source,

and it cannot be directly controlled from software.

10.3.2 32.768 kHz Calibrated Internal Oscillator

The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used

as the system clock source or as an asynchronous clock source for the Real Time Counter. It is

calibrated during production to provide a default frequency which is close to its nominal

frequency.

32 MHz

Run-time Calibrated

Internal Oscillator

32 kHz ULP

Internal Oscillator

32.768 kHz

Calibrated Internal

Oscillator

32.768 KHz

Crystal Oscillator

0.4 - 16 MHz

Crystal Oscillator

2 MHz

Run-Time Calibrated

Internal Oscillator

External

Clock Input

CLOCK CONTROL

UNIT

with PLL and

Prescaler

WDT/BOD

clkULP

RTC

clkRTC

EVSYS

PERIPHERALS

ADC

DAC

PORTS

...

clkPER

DMA

INTERRUPT

RAM

NVM MEMORY

FLASH

EEPROM

CPU

clkCPU

8067M–AVR–09/10

XMEGA A1

10.3.3 32.768 kHz Crystal Oscillator

The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be

used as system clock source or as asynchronous clock source for the Real Time Counter.

10.3.4 0.4 - 16 MHz Crystal Oscillator

The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and

crystals ranging from 400 kHz to 16 MHz.

10.3.5 2 MHz Run-time Calibrated Internal Oscillator

The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated

during productionn to provide a default frequency which is close to its nominal frequency. The

oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a

source for calibrating the frequency run-time to compensate for temperature and voltage drift

hereby optimizing the accuracy of the oscillator.

10.3.6 32 MHz Run-time Calibrated Internal Oscillator

The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated

during production to provide a default frequency which is close to its nominal frequency. The

oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a

source for calibrating the frequency run-time to compensate for temperature and voltage drift

hereby optimizing the accuracy of the oscillator.

10.3.7 External Clock input

The external clock input gives the possibility to connect a clock from an external source.

10.3.8 PLL with Multiplication factor 1 - 31x

The PLL provides the possibility of multiplying a frequency by any number from 1 to 31. In com-

bination with the prescalers, this gives a wide range of output frequencies from all clock sources.

8067M–AVR–09/10

XMEGA A1

11. Power Management and Sleep Modes

11.1 Features

•5 sleep modes

–Idle

– Power-down

–Power-save

–Standby

– Extended standby

•Power Reduction registers to disable clocks to unused peripherals

11.2 Overview

The XMEGA A1 provides various sleep modes tailored to reduce power consumption to a mini-

mum. All sleep modes are available and can be entered from Active mode. In Active mode the

CPU is executing application code. The application code decides when and what sleep mode to

enter. Interrupts from enabled peripherals and all enabled reset sources can restore the micro-

controller from sleep to Active mode.

In addition, Power Reduction registers provide a method to stop the clock to individual peripher-

als from software. When this is done, the current state of the peripheral is frozen and there is no

power consumption from that peripheral. This reduces the power consumption in Active mode

and Idle sleep mode.

11.3 Sleep Modes

11.3.1 Idle Mode

In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the

Interrupt Controller, Event System and DMA Controller are kept running. Interrupt requests from

all enabled interrupts will wake the device.

11.3.2 Power-down Mode

In Power-down mode all system clock sources, and the asynchronous Real Time Counter (RTC)

clock source, are stopped. This allows operation of asynchronous modules only. The only inter-

rupts that can wake up the MCU are the Two Wire Interface address match interrupts, and

asynchronous port interrupts, e.g pin change.

11.3.3 Power-save Mode

Power-save mode is identical to Power-down, with one exception: If the RTC is enabled, it will

keep running during sleep and the device can also wake up from RTC interrupts.

11.3.4 Standby Mode

Standby mode is identical to Power-down with the exception that all enabled system clock

sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces

the wake-up time when external crystals or resonators are used.

11.3.5 Extended Standby Mode

Extended Standby mode is identical to Power-save mode with the exception that all enabled

system clock sources are kept running while the CPU and Peripheral clocks are stopped. This

reduces the wake-up time when external crystals or resonators are used.

8067M–AVR–09/10

XMEGA A1

12. System Control and Reset

12.1 Features

•Multiple reset sources for safe operation and device reset

– Power-On Reset

– External Reset

– Watchdog Reset

The Watchdog Timer runs from separate, dedicated oscillator

– Brown-Out Reset

Accurate, programmable Brown-Out levels

– PDI reset

– Software reset

•Asynchronous reset

– No running clock in the device is required for reset

•Reset status register

12.2 Resetting the AVR

During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Appli-

cation execution starts from the Reset Vector. The instruction placed at the Reset Vector should

be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector

address is the lowest Flash program memory address, ‘0’, but it is possible to move the Reset

Vector to the first address in the Boot Section.

The I/O ports of the AVR are immediately tri-stated when a reset source goes active.

The reset functionality is asynchronous, so no running clock is required to reset the device.

After the device is reset, the reset source can be determined by the application by reading the

Reset Status Register.

12.3 Reset Sources

12.3.1 Power-On Reset

The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.

12.3.2 External Reset

The MCU is reset when a low level is present on the RESET pin.

12.3.3 Watchdog Reset

The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled.

The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For

more details see “WDT - Watchdog Timer” on page 24.

12.3.4 Brown-Out Reset

The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage

and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.

12.3.5 PDI reset

The MCU can be reset through the Program and Debug Interface (PDI).

8067M–AVR–09/10

XMEGA A1

12.3.6 Software reset

The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.

12.4 WDT - Watchdog Timer

12.4.1 Features

•11 selectable timeout periods, from 8 ms to 8s.

•Two operation modes

– Standard mode

– Window mode

•Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator

•Configuration lock to prevent unwanted changes

12.4.2 Overview

The XMEGA A1 has a Watchdog Timer (WDT). The WDT will run continuously when turned on

and if the Watchdog Timer is not reset within a software configurable time-out period, the micro-

controller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset

the WDT, and prevent microcontroller reset.

The WDT has a Window mode. In this mode the WDR instruction must be run within a specified

period called a window. Application software can set the minimum and maximum limits for this

window. If the WDR instruction is not executed inside the window limits, the microcontroller will

be reset.

A protection mechanism using a timed write sequence is implemented in order to prevent

unwanted enabling, disabling or change of WDT settings.

For maximum safety, the WDT also has an Always-on mode. This mode is enabled by program-

ming a fuse. In Always-on mode, application software can not disable the WDT.

8067M–AVR–09/10

XMEGA A1

13. PMIC - Programmable Multi-level Interrupt Controller

13.1 Features

•Separate interrupt vector for each interrupt

•Short, predictable interrupt response time

•Programmable Multi-level Interrupt Controller

– 3 programmable interrupt levels

– Selectable priority scheme within low level interrupts (round-robin or fixed)

– Non-Maskable Interrupts (NMI)

•Interrupt vectors can be moved to the start of the Boot Section

13.2 Overview

XMEGA A1 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can

define three different priority levels for interrupts; high, medium or low. Medium level interrupts

may interrupt low level interrupt service routines. High level interrupts may interrupt both low-

and medium level interrupt service routines. Low level interrupts have an optional round robin

scheme to make sure all interrupts are serviced within a certain amount of time.

The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).

13.3 Interrupt vectors

When an interrupt is serviced, the program counter will jump to the interrupt vector address. The

interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for

specific interrupts in each peripheral. The base addresses for the XMEGA A1 devices are shown

in Table 13-1. Offset addresses for each interrupt available in the peripheral are described for

each peripheral in the XMEGA A manual. For peripherals or modules that have only one inter-

rupt, the interrupt vector is shown in Table 13-1. The program address is the word address.

Table 13-1. Reset and Interrupt Vectors

Program Address

(Base Address) Source Interrupt Description

0x000 RESET

0x002 OSCF_INT_vect Crystal Oscillator Failure Interrupt vector (NMI)

0x004 PORTC_INT_base Port C Interrupt base

0x008 PORTR_INT_base Port R Interrupt base

0x00C DMA_INT_base DMA Controller Interrupt base

0x014 RTC_INT_base Real Time Counter Interrupt base

0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base

0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base

0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base

0x030 SPIC_INT_vect SPI on port C Interrupt vector

0x032 USARTC0_INT_base USART 0 on port C Interrupt base

0x038 USARTC1_INT_base USART 1 on port C Interrupt base

0x03E AES_INT_vect AES Interrupt vector

8067M–AVR–09/10

XMEGA A1

0x040 NVM_INT_base Non-Volatile Memory Interrupt base

0x044 PORTB_INT_base Port B Interrupt base

0x048 ACB_INT_base Analog Comparator on Port B Interrupt base

0x04E ADCB_INT_base Analog to Digital Converter on Port B Interrupt base

0x056 PORTE_INT_base Port E Interrupt base

0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base

0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base

0x06A TCE1_INT_base Timer/Counter 1 on port E Interrupt base

0x072 SPIE_INT_vect SPI on port E Interrupt vector

0x074 USARTE0_INT_base USART 0 on port E Interrupt base

0x07A USARTE1_INT_base USART 1 on port E Interrupt base

0x080 PORTD_INT_base Port D Interrupt base

0x084 PORTA_INT_base Port A Interrupt base

0x088 ACA_INT_base Analog Comparator on Port A Interrupt base

0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base

0x096 TWID_INT_base Two-Wire Interface on Port D Interrupt base

0x09A TCD0_INT_base Timer/Counter 0 on port D Interrupt base

0x0A6 TCD1_INT_base Timer/Counter 1 on port D Interrupt base

0x0AE SPID_INT_vector SPI on port D Interrupt vector

0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base

0x0B6 USARTD1_INT_base USART 1 on port D Interrupt base

0x0BC PORTQ_INT_base Port Q INT base

0x0C0 PORTH_INT_base Port H INT base

0x0C4 PORTJ_INT_base Port J INT base

0x0C8 PORTK_INT_base Port K INT base

0x0D0 PORTF_INT_base Port F INT base

0x0D4 TWIF_INT_base Two-Wire Interface on Port F INT base

0x0D8 TCF0_INT_base Timer/Counter 0 on port F Interrupt base

0x0E4 TCF1_INT_base Timer/Counter 1 on port F Interrupt base

0x0EC SPIF_INT_vector SPI ion port F Interrupt base

0x0EE USARTF0_INT_base USART 0 on port F Interrupt base

0x0F4 USARTF1_INT_base USART 1 on port F Interrupt base

Table 13-1. Reset and Interrupt Vectors (Continued)

Program Address

(Base Address) Source Interrupt Description

8067M–AVR–09/10

XMEGA A1

14. I/O Ports

14.1 Features

•Selectable input and output configuration for each pin individually

•Flexible pin configuration through dedicated Pin Configuration Register

•Synchronous and/or asynchronous input sensing with port interrupts and events

– Sense both edges

– Sense rising edges

– Sense falling edges

– Sense low level

•Asynchronous wake-up from all input sensing configurations

•Two port interrupts with flexible pin masking

•Highly configurable output driver and pull settings:

– Totem-pole

– Pull-up/-down

– Wired-AND

– Wired-OR

– Bus-keeper

– Inverted I/O

•Optional Slew rate control

•Configuration of multiple pins in a single operation

•Read-Modify-Write (RMW) support

•Toggle/clear/set registers for Output and Direction registers

•Clock output on port pin

•Event Channel 0 output on port pin 7

•Mapping of port registers (virtual ports) into bit accessible I/O memory space

14.2 Overview

The XMEGA A1 devices have flexible General Purpose I/O Ports. A port consists of up to 8 pins,

ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asyn-

chronous input sensing, pin change interrupts and configurable output settings. All functions are

individual per pin, but several pins may be configured in a single operation.

14.3 I/O configuration

All port pins (Pn) have programmable output configuration. In addition, all port pins have an

inverted I/O function. For an input, this means inverting the signal between the port pin and the

pin register. For an output, this means inverting the output signal between the port register and

the port pin. The inverted I/O function can be used also when the pin is used for alternate func-

tions. The port pins also have configurable slew rate limitation to reduce electromagnetic

emission.

8067M–AVR–09/10

XMEGA A1

14.3.1 Push-pull

Figure 14-1. I/O configuration - Totem-pole

14.3.2 Pull-down

Figure 14-2. I/O configuration - Totem-pole with pull-down (on input)

14.3.3 Pull-up

Figure 14-3. I/O configuration - Totem-pole with pull-up (on input)

14.3.4 Bus-keeper

The bus-keeper’s weak output produces the same logical level as the last output level. It acts as

a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.

INn

OUTn

DIRn

INn

OUTn

DIRn

INn

OUTn

DIRn

8067M–AVR–09/10

XMEGA A1

Figure 14-4. I/O configuration - Totem-pole with bus-keeper

14.3.5 Others

Figure 14-5. Output configuration - Wired-OR with optional pull-down

Figure 14-6. I/O configuration - Wired-AND with optional pull-up

INn

OUTn

DIRn

INn

OUTn

INn

OUTn

8067M–AVR–09/10

XMEGA A1

14.4 Input sensing

•Sense both edges

•Sense rising edges

•Sense falling edges

•Sense low level

Input sensing is synchronous or asynchronous depending on the enabled clock for the ports,

and the configuration is shown in Figure 14-7 on page 30.

Figure 14-7. Input sensing system overview

When a pin is configured with inverted I/O the pin value is inverted before the input sensing.

14.5 Port Interrupt

Each ports have two interrupts with seperate priority and interrupt vector. All pins on the port can

be individually selected as source for each of the interrupts. The interrupts are then triggered

according to the input sense configuration for each pin configured as source for the interrupt.

14.6 Alternate Port Functions

In addition to the input/output functions on all port pins, most pins have alternate functions. This

means that other modules or peripherals connected to the port can use the port pins for their

functions, such as communication or pulse-width modulation. “Pinout and Pin Functions” on

page 49 shows which modules on peripherals that enables alternate functions on a pin, and

what alternate functions that is available on a pin.

INVERTED I/O

Interrupt

Control IREQ

Event

Synchronizer

INn

EDGE

DETECT

Asynchronous sensing

Synchronous sensing

EDGE

DETECT

8067M–AVR–09/10

XMEGA A1

15. T/C - 16-bit Timer/Counter

15.1 Features

•Eight 16-bit Timer/Counters

– Four Timer/Counters of type 0

– Four Timer/Counters of type 1

•Four Compare or Capture (CC) Channels in Timer/Counter 0

•Two Compare or Capture (CC) Channels in Timer/Counter 1

•Double Buffered Timer Period Setting

•Double Buffered Compare or Capture Channels

•Waveform Generation:

– Single Slope Pulse Width Modulation

– Dual Slope Pulse Width Modulation

– Frequency Generation

•Input Capture:

– Input Capture with Noise Cancelling

– Frequency capture

– Pulse width capture

– 32-bit input capture

•Event Counter with Direction Control

•Timer Overflow and Timer Error Interrupts and Events

•One Compare Match or Capture Interrupt and Event per CC Channel

•Supports DMA Operation

•Hi-Resolution Extension (Hi-Res)

•Advanced Waveform Extension (AWEX)

15.2 Overview

XMEGA A1 has eight Timer/Counters, four Timer/Counter 0 and four Timer/Counter 1. The dif-

ference between them is that Timer/Counter 0 has four Compare/Capture channels, while

Timer/Counter 1 has two Compare/Capture channels.

The Timer/Counters (T/C) are 16-bit and can count any clock, event or external input in the

microcontroller. A programmable prescaler is available to get a useful T/C resolution. Updates of

Timer and Compare registers are double buffered to ensure glitch free operation. Single slope

PWM, dual slope PWM and frequency generation waveforms can be generated using the Com-

pare Channels.

Through the Event System, any input pin or event in the microcontroller can be used to trigger

input capture, hence no dedicated pins is required for this. The input capture has a noise cancel-

ler to avoid incorrect capture of the T/C, and can be used to do frequency and pulse width

measurements.

A wide range of interrupt or event sources are available, including T/C Overflow, Compare

match and Capture for each Compare/Capture channel in the T/C.

PORTC, PORTD, PORTE and PORTF each has one Timer/Counter 0 and one Timer/Counter1.

Notation of these Timer/Counters are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1, TCE0,

TCE1, TCF0, and TCF1, respectively.

8067M–AVR–09/10

XMEGA A1

Figure 15-1. Overview of a Timer/Counter and closely related peripherals

The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by

2 bits (4x). This is available for all Timer/Counters. See “Hi-Res - High Resolution Extension” on

page 34 for more details.

The Advanced Waveform Extension can be enabled to provide extra and more advanced fea-

tures for the Timer/Counter. This are only available for Timer/Counter 0. See “AWEX - Advanced

Waveform Extension” on page 33 for more details.

AWeX

Compare/Capture Channel D

Compare/Capture Channel C

Compare/Capture Channel B

Compare/Capture Channel A

Waveform

Generation

Buffer

Comparator

Hi-Res

Fault

Protection

Capture

Control

Base Counter

Counter

Control Logic

Timer Period

Prescaler

DTI

Dead-Time

Insertion

Pattern

Generation

clkPER4

PORT

Event

System

clkPER

Timer/Counter

8067M–AVR–09/10

XMEGA A1

16. AWEX - Advanced Waveform Extension

16.1 Features

•Output with complementary output from each Capture channel

•Four Dead Time Insertion (DTI) Units, one for each Capture channel

•8-bit DTI Resolution

•Separate High and Low Side Dead-Time Setting

•Double Buffered Dead-Time

•Event Controlled Fault Protection

•Single Channel Multiple Output Operation (for BLDC motor control)

•Double Buffered Pattern Generation

16.2 Overview

The Advanced Waveform Extension (AWEX) provides extra features to the Timer/Counter in

Waveform Generation (WG) modes. The AWEX enables easy and safe implementation of for

example, advanced motor control (AC, BLDC, SR, and Stepper) and power control applications.

Any WG output from a Timer/Counter 0 is split into a complimentary pair of outputs when any

AWEX feature is enabled. These output pairs go through a Dead-Time Insertion (DTI) unit that

enables generation of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG

output with dead time insertion between LS and HS switching. The DTI output will override the

normal port value according to the port override setting. Optionally the final output can be

inverted by using the invert I/O setting for the port pin.

The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is

connected to. In addition, the waveform generator output from Compare Channel A can be dis-

tributed to, and override all port pins. When the Pattern Generator unit is enabled, the DTI unit is

bypassed.

The Fault Protection unit is connected to the Event System. This enables any event to trigger a

fault condition that will disable the AWEX output. Several event channels can be used to trigger

fault on several different conditions.

The AWEX is available for TCC0 and TCE0. The notation of these peripherals are AWEXC and

AWEXE.

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XMEGA A1

17. Hi-Res - High Resolution Extension

17.1 Features

•Increases Waveform Generator resolution by 2-bits (4x)

•Supports Frequency, single- and dual-slope PWM operation

•Supports the AWEX when this is enabled and used for the same Timer/Counter

17.2 Overview

The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform genera-

tion output by a factor of 4. When enabled for a Timer/Counter, the Fast Peripheral clock running

at four times the CPU clock speed will be as input to the Timer/Counter.

The High Resolution Extension can also be used when an AWEX is enabled and used with a

Timer/Counter.

XMEGA A1 devices have four Hi-Res Extensions that each can be enabled for each

Timer/Counters pair on PORTC, PORTD, PORTE and PORTF. The notation of these peripher-

als are HIRESC, HIRESD, HIRESE and HIRESF, respectively.

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XMEGA A1

18. RTC - 16-bit Real-Time Counter

18.1 Features

•16-bit Timer

•Flexible Tick resolution ranging from 1 Hz to 32.768 kHz

•One Compare register

•One Period register

•Clear timer on Overflow or Compare Match

•Overflow or Compare Match event and interrupt generation

18.2 Overview

The XMEGA A1 includes a 16-bit Real-time Counter (RTC). The RTC can be clocked from an

accurate 32.768 kHz Crystal Oscillator, the 32.768 kHz Calibrated Internal Oscillator, or from the

32 kHz Ultra Low Power Internal Oscillator. The RTC includes both a Period and a Compare

A wide range of Resolution and Time-out periods can be configured using the RTC. With a max-

imum resolution of 30.5 µs, time-out periods range up to 2000 seconds. With a resolution of 1

second, the maximum time-out period is over 18 hours (65536 seconds).

Figure 18-1. Real Time Counter overview

10-bit

prescaler Counter

Period

Compare

Overflow

Compare Match

1 kHz

32 kHz

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XMEGA A1

19. TWI - Two-Wire Interface

19.1 Features

•Four Identical TWI peripherals

•Simple yet Powerful and Flexible Communication Interface

•Both Master and Slave Operation Supported

•Device can Operate as Transmitter or Receiver

•7-bit Address Space Allows up to 128 Different Slave Addresses

•Multi-master Arbitration Support

•Up to 400 kHz Data Transfer Speed

•Slew-rate Limited Output Drivers

•Noise Suppression Circuitry Rejects Spikes on Bus Lines

•Fully Programmable Slave Address with General Call Support

•Address Recognition Causes Wake-up when in Sleep Mode

•I2C and System Management Bus (SMBus) compatible

19.2 Overview

The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock

(SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 indi-

vidually addressable devices. Since it is a multi-master bus, one or more devices capable of

taking control of the bus can be connected.

The only external hardware needed to implement the bus is a single pull-up resistor for each of

the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol.

PORTC, PORTD, PORTE, and PORTF each has one TWI. Notation of these peripherals are

TWIC, TWID, TWIE, and TWIF, respectively.

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XMEGA A1

20. SPI - Serial Peripheral Interface

20.1 Features

•Four Identical SPI peripherals

•Full-duplex, Three-wire Synchronous Data Transfer

•Master or Slave Operation

•LSB First or MSB First Data Transfer

•Seven Programmable Bit Rates

•End of Transmission Interrupt Flag

•Write Collision Flag Protection

•Wake-up from Idle Mode

•Double Speed (CK/2) Master SPI Mode

20.2 Overview

The Serial Peripheral Interface (SPI) allows high-speed full-duplex, synchronous data transfer

between different devices. Devices can communicate using a master-slave scheme, and data is

transferred both to and from the devices simultaneously.

PORTC, PORTD, PORTE, and PORTF each has one SPI. Notation of these peripherals are

SPIC, SPID, SPIE, and SPIF, respectively.

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XMEGA A1

21. USART

21.1 Features

•Eight Identical USART peripherals

•Full Duplex Operation (Independent Serial Receive and Transmit Registers)

•Asynchronous or Synchronous Operation

•Master or Slave Clocked Synchronous Operation

•High-resolution Arithmetic Baud Rate Generator

•Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

•Odd or Even Parity Generation and Parity Check Supported by Hardware

•Data OverRun Detection

•Framing Error Detection

•Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

•Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

•Multi-processor Communication Mode

•Double Speed Asynchronous Communication Mode

•Master SPI mode for SPI communication

•IrDA support through the IRCOM module

21.2 Overview

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a

highly flexible serial communication module. The USART supports full duplex communication,

and both asynchronous and clocked synchronous operation. The USART can also be set in

Master SPI mode to be used for SPI communication.

Communication is frame based, and the frame format can be customized to support a wide

range of standards. The USART is buffered in both direction, enabling continued data transmis-

sion without any delay between frames. There are separate interrupt vectors for receive and

transmit complete, enabling fully interrupt driven communication. Frame error and buffer over-

flow are detected in hardware and indicated with separate status flags. Even or odd parity

generation and parity check can also be enabled.

One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modula-

tion and demodulation for baud rates up to 115.2 kbps.

PORTC, PORTD, PORTE, and PORTF each has two USARTs. Notation of these peripherals

are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0, USARTE1, USARTF0,

USARTF1, respectively.

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XMEGA A1

22. IRCOM - IR Communication Module

22.1 Features

•Pulse modulation/demodulation for infrared communication

•Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps

•Selectable pulse modulation scheme

– 3/16 of baud rate period

– Fixed pulse period, 8-bit programmable

– Pulse modulation disabled

•Built in filtering

•Can be connected to and used by one USART at a time

22.2 Overview

XMEGA contains an Infrared Communication Module (IRCOM) for IrDA communication with

baud rates up to 115.2 kbps. This supports three modulation schemes: 3/16 of baud rate period,

fixed programmable pulse time based on the Peripheral Clock speed, or pulse modulation dis-

abled. There is one IRCOM available which can be connected to any USART to enable infrared

pulse coding/decoding for that USART.

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XMEGA A1

23. Crypto Engine

23.1 Features

•Data Encryption Standard (DES) CPU instruction

•Advanced Encryption Standard (AES) Crypto module

•DES Instruction

– Encryption and Decryption

– Single-cycle DES instruction

– Encryption/Decryption in 16 clock cycles per 8-byte block

•AES Crypto Module

– Encryption and Decryption

– Support 128-bit keys

– Support XOR data load mode to the State memory for Cipher Block Chaining

– Encryption/Decryption in 375 clock cycles per 16-byte block

23.2 Overview

The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two com-

monly used encryption standards. These are supported through an AES peripheral module and

a DES CPU instruction. All communication interfaces and the CPU can optionally use AES and

DES encrypted communication and data storage.

DES is supported by a DES instruction in the AVR XMEGA CPU. The 8-byte key and 8-byte

data blocks must be loaded into the Register file, and then DES must be executed 16 times to

encrypt/decrypt the data block.

The AES Crypto Module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key.

The key and data must be loaded into the key and state memory in the module before encryp-

tion/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is

done and decrypted/encrypted data can be read out, and an optional interrupt can be generated.

The AES Crypto Module also has DMA support with transfer triggers when encryption/decryp-

tion is done and optional auto-start of encryption/decryption when the state memory is fully

loaded.

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XMEGA A1

24. ADC - 12-bit Analog to Digital Converter

24.1 Features

•Two ADCs with 12-bit resolution

•2 Msps sample rate for each ADC

•Signed and Unsigned conversions

•4 result registers with individual input channel control for each ADC

•8 single ended inputs for each ADC

•8x4 differential inputs for each ADC

•4 internal inputs:

– Integrated Temperature Sensor

– DAC Output

– VCC voltage divided by 10

– Bandgap voltage

•Software selectable gain of 2, 4, 8, 16, 32 or 64

•Software selectable resolution of 8- or 12-bit.

•Internal or External Reference selection

•Event triggered conversion for accurate timing

•DMA transfer of conversion results

•Interrupt/Event on compare result

24.2 Overview

XMEGA A1 devices have two Analog to Digital Converters (ADC), see Figure 24-1 on page 42.

The two ADC modules can be operated simultaneously, individually or synchronized.

The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capa-

ble of converting up to 2 million samples per second. The input selection is flexible, and both

single-ended and differential measurements can be done. For differential measurements an

optional gain stage is available to increase the dynamic range. In addition several internal signal

inputs are available. The ADC can provide both signed and unsigned results.

This is a pipeline ADC. A pipeline ADC consists of several consecutive stages, where each

stage convert one part of the result. The pipeline design enables high sample rate at low clock

speeds, and remove limitations on samples speed versus propagation delay. This also means

that a new analog voltage can be sampled and a new ADC measurement started while other

ADC measurements are ongoing.

ADC measurements can either be started by application software or an incoming event from

another peripheral in the device. Four different result registers with individual input selection

(MUX selection) are provided to make it easier for the application to keep track of the data. Each

result register and MUX selection pair is referred to as an ADC Channel. It is possible to use

DMA to move ADC results directly to memory or peripherals when conversions are done.

Both internal and external analog reference voltages can be used. An accurate internal 1.0V

reference is available.

An integrated temperature sensor is available and the output from this can be measured with the

ADC. The output from the DAC, VCC/10 and the Bandgap voltage can also be measured by the

ADC.

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XMEGA A1

Figure 24-1. ADC overview

Each ADC has four MUX selection registers with a corresponding result register. This means

that four channels can be sampled within 1.5 µs without any intervention by the application other

than starting the conversion. The results will be available in the result registers.

The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop-

agation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit result.

ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This

eases calculation when the result is represented as a signed integer (signed 16-bit number).

PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB,

respectively.

ADC

Channel A

Channel B

Channel C

Channel D

Pin inputsPin inputs

1-64 X

Internal inputs

Channel A MUX selection

Channel B MUX selection

Channel C MUX selection

Channel D MUX selection

Event

Trigger

Configuration

Reference selection

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XMEGA A1

25. DAC - 12-bit Digital to Analog Converter

25.1 Features

•Two DACs with 12-bit resolution

•Up to 1 Msps conversion rate for each DAC

•Flexible conversion range

•Multiple trigger sources

•1 continuous output or 2 Sample and Hold (S/H) outputs for each DAC

•Built-in offset and gain calibration

•High drive capabilities

•Low Power Mode

25.2 Overview

The XMEGA A1 devices features two 12-bit, 1 Msps DACs with built-in offset and gain calibra-

tion, see Figure 25-1 on page 43.

A DAC converts a digital value into an analog signal. The DAC may use an internal 1.0 voltage

as the upper limit for conversion, but it is also possible to use the supply voltage or any applied

voltage in-between. The external reference input is shared with the ADC reference input.

Figure 25-1. DAC overview

Each DAC has one continuous output with high drive capabilities for both resistive and capaci-

tive loads. It is also possible to split the continuous time channel into two Sample and Hold (S/H)

channels, each with separate data conversion registers.

A DAC conversion may be started from the application software by writing the data conversion

registers. The DAC can also be configured to do conversions triggered by the Event System to

have regular timing, independent of the application software. DMA may be used for transferring

data from memory locations to DAC data registers.

The DAC has a built-in calibration system to reduce offset and gain error when loading with a

calibration value from software.

PORTA and PORTB each has one DAC. Notation of these peripherals are DACA and DACB.

respectively.

DAC

Channel A

Channel B

Event

Trigger

Configuration

Reference selection

Channel A

Channel B

8067M–AVR–09/10

XMEGA A1

26. AC - Analog Comparator

26.1 Features

•Four Analog Comparators

•Selectable Power vs. Speed

•Selectable hysteresis

– 0, 20 mV, 50 mV

•Analog Comparator output available on pin

•Flexible Input Selection

– All pins on the port

– Output from the DAC

– Bandgap reference voltage.

– Voltage scaler that can perform a 64-level scaling of the internal VCC voltage.

•Interrupt and event generation on

– Rising edge

– Falling edge

–Toggle

•Window function interrupt and event generation on

– Signal above window

– Signal inside window

– Signal below window

26.2 Overview

XMEGA A1 features four Analog Comparators (AC). An Analog Comparator compares two volt-

ages, and the output indicates which input is largest. The Analog Comparator may be configured

to give interrupt requests and/or events upon several different combinations of input change.

Both hysteresis and propagation delays may be adjusted in order to find the optimal operation

for each application.

A wide range of input selection is available, both external pins and several internal signals can

be used.

The Analog Comparators are always grouped in pairs (AC0 and AC1) on each analog port. They

have identical behavior but separate control registers.

Optionally, the state of the comparator is directly available on a pin.

PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.

8067M–AVR–09/10

XMEGA A1

Figure 26-1. Analog comparator overview

AC0

Pin inputs

Internal inputs

Pin inputs

Internal inputs

VCC scaled

Interrupt

sensitivity

control

Interrupts

AC1

Pin inputs

Internal inputs

Pin inputs

Internal inputs

VCC scaled

Events

Pin 0 output

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XMEGA A1

26.3 Input Selection

The Analog comparators have a very flexible input selection and the two comparators grouped

in a pair may be used to realize a window function. One pair of analog comparators is shown in

Figure 26-1 on page 45.

•Input selection from pin

– Pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator

– Pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator

•Internal signals available on positive analog comparator inputs

– Output from 12-bit DAC

•Internal signals available on negative analog comparator inputs

– 64-level scaler of the VCC, available on negative analog comparator input

– Bandgap voltage reference

– Output from 12-bit DAC

26.4 Window Function

The window function is realized by connecting the external inputs of the two analog comparators

in a pair as shown in Figure 26-2.

Figure 26-2. Analog comparator window function

AC0

AC1

Input signal

Upper limit of window

Lower limit of window

Interrupt

sensitivity

control

Interrupts

Events

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XMEGA A1

27. OCD - On-chip Debug

27.1 Features

•Complete Program Flow Control

– Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor

•Debugging on C and high-level language source code level

•Debugging on Assembler and disassembler level

•1 dedicated program address or source level breakpoint for AVR Studio / debugger

•4 Hardware Breakpoints

•Unlimited Number of User Program Breakpoints

•Unlimited Number of User Data Breakpoints, with break on:

– Data location read, write or both read and write

– Data location content equal or not equal to a value

– Data location content is greater or less than a value

– Data location content is within or outside a range

– Bits of a data location are equal or not equal to a value

•Non-Intrusive Operation

– No hardware or software resources in the device are used

•High Speed Operation

– No limitation on debug/programming clock frequency versus system clock frequency

27.2 Overview

The XMEGA A1 has a powerful On-Chip Debug (OCD) system that - in combination with Atmel’s

development tools - provides all the necessary functions to debug an application. It has support

for program and data breakpoints, and can debug an application from C and high level language

source code level, as well as assembler and disassembler level. It has full Non-Intrusive Opera-

tion and no hardware or software resources in the device are used. The ODC system is

accessed through an external debugging tool which connects to the JTAG or PDI physical inter-

faces. Refer to “PDI - Program and Debug Interface” on page 48.

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XMEGA A1

28. PDI - Program and Debug Interface

28.1 Features

•PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)

•JTAG Interface (IEEE std. 1149.1 compliant)

•Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG)

•Access to the OCD system

•Programming of Flash, EEPROM, Fuses and Lock Bits

28.2 Overview

The programming and debug facilities are accessed through the JTAG and PDI physical inter-

faces. The PDI physical interface uses one dedicated pin together with the Reset pin, and no

general purpose pins are used. JTAG uses four general purpose pins on PORTB.

The PDI is an Atmel proprietary protocol for communication between the microcontroller and

Atmel’s or third party development tools.

28.3 IEEE 1149.1 (JTAG) Boundary-scan

The JTAG physical layer handles the basic low-level serial communication over four I/O lines

named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and

boundary scan.

28.3.1 Boundary-scan Order

Table 29-12 on page 55 shows the Scan order between TDI and TDO when the Boundary-scan

chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned

out. The scan order follows the pin-out order. Bit 4, 5, 6 and 7 of Port B is not in the scan chain,

since these pins constitute the TAP pins when the JTAG is enabled.

28.3.2 Boundary-scan Description Language Files

Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in

a standard format used by automated test-generation software. The order and function of bits in

the Boundary-scan Data Register are included in this description. BSDL files are available for

ATxmega384/256/192/128/64A1 devices.

See Table 29-12 on page 55 for ATxmega384/256/192/128/64A1 Boundary Scan Order.

8067M–AVR–09/10

XMEGA A1

29. Pinout and Pin Functions

The pinout of XMEGA A1 is shown in “Pinout/Block Diagram” on page 3. In addition to general

I/O functionality, each pin may have several functions. This will depend on which peripheral is

enabled and connected to the actual pin. Only one of the alternate pin functions can be used at

time.

29.1 Alternate Pin Function Description

The tables below shows the notation for all pin functions available and describes its function.

29.1.1 Operation/Power Supply

29.1.2 Port Interrupt functions

29.1.3 Analog functions

29.1.4 EBI functions

VCC Digital supply voltage

AVCC Analog supply voltage

GND Ground

SYNC Port pin with full synchronous and limited asynchronous interrupt function

ASYNC Port pin with full synchronous and full asynchronous interrupt function

ACn Analog Comparator input pin n

AC0OUT Analog Comparator 0 Output

ADCn Analog to Digital Converter input pin n

DACn Digital to Analog Converter output pin n

AREF Analog Reference input pin

An Address line n

Dn Data line n

CSn Chip Select n

ALEn Address Latch Enable pin n (SRAM)

RERead Enable (SRAM)

WEExternal Data Memory Write (SRAM /SDRAM)

BAn Bank Address (SDRAM)

CAS Column Access Strobe (SDRAM)

CKE SDRAM Clock Enable (SDRAM)

CLK SDRAM Clock (SDRAM)

DQM Data Mask Signal/Output Enable (SDRAM)

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XMEGA A1

29.1.5 Timer/Counter and AWEX functions

29.1.6 Communication functions

29.1.7 Oscillators, Clock and Event

29.1.8 Debug/System functions

RAS Row Access Strobe (SDRAM)

2P 2 Port Interface

3P 3 Port Interface

OCnx Output Compare Channel x for Timer/Counter n

OCnx Inverted Output Compare Channel x for Timer/Counter n

OCnxLS Output Compare Channel x Low Side for Timer/Counter n

OCnxHS Output Compare Channel x High Side for Timer/Counter n

SCL Serial Clock for TWI

SDA Serial Data for TWI

SCLIN Serial Clock In for TWI when external driver interface is enabled

SCLOUT Serial Clock Out for TWI when external driver interface is enabled

SDAIN Serial Data In for TWI when external driver interface is enabled

SDAOUT Serial Data Out for TWI when external driver interface is enabled

XCKn Transfer Clock for USART n

RXDn Receiver Data for USART n

TXDn Transmitter Data for USART n

SSSlave Select for SPI

MOSI Master Out Slave In for SPI

MISO Master In Slave Out for SPI

SCK Serial Clock for SPI

TOSCn Timer Oscillator pin n

XTALn Input/Output for inverting Oscillator pin n

CLKOUT Peripheral Clock Output

EVOUT Event Channel 0 Output

RESET Reset pin

PDI_CLK Program and Debug Interface Clock pin

PDI_DATA Program and Debug Interface Data pin

T C K J TAG Tes t C lo ck

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XMEGA A1

29.2 Alternate Pin Functions

The tables below show the primary/default function for each pin on a port in the first column, the

pin number in the second column, and then all alternate pin functions in the remaining columns.

The head row shows what peripheral that enable and use the alternate pin functions.

TDI JTAG Test Data In

T D O JTAG Te st Da ta O u t

T M S JTAG Te st Mo de Se l e c t

Table 29-1. Port A - Alternate functions

PORT A PIN # INTERRUPT ADCA

POS

ADCA

NEG

ADCA

GAINPOS

ADCA

GAINNEG

ACA

POS

ACA

NEG

ACA

OUT

DACA REFA

GND 93

AVCC 94

PA0 95 SYNC ADC0 ADC0 ADC0 AC0 AC0 AREF

PA1 96 SYNC ADC1 ADC1 ADC1 AC1 AC1

PA2 97 SYNC/ASYNC ADC2 ADC2 ADC2 AC2 DAC0

PA3 98 SYNC ADC3 ADC3 ADC3 AC3 AC3 DAC1

PA4 99 SYNC ADC4 ADC4 ADC4 AC4

PA5 100 SYNC ADC5 ADC5 ADC5 AC5 AC5

PA6 1 SYNC ADC6 ADC6 ADC6 AC6

PA7 2 SYNC ADC7 ADC7 ADC7 AC7 AC0OUT

Table 29-2. Port B - Alternate functions

PORT B PIN # INTERRUPT ADCB

POS

ADCB

NEG

ADCB

GAINPOS

ADCB

GAINNEG

ACB

POS

ACB

NEG

ACB

OUT

DACB REFB JTAG

GND 3

AVCC 4

PB0 5 SYNC ADC0 ADC0 ADC0 AC0 AC0 AREF

PB1 6 SYNC ADC1 ADC1 ADC1 AC1 AC1

PB2 7 SYNC/ASYNC ADC2 ADC2 ADC2 AC2 DAC0

PB3 8 SYNC ADC3 ADC3 ADC3 AC3 AC3 DAC1

PB4 9 SYNC ADC4 ADC4 ADC4 AC4 TMS

PB5 10 SYNC ADC5 ADC5 ADC5 AC5 AC5 TDI

PB6 11 SYNC ADC6 ADC6 ADC6 AC6 TCK

PB7 12 SYNC ADC7 ADC7 ADC7 AC7 AC0OUT TDO

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XMEGA A1

Table 29-3. Port C - Alternate functions

PORT C PIN # INTERRUPT TCC0 AWEXC TCC1 USARTC0 USARTC1 SPIC TWIC CLOCKOUT EVENTOUT

GND 13

VCC 14

PC0 15 SYNC OC0A OC0ALS SDA

PC1 16 SYNC OC0B OC0AHS XCK0 SCL

PC2 17 SYNC/ASYNC OC0C OC0BLS RXD0

PC3 18 SYNC OC0D OC0BHS TXD0

PC4 19 SYNC OC0CLS OC1A SS

PC5 20 SYNC OC0CHS OC1B XCK1 MOSI

PC6 21 SYNC OC0DLS RXD1 MISO

PC7 22 SYNC OC0DHS TXD1 SCK CLKOUT EVOUT

Table 29-4. Port D - Alternate functions

PORT D PIN # INTERRUPT TCD0 TCD1 USARTD0 USARTD1 SPID TWID CLOCKOUT EVENTOUT

GND 23

VCC 24

PD0 25 SYNC OC0A SDA

PD1 26 SYNC OC0B XCK0 SCL

PD2 27 SYNC/ASYNC OC0C RXD0

PD3 28 SYNC OC0D TXD0

PD4 29 SYNC OC1A SS

PD5 30 SYNC OC1B XCK1 MOSI

PD6 31 SYNC RXD1 MISO

PD7 32 SYNC TXD1 SCK CLKOUT EVOUT

Table 29-5. Port E - Alternate functions

PORT E PIN # INTERRUPT TCE0 AWEXE TCE1 USARTE0 USARTE1 SPIE TWIE CLOCKOUT EVENTOUT

GND 33

VCC 34

PE0 35 SYNC OC0A OC0ALS SDA

PE1 36 SYNC OC0B OC0AHS XCK0 SCL

PE2 37 SYNC/ASYNC OC0C OC0BLS RXD0

PE3 38 SYNC OC0D OC0BHS TXD0

PE4 39 SYNC OC0CLS OC1A SS

PE5 40 SYNC OC0CHS OC1B XCK1 MOSI

PE6 41 SYNC OC0DLS RXD1 MISO

PE7 42 SYNC OC0DHS TXD1 SCK CLKOUT EVOUT

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XMEGA A1

Table 29-6. Port F - Alternate functions

PORT F PIN # INTERRUPT TCF0 TCF1 USARTF0 USARTF1 SPIF TWIF

GND 43

VCC 44

PF0 45 SYNC OC0A SDA

PF1 46 SYNC OC0B XCK0 SCL

PF2 47 SYNC/ASYNC OC0C RXD0

PF3 48 SYNC OC0D TXD0

PF4 49 SYNC OC1A SS

PF5 50 SYNC OC1B XCK1 MOSI

PF6 51 SYNC RXD1 MISO

PF7 52 SYNC TXD1 SCK

Table 29-7. Port H - Alternate functions

PORT H PIN # INTERRUPT SDRAM 3P SRAM ALE1 3P SRAM ALE12 3P LPC ALE1 3P LPC ALE1 2P LPC ALE12 2P

GND 53

VCC 54

PH0 55 SYNC WE WE WE WE WE WE

PH1 56 SYNC CAS RE RE RE RE RE

PH2 57 SYNC/ASYNC RAS ALE1 ALE1 ALE1 ALE1 ALE1

PH3 58 SYNC DQM ALE2 ALE2

PH4 59 SYNC BA0 CS0/A16 CS0 CS0/A16 CS0 CS0/A16

PH5 60 SYNC BA1 CS1/A17 CS1 CS1/A17 CS1 CS1/A17

PH6 61 SYNC CKE CS2/A18 CS2 CS2/A18 CS2 CS2/A18

PH7 62 SYNC CLK CS3/A19 CS3 CS3/A19 CS3 CS3/A19

Table 29-8. Port J - Alternate functions

PORT J PIN # INTERRUPT SDRAM 3P SRAM ALE1 3P SRAM ALE12 3P LPC ALE1 3P LPC ALE1 2P LPC ALE12 2P

GND 63

VCC 64

PJ0 65 SYNC D0 D0 D0 D0/A0 D0/A0 D0/A0/A8

PJ1 66 SYNC D1 D1 D1 D1/A1 D1/A1 D1/A1/A9

PJ2 67 SYNC/ASYNC D2 D2 D2 D2/A2 D2/A2 D2/A2/A10

PJ3 68 SYNC D3 D3 D3 D3/A3 D3/A3 D3/A3/A11

PJ4 69 SYNC A8 D4 D4 D4/A4 D4/A4 D4/A4/A12

PJ5 70 SYNC A9 D5 D5 D5/A5 D5/A5 D5/A5/A13

PJ6 71 SYNC A10 D6 D6 D6/A6 D6/A6 D6/A6/A14

PJ7 72 SYNC A11 D7 D7 D7/A7 D7/A7 D7/A7/A15

8067M–AVR–09/10

XMEGA A1

Table 29-9. Port K - Alternate functions

PORT K PIN # INTERRUPT SDRAM 3P SRAM ALE1 3P SRAM ALE12 3P LPC ALE1 3P LPC ALE1 2P LPC ALE12 2P

GND 73

VCC 74

PK0 75 SYNC A0 A0/A8 A0/A8/A16 A8

PK1 76 SYNC A1 A1/A9 A1/A9/A17 A9

PK2 77 SYNC/ASYNC A2 A2/A10 A2/A10/A18 A10

PK3 78 SYNC A3 A3/A11 A3/A11/A19 A11

PK4 79 SYNC A4 A4/A12 A4/A12/A20 A12

PK5 80 SYNC A5 A5/A13 A5/A13/A21 A13

PK6 81 SYNC A6 A6/A14 A6/A14/A22 A14

PK7 82 SYNC A7 A7/A15 A7/A15/A23 A15

Table 29-10. Port Q - Alternate functions

PORT Q PIN # INTERRUPT TOSC

VCC 83

GND 84

PQ0 85 SYNC TOSC1

PQ1 86 SYNC TOSC2

PQ2 87 SYNC/ASYNC

PQ3 88 SYNC

Table 29-11. Port R- Alternate functions

PORT R PIN # INTERRUPT PDI XTAL

PDI 89 PDI_DATA

RESET 90 PDI_CLOCK

PRO 91 SYNC XTAL2

PR1 92 SYNC XTAL1

8067M–AVR–09/10

XMEGA A1

Table 29-12. ATxmega384/256/192/128/64A1 Boundary Scan Order

Bit Number Signal Name Module

149 PQ3.Bidir

PORT Q

148 PQ3.Control

147 PQ2.Bidir

146 PQ2.Control

145 PQ1.Bidir

144 PQ1.Control

143 PQ0.Bidir

142 PQ0.Control

141 PK7.Bidir

PORT K

140 PK7.Control

139 PK6.Bidir

138 PK6.Control

137 PK5.Bidir

136 PK5.Control

135 PK4.Bidir

134 PK4.Control

133 PK3.Bidir

132 PK3.Control

131 PK2.Bidir

130 PK2.Control

129 PK1.Bidir

128 PK1.Control

127 PK0.Bidir

126 PK0.Control

125 PJ7.Bidir

PORT J

124 PJ7.Control

123 PJ6.Bidir

122 PJ6.Control

121 PJ5.Bidir

120 PJ5.Control

119 PJ4.Bidir

118 PJ4.Control

117 PJ3.Bidir

116 PJ3.Control

115 PJ2.Bidir

114 PJ2.Control

113 PJ1.Bidir

112 PJ1.Control

111 PJ0.Bidir

110 PJ0.Control

109 PH7.Bidir

PORT H

108 PH7.Control

107 PH6.Bidir

106 PH6.Control

105 PH5.Bidir

104 PH5.Control

103 PH4.Bidir

102 PH4.Control

101 PH3.Bidir

100 PH3.Control

99 PH2.Bidir

98 PH2.Control

97 PH1.Bidir

96 PH1.Control

95 PH0.Bidir

94 PH0.Control

8067M–AVR–09/10

XMEGA A1

93 PF7.Bidir

PORT F

92 PF7.Control

91 PF6.Bidir

90 PF6.Control

89 PF5.Bidir

88 PF5.Control

87 PF4.Bidir

86 PF4.Control

85 PF3.Bidir

84 PF3.Control

83 PF2.Bidir

82 PF2.Control

81 PF1.Bidir

80 PF1.Control

79 PF0.Bidir

78 PF0.Control

77 PE7.Bidir

PORT E

76 PE7.Control

75 PE6.Bidir

74 PE6.Control

73 PE5.Bidir

72 PE5.Control

71 PE4.Bidir

70 PE4.Control

69 PE3.Bidir

68 PE3.Control

67 PE2.Bidir

66 PE2.Control

65 PE1.Bidir

64 PE1.Control

63 PE0.Bidir

62 PE0.Control

61 PD7.Bidir

PORT D

60 PD7.Control

59 PD6.Bidir

58 PD6.Control

57 PD5.Bidir

56 PD5.Control

55 PD4.Bidir

54 PD4.Control

53 PD3.Bidir

52 PD3.Control

51 PD2.Bidir

50 PD2.Control

49 PD1.Bidir

48 PD1.Control

47 PD0.Bidir

46 PD0.Control

45 PC7.Bidir

PORT C

44 PC7.Control

43 PC6.Bidir

42 PC6.Control

41 PC5.Bidir

40 PC5.Control

39 PC4.Bidir

38 PC4.Control

37 PC3.Bidir

36 PC3.Control

35 PC2.Bidir

34 PC2.Control

33 PC1.Bidir

32 PC1.Control

31 PC0.Bidir

30 PC0.Control

Bit Number Signal Name Module

8067M–AVR–09/10

XMEGA A1

29 PB3.Bidir

PORT B

28 PB3.Control

27 PB2.Bidir

26 PB2.Control

25 PB1.Bidir

24 PB1.Control

23 PB0.Bidir

22 PB0.Control

21 PA7.Bidir

PORT A

20 PA7.Control

19 PA6.Bidir

18 PA6.Control

17 PA5.Bidir

16 PA5.Control

15 PA4.Bidir

14 PA4.Control

13 PA3.Bidir

12 PA3.Control

11 PA2.Bidir

10 PA2.Control

9 PA1.Bidir

8 PA1.Control

7 PA0.Bidir

6 PA0.Control

5 PR1.Bidir

PORT R

4PR1.Control

3 PR0.Bidir

2PR0.Control

1 RESET.Observe_Only RESET

0 PDI_DATA.Observe_Only PDI Data

Bit Number Signal Name Module

8067M–AVR–09/10

XMEGA A1

30. Peripheral Module Address Map

The address maps show the base address for each peripheral and module in XMEGA A1. For

complete register description and summary for each peripheral module, refer to the XMEGA A

Manual.

Table 30-1. Peripheral Module Address Map

Base Address Name Description

0x0000 GPIO General Purpose IO Registers

0x0010 VPORT0 Virtual Port 0

0x0014 VPORT1 Virtual Port 1

0x0018 VPORT2 Virtual Port 2

0x001C VPORT3 Virtual Port 3

0x0030 CPU CPU

0x0040 CLK Clock Control

0x0048 SLEEP Sleep Controller

0x0050 OSC Oscillator Control

0x0060 DFLLRC32M DFLL for the 32 MHz Internal RC Oscillator

0x0068 DFLLRC2M DFLL for the 2 MHz RC Oscillator

0x0070 PR Power Reduction

0x0078 RST Reset Controller

0x0080 WDT Watch-Dog Timer

0x0090 MCU MCU Control

0x00A0 PMIC Programmable Multilevel Interrupt Controller

0x00B0 PORTCFG Port Configuration

0x00C0 AES AES Module

0x0100 DMA DMA Controller

0x0180 EVSYS Event System

0x01C0 NVM Non Volatile Memory (NVM) Controller

0x0200 ADCA Analog to Digital Converter on port A

0x0240 ADCB Analog to Digital Converter on port B

0x0300 DACA Digital to Analog Converter on port A

0x0320 DACB Digital to Analog Converter on port B

0x0380 ACA Analog Comparator pair on port A

0x0390 ACB Analog Comparator pair on port B

0x0400 RTC Real Time Counter

0x0440 EBI External Bus Interface

0x0480 TWIC Two Wire Interface on port C

0x0490 TWID Two Wire Interface on port D

0x04A0 TWIE Two Wire Interface on port E

0x04B0 TWIF Two Wire Interface on port F

0x0600 PORTA Port A

0x0620 PORTB Port B

0x0640 PORTC Port C

0x0660 PORTD Port D

0x0680 PORTE Port E

0x06A0 PORTF Port F

0x06E0 PORTH Port H

0x0700 PORTJ Port J

0x0720 PORTK Port K

0x07C0 PORTQ Port Q

0x07E0 PORTR Port R

0x0800 TCC0 Timer/Counter 0 on port C

0x0840 TCC1 Timer/Counter 1 on port C

0x0880 AWEXC Advanced Waveform Extension on port C

0x0890 HIRESC High Resolution Extension on port C

0x08A0 USARTC0 USART 0 on port C

0x08B0 USARTC1 USART 1 on port C

0x08C0 SPIC Serial Peripheral Interface on port C

0x08F8 IRCOM Infrared Communication Module

0x0900 TCD0 Timer/Counter 0 on port D

0x0940 TCD1 Timer/Counter 1 on port D

0x0990 HIRESD High Resolution Extension on port D

0x09A0 USARTD0 USART 0 on port D

0x09B0 USARTD1 USART 1 on port D

8067M–AVR–09/10

XMEGA A1

0x09C0 SPID Serial Peripheral Interface on port D

0x0A00 TCE0 Timer/Counter 0 on port E

0x0A40 TCE1 Timer/Counter 1 on port E

0x0A80 AWEXE Advanced Waveform Extension on port E

0x0A90 HIRESE High Resolution Extension on port E

0x0AA0 USARTE0 USART 0 on port E

0x0AB0 USARTE1 USART 1 on port E

0x0AC0 SPIE Serial Peripheral Interface on port E

0x0B00 TCF0 Timer/Counter 0 on port F

0x0B40 TCF1 Timer/Counter 1 on port F

0x0B90 HIRESF High Resolution Extension on port F

0x0BA0 USARTF0 USART 0 on port F

0x0BB0 USARTF1 USART 1 on port F

0x0BC0 SPIF Serial Peripheral Interface on port F

Base Address Name Description

8067M–AVR–09/10

XMEGA A1

31. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

Arithmetic and Logic Instructions

ADD Rd, Rr Add without Carry Rd ←Rd + Rr Z,C,N,V,S,H 1

ADC Rd, Rr Add with Carry Rd ←Rd + Rr + C Z,C,N,V,S,H 1

ADIW Rd, K Add Immediate to Word Rd ←Rd + 1:Rd + K Z,C,N,V,S 2

SUB Rd, Rr Subtract without Carry Rd ←Rd - Rr Z,C,N,V,S,H 1

SUBI Rd, K Subtract Immediate Rd ←Rd - K Z,C,N,V,S,H 1

SBC Rd, Rr Subtract with Carry Rd ←Rd - Rr - C Z,C,N,V,S,H 1

SBCI Rd, K Subtract Immediate with Carry Rd ←Rd - K - C Z,C,N,V,S,H 1

SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd ←Rd + 1:Rd - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Rd ←Rd • Rr Z,N,V,S 1

ANDI Rd, K Logical AND with Immediate Rd ←Rd • K Z,N,V,S 1

OR Rd, Rr Logical OR Rd ←Rd v Rr Z,N,V,S 1

ORI Rd, K Logical OR with Immediate Rd ←Rd v K Z,N,V,S 1

EOR Rd, Rr Exclusive OR Rd ←Rd ⊕ Rr Z,N,V,S 1

COM Rd One’s Complement Rd ←$FF - Rd Z,C,N,V,S 1

NEG Rd Two’s Complement Rd ←$00 - Rd Z,C,N,V,S,H 1

SBR Rd,K Set Bit(s) in Register Rd ←Rd v K Z,N,V,S 1

CBR Rd,K Clear Bit(s) in Register Rd ←Rd • ($FFh - K) Z,N,V,S 1

INC Rd Increment Rd ←Rd + 1 Z,N,V,S 1

DEC Rd Decrement Rd ←Rd - 1 Z,N,V,S 1

TST Rd Test for Zero or Minus Rd ←Rd • Rd Z,N,V,S 1

CLR Rd Clear Register Rd ←Rd ⊕ Rd Z,N,V,S 1

SER Rd Set Register Rd ←$FF None 1

MUL Rd,Rr Multiply Unsigned R1:R0 ←Rd x Rr (UU) Z,C 2

MULS Rd,Rr Multiply Signed R1:R0 ←Rd x Rr (SS) Z,C 2

MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 ←Rd x Rr (SU) Z,C 2

FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 ←Rd x Rr<<1 (UU) Z,C 2

FMULS Rd,Rr Fractional Multiply Signed R1:R0 ←Rd x Rr<<1 (SS) Z,C 2

FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ←Rd x Rr<<1 (SU) Z,C 2

DES K Data Encryption if (H = 0) then R15:R0

else if (H = 1) then R15:R0

←

Encrypt(R15:R0, K)

Decrypt(R15:R0, K)

1/2

Branch Instructions

RJMP k Relative Jump PC ←PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC(15:0)

PC(21:16)

←

None 2

EIJMP Extended Indirect Jump to (Z) PC(15:0)

PC(21:16)

←

EIND

None 2

JMP k Jump PC ←k None 3

RCALL k Relative Call Subroutine PC ←PC + k + 1 None 2 / 3(1)

ICALL Indirect Call to (Z) PC(15:0)

PC(21:16)

←

None 2 / 3(1)

EICALL Extended Indirect Call to (Z) PC(15:0)

PC(21:16)

←

EIND

None 3(1)

8067M–AVR–09/10

XMEGA A1

CALL k call Subroutine PC ←k None 3 / 4(1)

RET Subroutine Return PC ←STACK None 4 / 5(1)

RETI Interrupt Return PC ←STACK I 4 / 5(1)

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ←PC + 2 or 3 None 1 / 2 / 3

CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1

CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1

CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ←PC + 2 or 3 None 1 / 2 / 3

SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ←PC + 2 or 3 None 1 / 2 / 3

SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ←PC + 2 or 3 None 2 / 3 / 4

SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC ←PC + 2 or 3 None 2 / 3 / 4

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC + k + 1 None 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC + k + 1 None 1 / 2

BREQ k Branch if Equal if (Z = 1) then PC ←PC + k + 1 None 1 / 2

BRNE k Branch if Not Equal if (Z = 0) then PC ←PC + k + 1 None 1 / 2

BRCS k Branch if Carry Set if (C = 1) then PC ←PC + k + 1 None 1 / 2

BRCC k Branch if Carry Cleared if (C = 0) then PC ←PC + k + 1 None 1 / 2

BRSH k Branch if Same or Higher if (C = 0) then PC ←PC + k + 1 None 1 / 2

BRLO k Branch if Lower if (C = 1) then PC ←PC + k + 1 None 1 / 2

BRMI k Branch if Minus if (N = 1) then PC ←PC + k + 1 None 1 / 2

BRPL k Branch if Plus if (N = 0) then PC ←PC + k + 1 None 1 / 2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ←PC + k + 1 None 1 / 2

BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ←PC + k + 1 None 1 / 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ←PC + k + 1 None 1 / 2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ←PC + k + 1 None 1 / 2

BRTS k Branch if T Flag Set if (T = 1) then PC ←PC + k + 1 None 1 / 2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ←PC + k + 1 None 1 / 2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ←PC + k + 1 None 1 / 2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ←PC + k + 1 None 1 / 2

BRIE k Branch if Interrupt Enabled if (I = 1) then PC ←PC + k + 1 None 1 / 2

BRID k Branch if Interrupt Disabled if (I = 0) then PC ←PC + k + 1 None 1 / 2

Data Transfer Instructions

MOV Rd, Rr Copy Register Rd ←Rr None 1

MOVW Rd, Rr Copy Register Pair Rd+1:Rd ←Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd ←K None 1

LDS Rd, k Load Direct from data space Rd ←(k) None 2(1)(2)

LD Rd, X Load Indirect Rd ←(X) None 1(1)(2)

LD Rd, X+ Load Indirect and Post-Increment Rd

←

(X)

X + 1

None 1(1)(2)

LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1,

Rd ← (X)

←

X - 1

(X)

None 2(1)(2)

LD Rd, Y Load Indirect Rd ← (Y) ←(Y) None 1(1)(2)

LD Rd, Y+ Load Indirect and Post-Increment Rd

←

(Y)

Y + 1

None 1(1)(2)

Mnemonics Operands Description Operation Flags #Clocks

8067M–AVR–09/10

XMEGA A1

LD Rd, -Y Load Indirect and Pre-Decrement Y

←

Y - 1

(Y)

None 2(1)(2)

LDD Rd, Y+q Load Indirect with Displacement Rd ←(Y + q) None 2(1)(2)

LD Rd, Z Load Indirect Rd ←(Z) None 1(1)(2)

LD Rd, Z+ Load Indirect and Post-Increment Rd

←

(Z),

Z+1

None 1(1)(2)

LD Rd, -Z Load Indirect and Pre-Decrement Z

←

Z - 1,

(Z)

None 2(1)(2)

LDD Rd, Z+q Load Indirect with Displacement Rd ←(Z + q) None 2(1)(2)

STS k, Rr Store Direct to Data Space (k) ←Rd None 2(1)

ST X, Rr Store Indirect (X) ←Rr None 1(1)

ST X+, Rr Store Indirect and Post-Increment (X)

←

Rr,

X + 1

None 1(1)

ST -X, Rr Store Indirect and Pre-Decrement X

(X)

←

X - 1,

None 2(1)

ST Y, Rr Store Indirect (Y) ←Rr None 1(1)

ST Y+, Rr Store Indirect and Post-Increment (Y)

←

Rr,

Y + 1

None 1(1)

ST -Y, Rr Store Indirect and Pre-Decrement Y

(Y)

←

Y - 1,

None 2(1)

STD Y+q, Rr Store Indirect with Displacement (Y + q) ←Rr None 2(1)

ST Z, Rr Store Indirect (Z) ←Rr None 1(1)

ST Z+, Rr Store Indirect and Post-Increment (Z)

←

Z + 1

None 1(1)

ST -Z, Rr Store Indirect and Pre-Decrement Z ←Z - 1 None 2(1)

STD Z+q,Rr Store Indirect with Displacement (Z + q) ←Rr None 2(1)

LPM Load Program Memory R0 ←(Z) None 3

LPM Rd, Z Load Program Memory Rd ←(Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Increment Rd

←

(Z),

Z + 1

None 3

ELPM Extended Load Program Memory R0 ←(RAMPZ:Z) None 3

ELPM Rd, Z Extended Load Program Memory Rd ←(RAMPZ:Z) None 3

ELPM Rd, Z+ Extended Load Program Memory and Post-

Increment

←

(RAMPZ:Z),

Z + 1

None 3

SPM Store Program Memory (RAMPZ:Z) ←R1:R0 None -

SPM Z+ Store Program Memory and Post-Increment

by 2

(RAMPZ:Z)

←

R1:R0,

Z + 2

None -

IN Rd, A In From I/O Location Rd ←I/O(A) None 1

OUT A, Rr Out To I/O Location I/O(A) ←Rr None 1

PUSH Rr Push Register on Stack STACK ←Rr None 1(1)

POP Rd Pop Register from Stack Rd ←STACK None 2(1)

Bit and Bit-test Instructions

LSL Rd Logical Shift Left Rd(n+1)

Rd(0)

←

Rd(n),

Rd(7)

Z,C,N,V,H 1

LSR Rd Logical Shift Right Rd(n)

Rd(7)

←

Rd(n+1),

Rd(0)

Z,C,N,V 1

Mnemonics Operands Description Operation Flags #Clocks

8067M–AVR–09/10

XMEGA A1

Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external

RAM interface.

2. One extra cycle must be added when accessing Internal SRAM.

ROL Rd Rotate Left Through Carry Rd(0)

Rd(n+1)

←

Rd(n),

Rd(7)

Z,C,N,V,H 1

ROR Rd Rotate Right Through Carry Rd(7)

Rd(n)

←

Rd(n+1),

Rd(0)

Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ←Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0) ↔Rd(7..4) None 1

BSET s Flag Set SREG(s) ←1SREG(s)1

BCLR s Flag Clear SREG(s) ←0SREG(s)1

SBI A, b Set Bit in I/O Register I/O(A, b) ←1 None 1

CBI A, b Clear Bit in I/O Register I/O(A, b) ←0 None 1

BST Rr, b Bit Store from Register to T T ←Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ←T None 1

SEC Set Carry C ←1C1

CLC Clear Carry C ←0C1

SEN Set Negative Flag N ←1N1

CLN Clear Negative Flag N ←0N1

SEZ Set Zero Flag Z ←1Z1

CLZ Clear Zero Flag Z ←0Z1

SEI Global Interrupt Enable I ←1I1

CLI Global Interrupt Disable I ←0I1

SES Set Signed Test Flag S ←1S1

CLS Clear Signed Test Flag S ←0S1

SEV Set Two’s Complement Overflow V ←1V1

CLV Clear Two’s Complement Overflow V ←0V1

SET Set T in SREG T ←1T1

CLT Clear T in SREG T ←0T1

SEH Set Half Carry Flag in SREG H ←1H1

CLH Clear Half Carry Flag in SREG H ←0H1

MCU Control Instructions

BREAK Break (See specific descr. for BREAK) None 1

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep) None 1

WDR Watchdog Reset (see specific descr. for WDR) None 1

Mnemonics Operands Description Operation Flags #Clocks

8067M–AVR–09/10

XMEGA A1

32. Packaging information

32.1 100A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) C

100A

10/5/2001

PIN 1 IDENTIFIER

0˚~7˚

PIN 1

A1 A2 A

eE1 E

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 15.75 16.00 16.25

D1 13.90 14.00 14.10 Note 2

E 15.75 16.00 16.25

E1 13.90 14.00 14.10 Note 2

B 0.17 – 0.27

C 0.09 – 0.20

L 0.45 – 0.75

e 0.50 TYP

Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.08 mm maximum.

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

8067M–AVR–09/10

XMEGA A1

32.2 100C1

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

100C1, 100-ball, 9 x 9 x 1.2 mm Body, Ball Pitch 0.80 mm

Chip Array BGA Package (CBGA)

100C1

5/25/06

TOP VIEW

SIDE VIEW

BOTTOM VIEW

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 1.10 – 1.20

A1 0.30 0.35 0.40

D 8.90 9.00 9.10

E 8.90 9.00 9.10

D1 7.10 7.20 7.30

E1 7.10 7.20 7.30

Øb 0.35 0.40 0.45

e 0.80 TYP

Marked A1 Identifier

678

0.90 TYP

A1 Corner

0.12 Z

Øb

8067M–AVR–09/10

XMEGA A1

32.3 100C2

TITLE DRAWING NO. GPC REV.

Package Drawing Contact:

packagedrawings@atmel.com 100C2CIF A

100C2, 100-ball (10 x 10 Array), 0.65 mm Pitch,

7.0 x 7.0 x 1.0 mm, Very Thin, Fine-Pitch

Ball Grid Array Package (VFBGA)

12/23/08

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 1.00

A1 0.20 – –

A2 0.65 – –

D 6.90 7.00 7.10

D1 5.85 BSC

E 6.90 7.00 7.10

E1 5.85 BSC

b 0.30 0.35 0.40

e 0.65 BSC

TOP VIEW

SIDE VIEW

A1 BALL ID

12 3 4 5 6 7 8 9 10

0.10

100 - Ø0.35 ± 0.05

A1 BALL CORNER

BOTTOM VIEW

8067M–AVR–09/10

XMEGA A1

33. Electrical Characteristics

33.1 Absolute Maximum Ratings*

33.2 DC Characteristics

Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature ..................................... -65°C to +150°C

Voltage on any Pin with respect to Ground..-0.5V to VCC+0.5V

Maximum Operating Voltage ............................................ 3.6V

DC Current per I/O Pin ............................................... 20.0 mA

DC Current VCC and GND Pins................................ 200.0 mA

Table 33-1. Current Consumption

Symbol Parameter Condition Min Typ Max Units

ICC

Power Supply Current(1)

Active

32 kHz, Ext. Clk VCC = 1.8V TBD

µA

VCC = 3.0V TBD

1 MHz, Ext. Clk VCC = 1.8V 365

VCC = 3.0V 790

2 MHz, Ext. Clk VCC = 1.8V 690 800

VCC = 3.0V 1400 1600

32 MHz, Ext. Clk VCC = 3.0V 18.35 20 mA

Idle

32 kHz, Ext. Clk VCC = 1.8V TBD

µA

VCC = 3.0V TBD

1 MHz, Ext. Clk VCC = 1.8V 135

VCC = 3.0V 255

2 MHz, Ext. Clk VCC = 1.8V 270 380

VCC = 3.0V 510 650

32 MHz, Ext. Clk VCC = 3.0V 8.15 9.2 mA

Power-down mode

All Functions Disabled VCC = 3.0V 0.1

µA

All Functions Disabled, T = 85°C VCC = 3.0V 2 5

ULP, WDT, Sampled BOD VCC = 1.8V 0.5

VCC = 3.0V 0.6

ULP, WDT, Sampled BOD, T=85°C VCC = 3.0V 3 10

Power-save mode

RTC 1 kHz from Low Power 32 kHz

TOSC

VCC = 1.8V 0.52

VCC = 3.0V 0.55

RTC from Low Power 32 kHz TOSC VCC = 3.0V 1.16

Reset Current

Consumption without Reset pull-up resistor current VCC = 3.0V TBD

8067M–AVR–09/10

XMEGA A1

Note: 1. All Power Reduction Registers set. Typical numbers measured at T = 25°C if nothing else is specified.

2. All parameters measured as the difference in current consumption between module enabled and disabled. All data at

VCC =3.0V, Clk

SYS = 1 MHz External clock with no prescaling, T = 25°C.

Module current consumption(2)

ICC

RC32M 395

µA

RC32M w/DFLL Internal 32.768 kHz oscillator as DFLL source TBD

RC2M 120

RC2M w/DFLL Internal 32.768 kHz oscillator as DFLL source 155

RC32K 30

PLL Multiplication factor = 10x 195

Watchdog normal mode TBD

BOD Continuous mode 120

BOD Sampled mode 1

Internal 1.00 V ref 85

Temperature reference 80

RTC with int. 32 kHz RC as

source No prescaling 30

RTC with ULP as source No prescaling 1

ADC 250 kS/s - Int. 1V Ref 3.6

mADAC Normal Mode 1000 kS/s, Single channel, Int. 1V Ref 1.8

DAC Low-Power Mode 1000 KS/s, Single channel, Int. 1V Ref 1

AC High-speed 220

µA

AC Low-power 110

USART Rx and Tx enabled, 9600 BAUD 7.5

DMA 180

Timer/Counter Prescaler DIV1 18

AES 195

Flash/EEPROM

Programming

Vcc = 2V 20 mA

Vcc = 3V 30

Table 33-1. Current Consumption

Symbol Parameter Condition Min Typ Max Units

8067M–AVR–09/10

XMEGA A1

33.3 Speed

The maximum CPU clock frequency of the XMEGA A1 devices is depending on VCC. As shown

in Figure 33-1 on page 69 the Frequency vs. VCC curve is linear between 1.8V < VCC <2.7V.

Figure 33-1. Operating Frequency vs. Vcc

Table 33-2. Operating voltage and frequency

Symbol Parameter Condition Min Typ Max Units

ClkCPU CPU clock frequency

VCC = 1.6V 0 12

MHz

VCC = 1.8V 0 12

VCC = 2.7V 0 32

VCC = 3.6V 0 32

1.8

MHz

2.7 3.6

1.6

Safe Operating Area

8067M–AVR–09/10

XMEGA A1

33.4 Flash and EEPROM Memory Characteristics

Notes: 1. Programming is timed from the internal 2 MHz oscillator.

2. EEPROM is not erased if the EESAVE fuse is programmed.

Table 33-3. Endurance and Data Retention

Symbol Parameter Condition Min Typ Max Units

Flash

Write/Erase cycles 25°C 10K Cycle

85°C 10K

Data retention 25°C 100 Year

55°C 25

EEPROM

Write/Erase cycles 25°C 80K Cycle

85°C 30K

Data retention 25°C 100 Year

55°C 25

Table 33-4. Programming time

Symbol Parameter Condition Min Typ(1) Max Units

Chip Erase Flash, EEPROM(2) and SRAM Erase 40

Flash

Page Erase 6

Page Write 6

Page WriteAutomatic Page Erase and Write 12

EEPROM

Page Erase 6

Page Write 6

Page WriteAutomatic Page Erase and Write 12

8067M–AVR–09/10

XMEGA A1

33.5 ADC Characteristics

Table 33-5. ADC Characteristics

Symbol Parameter Condition Min Typ Max Units

RES Resolution Programmable: 8/12 8 12 12 Bits

INL Integral Non-Linearity 500 kS/s -5 <±1 5 LSB

DNL Differential Non-Linearity 500 kS/s < ±0.75 LSB

Gain Error ±10 mV

Offset Error ±2 mV

ADCclk ADC Clock frequency Max is 1/4 of Peripheral Clock 2000 kHz

Conversion rate 2000 ksps

Conversion time

(propagation delay)

(RES+2)/2+GAIN

RES = 8 or 12, GAIN = 0 or 1 578

ADCclk

cycles

Sampling Time 1/2 ADCclk cycle 0.25 µS

Conversion range 0 VREF V

AVCC Analog Supply Voltage Vcc-0.3 Vcc+0.3 V

VREF Reference voltage 1.0 Vcc-0.6 V

Input bandwidth 2000 kHz

INT1V Internal 1.00V reference 1.00 V

INTVCC Internal VCC/1.6 VCC/1.6 V

SCALEDVCC Scaled internal VCC/10 input VCC/10 V

RAREF Reference input resistance >10 MΩ

Start-up time 12 24 ADCclk

cycles

Internal input sampling speed Temp. sensor, VCC/10, Bandgap 100 ksps

Table 33-6. ADC Gain Stage Characteristics

Symbol Parameter Condition Min Typ Max Units

Gain error 1 to 64 gain < ±1 %

Offset error < ±1

Vrms Noise level at input 64x gain VREF = Int. 1V 0.12

VREF = Ext. 2V 0.06

Clock rate Same as ADC 1000 kHz

8067M–AVR–09/10

XMEGA A1

33.6 DAC Characteristics

33.7 Analog Comparator Characteristics

33.8 Bandgap Characteristics

Table 33-7. DAC Characteristics

Symbol Parameter Condition Min Typ Max Units

INL Integral Non-Linearity VCC = 1.6-3.6V VREF = Ext. ref 5

LSB

DNL Differential Non-Linearity VCC = 1.6-3.6V VREF = Ext. ref 0.6 <±1

VREF= AVCC 0.6

Fclk Conversion rate 1000 ksps

AREF External reference voltage 1.1 AVCC-0.6 V

Reference input impedance >10 MΩ

Max output voltage Rload=100kΩAVCC*0.98

Min output voltage Rload=100kΩ0.01

Offset factory calibration accuracy Continues mode, VCC=3.0V,

VREF = Int 1.00V, T=85°C

TBD LSB

Gain factory calibration accuracy TBD

Table 33-8. Analog Comparator Characteristics

Symbol Parameter Condition Min Typ Max Units

Voff Input Offset Voltage VCC = 1.6 - 3.6V <±5 mV

Ilk Input Leakage Current VCC = 1.6 - 3.6V < 1000 pA

Vhys1 Hysteresis, No VCC = 1.6 - 3.6V 0 mV

Vhys2 Hysteresis, Small VCC = 1.6 - 3.6V mode = HS 25 mV

Vhys3 Hysteresis, Large VCC = 1.6 - 3.6V mode = HS 50

tdelay Propagation delay

VCC = 3.0V, T= 85°C mode = HS 100

nsVCC = 1.6 - 3.6V mode = HS 70

VCC = 1.6 - 3.6V mode = LP 140

Table 33-9. Bandgap Voltage Characteristics

Symbol Parameter Condition Min Typ Max Units

Bandgap startup time As reference for ADC or DAC 1 Clk_PER + 2.5µs µs

As input to AC or ADC TBD

Bandgap voltage 1.1

ADC/DAC ref T= 85°C, After calibration 0.99 1.01

Variation over voltage and temperature VCC = 1.6 - 3.6V, T = -40°C to 85°C±5 %

8067M–AVR–09/10

XMEGA A1

33.9 Brownout Detection Characteristics

Note: 1. BOD is calibrated to BOD level 0 at 85°C, and BOD level 0 is the default level.

33.10 PAD Characteristics

Table 33-10. Brownout Detection Characteristics(1)

Symbol Parameter Condition Min Typ Max Units

BOD level 0 falling Vcc 1.6

BOD level 1 falling Vcc 1.9

BOD level 2 falling Vcc 2.1

BOD level 3 falling Vcc 2.4

BOD level 4 falling Vcc 2.6

BOD level 5 falling Vcc 2.9

BOD level 6 falling Vcc 3.2

BOD level 7 falling Vcc 3.4

Hysteresis BOD level 0-5 2 %

Table 33-11. PAD Characteristics

Symbol Parameter Condition Min Typ Max Units

VIH Input High Voltage VCC = 2.4 - 3.6V 0.7*VCC VCC+0.5

VCC = 1.6 - 2.4V 0.8*VCC VCC+0.5

VIL Input Low Voltage VCC = 2.4 - 3.6V -0.5 0.3*VCC

VCC = 1.6 - 2.4V -0.5 0.2*VCC

VOL Output Low Voltage GPIO

IOH = 15 mA, VCC = 3.3V 0.45 0.76

IOH = 10 mA, VCC = 3.0V 0.3 0.64

IOH = 5 mA, VCC = 1.8V 0.2 0.46

VOH Output High Voltage GPIO

IOH = -8 mA, VCC = 3.3V 2.6 3

IOH = -6 mA, VCC = 3.0V 2.1 2.2

IOH = -2 mA, VCC = 1.8V 1.4 1.6

IIL Input Leakage Current I/O pin <0.001 1 µA

IIH Input Leakage Current I/O pin <0.001 1

RPI/O pin Pull/Buss keeper Resistor 20 kΩ

RRST Reset pin Pull-up Resistor 20

Input hysteresis 0.5 V

8067M–AVR–09/10

XMEGA A1

33.11 POR Characteristics

33.12 Reset Characteristics

33.13 Oscillator Characteristics

Table 33-12. Power-on Reset Characteristics

Symbol Parameter Condition Min Typ Max Units

VPOT- POR threshold voltage falling Vcc 1 V

VPOT+ POR threshold voltage rising Vcc 1.4

Table 33-13. Reset Characteristics

Symbol Parameter Condition Min Typ Max Units

Minimum reset pulse width 90 ns

Reset threshold voltage VCC = 2.7 - 3.6V 0.45*VCC V

VCC = 1.6 - 2.7V 0.42*VCC

Table 33-14. Internal 32.768 kHz Oscillator Characteristics

Symbol Parameter Condition Min Typ Max Units

Accuracy T = 85°C, VCC = 3V,

After production calibration -0.5 0.5 %

Table 33-15. Internal 2 MHz Oscillator Characteristics

Symbol Parameter Condition Min Typ Max Units

Accuracy T = 85°C, VCC = 3V,

After production calibration -1.5 1.5 %

DFLL Calibration step size T = 25°C, VCC = 3V 0.175

Table 33-16. Internal 32 MHz Oscillator Characteristics

Symbol Parameter Condition Min Typ Max Units

Accuracy T = 85°C, VCC = 3V,

After production calibration -1.5 1.5 %

DFLL Calibration stepsize T = 25°C, VCC = 3V 0.2

Table 33-17. Internal 32 kHz, ULP Oscillator Characteristics

Symbol Parameter Condition Min Typ Max Units

Output frequency 32 kHz ULP OSC T = 85°C, VCC = 3.0V 26 kHz

8067M–AVR–09/10

XMEGA A1

Notes: 1. Non-prescaled System Clock source.

2. Time from pin change on external interrupt pin to first available clock cycle. Additional interrupt response time is minimum 5

system clock source cycles.

Table 33-18. Maximum load capacitance (CL) and ESR recommendation for 32.768 kHz Crystal

Crystal CL [pF] Max ESR [kΩ]

6.5 60

935

Table 33-19. Device wake-up time from sleep

Symbol Parameter Condition(1) Min Typ(2) Max Units

Idle Sleep, Standby and Extended

Standby sleep mode

Int. 32.768 kHz RC 130

µS

Int. 2 MHz RC 2

Ext. 2 MHz Clock 2

Int. 32 MHz RC 0.17

Power-save and Power-down Sleep

mode

Int. 32.768 kHz RC 320

Int. 2 MHz RC 10.3

Ext. 2 MHz Clock 4.5

Int. 32 MHz RC 5.8

8067M–AVR–09/10

XMEGA A1

34. Typical Characteristics

34.1 Active Supply Current

Figure 34-1. Active Supply Current vs. Frequency

fSYS = 1 - 32 MHz, T = 25°C

Figure 34-2. Active Supply Current vs. VCC

fSYS = 1.0 MHz

3.3V

3.0V

2.7V

04812 16 20 24 2832

Frequency [MHz]

[mA]

1.8V

2.2V

85°C

25°C

-40°C

200

400

600

800

1000

1200

1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6

Vcc [V]

[uA]

8067M–AVR–09/10

XMEGA A1

34.2 Idle Supply Current

Figure 34-3. Idle Supply Current vs. Frequency

fSYS = 1 - 32 MHz, T = 25°C

Figure 34-4. Active Supply Current vs. VCC

fSYS = 1.0 MHz

3.3V

3.0V

2.7V

04812 16 20 24 2832

Frequency [MHz]

Icc [mA]

1.8V

2.2V

85°C

25°C

-40°C

100

150

200

250

300

350

400

1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6

[V]

[uA]

8067M–AVR–09/10

XMEGA A1

34.3 Power-down Supply Current

Figure 34-5. Power-down Supply Current vs. Temperature

34.4 Power-save Supply Current

Figure 34-6. Power-save Supply Current vs. Temperature

Sampled BOD, WDT, RTC from ULP enabled

3.3V

3.0V

2.7V

2.2V

1.8V

0.5

1.5

2.5

-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090

Temperature [°C]

[uA]

3.3V

2.7V

2.2V

1.8V

0.5

1.5

2.5

3.5

-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090

Temperature [°C]

[uA]

8067M–AVR–09/10

XMEGA A1

34.5 Pin Pull-up

Figure 34-7. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage

VCC = 1.8V

Figure 34-8. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage

VCC = 3.0V

85 °C 25 °C

-40 °C

100

0 0.2 0.4 0.6 0.81 1.2 1.4

reset

[V]

reset

[uA]

85 °C

25 °C

-40 °C

100

120

140

160

180

0 0.5 1 1.5 2 2.5

vreset [V]

Ireset [uA]

8067M–AVR–09/10

XMEGA A1

Figure 34-9. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage

VCC = 3.3V

34.6 Pin Thresholds and Hysteresis

Figure 34-10. I/O Pin Input Threshold Voltage vs. VCC

VIH - I/O Pin Read as “1”

85 °C

25 °C

-40 °C

100

120

140

160

180

00.511.522.53

reset

[V]

reset

[uA]

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6

[V]

threshold

[V]

8067M–AVR–09/10

XMEGA A1

Figure 34-11. I/O Pin Input Threshold Voltage vs. VCC

VIL - I/O Pin Read as “0”

Figure 34-12. I/O Pin Input Hysteresis vs. VCC.

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6

cc [V]

Vthreshold [V]

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6

Vcc [V]

threshold

[V]

8067M–AVR–09/10

XMEGA A1

Figure 34-13. Reset Input Threshold Voltage vs. VCC

VIH - I/O Pin Read as “1”

Figure 34-14. Reset Input Threshold Voltage vs. VCC

VIL - I/O Pin Read as “0”

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6

[V]

threshold

[V]

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6

[V]

threshold

[V]

8067M–AVR–09/10

XMEGA A1

34.7 Bod Thresholds

Figure 34-15. BOD Thresholds vs. Temperature

BOD Level = 1.6V

Figure 34-16. BOD Thresholds vs. Temperature

BOD Level = 2.9V

Rising Vcc

Falling Vcc

1.602

1.608

1.614

1.62

1.626

1.632

1.638

-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090

Temperature [°C]

BOT

[V]

Rising Vcc

Falling Vcc

2.905

2.92

2.935

2.95

2.965

2.98

2.995

3.01

-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090

Temperature [°C]

BOT

[V]

8067M–AVR–09/10

XMEGA A1

34.8 Bandgap

Figure 34-17. Internal 1.00V Reference vs. Temperature.

34.9 Analog Comparator

Figure 34-18. Analog Comparator Hysteresis vs. VCC

High-speed, Small hysteresis

3.0V

1.8V

0.999

0.9995

1.0005

1.001

1.0015

1.002

1.0025

1.003

1.0035

1.004

-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090

Temperature [°C]

REF

[V]

25°C

1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6

[V]

Hysteresis [mV]

8067M–AVR–09/10

XMEGA A1

Figure 34-19. Analog Comparator Hysteresis vs. VCC, High-speed

Large hysteresis

Figure 34-20. Analog Comparator Propagation Delay vs. VCC

High-speed

25°C

1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6

Vcc [V]

Hysteresis [mV]

25°C

100

120

1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6

[V]

Propagation Delay [ns]

8067M–AVR–09/10

XMEGA A1

34.10 Oscillators and Wake-up Time

Figure 34-21. Internal 32.768 kHz Oscillator Frequency vs. Temperature

1.024 kHz output

Figure 34-22. Ultra Low-Power (ULP) Oscillator Frequency vs. Temperature

1 kHz output

3.0 V

1.8 V

0.99

0.995

1.005

1.01

1.015

1.02

1.025

1.03

-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090

T [°C]

f [kHz]

3.0 V

1.8 V

0.87

0.88

0.89

0.9

0.91

0.92

0.93

-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090

T [°C]

f1kHz output [kHz]

8067M–AVR–09/10

XMEGA A1

Figure 34-23. Internal 2 MHz Oscillator CalA Calibration Step Size

T = -40 to 85

C, VCC = 3V

Figure 34-24. Internal 2 MHz Oscillator CalB Calibration Step Size

T = -40 to 85

C, VCC = 3V

0.001

0.002

0.003

0.004

0.005

0.006

020406080100120140

CALA [LSB]

Step size: f [MHz]

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0 10203040506070

CALB [LSB]

Step size: f [MHz]

8067M–AVR–09/10

XMEGA A1

Figure 34-25. Internal 32 MHz Oscillator CalA Calibration Step Size

T = -40 to 85

C, VCC = 3V

Figure 34-26. Internal 32 MHz Oscillator CalB Calibration Step Size

T = -40 to 85

C, VCC = 3V

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

020406080 100 120 140

CALA

Step size: f [MHz]

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 10203040506070

CALB

Step size: f [MHz]

8067M–AVR–09/10

XMEGA A1

34.11 PDI Speed

Figure 34-27. PDI Speed vs. VCC

25 °C

1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6

VCC [V]

fMAX [MHz]

8067M–AVR–09/10

XMEGA A1

35. Errata

35.1 ATxmega128A1 rev. H

•Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously

•VCC voltage scaler for AC is non-linear

•The ADC has up to ±2 LSB inaccuracy

•ADC gain stage output range is limited to 2.4 V

•Sampling speed limited to 500 ksps for supply voltage below 2.0V

•ADC Event on compare match non-functional

•Bandgap measurement with the ADC is non-functional when VCC is below 2.7V

•Accuracy lost on first three samples after switching input to ADC gain stage

•The input difference between two succeeding ADC samples is limited by VREF

•Increased noise when using internal 1.0V reference at low temperature

•Configuration of PGM and CWCM not as described in XMEGA A Manual

•PWM is not restarted properly after a fault in cycle-by-cycle mode

•BOD will be enabled at any reset

•BODACT fuse location is not correct

•Sampled BOD in Active mode will cause noise when bandgap is used as reference

•DAC has up to ±10 LSB noise in Sampled Mode

•DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V

•DAC refresh may be blocked in S/H mode

•Conversion lost on DAC channel B in event triggered mode

•Both DFLLs and both oscillators have to be enabled for one to work

•Access error when multiple bus masters are accessing SDRAM

•EEPROM page buffer always written when NVM DATA0 is written

•Pending full asynchronous pin change interrupts will not wake the device

•Pin configuration does not affect Analog Comparator Output

•Low level interrupt triggered when pin input is disabled

•JTAG enable does not override Analog Comparator B output

•NMI Flag for Crystal Oscillator Failure automatically cleared

•Flash Power Reduction Mode can not be enabled when entering sleep

•Some NVM Commands are non-functional

•Crystal start-up time required after power-save even if crystal is source for RTC

•Setting PRHIRES bit makes PWM output unavailable

•Accessing EBI address space with PREBI set will lock Bus Master

•RTC Counter value not correctly read after sleep

•Pending asynchronous RTC-interrupts will not wake up device

•TWI, the minimum I2C SCL low time could be violated in Master Read mode

•TWI address-mask feature is non-functional

•TWI, a general address call will match independent of the R/W-bit value

•TWI Transmit collision flag not cleared on repeated start

•Clearing TWI Stop Interrupt Flag may lock the bus

•TWI START condition at bus timeout will cause transaction to be dropped

•TWI Data Interrupt Flag erroneously read as set

•WDR instruction inside closed window will not issue reset

8067M–AVR–09/10

XMEGA A1

1. Bandgap voltage input for the ACs cannot be changed when used for both ACs

simultaneously

If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then

selected/deselected as input for another AC, the first comparator will be affected for up to

1 µs and could potentially give a wrong comparison result.

Problem fix/Workaround

If the Bandgap is required for both ACs simultaneously, configure the input selection for both

ACs before enabling any of them.

2. VCC voltage scaler for AC is non-linear

The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.

Figure 35-1. Analog Comparator Voltage Scaler vs. Scalefac

T = 25°C

Problem fix/Workaround

Use external voltage input for the analog comparator if accurate voltage levels are needed

3. The ADC has up to ±2 LSB inaccuracy

The ADC will have up to ±2 LSB inaccuracy, visible as a saw-tooth pattern on the input volt-

age/ output value transfer function of the ADC. The inaccuracy increases with increasing

voltage reference reaching ±2 LSB with 3V reference.

Problem fix/Workaround

None, the actual ADC resolution will be reduced with up to ±2 LSB.

4. ADC gain stage output range is limited to 2.4 V

The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential

input will only give correct output when below 2.4 V/gain. For the available gain settings, this

gives a differential input range of:

3.3 V

2.7 V

1.8 V

0.5

1.5

2.5

3.5

0 5 10 15 20 25 30 35 40 45 50 55 60 65

SCALEFAC

VSCALE [V]

8067M–AVR–09/10

XMEGA A1

Problem fix/Workaround

Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a cor-

rect result, or keep ADC voltage reference below 2.4 V.

5. Sampling speed limited to 500 ksps for supply voltage below 2.0V

The sampling frequency is limited to 500 ksps for supply voltage below 2.0V. At higher sam-

pling rate the INL error will be several hundred LSB.

Problem fix/Workaround

None.

6. ADC Event on compare match non-functional

ADC signalling event will be given at every conversion complete even if Interrupt mode (INT-

MODE) is set to BELOW or ABOVE.

Problem fix/Workaround

Enable and use interrupt on compare match when using the compare function.

7. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V

The ADC can not be used to do bandgap measurements when VCC is below 2.7V.

Problem fix/Workaround

None.

8. Accuracy lost on first three samples after switching input to ADC gain stage

Due to memory effect in the ADC gain stage, the first three samples after changing input

channel must be disregarded to achieve 12-bit accuracy.

Problem fix/Workaround

Run three ADC conversions and discard these results after changing input channels to ADC

gain stage.

9. The input difference between two succeeding ADC samples is limited by VREF

If the difference in input between two samples changes more than the size of the reference,

the ADC will not be able to convert the data correctly. Two conversions will be required

before the conversion is correct.

Problem fix/Workaround

Discard the first conversion if input is changed more than VREF, or ensure that the input

never changes more then VREF.

– 1x gain: 2.4 V

– 2x gain: 1.2 V

– 4x gain: 0.6 V

– 8x gain: 300 mV

– 16x gain: 150 mV

– 32x gain: 75 mV

– 64x gain: 38 mV

8067M–AVR–09/10

XMEGA A1

10. Increased noise when using internal 1.0V reference at low temperature

When operating at below 0°C and using internal 1.0V reference the RMS noise will be up

4 LSB, Peak-to-peak noise up to 25 LSB.

Problem fix/Workaround

Use averaging to remove noise.

11. Configuration of PGM and CWCM not as described in XMEGA A Manual

Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM),

but not Common Waveform Channel Mode.

Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode

(CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode.

Problem fix/Workaround

12 PWM is not restarted properly after a fault in cycle-by-cycle mode

When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not

return to normal operation at first update after fault condition is no longer present.

Problem fix/Workaround

Do a write to any AWeX I/O register to re-enable the output.

13. BOD will be enabled after any reset

If any reset source goes active, the BOD will be enabled and keep the device in reset if the

VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be

released until VCC is above the programmed BOD level even if the BOD is disabled.

Problem fix/Workaround

Do not set the BOD level higher than VCC even if the BOD is not used.

14. BODACT fuse location is not correct

The fuses for enabling BOD in active mode (BODACT) are located at FUSEBYTE2, bit 2

and 3 and not in FUSEBYTE 5 as described in the XMEGA A Manual..

Problem fix/Workaround

Access the fuses in FUSEBYTE2.

15. Sampled BOD in Active mode will cause noise when bandgap is used as reference

Using the BOD in sampled mode when the device is running in Active or Idle mode will add

noise on the bandgap reference for ADC, DAC and Analog Comparator.

Problem fix/Workaround

If the bandgap is used as reference for either the ADC, DAC or Analog Comparator, the

BOD must not be set in sampled mode.

Table 35-1. Configure PWM and CWCM according to this table:

PGM CWCM Description

0 0 PGM and CWCM disabled

0 1 PGM enabled

1 0 PGM and CWCM enabled

1 1 PGM enabled

8067M–AVR–09/10

XMEGA A1

16. DAC has up to ±10 LSB noise in Sampled Mode

The DAC has noise of up to ±10 LSB in Sampled Mode for entire operation range.

Problem fix/Workaround

Use the DAC in continuous mode.

17. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V

Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate out-

put when converting codes that give below 0.75V output:

– ±10 LSB for continuous mode

– ±200 LSB for Sample and Hold mode

Problem fix/Workaround

None.

18. DAC has up to ±10 LSB noise in Sampled Mode

If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is

done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this

will block refresh signals to the second channel.

Problem fix/Workaround

When using the DAC in S/H mode, ensure that none of the channels is running at maximum

conversion rate, or ensure that the conversion rate of both channels is high enough to not

require refresh.

19. Conversion lost on DAC channel B in event triggered mode

If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1

conversions are occasionally lost. This means that not all data-values written to the

Channel 1 data register are converted.

Problem fix/Workaround

Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Periph-

eral clock frequency so the conversion internal never is shorter than 1.5 µs.

20. Both DFLLs and both oscillators have to be enabled for one to work

In order to use the automatic runtime calibration for the 2 MHz or the 32 MHz internal oscil-

lators, the DFLL for both oscillators and both oscillators have to be enabled for one to work.

Problem fix/Workaround

Enable both DFLLs and both oscillators when using automatic runtime calibration for either

of the internal oscillators.

21. Access error when multiple bus masters are accessing SDRAM

If one bus master (CPU and DMA channels) is using the EBI to access an SDRAM in burst

mode and another bus master is accessing the same row number in a different BANK of the

SDRAM in the cycle directly after the burst access is complete, the access for the second

bus master will fail.

Problem fix/Workaround

Do not put stack pointer in SDRAM and use DMA Controller in 1 byte burst mode if CPU and

DMA Controller are required to access SDRAM at the same time.

8067M–AVR–09/10

XMEGA A1

22. EEPROM page buffer always written when NVM DATA0 is written

If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM

page buffer.

Problem fix/Workaround

Before writing to NVM DATA0, for example when doing software CRC or flash page buffer

write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM

DATA0 when EELOAD is set.

23. Pending full asynchronous pin change interrupts will not wake the device

Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the

sleep instruction is executed, will be ignored until the device is woken from another source

or the source triggers again. This applies when entering all sleep modes where the System

Clock is stopped.

Problem fix/Workaround

None.

24. Pin configuration does not affect Analog Comparator Output

The Output/Pull and inverted pin configuration does not affect the Analog Comparator out-

put function.

Problem fix/Workaround

None for Output/Pull configuration.

For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect

positive input to the negative AC input and vice versa), or use and external inverter to

change polarity of Analog Comparator output.

25. Low level interrupt triggered when pin input is disabled

If a pin input is disabled, but pin is configured to trigger on low level, interrupt request will be

sent.

Problem fix/Workaround

Ensure that Interrupt mask for the disabled pin is cleared.

26. JTAG enable does not override Analog Comparator B output

When JTAG is enabled this will not override the Analog Comparator B (ACB) output,

AC0OUT on pin 7 if this is enabled.

Problem fix/Workaround

Use Analog Comparator output for ACA when JTAG is used, or use the PDI as debug

interface.

27. NMI Flag for Crystal Oscillator Failure automatically cleared

NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when exe-

cuting the NMI interrupt handler.

Problem fix/Workaround

This device revision has only one NMI interrupt source, so checking the interrupt source in

software is not required.

8067M–AVR–09/10

XMEGA A1

28. Flash Power Reduction Mode can not be enabled when entering sleep

If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby

sleep mode, the device will only wake up on every fourth wake-up request. If Flash Power

Reduction Mode is enabled when entering Idle sleep mode, the wake-up time will vary with

up to 16 CPU clock cycles.

Problem fix/Workaround

Disable Flash Power Reduction mode before entering sleep mode.

29. Some NVM Commands are non-functional

The following NVM commands are non-functional:

Problem fix/Workaround

None for Flash Range CRC

Use separate programming commands for accessing application and boot section.

30. Crystal start-up time required after power-save even if crystal is source for RTC

Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be

ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscilla-

tor Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during

this period (0.5s).

Problem fix/Workaround

If faster start-up is required, go to sleep with internal oscillator as system clock.

31. Setting PRHIRES bit makes PWM output unavailable

Setting the HIRES Power Reduction (PR) bit for PORTx will make any Frequency or PWM

output for the corresponding Timer/Counters (TCx0 and TCx1) unavailable on the pin even if

the Hi-Res is not used.

Problem fix/Workaround

Do not write the HIRES PR bit on PORTx when frequency or PWM output from TCx0/1 is

used.

32. Accessing EBI address space with PREBI set will lock Bus Master

– 0x2B Erase Flash Page

– 0x2E Write Flash Page

– 0x2F Erase & Write Flash Page

– 0x3A Flash Range CRC

– 0x22 Erase Application Section Page

– 0x24 Write Application Section Page

– 0x25 Erase & Write Application Section Page

– 0x2A Erase Boot Loader Section Page

– 0x2C Write Boot Loader Section Page

– 0x2D Erase & Write Boot Loader Section Page

8067M–AVR–09/10

XMEGA A1

If EBI Power Reduction Bit is set while EBI is enabled, accessing external memory could

result in bus hang-up, blocking all further access to all data memory.

Problem fix/Workaround

Ensure that EBI is disabled before setting EBI Power Reduction bit.

33. RTC Counter value not correctly read after sleep

If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to

bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not

be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will

be the same as the value in the register when entering sleep.

The same applies if RTC Compare Match is used as wake-up source.

Problem fix/Workaround

Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.

34. Pending asynchronous RTC-interrupts will not wake up device

Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep

instruction is executed, will be ignored until the device is woken from another source or the

source triggers again.

Problem fix/Workaround

None.

35. TWI, the minimum I2C SCL low time could be violated in Master Read mode

If the TWI is in Master Read mode and issues a Repeated Start on the bus, this will immedi-

ately release the SCL line even if one complete SCL low period has not passed. This means

that the minimum SCL low time in the I2C specification could be violated.

Problem fix/Workaround

If this is a problem in the application, ensure in software that the Repeated Start is never

issued before one SCL low time has passed.

36. TWI address-mask feature is non-functional

The address-mask feature is non-functional, so the TWI can not perform hardware address

match on more than one address.

Problem fix/Workaround

If the TWI must respond to multiple addresses, enable Promiscuous Mode for the TWI to

respond to all address and implement the address-mask function in software.

37. TWI, a general address call will match independent of the R/W-bit value

When the TWI is in Slave mode and a general address call is issued on the bus, the TWI

Slave will get an address match regardless of the received R/W bit.

Problem fix/Workaround

Use software to check the R/W-bit on general call address match.

38. TWI Transmit collision flag not cleared on repeated start

The TWI transmit collision flag should be automatically cleared on start and repeated start,

but is only cleared on start.

8067M–AVR–09/10

XMEGA A1

Problem fix/Workaround

Clear the flag in software after address interrupt.

39. Clearing TWI Stop Interrupt Flag may lock the bus

If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the

hardware sets this flag due to a new address received, CLKHOLD is not cleared and the

SCL line is not released. This will lock the bus.

Problem fix/Workaround

Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is

not IDLE, wait for the SCL pin to be low before clearing APIF.

Code:

/* Only clear the interrupt flag if within a "safe zone". */

while ( /* Bus not IDLE: */

((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=

TWI_MASTER_BUSSTATE_IDLE_gc)) &&

/* SCL not held by slave: */

!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)

)

{

/* Ensure that the SCL line is low */

if ( !(COMMS_PORT.IN & PIN1_bm) )

break;

}

/* Check for an pending address match interrupt */

if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )

{

/* Safely clear interrupt flag */

COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;

}

40. TWI START condition at bus timeout will cause transaction to be dropped

If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a

START is detected, the transaction will be dropped.

Problem fix/Workaround

None.

41. TWI Data Interrupt Flag erroneously read as set

When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock

cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command

will show the DIF still set.

Problem fix/Workaround

Add one NOP instruction before checking DIF.

8067M–AVR–09/10

XMEGA A1

42. WDR instruction inside closed window will not issue reset

When a WDR instruction is execute within one ULP clock cycle after updating the window

control register, the counter can be cleared without giving a system reset.

Problem fix/Workaround

Wait at least one ULP clock cycle before executing a WDR instruction.

100

8067M–AVR–09/10

XMEGA A1

35.2 ATxmega128A1 rev. G

•Bootloader Section in Flash is non-functional

•Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously

•DAC is nonlinear and inaccurate when reference is above 2.4V

•ADC gain stage output range is limited to 2.4 V

•The ADC has up to ±2 LSB inaccuracy

•TWI, a general address call will match independent of the R/W-bit value

•TWI, the minimum I2C SCL low time could be violated in Master Read mode

•Setting HIRES PR bit makes PWM output unavailable

•EEPROM erase and write does not work with all System Clock sources

•BOD will be enabled after any reset

•Propagation delay analog Comparator increasing to 2 ms at -40°C

•Sampled BOD in Active mode will cause noise when bandgap is used as reference

•Default setting for SDRAM refresh period too low

•Flash Power Reduction Mode can not be enabled when entering sleep mode

•Enabling Analog Comparator B output will cause JTAG failure

•JTAG enable does not override Analog Comparator B output

•Bandgap measurement with the ADC is non-functional when VCC is below 2.7V

•DAC refresh may be blocked in S/H mode

•Inverted I/O enable does not affect Analog Comparator Output

•Both DFLLs and both oscillators has to be enabled for one to work

1. Bootloader Section in Flash is non-functional

The Bootloader Section is non-functional, and bootloader or application code cannot reside

in this part of the Flash.

Problem fix/Workaround

None, do not use the Bootloader Section.

2. Bandgap voltage input for the ACs cannot be changed when used for both ACs

simultaneously

If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then

selected/deselected as input for the another AC, the first comparator will be affected for up

to 1 us and could potentially give a wrong comparison result.

Problem fix/Workaround

If the Bandgap is required for both ACs simultaneously, configure the input selection for both

ACs before enabling any of them.

3. DAC is nonlinear and inaccurate when reference is above 2.4V

Using the DAC with a reference voltage above 2.4V give inaccurate output when converting

codes that give below 0.75V output:

– ±20 LSB for continuous mode

– ±200 LSB for Sample and Hold mode

Problem fix/Workaround

None, avoid using a voltage reference above 2.4V.

101

8067M–AVR–09/10

XMEGA A1

4. ADC gain stage output range is limited to 2.4 V

The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential

input will only give correct output when below 2.4 V/gain. For the available gain settings, this

gives a differential input range of:

Problem fix/Workaround

Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a cor-

rect result, or keep ADC voltage reference below 2.4 V.

5. The ADC has up to ±2 LSB inaccuracy

The ADC will have up to ±2 LSB inaccuracy, visible as a saw-tooth pattern on the input volt-

age/ output value transfer function of the ADC. The inaccuracy increases with increasing

voltage reference reaching ±2 LSB with 3V reference.

Problem fix/Workaround

None, the actual ADC resolution will be reduced with up to ±2 LSB.

6. TWI, a general address call will match independent of the R/W-bit value

When the TWI is in Slave mode and a general address call is issued on the bus, the TWI

Slave will get an address match regardless of the R/W-bit (ADDR[0] bit) value in the Slave

Address Register.

Problem fix/Workaround

Use software to check the R/W-bit on general call address match.

7. TWI, the minimum I2C SCL low time could be violated in Master Read mode

When the TWI is in Master Read mode and issuing a Repeated Start on the bus, this will

immediately release the SCL line even if one complete SCL low period has not passed. This

means that the minimum SCL low time in the I2C specification could be violated.

Problem fix/Workaround

If this causes a potential problem in the application, software must ensure that the Repeated

Start is never issued before one SCL low time has passed.

8. Setting HIRES PR bit makes PWM output unavailable

Setting the HIRES Power Reduction (PR) bit for PORTx will make any Frequency or PWM

output for the corresponding Timer/Counters (TCx0 and TCx1) unavailable on the pin.

Problem fix/Workaround

Do not write the HIRES PR bit on PORTx when frequency or PWM output from TCx0/1 is

used.

– 1x gain: 2.4 V

– 2x gain: 1.2 V

– 4x gain: 0.6 V

– 8x gain: 300 mV

– 16x gain: 150 mV

– 32x gain: 75 mV

– 64x gain: 38 mV

102

8067M–AVR–09/10

XMEGA A1

9. EEPROM erase and write does not work with all System Clock sources

When doing EEPROM erase or Write operations with other clock sources than the 2 MHz

RCOSC, Flash will be read wrongly for one or two clock cycles at the end of the EEPROM

operation.

Problem fix/Workaround

Alt 1: Use the internal 2 MHz RCOSC when doing erase or write operations on EEPROM.

Alt 2: Ensure to be in sleep mode while completing erase or write on EEPROM. After starting

erase or write operations on EEPROM, other interrupts should be disabled and the device

put to sleep.

10. BOD will be enabled after any reset

If any reset source goes active, the BOD will be enabled and keep the device in reset if the

VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be

released until VCC is above the programmed BOD level even if the BOD is disabled.

Problem fix/Workaround

Do not set the BOD level higher than VCC even if the BOD is not used.

11. Propagation delay analog Comparator increasing to 2 ms at -40 °C

When the analog comparator is used at temperatures reaching down to -40 °C, the propaga-

tion delay will increase to ~2 ms.

Problem fix/Workaround

None

12. Sampled BOD in Active mode will cause noise when bandgap is used as reference

Using the BOD in sampled mode when the device is running in Active or Idle mode will add

noise on the bandgap reference for ADC and DAC.

Problem fix/Workaround

If the bandgap is used as reference for either the ADC or the DAC, the BOD must not be set

in sampled mode.

13. Default setting for SDRAM refresh period too low

If the SDRAM refresh period is set to a value less then 0x20, the SDRAM content may be

corrupted when accessing through On-Chip Debug sessions.

Problem fix/Workaround

The SDRAM refresh period (REFRESHH/L) should not be set to a value less then 0x20.

14. Flash Power Reduction Mode can not be enabled when entering sleep mode

If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby

sleep mode, the device will only wake up on every fourth wake-up request.

If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time

will vary with up to 16 CPU clock cycles.

Problem fix/Workaround

Disable Flash Power Reduction mode before entering sleep mode.

103

8067M–AVR–09/10

XMEGA A1

15. JTAG enable does not override Analog Comparator B output

When JTAG is enabled this will not override the Anlog Comparator B (ACB)ouput, AC0OUT

on pin 7 if this is enabled.

Problem fix/Workaround

AC0OUT for ACB should not be enabled when JTAG is used. Use only analog comparator

output for ACA when JTAG is used, or use the PDI as debug interface.

16. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V

The ADC cannot be used to do bandgap measurements when VCC is below 2.7V.

Problem fix/Workaround

If internal voltages must be measured when VCC is below 2.7V, measure the internal 1.00V

reference instead of the bandgap.

17. DAC refresh may be blocked in S/H mode

If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is

done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this

will block refresh signals to the second channel.

Problem fix/Workarund

When using the DAC in S/H mode, ensure that none of the channels is running at maximum

conversion rate, or ensure that the conversion rate of both channels is high enough to not

require refresh.

18. Inverted I/O enable does not affect Analog Comparator Output

The inverted I/O pin function does not affect the Analog Comparator output function.

Problem fix/Workarund

Configure the analog comparator setup to give a inverted result (i.e. connect positive input to

the negative AC input and vice versa), or use and externel inverter to change polarity of

Analog Comparator Output.

19. Both DFLLs and both oscillators has to be enabled for one to work

In order to use the automatic runtime calibration for the 2 MHz or the 32 MHz internal oscilla-

tors, the DFLL for both oscillators and both oscillators has to be enabled for one to work.

Problem fix/Workarund

Enabled both DFLLs and oscillators when using automatic runtime calibration for one of the

internal oscillators.

104

8067M–AVR–09/10

XMEGA A1

36. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The

referring revision in this section are referring to the document revision.

36.1 8067M – 09/10

36.2 8067L – 08/10

36.3 8067K – 02/10

36.4 8067J – 02/10

1. Updated Errata “ATxmega128A1 rev. H” on page 90

1. Removed Footnote 3 of Figure 2-1 on page 3

2. Updated “Features” on page 27. Event Channel 0 output on port pin 7

3. Updated “DC Characteristics” on page 67, by adding Icc for Flash/EEPROM Programming.

4. Added AVCC in “ADC Characteristics” on page 71.

5. Updated Start up time in “ADC Characteristics” on page 71.

6. Updated “DAC Characteristics” on page 72. Removed DC output impedence.

7. Fixed typo in “Packaging information” section.

8. Fixed typo in “Errata” section.

1. Added “PDI Speed vs. VCC” on page 89.

1. Removed JTAG Reset from the datasheet.

2. Updated “Timer/Counter and AWEX functions” on page 50.

3. Updated “Alternate Pin Functions” on page 51.

3. Updated all “Electrical Characteristics” on page 67.

4. Updated “PAD Characteristics” on page 73.

5. Changed Internal Oscillator Speed to “Oscillators and Wake-up Time” on page 86.

6. Updated “Errata” on page 90

105

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XMEGA A1

36.5 8067I – 04/09

36.6 8067H – 04/09

36.7 8067G – 11/08

36.8 8067F – 09/08

1. Updated “Ordering Information” on page 2.

2. Updated “PAD Characteristics” on page 73.

1. Editorial updates.

2. Updated “Overview” on page 48.

3. Updated Table 29-9 on page 54.

4. Updated “Peripheral Module Address Map” on page 58. IRCOM has address map: 0x08F8.

5. Updated “Electrical Characteristics” on page 67.

6. Updated “PAD Characteristics” on page 73.

7. Updated “Typical Characteristics” on page 76.

1. Updated “Block Diagram” on page 6.

2. Updated feature list in “Memories” on page 10.

3. Updated “PDI - Program and Debug Interface” on page 48.

4. Updated “Peripheral Module Address Map” on page 58. IRCOM has address 0x8F0.

5. Added “Electrical Characteristics” on page 67.

6. Added “Typical Characteristics” on page 76.

7. Added “ATxmega128A1 rev. H” on page 90.

8. Updated “ATxmega128A1 rev. G” on page 100.

1. Updated “Features” on page 1

2. Updated “Ordering Information” on page 2

3. Updated Figure 7-1 on page 11 and Figure 7-2 on page 11.

4. Updated Table 7-2 on page 15.

5. Updated “Features” on page 41 and “Overview” on page 41.

6. Removed “Interrupt Vector Summary” section from datasheet.

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XMEGA A1

36.9 8067E – 08/08

36.10 8067D – 07/08

36.11 8067C – 06/08

36.12 8067B – 05/08

1. Changed Figure 2-1’s title to “Block diagram and pinout” on page 3.

2. Updated Figure 2-2 on page 4.

3. Updated Table 29-2 on page 51 and Table 29-3 on page 52.

1. Updated “Ordering Information” on page 2.

2. Updated “Peripheral Module Address Map” on page 58.

3. Inserted “Interrupt Vector Summary” on page 56.

1. Updated the Front page and “Features” on page 1.

2. Updated the “DC Characteristics” on page 67.

3. Updated Figure 3-1 on page 6.

4. Added “Flash and EEPROM Page Size” on page 15.

5. Updated Table 33-6 on page 71 with new data: Gain Error, Offset Error and Signal -to-Noise

Ratio (SNR).

6. Updated Errata “ATxmega128A1 rev. G” on page 100.

1. Updated “Pinout/Block Diagram” on page 3 and “Pinout and Pin Functions” on page 49.

2. Added XMEGA A1 Block Diagram, Figure 3-1 on page 6.

3. Updated “Overview” on page 5 included the XMEGA A1 explanation text on page 6.

4. Updated AVR CPU “Features” on page 8.

5. Updated Event System block diagram, Figure 9-1 on page 18.

6. Updated “PMIC - Programmable Multi-level Interrupt Controller” on page 25.

7. Updated “AC - Analog Comparator” on page 44.

8. Updated “Alternate Pin Function Description” on page 49.

9. Updated “Alternate Pin Functions” on page 51.

10. Updated “Typical Characteristics” on page 76.

11. Updated “Ordering Information” on page 2.

12. Updated “Overview” on page 5.

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XMEGA A1

36.13 8067A – 02/08

13. Updated Figure 6-1 on page 8.

14. Inserted a new Figure 15-1 on page 32.

15. Updated Speed grades in “Speed” on page 69.

16. Added a new ATxmega384A1 device in “Features” on page 1, updated “Ordering Information” on

page 2 and “Memories” on page 10.

17. Replaced the Figure 3-1 on page 6 by a new XMEGA A1 detailed block diagram.

18. Inserted Errata “ATxmega128A1 rev. G” on page 100.

1. Initial revision.

8067M–AVR–09/10

XMEGA A1

Table of Contents

Features ..................................................................................................... 1

Typical Applications ................................................................................ 1

1 Ordering Information ............................................................................... 2

2 Pinout/Block Diagram .............................................................................. 3

3 Overview ................................................................................................... 5

3.1 Block Diagram ...................................................................................................6

4 Resources ................................................................................................. 7

4.1 Recommended reading .....................................................................................7

5 Disclaimer ................................................................................................. 7

6 AVR CPU ................................................................................................... 8

6.1 Features ............................................................................................................8

6.2 Overview ............................................................................................................8

6.3 Register File ......................................................................................................9

6.4 ALU - Arithmetic Logic Unit ...............................................................................9

6.5 Program Flow ....................................................................................................9

7 Memories ................................................................................................ 10

7.1 Features ..........................................................................................................10

7.2 Overview ..........................................................................................................10

7.3 In-System Programmable Flash Program Memory .........................................11

7.4 Data Memory ...................................................................................................11

7.5 Production Signature Row ...............................................................................14

7.6 User Signature Row ........................................................................................14

7.7 Flash and EEPROM Page Size .......................................................................15

8 DMAC - Direct Memory Access Controller .......................................... 16

8.1 Features ..........................................................................................................16

8.2 Overview ..........................................................................................................16

9 Event System ......................................................................................... 17

9.1 Features ..........................................................................................................17

9.2 Overview ..........................................................................................................17

10 System Clock and Clock options ......................................................... 19

10.1 Features ..........................................................................................................19

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XMEGA A1

10.2 Overview ..........................................................................................................19

10.3 Clock Options ..................................................................................................20

11 Power Management and Sleep Modes ................................................. 22

11.1 Features ..........................................................................................................22

11.2 Overview ..........................................................................................................22

11.3 Sleep Modes ....................................................................................................22

12 System Control and Reset .................................................................... 23

12.1 Features ..........................................................................................................23

12.2 Resetting the AVR ...........................................................................................23

12.3 Reset Sources .................................................................................................23

12.4 WDT - Watchdog Timer ...................................................................................24

13 PMIC - Programmable Multi-level Interrupt Controller ....................... 25

13.1 Features ..........................................................................................................25

13.2 Overview ..........................................................................................................25

13.3 Interrupt vectors ...............................................................................................25

14 I/O Ports .................................................................................................. 27

14.1 Features ..........................................................................................................27

14.2 Overview ..........................................................................................................27

14.3 I/O configuration ..............................................................................................27

14.4 Input sensing ...................................................................................................30

14.5 Port Interrupt ....................................................................................................30

14.6 Alternate Port Functions ..................................................................................30

15 T/C - 16-bit Timer/Counter ..................................................................... 31

15.1 Features ..........................................................................................................31

15.2 Overview ..........................................................................................................31

16 AWEX - Advanced Waveform Extension ............................................. 33

16.1 Features ..........................................................................................................33

16.2 Overview ..........................................................................................................33

17 Hi-Res - High Resolution Extension ..................................................... 34

17.1 Features ..........................................................................................................34

17.2 Overview ..........................................................................................................34

18 RTC - 16-bit Real-Time Counter ............................................................ 35

18.1 Features ..........................................................................................................35

iii

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XMEGA A1

18.2 Overview ..........................................................................................................35

19 TWI - Two-Wire Interface ....................................................................... 36

19.1 Features ..........................................................................................................36

19.2 Overview ..........................................................................................................36

20 SPI - Serial Peripheral Interface ............................................................ 37

20.1 Features ..........................................................................................................37

20.2 Overview ..........................................................................................................37

21 USART ..................................................................................................... 38

21.1 Features ..........................................................................................................38

21.2 Overview ..........................................................................................................38

22 IRCOM - IR Communication Module .................................................... 39

22.1 Features ..........................................................................................................39

22.2 Overview ..........................................................................................................39

23 Crypto Engine ........................................................................................ 40

23.1 Features ..........................................................................................................40

23.2 Overview ..........................................................................................................40

24 ADC - 12-bit Analog to Digital Converter ............................................. 41

24.1 Features ..........................................................................................................41

24.2 Overview ..........................................................................................................41

25 DAC - 12-bit Digital to Analog Converter ............................................. 43

25.1 Features ..........................................................................................................43

25.2 Overview ..........................................................................................................43

26 AC - Analog Comparator ....................................................................... 44

26.1 Features ..........................................................................................................44

26.2 Overview ..........................................................................................................44

26.3 Input Selection .................................................................................................46

26.4 Window Function .............................................................................................46

27 OCD - On-chip Debug ............................................................................ 47

27.1 Features ..........................................................................................................47

27.2 Overview ..........................................................................................................47

28 PDI - Program and Debug Interface ..................................................... 48

28.1 Features ..........................................................................................................48

28.2 Overview ..........................................................................................................48

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XMEGA A1

28.3 IEEE 1149.1 (JTAG) Boundary-scan ...............................................................48

29 Pinout and Pin Functions ...................................................................... 49

29.1 Alternate Pin Function Description ..................................................................49

29.2 Alternate Pin Functions ...................................................................................51

30 Peripheral Module Address Map .......................................................... 58

31 Instruction Set Summary ...................................................................... 60

32 Packaging information .......................................................................... 64

32.1 100A ................................................................................................................64

32.2 100C1 ..............................................................................................................65

32.3 100C2 ..............................................................................................................66

33 Electrical Characteristics ...................................................................... 67

33.1 Absolute Maximum Ratings* ...........................................................................67

33.2 DC Characteristics ...........................................................................................67

33.3 Speed ..............................................................................................................69

33.4 Flash and EEPROM Memory Characteristics .................................................70

33.5 ADC Characteristics ........................................................................................71

33.6 DAC Characteristics ........................................................................................72

33.7 Analog Comparator Characteristics .................................................................72

33.8 Bandgap Characteristics .................................................................................72

33.9 Brownout Detection Characteristics ................................................................73

33.10 PAD Characteristics ........................................................................................73

33.11 POR Characteristics ........................................................................................74

33.12 Reset Characteristics ......................................................................................74

33.13 Oscillator Characteristics .................................................................................74

34 Typical Characteristics .......................................................................... 76

34.1 Active Supply Current ......................................................................................76

34.2 Idle Supply Current ..........................................................................................77

34.3 Power-down Supply Current ............................................................................78

34.4 Power-save Supply Current .............................................................................78

34.5 Pin Pull-up .......................................................................................................79

34.6 Pin Thresholds and Hysteresis ........................................................................80

34.7 Bod Thresholds ...............................................................................................83

34.8 Bandgap ..........................................................................................................84

34.9 Analog Comparator .........................................................................................84

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XMEGA A1

34.10 Oscillators and Wake-up Time ........................................................................86

34.11 PDI Speed .......................................................................................................89

35 Errata ....................................................................................................... 90

35.1 ATxmega128A1 rev. H ....................................................................................90

35.2 ATxmega128A1 rev. G ..................................................................................100

36 Datasheet Revision History ................................................................ 104

36.1 8067M – 09/10 ...............................................................................................104

36.2 8067L – 08/10 ................................................................................................104

36.3 8067K – 02/10 ...............................................................................................104

36.4 8067J – 02/10 ................................................................................................104

36.5 8067I – 04/09 .................................................................................................105

36.6 8067H – 04/09 ...............................................................................................105

36.7 8067G – 11/08 ...............................................................................................105

36.8 8067F – 09/08 ...............................................................................................105

36.9 8067E – 08/08 ...............................................................................................106

36.10 8067D – 07/08 ...............................................................................................106

36.11 8067C – 06/08 ...............................................................................................106

36.12 8067B – 05/08 ...............................................................................................106

36.13 8067A – 02/08 ...............................................................................................107

Table of Contents....................................................................................... i

8067M–AVR–09/10

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