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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DSeparate Low Noise Preamp and PGA
Stages
DShutdown Control
DPreamp Features
− Low Voltage Noise . . . 1.7 nV/√Hz
− Accessible Output Pin for External
Filtering
− Voltage Feedback, Gmin = −1, 2
− 100 MHz Bandwidth (−3 dB)
DPGA Features
− Digitally Programmable Gain
− −22 dB to 20 dB Gain/Attenuation Range
− 6 dB Step Resolution
− Output Clamp Protection
− 70 MHz Bandwidth (−3 dB)
− 175 V/µs Slew Rate
DWide Supply Range ±4.5 V to ±16 V
DPowerPAD Package for Enhanced
Thermal Performance
description
The THS7001 (single) and THS7002 (dual) are high-speed programmable-gain amplifiers, ideal for applications
where load impedance can often vary. Each channel on this device consists of a separate low-noise input
preamp and a programmable gain amplifier (PGA). The preamp is a voltage-feedback amplifier offering a low
1.7-nV/√Hz voltage noise with a 100-MHz (−3 dB) bandwidth. The output pin of the preamp is accessible so that
filters can be easily added to the amplifier.
The 3-bit digitally-controlled PGA provides a −22-dB to 20-dB attenuation/gain range with a 6-dB step
resolution. In addition, the PGA provides both high and low output clamp protection to prevent the output signal
from swinging outside the common-mode input range of an analog-to-digital converter. The PGA provides a
wide 70-MHz (−3 dB) bandwidth, which remains relatively constant over the entire gain/attenuation range.
Independent shutdown control is also provided for power conservation and multiplexing. These devices operate
over a wide ±4.5-V to ±16-V supply voltage range.
_
+
PREAMP VCC+
PREAMP IN+
PREAMP IN−
PREAMP VCC−
Preamp
PREAMP
OUT PGA IN− G2
G1
G0
PGA REFSHDN PGA
VCC+ GNDPGA
VCC−
CLAMP+ (VH)
CLAMP− (VL)
PGA OUT
_
+
Figure 1. THS7001 Block Diagram
Copyright 1999, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CAUTION: The THS7001 and THS7002 provides ESD protection circuitry. However, permanent damage can still occur if this
device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance
degradation or loss of functionality.
PowerPAD is a trademark of Texas Instruments Incorporated.
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND-A
PGA-A REF
PGA-A IN−
PREAMP OUT A
PREAMP-A IN−
PREAMP-A IN+
PREAMP VCC−
PREAMP VCC+
PREAMP-B IN+
PREAMP-B IN−
PREAMP OUT B
PGA-B IN−
PGA-B REF
GND-B
G0-A
G1-A
G2-A
SHDN−A
PGA-A OUT
CLAMP− (VL)
PGA VCC−
PGA VCC+
CLAMP+ (VH)
PGA-B OUT
SHDN−B
G2-B
G1-B
G0-B
THS7002
PWP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
VREFPGA
−VINPGA
VOUTPre-AMP
−VINPre-Amp
+VINPre-Amp
VCC−Pre-Amp
VCC+Pre-Amp
Spare/NC
Spare/NC
G0
G1
G2
SHDN
VOUTPGA
VLNegative Clamp
VCC−PGA
VCC+PGA
VHPositive Clamp
Spare/NC
THS7001
PWP PACKAGE
(TOP VIEW)
AVAILABLE OPTIONS
NUMBER OF
PACKAGED DEVICES
EVALUATION
TA
NUMBER OF
CHANNELS PowerPAD PLASTIC TSSOP
(PWP)
EVALUATION
MODULE
0°C to 70°C
1 THS7001CPWP THS7001EVM
0°C to 70°C2 THS7002CPWP THS7002EVM
−40°C to 85°C
1 THS7001IPWP —
−40°C to 85°C2 THS7002IPWP —
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
block diagram
_
+
PREAMP VCC+
PREAMP A IN+
PREAMP A IN−
SHDN−A
Preamp
PREAMP
OUT A PGA−A
IN− G2AG1AG0APGA−A REF
PGA
VCC+ PGA−B
GND
PGA
VCC−
CLAMP+ (VH)
CLAMP− (VL)
PGA−A OUT
_
+
_
PREAMP VCC−
PREAMP B IN−
PREAMP B IN+
SHDN−B
Preamp
PREAMP
OUT B PGA−B REF
PGA−B OUT
+
G2BG1BG0B
PGA−A
GND
_
+
PGA−B
IN−
Figure 2. THS7002 Dual Channel PGA
input preamp
To achieve the minimum input equivalent noise required for very small input signals, the input preamp is
configured as a classic voltage feedback amplifier with a minimum gain of 2 or −1. The output of the preamp
is accessible, allowing for adjustment of gain using external resistors and for external filtering between the
preamp and the PGA.
programmable gain amplifier (PGA)
The PGA is an inverting, programmable gain amplifier. The gain is digitally programmable using three control
bits (TTL-compatible terminals) that are encoded to provide eight distinct levels of gain/attenuation. Nominal
gain/attenuation is shown in Table 1.
Table 1. Nominal Gain/Attenuation
G2G1G0PGA GAIN
(dB) PGA GAIN
(V/V)
0 0 0 −22 0.08
0 0 1 −16 0.16
0 1 0 −10 0.32
0 1 1 −4 0.63
1 0 0 2 1.26
1 0 1 8 2.52
1 1 0 14 5.01
1 1 1 20 10.0
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4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
output clamping
Output clamping for both upper (VH) and lower (VL) levels for the PGAs is provided. There is only one terminal
for the positive output clamp and one for the negative output clamp for both channels.
shutdown control
The SHDN terminals allow for powering down the internal circuitry for power conservation or for multiplexing.
Separate shutdown controls are available for each channel. The control levels are TTL compatible.
absolute maximum ratings over operating free-air temperature (see Notes 1 and 2)†
Supply voltage, VCC ±16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI ±VCC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO (preamp) (see Note 1) 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IO (PGA) (see Note 1) 85 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID ±4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total continuous power dissipation at (or below) TA = 25°C (see Note 2): THS7001 3.83 W. . . . . . . . . . . . . .
THS7002 4.48 W. . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, TA:C-suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I-suffix −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg −65°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The THS7001 and THS7002 incorporates a PowerPAD on the underside of the chip. The PowerPAD acts as a heatsink and must
be connected to a thermal dissipation plane for proper power dissipation. Failure to do so can result in exceeding the maximum
junction temperature, which could permanently damage the device. See the Thermal Information section of this document for more
information about PowerPAD technology.
2. For operation above TA = 25°C, derate the THS7001 linearly to 2 W at the rate of 30.6 mW/°C and derate the THS7002 linearly t o
2.33 W at the rate of 35.9 mW/°C.
recommended operating conditions
MIN NOM MAX UNIT
Preamp supply voltage, VCC+ and VCC− Split supply ±4.5 ±16 V
PGA supply voltage, VCC+ and VCC− Split supply ±4.5‡±16 V
Operating free-air temperature, TA
C-suffix 0 70 °C
Operating free-air temperature, T
AI-suffix −40 85 °C
‡PGA minimum supply voltage must be less than or equal to preamp supply voltage.
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preamp electrical characteristics, G = 2, TA = 25°C, RL = 150 Ω, (unless otherwise noted)
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
VCC Supply voltage operating range Split supply ±4.5 ±16.5 V
RL = 1 kΩ
VCC = ±5 V ±3.6 ±3.8
VOM
Maximum output voltage swing
RL = 1 kΩVCC = ±15 V ±13 ±13.6
V
VOM Maximum output voltage swing RL = 150 ΩVCC = ±5 V ±3.5 ±3.7 V
RL = 250 ΩVCC = ±15 V ±11 ±12.6
VIO
Input offset voltage
VCC = ±5 V or ±15 V
TA = 25°C 1 5
mV
VIO Input offset voltage VCC = ±5 V or ±15 V TA = full range 7mV
Input offset voltage drift 10 µV/°C
VICR
Common-mode input voltage range
VCC = ±5 V ±3.8 ±4.2
V
VICR Common-mode input voltage range VCC = ±15 V ±13.8 ±14 V
IO
Output current (see Note 3)
RL = 20 Ω
VCC = ±5 V 40 70
mA
IOOutput current (see Note 3) RL = 20 ΩVCC = ±15 V 60 95 mA
IOC Short-circuit output current (see Note 3) VCC = ±15 V 120 mA
IIB
Input bias current
VCC = ±5 V or ±15 V
TA = 25°C 2.5 6
A
IIB Input bias current VCC = ±5 V or ±15 V TA = full range 8µA
IIO
Input offset current
VCC = ±5 V or ±15 V
TA = 25°C 30 175
nA
IIO Input offset current VCC = ±5 V or ±15 V TA = full range 400 nA
Input offset current drift 0.3 nA/°C
VCC =
±
5 V,
TA = 25°C 80 89
CMRR
Common-mode rejection ratio
VCC = ±5 V,
VIC = ±2.5 V TA = full range 78
dB
CMRR Common-mode rejection ratio
VCC =
±
15 V,
TA = 25°C 80 88 dB
VCC = ±15 V,
VIC = ±12 V TA = full range 78
PSRR
Power supply rejection ratio
VCC = ±5 V or ±15 V
TA = 25°C 85 100
dB
PSRR Power supply rejection ratio VCC = ±5 V or ±15 V TA = full range 80 dB
RIInput resistance 1 MΩ
CIInput capacitance 1.5 pF
ROOutput resistance Open loop 13 Ω
VCC = ±5 V
TA = 25°C 5.5 7
ICC
Quiescent current (per channel)
VCC = ±5 V TA = full range 8
mA
ICC Quiescent current (per channel)
VCC = ±15 V
TA = 25°C 7 8 mA
VCC = ±15 V TA = full range 9
†Full range for the THS7001/02C is 0°C to 70°C. Full range for the THS7001/022I is −40°C to 85°C.
NOTE 3: A heatsink may be required to keep the junction temperature below absolute maximum when an output is heavily loaded or shorted.
(See absolute maximum ratings and thermal information section.)
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6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
preamp operating characteristics, G = 2, TA = 25°C, RL = 150 Ω, (unless otherwise noted)
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
SR
Slew rate (see Note 4)
G = −1
VO = ±2 V,
VCC = ±5 V 65
V/ s
SR Slew rate (see Note 4) G = −1 VO = ±10 V,
VCC = ±15 V 85 V/µs
Settling time to 0.1%
VCC = ±5 V 85
ts
Settling time to 0.1%
G = −1,
VCC = ±15 V 70
ns
ts
Settling time to 0.01%
G = −1,
5 V Step VCC = ±5 V 95 ns
Settling time to 0.01%
5 V Step
VCC = ±15 V 90
THD Total harmonic distortion VCC = ±15 V,
VO(PP) = 2V fc = 1 MHz,
RL = 250 Ω−88 dBc
VnInput noise voltage VCC = ±5 V or ±15 V, f = 10 kHz 1.7 nV/√Hz
InInput noise current VCC = ±5 V or ±15 V, f = 10 kHz 0.9 pA/√Hz
BW
Small-signal bandwidth (−3 dB)
VO(PP) = 0.4V,
VCC = ±5 V 85
MHz
BW Small-signal bandwidth (−3 dB)
VO(PP) = 0.4V,
G = 2 VCC = ±15 V 100 MHz
Bandwidth for 0.1 dB flatness
VO(PP) = 0.4V,
VCC = ±5 V 35
MHz
Bandwidth for 0.1 dB flatness
VO(PP) = 0.4V,
G = 2 VCC = ±15 V 45 MHz
Full power bandwidth (see Note 5)
VCC = ±5 V,VO = 5 VO(PP) 4.1
MHz
Full power bandwidth (see Note 5) VCC = ±15 V,VO = 20 VO(PP) 1.4 MHz
AD
Differential gain error
G = 2, 100 IRE,
VCC = ±5 V 0.02%
ADDifferential gain error
G = 2, 100 IRE,
NTSC VCC = ±15 V 0.02%
φD
Differential phase error
G = 2, 100 IRE,
VCC = ±5 V 0.01°
φDDifferential phase error
G = 2, 100 IRE,
NTSC VCC = ±15 V 0.01°
VCC = ±5 V,
VO = ±2.5 V,
TA = 25°C 85 89
Open loop gain
CC
V
O
=
±
2.5 V,
RL = 1 kΩTA = full range 83
dB
Open loop gain
VCC =
±
15 V,
TA = 25°C 86 91
dB
VCC = ±15 V,
VO = ±10 V, RL = 1 kΩTA = full range 84
Channel-to-channel crosstalk (THS7002) VCC = ±5 V or ±15 V, f = 1 MHz −85 dB
†Full range for the THS7001/02C is 0°C to 70°C. Full range for the THS7001/02I is −40°C to 85°C.
NOTES: 4. Slew rate is measured from an output level range of 25% to 75%.
5. Full power bandwidth = slew rate/2π V(PP).
shutdown electrical characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Standby current, disabled
Preamp
VCC = ±5 V 0.2 0.3
I
CC(standby)
Standby current, disabled
(per channel)
Preamp V
I(SHDN)
= 2.5 V VCC = ±15 V 0.65 0.8 mA
ICC(standby)
(per channel)
PGA
VI(SHDN) = 2.5 V
VCC = ±5 V or ±15 V 0.8 1.2
mA
VIH(SHDN) Shutdown voltage for power up
VCC = ±5 V or ±15 V,
Relative to GND
0.8 V
VIL(SHDN) Shutdown voltage for power down VCC = ±5 V or ±15 V, Relative to GND 2V
IIH(SHDN) Shutdown input current high
VCC = ±5 V or ±15 V,
VI(SHDN) = 5 V 300 400 µA
IIL(SHDN) Shutdown input current low
V
CC
=
±
5 V or
±
15 V,
VI(SHDN) = 0.5 V 25 50 µA
tdis Disable time†VCC = ±5 V or ±15 V, Preamp and PGA 100 ns
ten Enable time†VCC = ±5 V or ±15 V, Preamp and PGA 1.5 µs
†Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current
has reached half its final value.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PGA electrical characteristics, TA = 25°C, Gain = 2 dB, RL = 1 kΩ, (unless otherwise noted)
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
VCC Supply voltage range Split supply ±4.5‡±16.5 V
VOM
Maximum output voltage swing
RL = 1 kΩ
VCC = ±5 V ±3.6 ±4.1
V
VOM Maximum output voltage swing RL = 1 kΩVCC = ±15 V ±13.2 ±13.8 V
VIO
Input offset voltage
VCC = ±5 V or ±15 V
TA = 25°C 2 9
mV
VIO Input offset voltage VCC = ±5 V or ±15 V TA = full range 11 mV
Input offset voltage drift 10 µV/°C
Reference input voltage range
VCC = ±5 V ±3.8 ±4.0
V
Reference input voltage range VCC = ±15 V ±13.5 ±13.8 V
IIB
Input bias current (reference terminal)
VCC = ±5 V or ±15 V
TA = 25°C 1 2
A
IIB Input bias current (reference terminal) VCC = ±5 V or ±15 V TA = full range 3µA
IOOutput current RL = 20 ΩVCC = ±5 V 30 50 mA
IOS Short-circuit output current 80 mA
PSRR
Power supply rejection ratio
VCC = ±5 V or ±15 V
TA = 25°C 75 82
dB
PSRR
Power supply rejection ratio
V
CC
=
±
5 V or
±
15 V
TA = full range 72
dB
RI
Input resistance
Gain = 20 dB 0.27
kΩ
RIInput resistance Gain = −22 dB 3kΩ
ROOutput resistance Open loop 20 Ω
VCC = ±5 V
TA = 25°C 4.8 6
ICC
Quiescent supply current (per channel)
VCC = ±5 V TA = full range 7
mA
ICC Quiescent supply current (per channel)
VCC = ±15 V
TA = 25°C 5 7 mA
VCC = ±15 V TA = full range 8
†Full range for the THS7001/02C is 0°C to 70°C. Full range for the THS7001/02I is −40°C to 85°C.
‡PGA minimum supply voltage must be less than or equal to preamp supply voltage.
output limiting characteristics
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
VCC = ±15 V,
VI = ±10 V,
VH = 10 V,
VL = −10 V,
TA = 25°C±250 ±300
Clamp accuracy
CC
V
I
=
±
10 V,
Gain = 2 dB
H
V
L
= −10 V,
TA = full range ±350
mV
Clamp accuracy VCC = ±5 V,
VI = ±2.5 V,
VH = 2 V,
VL = −2 V,
TA = 25°C±50 ±80 mV
CC
V
I
=
±
2.5 V,
Gain = 2 dB
H
V
L
= −2 V,
TA = full range ±100
Clamp overshoot
VCC = ±15 V,
VI = ±10 V, VH = 10 V,
tr and tf = 1 ns VL = −10 V, 0.5%
Clamp overshoot VCC = ±5 V,
VI = ±2.5 V, VH = 2 V,
tr and tf = 1 ns VL = −2 V, 0.3%
Overdrive recovery time
VCC = ±15 V,
VI = ±10 V VH = 10 V, VL = −10 V, 7
ns
Overdrive recovery time VCC = ±5 V,
VI = ±2.5 V VH = 2 V, VL = 2 V, 6ns
Clamp input bias current
VO = 3.3 V,
VL = 3.3 V,
TA = 25°C 1 5
A
Clamp input bias current
VO = 3.3 V,
VH = 3.3 V
VL = 3.3 V,
TA = full range 8µA
†Full range for the THS7002C is 0°C to 70°C. Full range for the THS7002I is −40°C to 85°C.
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PGA electrical characteristics, TA = 25°C, Gain = 2 dB, RL = 1 kΩ, (unless otherwise noted)
(continued)
digital gain characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage
Relative to GND
2 V
VIL Low-level input voltage Relative to GND 0.8 V
IIH High-level input current VIH = 5 V 20 100 nA
IIL Low-level input current (sink current) VIL = 0.5 V 0.9 2 µA
tdGain-change delay time†VCC = ±5 V or ±15 V 2µs
†Gain-change delay time is the time needed to reach 90% of its final gain value.
PGA operating characteristics, TA = 25°C, Gain = 2 dB, RL = 1 kΩ, (unless otherwise noted)
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
SR
Slew rate (see Note 4)
VCC = ±5 V, VO = ±2.5 V 160
V/ s
SR Slew rate (see Note 4) VCC = ±15 V, VO = ±10 V 175 V/µs
ts
Settling time to 0.1%
5 V Step
VCC = ±15 V 125
ns
tsSettling time to 0.1% 5 V Step VCC = ±5 V 120 ns
THD Total harmonic distortion VCC = ±15 V,
fc = 1 MHz, VO(PP)= 2 V,
Gain = 8 dB −69 dBc
Gain = 20 dB,
VCC = ±15 V 65
Gain = 20 dB,
VO(PP) = 0.4 V VCC = ±5 V 60
BW
Small-signal bandwidth (−3 dB)
Gain = 2 dB,
VCC = ±15 V 75
MHz
BW Small-signal bandwidth (−3 dB)
Gain = 2 dB,
VO(PP) = 0.4 V VCC = ±5 V 70 MHz
Gain = −22 dB,
VCC = ±15 V 80
Gain = −22 dB,
VO(PP) = 0.4 V VCC = ±5 V 70
Bandwidth for 0.1 dB flatness
Gain = 2 dB,
VCC = ±15 V 20
MHz
Bandwidth for 0.1 dB flatness
Gain = 2 dB,
VO(PP) = 0.4 V VCC = ±5 V 18 MHz
Full power bandwidth (see Note 5)
VO(PP) = 5 V, VCC = ±5 V 10
MHz
Full power bandwidth (see Note 5) VO(PP) = 20 V, VCC = ±15 V 2.8 MHz
AD
Differential gain error
G = 8 dB, 100 IRE,
VCC = ±5 V 0.04%
ADDifferential gain error
G = 8 dB, 100 IRE,
NTSC, RL = 150 ΩVCC = ±15 V 0.04%
φD
Differential phase error
G = 8 dB,
±
100 IRE,
VCC = ±15 V 0.07
°
φDDifferential phase error
G = 8 dB, ±100 IRE,
NTSC, RL = 150 ΩVCC = ±5 V 0.09 °
Gain accuracy (see Note 6)
Gain = −22 dB to 20 dB,
All 8 steps,
TA = 25°C −7.5% 0% 7.5%
Gain accuracy (see Note 6)
All 8 steps,
VCC = ±5 V or ±15 V TA = full range −8.5% 8.5%
Channel-to-channel gain accuracy
Gain = −22 dB to 20 dB,
All 8 steps,
TA = 25°C −5.5% 0% 5.5%
Channel-to-channel gain accuracy
(THS7002 only) (see Note 7)
All 8 steps,
VCC = ±5 V or ±15 V TA = full range −6.5% 6.5%
Vn
Input referred noise voltage
VCC =
±
5 V or
±
15 V,
Gain = 20 dB 10
nV/√Hz
VnInput referred noise voltage
VCC = ±5 V or ±15 V,
f = 10 kHz Gain = −22 dB 500
nV/√Hz
PGA channel-to-channel crosstalk
(THS7002 only) VCC = ±5 V or ±15 V, f = 1 MHz −77 dB
†Full range for the THS7001/02C is 0°C to 70°C. Full range for the THS7001/02I is −40°C to 85°C.
NOTES: 4. Slew rate is measured from an output level range of 25% to 75%.
5. Full power bandwidth = slew rate/2π VPEAK
6. Specified as −100 × (output voltage − (input voltage × gain))/(input voltage × gain)
7. Specified as 100 × (output voltage B− output voltage A)/output voltage A
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 3
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
3
2.5
2
1.5
1
0.5
−40 −20 0 20 40 60
TA − Free-AIR Temperature − _C
V
0
IO − Input Offset Voltage − mV
80 100
3.5
Preamp
VCC = ±15 V
PGA
VCC = ±5 V
Preamp
VCC = ±5 V
VCC = ±15 V
PGA
Figure 4
STANDBY SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
Standby Supply Current − mA
2
1.5
1
0.5
0
−0.5
−40 −20 0 20 40 60 80 100
Preamp − ICC
Preamp − IEE
PGA − IEE
PGA − ICC
TA − Free-Air Temperature − _C
VCC = ±15 V
Figure 5
QUIESCENT SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
9
8
7
6
5
−40 −20 0 20 40 60
TA − Free-Air Temperature − _C
4
Supply Current −
3
Preamp
mAI
CC
−
80 100
VCC = ±15 V
Preamp
VCC = ±5 V
PGA
VCC = ±5 V
Per Channel
PGA
VCC = ±15 V
Figure 6
PSRR
vs
FREQUENCY
120
100
80
60
40
20
10 100 1k 10k 100k 1M
0
PSRR − Power-Supply Rejection Ratio − dB
f − Frequency − Hz
VCC = ±15 V & ±5 V
10M
PGA - VCC +
PGA - VCC −
Preamp - VCC + & VCC −
100M
Figure 7
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
Iib − Input Bias Current − uA
3
2.5
2
1.5
1
0
−40 −20 0 20 40 60 80 100
PGA: VCC = ±15 V and ±5 V
TA − Free-Air Temperature − _C
Pre−Amp: V CC = ±15 V
Pre−Amp: VCC = ±5 V
0.5
Figure 8
100
10
1
100k 10M 100M
0.1
f − Frequency − Hz
1M
− Output Impedance −Z
oΩ
500M
0.01
VCC = ±15 V & ±5 V
V|(PP)= 2 V
PGA: G = −22 dB
PGA: G = +20 dB
Preamp: G = +2
CLOSED-LOOP OUTPUT
IMPEDANCE vs
FREQUENCY
Figure 9
PREAMP INPUT COMMON-MODE
VOLTAGE RANGE
vs
SUPPLY VOLTAGE
15
13
11
9
7
579111315
±VCC − Supply Voltage − V
−
5
Input Common-Mode Range −
3
TA = 25 _C
V
+
VICR −
Figure 10
PREAMP OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
14
12
10
8
6
4
57 9111315
|V V
2
− Output Voltage Swing −
±VCC − Supply Voltage − V
O
|
RL = 250 Ω
TA = 25° C
RL = 1 kΩ
Figure 11
PREAMP CMRR
vs
FREQUENCY
CMRR − Common-Mode Rejection Ratio − dB
f − Frequency − Hz
100
80
60
40
20
0100 1k 10k 100k 1M 10M 100M
VCC = ±15 V and ±5 V
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 12
PREAMP OPEN LOOP GAIN AND
PHASE RESPONSE
vs
FREQUENCY
Open Loop Gain − dB
100
80
60
40
20
0
100 1k 10k 100k 1M 10M 100M 1G
VCC = ±15 V and ±5 V
RL = 250 Ω
f − Frequency − Hz
Gain
Phase
0
−20
45_
0_
−45_
−90_
−135_
−180_
−225_
Phase
Figure 13
PREAMP INPUT REFERRED VOLTAGE NOISE
AND CURRENT NOISE
vs
FREQUENCY
20
10
10 100 1k
f − Frequency − Hz
1
10k
0.1 100k
nV/ Hz
− Voltage Noise −Vn
In− Current Noise − pA/ Hz
VCC = ±15 V and ±5 V
TA = 25 _C
IN
VN
Figure 14
Output Amplitude − dB
f − Frequency − Hz
100k 1M 10M 100M
8
7
6
5
4
3
2
1
0
−1 500M
PREAMP OUTPUT AMPLITUDE
vs
FREQUENCY
VCC = ±5 V
G = 2
RL = 150 Ω
VO(PP) = 0.4 V
RF = 100 Ω
RF = 499 Ω
RF = 1 kΩ
Figure 15
Output Amplitude − dB
f − Frequency − Hz
100k 1M 10M 100M
VCC = ±15 V
G = 2
RL = 150 Ω
VO(PP) = 0.4 V
RF = 100 Ω
RF = 499 Ω
RF = 1 kΩ
8
7
6
5
4
3
2
1
0
−1 500M
PREAMP OUTPUT AMPLITUDE
vs
FREQUENCY
Figure 16
Output Amplitude − dB
f − Frequency − Hz
100k 1M 10M 100M
2
1
0
−1
−2
−3
−4
−5
−6
−7 500M
PREAMP OUTPUT AMPLITUDE
vs
FREQUENCY
VCC = ±5 V
G = −1
RL = 150 Ω
VO(PP) = 0.4 V
RF = 1 kΩ
RF = 499 Ω
RF = 100 Ω
Figure 17
Output Amplitude − dB
f − Frequency − Hz
100k 1M 10M 100M
2
1
0
−1
−2
−3
−4
−5
−6
−7 500M
PREAMP OUTPUT AMPLITUDE
vs
FREQUENCY
VCC = ±15 V
G = −1
RL = 150 Ω
VO(PP) = 0.4 V
RF = 1 kΩ
RF = 499 Ω
RF = 100 Ω
Figure 18
Output Amplitude − dB
f − Frequency − Hz
100k 1M 10M 100M
16
14
12
10
8
6
4
2
0
−1 500M
PREAMP OUTPUT AMPLITUDE
vs
FREQUENCY
VCC = ±5 V
G = 5
RL = 150 Ω
VO(PP) = 0.4 V
RF = 499 Ω
RF = 5.1 kΩ
Figure 19
Output Amplitude − dB
f − Frequency − Hz
100k 1M 10M 100M
16
14
12
10
8
6
4
2
0
−1 500M
PREAMP OUTPUT AMPLITUDE
vs
FREQUENCY
VCC = ±15 V
G = 5
RL = 150 Ω
VO(PP) = 0.4 V
RF = 499 Ω
RF = 5.1 kΩ
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 20
PREAMP LARGE AND SMALL
SIGNAL FREQUENCY
RESPONSE
100k
V − Normalized Output Voltage − dBV
f − Frequency − Hz
0
12
6
0
−12
−6
−18 1M 10M 100M 500M
VO(PP) = 1.6 V
VO(PP) = 0.8 V
VO(PP) = 0.2 V
VO(PP) = 0.4 V
VCC = ± 5 V
RL = 150 Ω
G = +2
Figure 21
PREAMP LARGE AND SMALL
SIGNAL FREQUENCY
RESPONSE
100k
V − Normalized Output Voltage − dBV
f − Frequency − Hz
0
12
6
0
−12
−6
−18 1M 10M 100M 500M
VO(PP) = 1.6 V
VO(PP) = 0.8 V
VO(PP) = 0.2 V
VO(PP) = 0.4 V
VCC = ± 15 V
RL = 150 Ω
G = +2
Figure 22
−100
−90
−80
−70
−60
−50
−40
−30
PREAMP HARMONIC
DISTORTION
vs
FREQUENCY
f − Frequency − Hz
100k 1M 10M
Distortion − dBc
RL= 250 Ω
Gain=+8 dB
VO(PP)= 2 V
VCC=+/−5 V
3rd Harmonic
VCC=+/−15 V
3rd Harmonic
VCC=+/−5 V
2nd Harmonic
VCC=+/−15 V
2nd Harmonic
Figure 23
−100
−90
−80
−70
−60
−50
−40
−30
0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0
PREAMP HARMONIC
DISTORTION
vs
OUTPUT VOLTAGE
VO(PP) − Peak-To-Peak Output Voltage − V
Distortion − dBc
Gain=5
RF=300 Ω
RL=1 kΩ
f=1 MHz
VCC=+/−15 V
2nd Harmonic
VCC=+/−5 V
2nd Harmonic
VCC=+/−5 V
3rd Harmonic
VCC=+/−15 V
3rd Harmonic
Figure 24
PREAMP SLEW RATE
vs
FREE-AIR TEMPERATURE
90
80
70
60
50
40
−40 −20 0 20 40 60
30
SR − Slew Rate − V/uS
TA − Free-Air Temperature − °C
VCC = ±5 V
VO (PP) = 5 V
80 100
VCC = ±15 V
VO (PP) = 20 V
100
RL= 200 Ω
Figure 25
PREAMP 400-mV
STEP RESPONSE
0.3
0.2
0.1
0
−0.1
−0.2
0 50 100 150 200 250
VV
−0.3
− Output Voltage −
t − Time − ns
O
G = +2
VCC = ±5 V
RL = 200 Ω
300
Figure 26
PREAMP 5-V
STEP RESPONSE
3
2
1
0
−1
−2
0 50 100 150 200 250
VV
−3
− Output Voltage −
t − Time − ns
O
G = −1
VCC = ±5 V
RL = 200 Ω
300
Figure 27
PREAMP 5-V
STEP RESPONSE
3
2
1
0
−1
−2
0 50 100 150 200 250
VV
−3
− Output Voltage −
t − Time − ns
O
G= +2
VCC = ±5 V
RL = 200 Ω
300
Figure 28
PREAMP 20-V
STEP RESPONSE
7.5
5
2.5
0
−2.5
−5
0 200 400 600 800 1000
VV
−7.5
− Output Voltage −
t − Time − ns
O
G = +5
VCC = ±15 V
RL = 200 Ω
−10
−12.5
10
12.5
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 29
THS7002 PREAMP
CHANNEL-TO-CHANNEL
CROSSTALK
−40
−60
100k 10M 100M
−90
Crosstalk − dB
f − Frequency − Hz
VCC = ±15 V & ±5 V
G = 2
VO(PP) = 1.3 V
RL = 1 kΩ
RF = 499 Ω
1M
Preamp−1 Input
Preamp−2 Output
−80
−50
−70
Preamp−2 Input
Preamp−1 Output
Figure 30
PREAMP-TO-PGA CROSSTALK
vs
FREQUENCY
−40
100k
f − Frequency − Hz
Preamp − Input
PGA − Output
Crosstalk − dB
−50
−60
−70
−80
−90 1M 10M 100M
VCC = ±15 V & ±5 V
RL = 1 kΩ
Preamp:
G = 2
RF = 499 Ω
PGA:
G = +2 dB
PGA − Input
Preamp − Output
Figure 31
nV/ HzInput Referred Voltage Noise −
PGA INPUT REFERRED VOLTAGE
NOISE
vs
FREQUENCY
10k
1k
100
10
10 100 1k 10k 100k
f − Frequency − Hz
1
G = − 22 dB G = − 10 dBG = − 16 dB G = − 4 dB
G = + 2 dB
G = + 8 dB G = +14 dB
G = +20 dB
Figure 32
PGA CHANNEL-TO-CHANNEL
GAIN ACCURACY
vs
GAIN SETTING
Channel-To-Channel Gain Accuracy − %
Gain Setting − dB
0.4
0.3
0.2
0.1
0
−0.1
−25 −20 −15 −10 −5 0 5
−0.2
−0.3
−0.4 10 15 20
VCC = 25_ C
VCC = ±5 V
VCC = ±15 V
Figure 33
−0.4
−0.3
−0.2
−0.1
−0.0
0.1
0.2
0.3
0.4
−40 −20 0 20 40 60 80 100
NORMALIZED PGA GAIN
ACCURACY
vs
TEMPERATURE
TA − Free-AiirTemperature − °C
Gain Accuracy − %
VCC=±5 V ±15 V
Typical For All Gains
Figure 34
PGA FREQUENCY RESPONSE
26
2
100k 10M 100M
−28
Output Level − dB
f − Frequency − Hz
1M
G = 1,1,1
−22
20
−4
VCC = ±15 V
RL = 1 kΩ
VO(PP) =
0.4 V
−16
−10
8
14
1G
G = 1,1,0
G = 1,0,1
G = 1,0,0
G = 0,1,1
G = 0,1,0
G = 0,0,1
G = 0,0,0
Figure 35
PGA FREQUENCY RESPONSE
26
2
100k 10M 100M
−28
Output Level − dB
f − Frequency − Hz
1M
G = 1,1,1
−22
20
−4
VCC = ± 5 V
RL = 1 kΩ
VO(PP) =
0.4 V
−16
−10
8
14
1G
G = 1,1,0
G = 1,0,1
G = 1,0,0
G = 0,1,1
G = 0,1,0
G = 0,0,1
G = 0,0,0
Figure 36
PGA LARGE AND SMALL
SIGNAL FREQUENCY
RESPONSE
100k 10M 100M
V − Normalized Output Voltage − dBV
f − Frequency − Hz
1M 1G
0
12 VO(PP) = 3.2 V
6VO(PP) = 1.6 V
0VO(PP) = 0.8 V
−12 VO(PP) = 0.2 V
−6 VO(PP) = 0.4 V
VCC = ± 5 V
RL = 1 kΩ
G = +2 dB
−18
18
Figure 37
PGA LARGE AND SMALL
SIGNAL FREQUENCY
RESPONSE
100k 10M 100M
V − Normalized Output Voltage − dBV
f − Frequency − Hz
1M
0
12 VO(PP) = 3.2 V
6VO(PP) = 1.6 V
0VO(PP) = 0.8 V
−12 VO(PP) = 0.2 V
−6 VO(PP) = 0.4 V
VCC = ± 15 V
RL = 1 kΩ
G = +2 dB
−18
18
1G
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 38
−100
−90
−80
−70
−60
−50
−40
−30
PGA HARMONIC
DISTORTION
vs
FREQUENCY
f − Frequency − Hz
100k 1M 10M
Distortion − dBc
RL= 1 kΩ
Gain=+8 dB
VO(PP)= 2 V
VCC=±15 V
3rd Harmonic
VCC=±5 V
2nd Harmonic
VCC=±5 V
3rd Harmonic
VCC=±15 V
2nd Harmonic
Figure 39
PGA HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−40
−50
−60
−70
−80
−90
0 2.5 5 7.5 10 12.5 15 17.5
VO(PP) − Peak -To-Peak Output Volage − V
Distortion − dBc
RL = 1 kΩ
G= +8 dB
f = 1 MHz
−100 20
VCC ±5 V
3rd Harmonic
VCC ±5 V
2nd Harmonic
VCC ±15 V
2nd Harmonic
VCC ±15V
3rd Harmonic
Figure 40
100
120
140
160
180
200
220
−40 −20 0 20 40 60 80 100
PGA SLEW RATE
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
RL=1 k Ω
VCC=+/−5 V
VO(P-P)=5 V
SR − Slew Rate − V/ Sµ
VCC=+/−15 V
VO(P-P)=20 V
Figure 41
PGA CLAMP ACCURACY
vs
FREE-AIR TEMPERATURE
300
200
100
0
−100
−300
−40 −20 0 20 40 60 80 100
TA − Free-Air Temperature − _C
VH − 15V
15-V Condition:
VH, VL = ±10 V
VI = ±10 V
Clamp Accuracy − mV
VH − 5V
VL − 15V
VL − 5V
5-V Condition:
VH, VL = ±2 V
VI = ±2 V
G = +2 dB
−200
Figure 42
t − Time − ns
0
−1
−3
0 100 200 300
− Output Voltage − V
1
2
PGA CLAMP RESPONSE
4
400 500
3
−2
−4
Clamped
Output
VH = 2 V
VL = −2 V
Unclamped
Output
V
O
VCC = ±5 V
Gain = 1,0,0 (+ 2 dB)
RL = 500 Ω
Figure 43
t − Time − ns
0
−1
−3
0 100 200 300
1
2
PGA CLAMP RESPONSE
4
400 500
3
−2
−4
VCC = +15 V, +5 V
Gain = 1,0,0 (+2 dB)
VH = VCC+
Unclamped Output
Clamped Output
VL = 0 V
− Output Voltage − V
V
O
Figure 44
t − Time − ns
4
2
−2
0 50 100 150
6
8
12
200 250
10
0
−4
PGA CLAMP RESPONSE
VCC = +15 V
Gain = 1,0,0 (+2 dB)
VL = VCC−
Unclamped
Output
− Output Voltage − V
VO
Clamped
Output
VH = 5 V
Figure 45
100k
Shutdown Isolation − dB
f − Frequency − Hz
−20
−30
−40
−90
−80
−100 1M 10M 100M 500M
SHUTDOWN ISOLATION
vs
FREQUENCY
−60
−50
−70
Preamp: Forward Iso.
Preamp: Reverse Iso.
PGA: Reverse Iso.
PGA: Forward Iso.
VCC = ± 5 V & ± 15 V
VI(PP) = 2.5 V
Figure 46
VSHDN (5 V/Div) VCC = ±5 V,±15
Gain = 1,0,1
(+8 dB)
t − Time − ns
0 100 200 300 400 500 600 700 800 9001000
RL = ∞
RL = 500 Ω
PGA SHUTDOWN RESPONSE
− Output Voltage − V
V
O
VOUT
(500 mV/Div)
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 47
t − Time − ns
0 102030405060708090100
VCC = ±15 V
VCC = ±5 V
VSHDN (5 V/Div)
PGA SHUTDOWN RESPONSE
− Output Voltage − V
VO
VOUT (500 mV/Div)
Gain = 1,0,1
(+8 dB)
RL = 500 Ω
Figure 48
t − Time − ns
012345678910
RL = ∞
VCC = ±15 V
VSHDN (5 V/Div)
PREAMP SHUTDOWN RESPONSE
− Output Voltage − V
V
O
RL = 150 Ω
VCC = ±5 V
Figure 49
VO (500 mV/Div)
PGA 5-V STEP RESPONSE
3
2
1
0
−1
−2
0 50 100 150 200 250
t − Time − ns
V
−3
G = 2 dB
VCC = ±5 V
RL = 1 kΩ
O
− Output Voltage − V
300
PGA 20-V STEP RESPONSE
2.5
0
−2.5
−5.0
−7.5
−10.0
0 100 200 300 400 500
t − Time − ns
V
−12.5
5.0
7.5
10.0
12.5 G = 8 dB
VCC = ±15 V
RL = 1 kΩ
O− Output Voltage − V
Figure 50
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
theory of operation
Each section of the THS7001 and THS7002 consists of a pair of high speed operational amplifiers configured
in a voltage feedback architecture. They are built using a 30-V, dielectrically isolated, complementary bipolar
process with NPN and PNP transistors possessing fTs of several GHz. This results in exceptionally high
performance amplifiers that have a wide bandwidth, high slew rate, fast settling time, and low distortion. A
simplified schematic of the preamplifiers are shown in Figure 51.
IN−
IN+
OUT
VCC−
VCC+
Figure 51. Pre-Amp Simplified Schematic
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true for the preamplifiers, which typically amplify
small signals. The noise model is shown in Figure 52. This model includes all of the noise sources as follows:
•en = amplifier internal voltage noise (nV/√Hz)
•IN+ = noninverting current noise (pA/√Hz)
•IN− = inverting current noise (pA/√Hz)
•eRx = thermal voltage noise associated with each resistor (eRx = 4 kTRx)
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
noise calculations and noise figure (continued)
_
+
RF
RS
RG
eRg
eRf
eRs en
IN+
Noiseless
IN−
eni eno
Figure 52. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
eni +ǒenǓ2)ǒIN ) RSǓ2)ǒIN– ǒRFøRGǓǓ2)4kTR
s)4kT
ǒRFøRGǓ
Ǹ
Where: k = Boltzmann’s constant = 1.380658 × 10−23
T = temperature in degrees Kelvin (273 +°C)
RF || RG = parallel resistance of RF and RG
(1)
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
eno +eni AV+eniǒ1)RF
RGǓ(Noninverting Case) (2)
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RF + RG), the input noise can be reduced considerably because of
the parallel resistance term. This leads to the general conclusion that the most dominant noise sources are the
source resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a
root-mean-squares method, noise sources smaller than 25% of the largest noise source can be effectively
ignored. This can greatly simplify the formula and make noise calculations much easier to calculate.
By using the low noise preamplifiers as the first element in the signal chain, the input signal’s signal-to-noise
ratio (SNR) is maintained throughout the entire system. This is because the dominant system noise is due to
the first amplifier. This can be seen with the following example:
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
noise calculations and noise figure (continued)
RF1
A1
Vin
_
+
_
+
RG1
RF2
RG2
eni1
+
eno1
eni2
eno2
AV1= 1+ RF1
RG1 AV2= 1+ RF2
RG2
Figure 53. Simplified Composite Amplifier System
The noise due to amplifier 1 (A1) is the same as derived in equations 1 and 2. The composite system noise is
calculated as follows:
eno2 +eni22)eno12
Ǹ AV2
(3)
+eni22)ǒeni1AV1Ǔ2
Ǹ AV2
In a typical system, amplifier 1 (A1) has a large gain (AV1). Because the noise is summed in the RMS method,
if the A1 output noise is more than 25% larger than the input noise of amplifier 2, the contribution of
amplifier 2’s input noise to the composite amplifier output noise can effectively be ignored. This reduces
equation 3 down to:
(4)
eno2 ≅eni1 AV1 AV2
Equation 4 shows that the very first amplifier (the preamplifier) is critical in any low-level signal system. This also
shows that practically any noisy amplifier can be used after the preamplifier with minimal SNR degradation.
For more information on noise analysis, please refer to the Noise Analysis section in Operational Amplifier
Circuits Applications Report (literature number SLVA043).
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
NF +10logȧ
ȧ
ȱ
Ȳ
e2
ni
ǒeRsǓ2ȧ
ȧ
ȳ
ȴ
SLOS214C − O C TOBER 1998 − REVISED MARCH 2007
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
noise calculations and noise figure (continued)
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
NF +10logȧ
ȧ
ȧ
ȧ
ȧ
ȱ
Ȳ
1)
ȧ
ȡ
ȢǒenǓ2
)ǒIN ) RSǓ2ȧ
ȣ
Ȥ
4kTR
S
ȧ
ȧ
ȧ
ȧ
ȧ
ȳ
ȴ
Figure 54 shows the noise figure graph for the THS7001 and THS7002.
PREAMP NOISE FIGURE
vs
SOURCE RESISTANCE
14
12
10
8
6
4
10 100 1k
Source Resistance − Ω
2
Noise Figure − dB
10k
16 f = 10 kHz
TA = 25 _C
0
Figure 54. Noise Figure vs Source Resistance
optimizing frequency response for the preamplifiers
Internal frequency compensation of the THS7001 and THS7002 was selected to provide very wide bandwidth
performance and still maintain a very low noise floor. In order to meet these performance requirements, the
preamplifiers must have a minimum gain of 2 (−1). Because everything is referred to the noninverting terminal
of an operational amplifier, the noise gain in a G = −1 configuration is the same as a G = 2 configuration.
One of the keys of maintaining a smooth frequency response, and hence, a stable pulse response, is to pay
particular attention to the inverting terminal. Any stray capacitance at this node causes peaking in the frequency
response. There are two things that can be done to help minimize this effect. The first is to simply remove any
ground planes under the inverting terminal of the amplifier. This also includes the trace that connects to this
terminal. Additionally, the length of this trace should be minimized. The capacitance at this node causes a lag
in the voltage being fed back due to the charging and discharging of the stray capacitance. If this lag becomes
too long, the amplifier will not be able to correctly keep the noninverting terminal voltage at the same potential
as the inverting terminal’s voltage. Peaking and possibly oscillations can occur if this happens.
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APPLICATION INFORMATION
optimizing frequency response for the preamplifiers (continued)
The next thing that helps to maintain a smooth frequency response is to keep the feedback resistor (Rf) and
the gain resistor (Rg) values fairly low. These two resistors are effectively in parallel when looking at the ac
small-signal response. This is why in a configuration with a gain of 5, a feedback resistor of 5.1 kΩ with a gain
resistor of 1.2 kΩ only shows a small peaking in the frequency response. The parallel resistance is less than
1 kΩ. This value, in conjunction with a very small stray capacitance test PCB, forms a zero on the edge of the
amplifier ’s natural frequency response. To eliminate this peaking, all that needs to be done is to reduce the
feedback and gain resistances. One other way to compensate for this stray capacitance is to add a small
capacitor in parallel with the feedback resistor. This helps to neutralize the effects of the stray capacitance. To
keep this zero out of the operating range, the stray capacitance and resistor value’ s time constant must be kept
low . But, as can be seen in Figures 14 − 19, a value too low starts to reduce the bandwidth of the amplifier. Table
1 shows some recommended feedback resistors to be used with the THS7001 and THS7002 preamplifiers.
Table 2. Recommended Feedback Resistors
GAIN Rf for VCC = ±15 V and ± 5 V
2499 Ω
−1 499 Ω
51 kΩ
PGA gain control
The PGA section of the THS7001 and THS7002 IC allows for digital control of the gain. There are three digital
control pins for each side of the PGA (AG0 – AG2, and BG0 – BG2). Standard TTL or CMOS Logic will control
these pins without any difficulties. The applied logic levels are referred to the DGND pins of the THS7002. The
gain functions are not latched and therefore always rely on the logic at these pins to maintain the correct gain
settings. A 3.3 kΩ resistor to ground is usually applied at each input to ensure a fixed logic state. The gain control
acts like break-before-make SPDT switches. Because of this action, the PGA will go into an open-loop condition.
This may cause the output to behave unpredictably until the switches closes in less than 1.5 µs. Due to the
topology of this circuit, the controlling circuitry must be able to sink up to 2 µA of current when 0-V is applied
to the gain control pin. A simplified circuit diagram of the gain control circuitry is shown in Figure 55.
+VCC
To Internal
Bias Circuitry
Control
−VCC
DGND
Gain
Figure 55. Simplified PGA Gain Control
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APPLICATION INFORMATION
PGA gain control (continued)
One aspect of the THS7001 and THS7002 PGA signal inputs is that there are internal variable resistors (RF
and RG), which set the gain. The resistance of RG changes from about 270-Ω (Gain = +20 dB) to about 3-kΩ
(Gain = −22 dB). Therefore, any source impedance at the input to the PGA amplifiers will cause a gain error
to be seen at the output. A buffer/amplifier is highly recommended to directly drive the input of the PGA section
to help minimize this effect.
Another thing which should be kept in mind is that when each amplifier ’s VREF is connected to ground, the
internal RG resistor is connected to a virtual ground. Therefore, if a termination resistor is used on the source
side, the total terminating resistance is the parallel combination of the terminating resistance and the internal
RG resistor. This, in conjunction with the series impedance problem mentioned previously, can potentially cause
a voltage mismatch between the output of a 50-Ω source and the expected PGA output voltage. These points
can be easily seen in the simplified diagram of the THS7001 and THS7002 PGA section (see Figure 56).
+
−PGA
VOUT
No Source Impedance
VIN
RGRF
PGA
G0 G1 G2
PGA
−VIN
Negative
Clamp VL
Positive
Clamp VH
THS7001 and THS7002 IC
PGA
VREF
RTERMINATION
RSOURCE
RTOTAL TERMINATION +RTERMINATION ǒRSOURCE )RGǓ
RTERMINATION )ǒRSOURCE )RGǓ
Figure 56. Simplified PGA Section of the THS7001 and THS7002
voltage reference terminal
If a voltage is applied to the PGA’s VREF terminal, then the output of the PGA section will amplify the applied
reference voltage by one plus the selected gain. Thus, the output gain strictly due to VREF will be from +0.6 dB
to +21 dB according to the following formula:
VOUT
VREF +20 X Log10ƪ1)ǒPGA GainǒVńVǓǓƫ
For most configurations, it is recommended that this pin be connected to the signal ground.
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APPLICATION INFORMATION
output clamping
Typically, the output of the PGA will directly drive an analog-to-digital converter (ADC). Because of the limited
linear input range and saturation characteristics of most ADCs, the PGA’s outputs incorporate a voltage clamp.
Unlike a lot of clamping amplifiers which clamp only at the input, the THS7001 and THS7002 clamps at the
output stage. This insures that the output will always be protected regardless of the Gain setting and the input
voltage. The clamps activate almost instantaneously and recover from saturation in less than 7 ns. This can be
extremely important when the THS7001 and THS7002 is used to drive some ADCs which have a very long
overdrive recovery time. It is also recommended to add a pair of high frequency bypass capacitors to the clamp
inputs. These capacitors will help eliminate any ringing which may ocur when a large pulse is applied to the
amplifier. This pulse will force the clamp diodes to abruptly turn on, drawing current from the reference voltages.
Just like a power supply trace, you must minimize the inductance seen by the clamp pins. The bypass capacitors
will supply the sudden current demands when the clamps are suddenly turned on. A simplified clamping circuit
diagram is shown in Figure 57. +VCC
−VCC
To Bias Circuits
VH
VL
OUT
Output
Transistor
Output
Transistor
Drive
V1
0.1 µF
V2
0.1 µF
Figure 57. Simplified THS7001 and THS7002 Clamp Circuit
Because the internal clamps utilize the same clamping reference voltages, the outputs of both PGAs on the
THS7002 are clamped to the same values. These clamps are typically connected to the power supply pins to
allow a full output range. But, they can be connected to any voltage reference desired. The clamping range is
limited t o + V CC and GND for VH and –VCC and GND for VL. It is possible to go beyond GND for each respective
clamp, but it is not recommended. This is because this operation relies on the internal bias currents in the Class
AB output stage to maintain their linearity. There may also be a chance to reverse bias the PN junctions and
possibly cause internal damage to these junctions. But for reference, the graphs in Figure 58 show the output
voltage versus the clamping voltage with different loads.
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APPLICATION INFORMATION
output clamping (continued)
−4
−3
−2
−1
0
1
2
3
4
−4−3−2−1012345
OUTPUT VOLTAGE
vs
CLAMP VOLTAGE (VL)
Clamp Voltage − V
RL=5.1 k Ω
VO− Output Voltage − V
VCC=±5 V & ±15 V
VI=5 V
Gain=+2 dB
RL=500 Ω
−4
−3
−2
−1
0
1
2
3
4
−5−4−3−2−101234
OUTPUT VOLTAGE
vs
CLAMP VOLTAGE (VH)
Clamp Voltage − V
RL=5.1 k Ω
VO− Output Voltage − V
VCC=±5 V & ±15 V
VI=−5 V
Gain=+2 dB
RL=500 Ω
Figure 58. Output Voltage vs Clamp Voltage
The accuracy of this clamp is dependant on the amount of current flowing through the internal clamping diodes.
As is typical with all diodes, the voltage drop across this diode increases with current. Therefore, the accuracy
of the clamp is highly dependant upon the output voltage, the clamping voltage difference, and the output
current. The accuracy of the clamps with different load resistances are shown in Figure 59.
−200
−160
−120
−80
−40
0
40
−5 −4 −3 −2 −1 0
VL=−4 V
NEGATIVE CLAMP ACCURACY (V
L
)
Expected Output Voltage− V
RL=500 Ω
Gain = +2dB
VL=−1 V
VL=−2 V
VL=−3 V
−160
−120
−80
−40
0
40
80
−5 −4 −3 −2 −1 0
VL=−4 V
RL=1 k Ω
Gain = +2dB
VL=−1 V
VL=−2 V
VL=−3 V
NEGATIVE CLAMP ACCURACY (V
L
)
Expected Output Voltage − V
−160
−120
−80
−40
0
40
80
−5 −4 −3 −2 −1 0
VL=−4 V
RL=5.1 k Ω
Gain = +2dB VL=−1 V
VL=−2 V
VL=−3 V
NEGATIVE CLAMP ACCURACY (V
L
)
Expected Output Voltage − V
V
O
− V
CLAMP
VO− VCLAMP
VO− VCLAMP
−80
−40
0
40
80
120
160
012345
VH=4 V
RL=500 Ω
Gain = +2dB
VH=1 V
VH=2 V
VH=3 V
POSITIVE CLAMP ACCURACY (V
H
)
Expected Output Voltage − V
−120
−80
−40
0
40
80
120
012345
VH=4 V
RL=1 k Ω
Gain = +2dB
VH=1 V
VH=2 V
VH=3 V
POSITIVE CLAMP ACCURACY (V
H
)
Expected Output Voltage − V
−120
−80
−40
0
40
80
120
012345
VH=4 V
RL=5.1 k Ω
Gain = +2dB
VH=1 V
VH=2 V
VH=3 V
POSITIVE CLAMP ACCURACY (V
H
)
Expected Output Voltage − V
VO− VCLAMP
VO− VCLAMP
VO− VCLAMP
Figure 59. Clamping Accuracy
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APPLICATION INFORMATION
shutdown control
There are two shutdown pins which control the shutdown for each half of the THS7002 and one shutdown pin
for the THS7001. When the shutdown pins signals are low, the THS7001 and THS7002 is active. But, when a
shutdown pin is high (+5 V), a preamplifier and the respective PGA section is turned off. Just like the Gain
controls, the shutdown logic is not latched and should always have a signal applied to them. A 3.3-kΩ resistor
to ground is usually applied to ensure a fixed logic state. A simplified circuit can be seen in Figure 60.
+VCC
To Internal
Bias Circuitry
Control
−VCC
DGND
DGND
53 kΩ
Gain
Figure 60. Simplified THS7001 and THS7002 Shutdown Circuit
One aspect of the shutdown feature, which is often over-looked, is that the PGA section will still have an output
while in shutdown mode. This is due to the internally fixed RF and RG resistors. This ef fect is true for any amplifier
connected as an inverter. The internal circuitry may be powered down and in a high-impedance state, but the
resistors are always there. This will then allow the input signal current to flow through these resistors and into
the output. The equivalent resistance of RF and RG is approximately 3 kΩ. To minimize this effect, a shunt
resistor to ground may be utilized, This will act as a classic voltage divider and will reduce the feed-through
voltage seen at the PGA output. The drawback to this is the increased load on the PGA while in the active state.
driving a capacitive load
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS7001 and THS7002 has been internally compensated to maximize its
bandwidth and slew rate performance. When an amplifier is compensated in this manner, capacitive loading
directly on the output will decrease the device’s phase margin leading to high frequency ringing or oscillations.
Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with
the output of the amplifier, as shown in Figure 61. A minimum value of 20 Ω should work well for most
applications. For example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates
any capacitance loading and provides the proper line impedance matching at the source end.
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APPLICATION INFORMATION
driving a capacitive load (continued)
+
_
PREAMP
CLOAD
499 Ω
Input
Output
499 Ω
20 Ω
Figure 61. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input of fset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOS +ǒ"VIO "IIB)RSǓǒ1)RF
RGǓ"IIB*RF
+
−
VIO
RG
RS
RF
IIB−
VOS
IIB+
+−
Figure 62. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the THS7001
and THS7002 preamplifier (see Figure 63).
VIVO
C1
+
−
RGRF
R1
f–3dB +1
2pR1C1
VO
VI+ǒ1)RF
RGǓǒ1
1)sR1C1Ǔ
Figure 63. Single-Pole Low-Pass Filter
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APPLICATION INFORMATION
general configurations (continued)
If even more attenuation is needed, a multiple-pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the THS7001 and THS7002 preamplifier should have a bandwidth that is 8 to 10 times
the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier.
VI
C2
R2R1
C1
RF
RG
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
(
=1
Q
2 − )
RGRF
_
+f–3dB +1
2pRC
Figure 64. 2-Pole Low-Pass Sallen-Key Filter
ADSL
The ADSL receive band consists of up to 255 separate carrier frequencies each with its own modulation and
amplitude level. With such an implementation, it is imperative that signals received off the telephone line have
as high a signal-to-noise ratio (SNR) as possible. This is because of the numerous sources of interference on
the line. The best way to accomplish this high SNR is to have a low-noise preamplifier on the front-end. It is also
important to have the lowest distortion possible to help minimize against interference within the ADSL carriers.
The THS7001 and THS7002 was designed with these two priorities in mind.
By taking advantage of the superb characteristics of the complimentary bipolar process (BICOM), the THS7001
and THS7002 offers extremely low noise and distortion while maintaining a high bandwidth. There are some
aspects that help minimize distortion in any amplifier. The first is to extend the bandwidth of the amplifier as high
as possible without peaking. This allows the amplifier to eliminate any nonlinearities in the output signal. Another
thing that helps to minimize distortion is to increase the load impedance seen by the amplifier, thereby reducing
the currents in the output stage. This will help keep the output transistors in their linear amplification range and
will also reduce the heating effects.
One central-office side terminal circuit implementation, shown in Figure 65, uses a 1:2 transformer ratio. While
creating a power and output voltage advantage for the line drivers, the 1:2 transformer ratio reduces the SNR
for the received signals. The ADSL standard, ANSI T1.413, stipulates a noise power spectral density of –140
dBm/Hz, which is equivalent to 31.6 nV/√Hz for a 100 Ω system. Although many amplifiers can reach this level
of performance, actual ADSL system testing has indicated that the noise power spectral density may typically
be ≤ –150 dBm/Hz, or ≤ 10 nV/√Hz. With a transformer ratio of 1:2, this number reduces to less than 5 nV/√Hz.
The THS7002 preamplifiers, with an equivalent input noise of 1.7 nV/√Hz, is an excellent choice for this
application. Coupled with a very low 0.9 pA/√Hz equivalent input current noise and low value resistors, the
THS7001 and THS7002 will ensure that the received signal SNR will be as high as possible.
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APPLICATION INFORMATION
ADSL (continued)
_
+
6.8 µF0.1 µF
−12 V
6.8 µF0.1 µF
12 V
1 kΩ
1 kΩ
+
+
VI+
_
+
6.8 µF0.1 µF
−12 V
6.8 µF0.1 µF
12 V
1 kΩ
1 kΩ
+
+
VI−
+
−
499 Ω
499 Ω
1 kΩ
12.5 Ω
+
−
499 Ω
0.1 µF
499 Ω
1 kΩ
1:2
Telephone Line
12.5 Ω
12 V
−12 V
0.01 µF
THS7002
Preamp 1
THS7002
Preamp 2
VO+
VO−
THS6012
Driver 1
THS6012
Driver 2
100 Ω
Driver Block
Receiver Block
Figure 65. THS7002 Central-Office ADSL Application
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APPLICATION INFORMATION
ADSL (continued)
Typically, the outputs of the preamplifiers are carried into a CODEC, which incorporates an analog-to-digital
converter (ADC). The problem with this setup is that it only uses fixed gain elements. But, when the client is close
to the central office, the gain must be set to receive a high-level signal; or for the opposite, set to receive a
low-level signal. To solve this problem, a programmable-gain amplifier (PGA) should be used. The THS7001
and THS7002 PGAs allow the gain of the receiver signals to be varied from −22 dB to 20 dB. By allowing the
gains to b e controlled with a TTL-compatible signal, it is very easy to integrate the THS7001 and THS7002 into
any system.
By having the preamplifier output separate from the PGA input, inserting more amplifiers into the system can
be accomplished easily. The functionality of the amplifier is typically as an active fixed gain filter. This is shown
in Figure 66.
PGA
To
CODEC
_
+
_
+
V0+ R1R2
C1
C2
RGRF
G0G1G2
TO DSP
3.3 k
3.3 k
3.3 k
THS6062
VL
+5 VVH
RECEIVER
BLOCK
OPTIONAL CIRCUIT
Preamp
Figure 66. Typical PGA Setup (One Channel)
circuit layout considerations
In order to achieve the levels of high-frequency performance of the THS7001 and THS7002, it is essential that
proper printed-circuit board high-frequency design techniques be followed. A general set of guidelines is given
below. In addition, a THS7001 and THS7002 evaluation board is available to use as a guide for layout or for
evaluating the device performance.
DGround planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
DProper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches (2,54 mm) between the device
power terminals and the ceramic capacitors.
DSockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
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APPLICATION INFORMATION
circuit layout considerations (continued)
DShort trace runs/compact part placements—Optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
DSurface-mount passive components—Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
thermal information
The THS7001 and THS7002 is supplied in a thermally-enhanced PWP package, which is a member of the
PowerPAD. This package is constructed using a downset leadframe upon which the die is mounted [see
Figure 67(a) and Figure 67(b)]. This arrangement exposes the lead frame as a thermal pad on the underside
of the package [see Figure 67(c)]. Because this pad has direct contact with the die, excellent thermal
performance can be achieved by providing a good thermal path away from the pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area requirement and ease of
assembly of surface mount with the heretofore awkward mechanical methods of heatsinking.
thermal information (continued)
DIE
Side View (a)
End View (b)
Bottom View (c)
DIE
Thermal
Pad
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 67. Views of Thermally Enhanced PWP Package
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APPLICATION INFORMATION
general PowerPAD design considerations
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
THS7002
Thermal pad area (120 mils x 300 mils)
(3,05 mm x 7,62 mm)
with 10 vias
Via diameter = 13 mils (0,33 mm)
THS7001
Thermal pad area (120 mils x 250 mils)
(3,05 mm x 6,35 mm)
with 8 vias
Via diameter = 13 mils (0,33 mm)
Figure 68. PowerPAD PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 68. There should be etch for the leads as
well as etch for the thermal pad.
2. Place the thermal transfer holes in the area of the thermal pad. These holes should be 13 mils (0,33 mm)
in diameter. They are kept small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the IC. These additional vias may be larger than the 13-mil (0,33 mm)
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology . Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however , low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the IC package should make their connection to the internal ground plane with a complete
connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its
thermal transfer holes exposed. The bottom-side solder mask should cover the thermal transfer holes of
the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the
reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS7001PWP/THS7002PWP IC is simply placed in position and
run through the solder reflow operation as any standard surface-mount component. This results in a part
that is properly installed.
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)123456
The actual thermal performance achieved with the THS7001PWP/THS7002PWP in its PowerPAD package
depends on the application. In the example above, if the size of the internal ground plane is approximately
3 inches × 3 inches (76,2 mm x 76.2 mm), then the expected thermal coefficient, θJA, is about 32.6°C/W for the
THS7001 and 27.9_C/W for the THS7002. For a given θJA, the maximum power dissipation is shown in Figure
69 and is calculated by the following formula:
PD+ǒTMAX–TA
qJA Ǔ
Where: PD= Maximum power dissipation of THS7001 and THS7002 IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case (THS7001 = 1.4°C/W; THS7002 = 0.72°C/W)
θCA = Thermal coefficient from case to ambient air (°C/W)
THS7002
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
7
6
5
4
3
2
−40 −20 0 20 40 60
TA − Free-Air Temperature − _C
W
1
Maximum Power Dissipation −
80 100
8
TJ = 150 _C
0
θJA = 27.9 _C/W
2 oz. Trace and
Copper Pad With
Solder
θJA = 56.2 _C/W
2 oz. Trace and
Copper Pad
Without Solder
THS7001
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
7
6
5
4
3
2
−40 −20 0 20 40 60
TA − Free-Air Temperature − _C
W
1
Maximum Power Dissipation −
80 100
8
TJ = 150 _C
0
θJA = 32.6 _C/W
2 oz. Trace and
Copper Pad With
SolderθJA = 74.4 _C/W
2 oz. Trace and
Copper Pad
Without Solder
NOTE A: Results are with no air flow and PCB size = 3”×3” (76,2 mm x 76,2 mm)
Figure 69. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments technical brief, PowerPAD Thermally Enhanced Package. This document can be found
at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered
through your local TI sales office. Refer to literature number SLMA002 when ordering.
evaluation board
An evaluation board is available both the THS7001 (literature number SLOP250) and for the THS7002
(literature number SLOP136). These boards has been configured for very low parasitic capacitance in order
to realize the full performance of the amplifiers. These EVM’s incorporate DIP switches to demonstrate the full
capabilities of the THS7001 and THS7002 independent of any digital control circuitry. For more information,
please refer to the THS7001 EVM User’s Guide (literature number SLOU057)and the THS7002 EVM User’s
Guide (literature number SLOU037). To order a evaluation board contact your local TI sales office or distributor.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS7001CPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
THS7001CPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
THS7001CPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
THS7001CPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
THS7001IPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
THS7001IPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
THS7002CPWP ACTIVE HTSSOP PWP 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
THS7002CPWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
THS7002CPWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
THS7002CPWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
THS7002IPWP ACTIVE HTSSOP PWP 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
THS7002IPWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
THS7002IPWPRG4 ACTIVE HTSSOP PWP 28 TBD Call TI Call TI Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 2
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS7001CPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
THS7002CPWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS7001CPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
THS7002CPWPR HTSSOP PWP 28 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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