HYMD512M646ALFS8-J - SK Hynix - Datasheet.Directory

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.0 / June 2007 1

200pin DDR SDRAM SO-DIMMs based on 512Mb D ver. (FBGA)

FEATURES

ADDRESS TABLE

Organization Ranks SDRAMs # of DRAMs # of row/bank/column Address Refresh

Method

1GB 128M x 64 2 64Mb x 8 16 13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11) 8K / 64ms

PERFORMANCE RANGE

Note:

1. 2.6V ±0.1V VDD and VDDQ Power supply for DDR400 and 2.5V ±0.2V for DDR333 and below

Part-Number Suffix -D431-J -H

Speed Bin DDR400B DDR333 DDR266B

CL - tRCD- tRP 3-3-3 2.5-3-3 2.5-3-3

Max Clock

Frequency

CL=3 200 - -

CL=2.5 166 166 133

CL=2 133 133 133

This Hynix unbuffered Small Outline, Dual In-Line Memory Module (DIMM) series consists of 512Mb D ver.

DDR SDRAMs in 60 ball FBGA packages on a 200pin glass-epo xy substr ate. This Hynix 512Mb D ver. base d unbuffer ed

SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard.

It is suitable for easy interchange and addition.

• JEDEC Standard 200-pin small outline, dual in-line

memory module (SO-DIMM)

• Two ranks 128M x 64 organization

•2.6V

±0.1V VDD and VDDQ Power supply for

DDR400, 2.5V ±0.2V for DDR333 and below

• All inputs and outputs are compatible with SSTL_2

interface

• Fully differential clock operations (CK & /CK) with

133/166/200MHz

• DLL aligns DQ and DQS transition with CK transition

• Programmable CAS Latency : DDR266(2.5 clock),

DDR333(2.5 clock), DDR400(3 clock)

• Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

• Edge-aligned DQS with data outs and Center -aligned

DQS with data inputs

• Auto refresh and self refresh supported

• 8192 refresh cycles / 64ms

• Serial Presence Detect (SPD) with EEPROM

• Built with 512Mb DDR SDRAMs in 60 ball

FBGA packages

• All lead-free products (RoHS compliant)

Rev. 1.0 / June 2007 2

11

200pin DDR SDRAM SO-DIMMs

ORDERING INFORMATION

Note:

1. The “Lead-free” products contain Lead less than 0.1% by weight and satisfy Ro HS - please contact Hynix for product availability.

* These Products are built with HY5DU124(8,16)22D[L]FP the Hynix DDR SDRAM component

Part Number Density Organization # of

DRAMs Material DIMM Dimension

HYMD512M646D[L]FP8-D43/J/H 1GB 128M x 8 16 Lead-free167.60 x 31.75 x 3.8 [mm3]

Rev. 1.0 / June 2007 3

11

200pin DDR SDRAM SO-DIMMs

PIN DESCRIPTION

PIN ASSIGNMENT

Note:

1. * : These pins are not used in this module.

2. Pin 167 is NC for 256MB, 512MB, and 1GB, or A13 for 2GB module.

Pin Pin Description Pin Pin Description

CK0, /CK0 Differential Clock Inputs VDDQ DQs Power Supply

/CS0, /CS1 Chip Select Input VSS Ground

CKE0, CKE1 Clock Enable Input VREF Reference Power Supply

/RAS, /CAS, /WE Commend Sets Inputs VDDSPD Power Supply for SPD

A0 ~ A12 Address SA0~SA2 E2PROM Address Inputs

BA0, BA1 Bank Address SCL E2PROM Clock

DQ0~DQ63 Data Inputs/Outputs SDA E2PROM Data I/O

CB0~CB7 Data Strobe Inputs/Outputs WP Write Protect Flag

DQS0~DQS17 Data Strobe Inputs/Outputs VDDID VDD Identification Flag

DM0~7 Data-in Mask DU Do not Use

VDD Power Su pp ly NC No Connection

/RESET Reset Enable FETEN FET Enable

Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name

1 VREF 32 A5 62 VDDQ 93 VSS 124 VSS 154 /RAS

2 DQ0 33 DQ24 63 /WE 94 DQ4 125 A6 155 DQ45

3 VSS 34 VSS 64 DQ41 95 DQ5 126 DQ28 156 VDDQ

4 DQ1 35 DQ25 65 /CAS 96 VDDQ 127 DQ29 157 /CS0

5 DQS0 36 DQS3 66 VSS 97 DM0,DQS9 128 VDDQ 158 /CS1

6 DQ2 37 A4 67 DQS5 98 DQ6 129 DM3,DQS12 159 DM5,DQS14

7 VDD 38 VDD 68 DQ42 99 DQ7 130 A3 160 VSS

8 DQ3 39 DQ26 69 DQ43 100 VSS 131 DQ30 161 DQ46

9 NC 40 DQ27 70 VDD 101 NC 132 VSS 162 DQ47

10 /RESET 41 A2 71 /CS2* 102 NC 133 DQ31 163 NC

11 VSS 42 VSS 72 DQ48 103 NC 134 CB4* 164 VDDQ

12 DQ8 43 A1 73 DQ49 104 VDDQ 135 CB5* 165 DQ52

13 DQ9 44 CB0* 74 VSS 105 DQ12 136 VDDQ 166 DQ53

14 DQS1 45 CB1* 75 CK2* 106 DQ13 137 CK0 167 A132, NC

15 VDDQ 46 VDD 76 /CK2* 107 DM1,DQS10 138 /CK0 168 VDD

16 CK1* 47 DQS8 77 VDDQ 108 VDD 139 VSS 169 DM6

17 /CK1* 48 A0 78 DQS6 109 DQ14 140 DM8,DQS17 170 DQ54

18 VSS 49 CB2* 79 DQ50 110 DQ15 141 A10 171 DQ55

19 DQ10 50 VSS 80 DQ51 111 CKE1 142 CB6* 172 VDDQ

20 DQ11 51 CB3* 81 VSS 112 VDDQ 143 VDDQ 173 NC

21 CKE0 52 BA1 82 VDDID 113 BA2* 144 CB7* 174 DQ60

22 VDDQ Key 83 DQ56 114 DQ20 key 175 DQ61

23 DQ16 53 DQ32 84 DQ57 115 A12 145 VSS 176 VSS

24 DQ17 54 VDDQ 85 VDD 116 VSS 146 DQ36 177 DM7,DQS16

25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178 DQ62

26 VSS 56 DQS4 87 DQ58 118 A11 148 VDD 179 DQ63

27 A9 57 DQ34 88 DQ59 119 DM2,DQS11 149 DM4,DQS13 180 VDDQ

28 DQ18 58 VSS 89 VSS 120 VDD 150 DQ38 181 SA0

29 A7 59 BA0 90 NU 121 DQ22 151 DQ39 182 SA1

30 VDDQ 60 DQ35 91 SDA 122 A8 152 VSS 183 SA2

31 DQ19 61 DQ40 92 SCL 123 DQ23 153 DQ44 184 VDDSPD

Rev. 1.0 / June 2007 4

11

200pin DDR SDRAM SO-DIMMs

1GB, 128M x 64 Unbuffered SO-DIMM : HYMD512M646D[L]FP8

FUNCTIONAL BLOCK DIAGRAM

DM /CS DQS

D8

DM /CS DQS

D9

DM /CS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

/CS DQS

D0

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM /CS DQS

D1

DM /CS DQS

D2

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM /CS DQS

DQ32

DQ33

DQ35

DQ36

DQ37

DQ38

DQ39

DM /CS DQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM /CS DQS

D5

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM /CS DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM /CS DQS

D7

DM0

DQS0 DM4

DQS4

DQ8

DQ9

DM1

DQS1

DM2

DQS2

DM3

DQS3 DM7

DQS7

DM6

DQS6

DM5

DQS5

/CS0

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM /CS DQS

D13

DM /CS DQS

D15

DM /CS DQS

D10

/CS1

D11D3

D14

D6

D4 D1

2

DM /CS DQS

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

D12

DQ34

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O0 I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

DM

Strap:see Note 4

VDD SPD

VDD /VDDQ

VREF

VSS

VDDID

SPD

DO-D15

BA0-BA1

A0-A12

/RAS

/CAS

CKE0

/WE

BA0-BA1 : SDRAMs D0-D15

A0-A12 : SDRAMs D0-D15

/RAS : SDRAMs D0-D15

/CAS : SDRAMs D0-D15

CKE : SDRAMs D0-D7

/WE : SDRAMs D0-D15

CKE1 CKE : SDRAMs D8-D15

Note :

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/S relatio n s h ips must be ma in ta in e d a s sh o wn.

3. DQ, DQS, DM/DQS resistors : 22 Ohms ? 5%.

4. VDDID strap connections (for memory device VDD, VDDQ) :

STRAP OUT (OPEN) : VDD = VDDQ

STRAP IN (VSS) : VDD ≠ VDDQ

WP

SCL SDA

A0 A1 A2

SA0 SA1 SA2

Serial PD

CK0 8 loads

/CK0

CK1

/CK1

CK2

/CK2

8 loads

0 loads

Rev. 1.0 / June 2007 5

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200pin DDR SDRAM SO-DIMMs

ABSOLUTE MAXIMUM RATINGS1

Note:

1. Operation at above absolute maximum rating can adversely affect device reliability

Parameter Symbol Rating Unit

Operating Temperature (Ambient) TA0 ~ 70 oC

Storage Temperature TSTG -55 ~ 150 oC

Voltage on VDD relative to VSS VDD -1.0 ~ 3.6 V

Voltage on VDDQ relative to VSS VDDQ -1.0 ~ 3.6 V

Voltage on inputs relative to Vss VINPUT -1.0 ~ 3.6 V

Voltage on I/O pins realtive to Vss VIO -0.5 ~3.6 V

Output Short Circuit Current IOS 50 mA

Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 oC ⋅ Sec

DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)

Notes:

1. VDDQ must not exceed the level of VDD.

2. For DDR400, VDD=2.6V ±0.1V, VDDQ=2.6V ±0.1V

3. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.

4. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to

peak noise on VREF may not exceed ±2% of the DC value.

5. VID is the magnitude of the difference between the input level on CK and the input level on /CK.

6. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-

ture and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum differ-

ence between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum

pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.

7. VIN=0 to VDD, All other pins are not tested under VIN =0V.

8. DQs are disabled, VOUT=0 to VDDQ.

Parameter Symbol Min Typ. Max Unit Note

Power Supply Voltage (DDR 200, 266, 333) VDD 2.3 2.5 2.7 V

Power Supply Voltage (DDR 400) VDD 2.5 2.6 2.7 V 2

Power Supply Voltage (DDR 200, 266, 333) VDDQ 2.3 2.5 2.7 V 1

Power Supply Voltage (DDR 400) VDDQ 2.5 2.6 2.7 V 1,2

Input High Voltage VIH VREF + 0.15 - VDDQ + 0.3 V

Input Low Voltage VIL -0.3 - VREF - 0.15 V 3

Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V

Reference Volta ge VREF 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V 4

Input Voltage Level, CK and CK inputs VIN(DC) -0.3 - VDDQ+0.3 V

Input Differential Voltage, CK and CK inputs VID(DC) 0.36 - VDDQ+0.6 V 5

V-I Matching: Pullup to Pulldown Current Ratio VI(RATIO) 0.71 - 1.4 - 6

Input Leakage Current ILI -2 - 2 uA 7

Output Leakage Current ILO -5 - 5 uA 8

Normal Strength

Output Driver

(VOUT=VTT°æ0.84)

Output High Current

(min VDDQ, min VREF, min VTT ) IOH -16.8 - - mA

Output Low Current

(min VDDQ, max VREF, max VTT ) IOL 16.8 - - mA

Half Strength Out-

put Driver

(VOUT=VTT°æ0.68)

Output High Current

(min VDDQ, min VREF, min VTT ) IOH -13.6 - - mA

Output Low Current

(min VDDQ, max VREF, max VTT ) IOL 13.6 - - mA

Rev. 1.0 / June 2007 6

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200pin DDR SDRAM SO-DIMMs

IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)

1GB, 128M x 64 Unbuffered SO-DIMM: HYMD512M646D[L]FP8

* Module IDD was calculat ed on the basis of component I DD and can be differently measured according to DQ lo ading cap.

Symbol Test Conditio n Speed Unit Note

DDR400B DDR333 DDR266B

IDD0

One bank; Active - Precharge; tRC=tRC(min);

tCK=tCK(min); DQ,DM and DQS inputs changing twice

per clock cycle; address and control inputs changing

once per clock cycle

1520 1440 1280 mA

IDD1

One bank; Active - Read - Precharge; Burst Length=2;

tRC=tRC(min); tCK =tCK ( min ) ; address and control

inputs changing once per clock cycle

1840 1680 1440 mA

IDD2P All banks idle; Power down mode; CKE=Low,

tCK=tCK(min) 160 mA

IDD2F

/CS=High, All banks idle; tCK=tCK(min); CKE= High;

address and control inputs changing once per clock

cycle. VIN=VREF for DQ, DQS and DM

560 mA

IDD3P One bank active ; Po we r down mode; CK E=Low,

tCK=tCK(min) 720 mA

IDD3N

/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;

tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS

inputs changing twice per clock cycle; Address and

other control inputs ch anging once per clock cycle

960 mA

IDD4R

Burst=2; Reads; Continuous burst; One bank acti ve;

Address and control inputs changing once per clock

cycle; tCK=tCK (min ) ; IOUT=0mA

2160 2000 1840 mA

IDD4W

Burst=2; Writes; Continuous burst; One bank active;

Address and control inputs changing once per clock

cycle; tCK=tCK(min); DQ, DM and DQS inputs chang-

ing twice per clock cycle

2320 2160 1920 mA

IDD5

tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,

10*tCK for DDR266A & DDR266B at 133Mhz; distrib-

uted refresh

2560 2400 2240 mA

IDD6 CKE=<0.2V; External clock on; tCK

=tCK(min)

Normal 80 mA

Low Power 48 mA

IDD7 Four bank interleaving with BL=4 Refer to the follow-

ing page for detailed test condit ion 3360 3280 3200 mA

Rev. 1.0 / June 2007 7

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200pin DDR SDRAM SO-DIMMs

AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)

Notes :

1. VID is the magnitude of the difference between the input level on CK and the input on /CK.

2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)

OUTPUT LOAD CIRCUIT

Parameter Symbol Min Max Unit Note

Input High (L ogic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 - V

Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) -VREF - 0.31 V

Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ + 0.6 V 1

Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2

Parameter Value Unit

Reference Volta ge VDDQ x 0.5 V

Termination Voltage VDDQ x 0.5 V

AC Input High Level Vo ltage (VIH, min) VREF + 0.31 V

AC Input Low Level Vol tage (VIL, max) VREF - 0.31 V

Input Timing Measureme nt Reference Level Voltage VREF V

Output Timing Measurement Reference Level Voltage VTT V

Input Signal maximum peak swing 1.5 V

Input minimum Signal Slew Rate 1 V/ns

Termination Resistor (RT)50Ω

Series Resistor (RS)25Ω

Output Load Capacitance for Access Time Measurement (CL)30 pF

VREF

VTT

RT=50Ω

Zo=50Ω

CL=30pF

Output

Rev. 1.0 / June 2007 8

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200pin DDR SDRAM SO-DIMMs

CAPACITANCE (TA=25oC, f=100MHz)

1GB : HYMD512M646D[L]FP8

Input/Output Pins Symbol Min Max Unit

A0 ~ A12, BA0, BA1 CIN1 50 68 pF

/RAS, /CAS, /WE CIN2 50 68 pF

CKE0, CKE1 CIN3 36 48 pF

/CS0, /CS1 CIN4 36 48 pF

CK0, /CK0, CK1, /CK1, CK2, /CK2 CIN5 30 38 pF

DM0 ~ DM7 CIN6 10 18 pF

DQ0 ~ DQ63, DQS0 ~ DQS7 CIO1 10 18 pF

Rev. 1.0 / June 2007 9

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200pin DDR SDRAM SO-DIMMs

AC CHARACTERISTICS (note: 1 - 9 / AC operating conditions unless otherwise noted)

Parameter Symbol DDR400B DDR333 DDR266A DDR266B DDR200 UNIT

Min Max Min Max Min Max Min Max Min Max

Row Cycle Time tRC 55 - 60 - 65 - 65 - 70 - ns

Auto Refresh R o w

Cycle Time tRFC 70 - 72 - 75 - 75 - 80 - ns

Row Active Time tRAS 40 70K 42 70K 45 120K 45 120K 50 120K ns

Active to Read with

Auto Precharge Delay tRAP tRCD or

tRASmin -tRCD or

tRASmin -ns

Row Address to

Column Address Delay tRCD 15 - 18 - 20 - 20 - 20 - ns

Row Active to Row

Active Delay tRRD 10 - 12 - 15 - 15 - 15 - ns

Column Address to

Column Address Delay tCCD 1 - 1 - 1 - 1 - 1 - tCK

Row Precharge Time tRP 15 - 18 - 20 - 20 - 20 - ns

Write Recove ry Time tWR 15 - 15 - 15 - 15 - 15 - ns

Internal Write to Read

Command Delay tWTR 2 - 1 - 1 - 1 - 1 - tCK

Auto Precharge Write

Recovery + Precharge

Time22 tDAL

(tWR/

tCK)

+

(tRP/tCK)

-

(tWR/

tCK)

+

(tRP/tCK)

-

(tWR/

tCK)

+

(tRP/tCK)

-

(tWR/

tCK)

+

(tRP/tCK)

-

(tWR/

tCK)

+

(tRP/tCK)

-tCK

System

Clock Cycle

Time24

CL = 3

tCK

510--------

CL = 2.5 - - 6 12 7.5 12 7.5 12 8.0 12 ns

CL = 2 - - 7.5127.51210121012ns

Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Data-Out edge to Clock

edge Skew tAC -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns

DQS-Out edge to Clock

edge Skew tDQSCK -0.55 0.55 -0.6 0.6 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns

DQS-Out edge to Data-

Out edge Skew21 tDQSQ - 0.4 - 0.4 - 0.5 - 0.5 - 0.6 ns

Data-Out hold time

from DQS20 tQH tHP

-tQHS -tHP

-tQHS -ns

Clock Half Period19,20 tHP min

(tCL,tCH) -min

(tCL,tCH) -ns

Data Hold Skew

Factor20 tQHS - 0.5 - 0.5 - 0.75 - 0.75 - 0.75 ns

Valid Data Output

Window tDV tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ ns

Rev. 1.0 / June 2007 10

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200pin DDR SDRAM SO-DIMMs

- Continue

Parameter Symbol DDR400B DDR333 DDR266A DDR266B DDR200 UNIT

Min Max Min Max Min Max Min Max Min Max

Data-out high-impedance window

from CK,/CK10 tHZ -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns

Data-out low-imped a nce window

from CK, /CK10 tLZ -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns

Input Setup Time (f ast slew

rate)14,16-18 tIS 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns

Input Hold Time (fast slew

rate)14,16-18 tIH 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns

Input Setup Time (slow slew

rate)15-18 tIS 0.7 - 0.8 - 1.0 - 1.0 - 1.1 - ns

Input Hold Time (slow sl ew

rate)15-18 tIH 0.7 - 0.8 - 1.0 - 1.0 - 1.1 - ns

Input Pulse Width17 tIPW 2.2 - 2.2 - 2.2 - 2.2 - 2.5 - ns

Write DQS High Level Width tDQSH 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - tCK

Write DQS Low Level Width tDQSL 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - tCK

Clock to First Rising edge of DQS-

In tDQSS 0.72 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK setup ti m e tDSS 0.2 -0.2-0.2-0.2-0.2-tCK

DQS falling edge hold time from

CK tDSH 0.2 -0.2-0.2-0.2-0.2-tCK

DQ & DM input setup ti me25 tDS 0.4 - 0.45 - 0.5 - 0.5 - 0.6 - ns

DQ & DM input hold time25 tDH 0.4 - 0.45 - 0.5 - 0.5 - 0.6 - ns

DQ & DM Input Pulse Width17 tDIPW 1.75 - 1.75 - 1.75 - 1.75 - 2 - ns

Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK

Write DQS Preamble Setup Time12 tWPRES 0-0-0-0-0-ns

Write DQS Preamble Hold Time tWPREH 0.25 - 0.25 - 0.25 - 0.25 - 0.25 - tCK

Write DQS Postamble Time11 tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK

Mode Register Set Delay tMRD 2-2-2-2-2-tCK

Exit Self Refresh to non-Read

command23 tXSNR 75 - 75 - 75 - 75 - 80 - ns

Exit Sel f Refresh to Re ad

command tXSRD 200 - 200 - 200 - 200 - 200 - tCK

Average Periodic Refresh

Interval13,25 tREFI -7.8 - 7.8 - 7.8 - 7.8 - 7.8 us

Rev. 1.0 / June 2007 11

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200pin DDR SDRAM SO-DIMMs

Notes:

1. All voltages referenced to Vss.

2. Tests fo r ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels,

but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to

be either a precise representation of the typic al system envir onment nor a depicti on of the actual load presented by a production

tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment .

Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester elec-

tronics).

4. AC timing and IDD tests may use a VIL to VIHswing of up to 1.5 V in the test environment, but input timing is still referenced to

VREF (or to the crossing point for CK, /CK), and parameter specifications are guaranteed for the specified ac inpu t levels under

normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).

5. The ac and dc inpu t level specification s are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result

of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the

dc input LOW (HIGH) level.

6. Inputs are not recognized as valid until VREF stabilizes. Ex ception: during the period before VREF stabi li z es , CK E < 0.2VDDQ is

recognized as LOW.

7. The CK, /CK input referen ce level ( for timing referenced to CK, /CK) is the point at whic h CK and /CK cross; t h e input reference

level for signals other than CK, /CK is VRE F.

8. The output timing reference voltage level is VTT.

9. Oper at ion or timi ng t hat is n ot s pecifi ed is illega l and after such an event, in order to guarantee proper operation, the DRAM must

be powered down and then restarted through the specified initialization sequence before normal operation can continue.

10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to

a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).

11. The maximum limit for this parameter is not a de vice limit. The devi ce w ill operate with a greater value for this parameter, but

system performance (bus turnaround) will degrade accordingly.

12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A

valid transition is defined as monotonic and meeting the input sl ew rate specifications of the device. When no writes were previ-

ously in progress on the bus, DQS will be t ransition ing from High-Z to logic LOW. If a previous write was in progress, DQS could

be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.

13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

14. For command/address inpu t slew rate ≥1.0 V/ns.

15. For command/address input slew rate ≥0.5 V/ns and ＜1.0 V/ns

16. For CK & /CK slew rate ≥1.0 V/ns (single-ended)

17. These parameters guarantee device timing, but they are not nec essarily tested on each d evice.

They may be guaranteed by device design or tester correlation.

18. Slew Rate is measured between VOH(ac) and VOL(ac).

19. Min (tCL, tCH) r ef e rs to th e sma ller of th e actu al clock low ti me and th e actual cl ock hi gh ti me as pr ov ided t o the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).

For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half

period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.

Figure: Timing Referenc e Lo ad

VDDQ

50

Output

(VOUT)

30 pF

Ω

Rev. 1.0 / June 2007 12

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200pin DDR SDRAM SO-DIMMs

20.tQH = tHP - tQHS, where:

tHP = minimum half clock period f or any giv en cycle and is defined by clock high or clock lo w (tCH, tCL). tQHS accounts fo r 1) The

pulse duration distortio n of on-chip clock circuits; and 2) The worst case push--ou t of DQS on one transition followed by the

worst case pull--in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects,

and p-channel to n-channel variation of the output drivers.

21. tDQSQ:

Consists of data pin skew and output pattern effects, and p-channel to n-chan nel variation of the output drivers for any given

cycle.

22. tDAL = (tWR/tCK) + (tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer.

Example: For DDR266B at CL=2.5 and tCK=7.5 ns

tDAL = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks

= ((2) + (3)) clocks

= 5 clocks

23. In all circumstances, tXSNR can be satisfied using

tXSNR = tRFCmin + 1*tCK

24. The only time that the clock frequency is allowed to change is du ring self-refresh mode.

25. If refr esh timin g or tDS/tDH is viol ated, dat a cor ruptio n may occ ur and the data mu st be r e- writ ten with v a lid data bef o re a valid

READ can be executed.

Rev. 1.0 / June 2007 13

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200pin DDR SDRAM SO-DIMMs

SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS

The following tables are described specification parameters that required in systems using DDR devices to ensure

proper performannce. These characteristics are for system simulation purposes and are guaranteed by design.

Input Slew Rate for DQ/DM/DQS (Table a.)

Address & Control Input Setup & Hold Time Derating (Table b.)

DQ & DM Input Setup & Hold Time Derating (Table c.)

DQ & DM Input Setup & Hold Time Derating for Rise/Fall Delta Slew Rate (Table d.)

Output Slew Rate Characteristics (for x4, x8 Devices) (Table e.)

Output Slew Rate Characteristics (for x16 Device) (Table f.)

Output Slew Rate Matching Ratio Characteristics (Table g.)

AC CHARACTERISTICS DDR400 DDR333 DDR266 DDR200 UNIT Note

PARAMETER Symbol min max min max min max min max

DQ/DM/DQS input slew rate

measured between VIH(DC),

VIL(DC) and VIL(DC), VIH(DC) DCSLEW 0.5 4.0 0.5 4.0 0.5 4.0 0.5 4.0 V/ns 1,12

Input Slew Rate Delta tIS Delta tIH UNIT Note

0.5 V/ns 0 0 ps 9

0.4 V/ns +50 0 ps 9

0.3 V/ns +100 0 ps 9

Input Slew Rate Delta tDS Delta tDH UNIT Note

0.5 V/ns 0 0 ps 11

0.4 V/ns +75 0 ps 11

0.3 V/ns +150 0 ps 11

Input Slew Rate Delta tDS Delta tDH UNIT Note

±0.0 ns/V 00ps10

±0.25 ns/V +50 +50 ps 10

±0.5 ns/V +100 +100 ps 10

Slew Rate Characteristic Typical Range (V/

ns) Minimum (V/ns) Maximum (V/ns) Note

Pullup Slew Rate 1.2 - 2.5 1.0 4.5 1,3,4,6,7,8

Pulldown Slew Rate 1.2 - 2.5 1.0 4.5 2,3,4,6,7,8

Slew Rate Characteristic Typical Range (V/

ns) Minimum (V/ns) Maximum (V/ns) Note

Pullup Slew Rate 1.2 - 2.5 1.0 4.5 1,3,4,6,7,8

Pulldown Slew Rate 1.2 - 2.5 1.0 4.5 2,3,4,6,7,8

Slew Rate Characteristic DDR266A DDR266B DDR200 Note

Parameter min max min max min max

Output Sle w Rate M a tching Ratio

(Pullup to Pulldown) - - - - 0.71 1.4 5,12

Rev. 1.0 / June 2007 14

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200pin DDR SDRAM SO-DIMMs

Notes:

1. Pullup slew rate is characterized under the te st conditions as shown in bel ow Figure.

2. Pulldown slew rate is measured under the test conditions shown in below Figure.

3. Pullup slew rate is measured between (VDDQ/2 - 320 mV ±250mV)

Pulldown slew rate is measured between (VDDQ/2 + 320mV ±250mV)

Pullup and Pu lldown slew r ate con ditions are to be met fo r any pat tern of d ata, includi ng all outp uts switch ing and on ly one output

switching.

Example: For typical slew, DQ0 is switching

For minimum slew rate, all DQ bits are switching worst case pattern

For maximum slew rate, only one DQ is switching from either high to low, or low to high.

The re maining DQ bits remain the same as for previous state.

4. Evaluation conditions

Typical: 25 oC (Ambient), VDDQ = nominal, typical process

Minimum: 70 oC (Ambient), VDDQ = minimum, slow-slow process

Maximum: 0 oC (Ambient), VDDQ = Maximum, fast-fast process

5. The ratio of pullup sl ew r a te to pulldown slew r ate is specified for the same temperature and voltage, o v er the entir e temperature

and voltage range. F or a giv en output, it r epresents th e maximum differ ence between pullup and pulldown drivers due to process

variation.

6. Verified under typical conditions for qualification purposes.

7. TSOP-II package devices only.

8. Only intended for operation up to 256 Mbps per pin.

9. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns as shown in Table b.

The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), sim-

ilarly for rising transitions.

10. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables c

& d. Input sl ew r ate is base d on the larger o f AC -A C delta rise, f all r ate and D C -DC delta rise, f all r ate. Input slew r ate is bas ed on

the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), simil a rly for rising transitions. The

delta rise/fall rate is calculated as:

{1/(Slew Rate1)} - {1/(slew Rate2)}

For example:

If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the del ta rise, fall rate is -0.5 ns/V. Usin g the table given, this would

result in the need for an increase in tDS and tDH of 100ps.

11. Table c is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the

lesser of the AC- AC slew r ate and the DC -DC slew rate. The input slew r ate is based on the lesser of the slew rates determined by

either VIH(ac) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions.

12. DQS, DM, an d D Q input slew rate is specified to prevent double clocking of data a nd preserve setup and ho ld times. Signa l t ran-

sitions through the DC region must be monot onic.

50

Output

(VOUT)

VSSQ

Test Point

Figure: Pullup S lew rate

Ω

VDDQ

50

Test Point

Output

(VOUT)

Figure: Pulldown Slew rate

Ω

Rev. 1.0 / June 2007 15

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200pin DDR SDRAM SO-DIMMs

SIMPLIFIED COMMAND TRUTH TABLE

Notes :

1. DM states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering during Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP

period from Precharge command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+tRP).

4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time(tWR) is needed to guarantee that the last data has been

completely written.

5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.

WRITE MASK TRUTH TABLE

Note:

1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data.

In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.

Command CKEn-1 CKEn /CS /RAS /CAS /WE ADDR A10/AP BA Note

Extended Mode Register Set H X L L L L OP code 1,2

Mode Register Set H X L L L L OP code 1,2

Device Deselect HX

HXXX X1

No Operation L H H H

Bank Active H X L L H H RA V 1

Read HXLHLHCA

LV1

Read with A u to precharge H1,3

Write HXLHLLCA

LV1

Write with Autoprecharge H1,4

Precharge All Banks HXLLHLX

HX1,5

Precharge selected Bank LV1

Read Burst Stop H X L H H L X 1

Auto Refresh H HLLLH X 1

Self Refresh EntryH L LLLH X1

Exit L H HXXX 1

LHHH

Precharge Power

Down Mode

Entry H L HXXX

X

1

LHHH 1

Exit L H HXXX 1

LHHH 1

Active Power Down

Mode Entry H L HXXX X1

LVVV 1

Exit L H X 1

Function CKEn-1 CKEn /CS, /RAS, /CAS, /WE DM ADDR A10/AP BA Note

Data Write H X X L X 1

Data-In Mask H X X H X 1

( H=Logic High Level, L=Logic Low Level, X=Don’t Care , V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

Rev. 1.0 / June 2007 16

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200pin DDR SDRAM SO-DIMMs

1GB, 128M x 64 Unbuffered SO-DIMM: HYMD512M646D[L]FP8

PACKAGE DIMENSIONS

Front

31.75 mm

20.00 mm

1 39 41 199

2.00 mm

Component

Keepout

Area

2.00 m m

Back Side

67.60 m m 3.8mm

MAX.

1.1mm

MAX.

Millimeters

Inches

Unit :

Rev. 1.0 / June 2007 17

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200pin DDR SDRAM SO-DIMMs

REVISION HIST ORY

Revision History Date Remark

1.0 First Ve rsi on Release June 2007