74F280B
9-bit odd/even parity generator/checker
Product specification
IC15 Data Handbook
1996 Mar 12
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74F280B9-bit odd/even parity generator/checker
2
1996 Mar 12 853-0363 16555
FEATURES
•High-impedance NPN base inputs for reduced loading
(20µA in Low and High states)
•Buffered inputs — one normalized load
•Word length easily expanded by cascading
•Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F280B is a 9-bit Parity Generator or Checker commonly used
to detect errors in high speed data transmission or data retrieval
systems. Both Even (∑E) and Odd (∑O) parity outputs are available
for generating or checking even or odd parity on up to 9 bits.
The Even (∑E) parity output is High when an even number of Data
inputs (I0 - I8) are High. The Odd (∑O) parity output is High when an
odd number of Data inputs are High.
Expansion to larger word sizes is accomplished by tying the Even
(∑E) outputs of up to nine parallel devices to the data inputs of the
final stage. This expansion scheme allows an 81-bit data word to be
checked in less than 20ns.
PIN CONFIGURATION
14
13
12
11
10
9
87
6
5
4
3
2
1VCC
I5
I4
I3
I2
I1
I0
I6
I7
I8
ΣE
GND
NC
ΣO
SF00849
TYPE TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F280B 5.5ns 26mA
ORDERING INFORMATION
DESCRIPTION COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
INDUSTRIAL RANGE
VCC = 5V ±10%,
Tamb = –40°C to +85°CPKG. DWG. #
14-pin plastic DIP N74F280BN I74F280BN SOT27-1
14-pin plastic SO N74F280BD I74F280BD SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74F(U.L.)
HIGH/LOW LOAD VALUE
HIGH/LOW
I0 - I8Data inputs 1.0/0.033 20µA/20µA
∑E, ∑OParity outputs 50/33 1.0mA/20mA
NOTE:
One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
8 9 10 11 12 13 1 2 4
56
ΣO
ΣE
I0I1I2I3I4I5I6I7I8
SF00845
IEC/IEEE SYMBOL
8
9
10
11
12
13
1
2
4
5
6
ΣO
ΣE
VCC=Pin 14
GND=Pin 7
2K
SF00846
Philips Semiconductors Product specification
74F280B9-bit odd/even parity generator/checker
1996 Mar 12 3
LOGIC DIAGRAM
ΣE
ΣO
5
6
8
9
10
11
12
13
1
2
4
I0
I1
I2
I3
I4
I5
I6
I7
I8
SF00847
VCC=Pin 14
GND=Pin 7
FUNCTION TABLE
INPUTS OUTPUTS
Number of High Data Inputs (I0 - I8)∑E∑O
Even — 0, 2, 4, 6, 8 H L
Odd — 1, 3, 5, 7, 9 L H
H = High voltage level
L = Low voltage level
Philips Semiconductors Product specification
74F280B9-bit odd/even parity generator/checker
1996 Mar 12 4
ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMETER RATING UNIT
VCC Supply voltage –0.5 to +7.0 V
VIN Input voltage –0.5 to +7.0 V
IIN Input current –30 to +5 mA
VOUT Voltage applied to output in High output state –0.5 to VCC V
IOUT Current applied to output in Low output state 40 mA
T
O
p
erating free air tem
p
erature range
Commercial range 0 to +70 °C
T
amb
Operating
free
-
air
temperat
u
re
range
Industrial range –40 to +85 °C
Tstg Storage temperature –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
Min Nom Max
UNIT
VCC Supply voltage 4.5 5.0 5.5 V
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
IIK Input clamp current –18 mA
IOH High-level output current –1 mA
IOL Low-level output current 20 mA
T
O
p
erating free air tem
p
erature range
Commercial range 0 70 °C
T
amb
Operating
free
-
air
temperat
u
re
range
Industrial range –40 85 °C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITIONS1
MIN TYP2MAX
UNIT
VO
High level out
p
ut voltage
VCC = MIN, VIL = MAX ±10%VCC 2.5
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
VIH = MIN, IOH = MAX ±5%VCC 2.7 3.4
V
VO
Low level out
p
ut voltage
VCC = MIN, VIL = MAX ±10%VCC 0.35 0.50
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
VIH = MIN, IOL = MAX ±5%VCC 0.35 0.50
V
VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V
IIInput current at maximum input voltage VCC = 0.0V, VI = 7.0V 100 µA
I
High level in
p
ut current
Commercial range
VCC = MAX V =27V
20 µA
I
IH
High
-
le
v
el
inp
u
t
c
u
rrent
Industrial range
V
CC =
MAX
,
V
I =
2
.
7V
40 µA
IIL Low-level input current VCC = MAX, VI = 0.5V –20 µA
IOS Short-circuit output current3VCC = MAX –60 –150 mA
ICC Supply current (total) VCC = MAX 26 35 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
Philips Semiconductors Product specification
74F280B9-bit odd/even parity generator/checker
1996 Mar 12 5
AC ELECTRICAL CHARACTERISTICS
LIMITS
TEST
Tamb= +25°C
V=+5V
Tamb = 0°C to +70°C
V=+5V±10%
Tamb = -4 0°C to +85°C
V=+5V±10%
SYMBOL PARAMETER
TEST
CONDITIONS
V
CC = +
5
.
V
C
L
= 50
p
F
,
V
CC = +
5
.
V
±
10%
C
L
= 50
p
F
,
V
CC = +
5
.
V
±
10%
C
L
= 50
p
F
,
UNIT
CONDITIONS
CL
=
50pF,
RL = 500Ω
CL
=
50pF,
RL = 500Ω
CL
=
50pF,
RL = 500Ω
Min Typ Max Min Max Min Max
tPLH
tPHL Propagation delay
I0 - I8 to ΣE
74F280B
W aveform 1, 2 4.0
4.0 6.5
7.0 9.0
10.0 3.5
3.5 10.0
11.1 3.0
3.5 11.0
12.0 ns
ns
tPLH
tPHL Propagation delay
I0 - I8 to ΣO
74F280B
W aveform 1, 2 4.0
4.0 6.5
7.0 9.0
10.0 3.5
3.5 10.0
11.0 3.0
3.5 11.0
12.0 ns
ns
AC WAVEFORMS
For all waveforms, VM=1.5V.
VM
VMVM
VM
I0 - I8
ΣE, ΣO
tPHL tPLH
SF00848
W aveform 1. Propagation Delay for Inverting Outputs
VM
VMVM
VM
I0 - I8
ΣE, ΣO
tPLH tPHL
SF00850
W aveform 2. Propagation Delay for Non-Inverting Outputs
TEST CIRCUIT AND WAVEFORM
tw90%
VM
10%
90%
VM10%
90%
VM10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf )
INPUT PULSE REQUIREMENTS
rep. rate twtTLH tTHL
1MHz 500ns 2.5ns 2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN VOUT
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
RL= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
CL= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
RT= Termination resistance should be equal to ZOUT of
pulse generators.
tTHL (tf )
tTLH (tr )
tTLH (tr )AMP (V)
amplitude
3.0V 1.5V
VM
SF00006
Philips Semiconductors Product specification
74F280B
9-bit parity odd/even parity generator/checker
1996 Mar 12 6
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
Philips Semiconductors Product specification
74F280B
9-bit parity odd/even parity generator/checker
1996 Mar 12 7
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
Philips Semiconductors Product specification
74F280B
9-bit parity odd/even parity generator/checker
1996 Mar 12 8
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Date of release: 12-99
Document order number: 9397 750 06706
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
