Freescale Semiconductor MPC8347EAEC Rev. 2, 8/2006 Technical Data MPC8347EA PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications The MPC8347EA contains a PowerPCTM processor core (built on Power ArchitectureTM technology) with system logic for networking, storage, and general-purpose embedded applications. For functional characteristics of the processor, refer to the MPC8349EA PowerQUICCTM II Pro Integrated Host Processor Reference Manual, Rev. 0. To locate published errata or updates for this document, contact your Freescale sales office. NOTE The information in this document is accurate for revision 3.0 silicon and later. For information on revision 1.1 silicon and earlier versions, see the MPC8347E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications. See Section 23.1, "Part Numbers Fully Addressed by this Document," for silicon revision level determination. (c) Freescale Semiconductor, Inc., 2006. All rights reserved. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 17. 18. 19. 20. 21. 22. 23. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 14 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 19 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ethernet: Three-Speed Ethernet, MII Management . 29 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 70 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 System Design Information . . . . . . . . . . . . . . . . . . 111 Document Revision History . . . . . . . . . . . . . . . . . . 117 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 117 Overview 1 Overview This section provides a high-level overview of the MPC8347EA features. Figure 1 shows the major functional units within the MPC8347EA. Security DUART Dual I2C Timers GPIO High-Speed USB 2.0 Dual Role e300 Core Interrupt Controller 10/100/1000 Ethernet 32KB D-Cache 10/100/1000 Ethernet 32KB I-Cache Local Bus PCI SEQ DDR SDRAM Controller DMA Host Figure 1. MPC8347EA Block Diagram Major features of the MPC8347EA are as follows: * Embedded PowerPC e300 processor core; operates at up to 667 MHz -- High-performance, superscalar processor core -- Floating-point, integer, load/store, system register, and branch processing units -- 32-Kbyte instruction cache, 32-Kbyte data cache -- Lockable portion of L1 cache -- Dynamic power management -- Software-compatible with the other Freescale processor families that implement the PowerPC architecture * Double data rate, DDR1/DDR2 SDRAM memory controller -- Programmable timing supporting DDR1 and DDR2 SDRAM -- 32- or 64-bit data interface, up to 400 MHz data rate -- Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable -- DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports -- Full error checking and correction (ECC) support -- Support for up to 16 simultaneous open pages (up to 32 pages for DDR2) -- Contiguous or discontiguous memory mapping -- Read-modify-write support -- Sleep-mode support for SDRAM self refresh -- Auto refresh MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor Overview * * * -- On-the-fly power management using CKE -- Registered DIMM support -- 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2 Dual three-speed (10/100/1000) Ethernet controllers (TSECs) -- Dual controllers designed to comply with IEEE Std. 802.3TM, 802.3u, 820.3x, 802.3z, 802.3ac -- Ethernet physical interfaces: - 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex - 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex -- Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100 programming models -- 9.6-Kbyte jumbo frame support -- RMON statistics support -- Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module -- MII management interface for control and status -- Programmable CRC generation and checking PCI interface -- Designed to comply with PCI specification revision 2.3 -- Data bus width: - 32-bit data PCI interface operating at up to 66 MHz -- PCI 3.3-V compatible -- PCI host bridge capabilities -- PCI agent mode on PCI interface -- PCI-to-memory and memory-to-PCI streaming -- Memory prefetching of PCI read accesses and support for delayed read transactions -- Posting of processor-to-PCI and PCI-to-memory writes -- On-chip arbitration supporting five masters on PCI -- Accesses to all PCI address spaces -- Parity supported -- Selectable hardware-enforced coherency -- Address translation units for address mapping between host and peripheral -- Dual address cycle for target -- Internal configuration registers accessible from PCI Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std. 802.11iTM, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs): -- Public key execution unit (PKEU) : - RSA and Diffie-Hellman algorithms - Programmable field size up to 2048 bits MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 3 Overview * * - Elliptic curve cryptography - F2m and F(p) modes - Programmable field size up to 511 bits -- Data encryption standard (DES) execution unit (DEU) - DES and 3DES algorithms - Two key (K1, K2) or three key (K1, K2, K3) for 3DES - ECB and CBC modes for both DES and 3DES -- Advanced encryption standard unit (AESU) - Implements the Rijndael symmetric-key cipher - Key lengths of 128, 192, and 256 bits - ECB, CBC, CCM, and counter (CTR) modes -- XOR parity generation accelerator for RAID applications -- ARC four execution unit (AFEU) - Stream cipher compatible with the RC4 algorithm - 40- to 128-bit programmable key -- Message digest execution unit (MDEU) - SHA with 160-, 224-, or 256-bit message digest - MD5 with 128-bit message digest - HMAC with either algorithm -- Random number generator (RNG) -- Four crypto-channels, each supporting multi-command descriptor chains - Static and/or dynamic assignment of crypto-execution units through an integrated controller - Buffer size of 256 bytes for each execution unit, with flow control for large data sizes Universal serial bus (USB) dual role controller -- USB on-the-go mode with both device and host functionality -- Complies with USB specification Rev. 2.0 -- Can operate as a stand-alone USB device - One upstream facing port - Six programmable USB endpoints -- Can operate as a stand-alone USB host controller - USB root hub with one downstream-facing port - Enhanced host controller interface (EHCI) compatible - High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations -- External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI) Universal serial bus (USB) multi-port host controller -- Can operate as a stand-alone USB host controller - USB root hub with one or two downstream-facing ports MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 4 Freescale Semiconductor Overview * * * * - Enhanced host controller interface (EHCI) compatible - Complies with USB specification Rev. 2.0 -- High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations -- Direct connection to a high-speed device without an external hub -- External PHY with serial and low-pin count (ULPI) interfaces Local bus controller (LBC) -- Multiplexed 32-bit address and data operating at up to 133 MHz -- Eight chip selects for eight external slaves -- Up to eight-beat burst transfers -- 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller -- Three protocol engines on a per chip select basis: - General-purpose chip select machine (GPCM) - Three user-programmable machines (UPMs) - Dedicated single data rate SDRAM controller -- Parity support -- Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit) Programmable interrupt controller (PIC) -- Functional and programming compatibility with the MPC8260 interrupt controller -- Support for 8 external and 35 internal discrete interrupt sources -- Support for 1 external (optional) and 7 internal machine checkstop interrupt sources -- Programmable highest priority request -- Four groups of interrupts with programmable priority -- External and internal interrupts directed to host processor -- Redirects interrupts to external INTA pin in core disable mode. -- Unique vector number for each interrupt source Dual industry-standard I2C interfaces -- Two-wire interface -- Multiple master support -- Master or slave I2C mode support -- On-chip digital filtering rejects spikes on the bus -- System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware DMA controller -- Four independent virtual channels -- Concurrent execution across multiple channels with programmable bandwidth control -- Handshaking (external control) signals for all channels: DMA_DREQ[0:3], DMA_DACK[0:3], DMA_DDONE[0:3] -- All channels accessible to local core and remote PCI masters MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 5 Overview * * * * * * -- Misaligned transfer capability -- Data chaining and direct mode -- Interrupt on completed segment and chain DUART -- Two 4-wire interfaces (RxD, TxD, RTS, CTS) -- Programming model compatible with the original 16450 UART and the PC16550D Serial peripheral interface (SPI) for master or slave General-purpose parallel I/O (GPIO) -- 52 parallel I/O pins multiplexed on various chip interfaces System timers -- Periodic interrupt timer -- Real-time clock -- Software watchdog timer -- Eight general-purpose timers Designed to comply with IEEE Std. 1149.1TM, JTAG boundary scan Integrated PCI bus and SDRAM clock generation MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 6 Freescale Semiconductor Electrical Characteristics 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal charaistics for the MPC8347EA. The MPC8347EA is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings 1 Characteristic Symbol Max Value Unit Core supply voltage VDD -0.3 to 1.32 V PLL supply voltage AVDD -0.3 to 1.32 V DDR and DDR2 DRAM I/O voltage GVDD -0.3 to 2.75 -0.3 to 1.98 V Three-speed Ethernet I/O, MII management voltage LVDD -0.3 to 3.63 V PCI, local bus, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD -0.3 to 3.63 V Input voltage MVIN -0.3 to (GVDD + 0.3) V 2, 5 MVREF -0.3 to (GVDD + 0.3) V 2, 5 Three-speed Ethernet signals LVIN -0.3 to (LVDD + 0.3) V 4, 5 Local bus, DUART, CLKIN, system control and power management, I2C, and JTAG signals OVIN -0.3 to (OVDD + 0.3) V 3, 5 PCI OVIN -0.3 to (OVDD + 0.3) V 6 TSTG -55 to 150 *C DDR DRAM signals DDR DRAM reference Storage temperature range Notes Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 6. OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 3. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 7 Electrical Characteristics 2.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8347EA. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. Table 2. Recommended Operating Conditions Symbol Recommended Value Unit Notes Core supply voltage VDD 1.2 V 60 mV V 1 PLL supply voltage AVDD 1.2 V 60 mV V 1 DDR and DDR2 DRAM I/O voltage GVDD 2.5 V 125 mV 1.8 V 90 mV V Three-speed Ethernet I/O supply voltage LVDD1 3.3 V 330 mV 2.5 V 125 mV V Three-speed Ethernet I/O supply voltage LVDD2 3.3 V 330 mV 2.5 V 125 mV V PCI, local bus, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD 3.3 V 330 mV V Characteristic Notes: 1. GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction--either in the positive or negative direction. Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8347EA. G/L/OVDD + 20% G/L/OVDD + 5% VIH G/L/OVDD GND GND - 0.3 V VIL GND - 0.7 V Not to Exceed 10% of tinterface1 Note: 1. tinterface refers to the clock period associated with the bus clock interface. Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 8 Freescale Semiconductor Electrical Characteristics Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8347EA for the 3.3-V signals, respectively. 11 ns (Min) +7.1 V 7.1 V p-to-p (Min) Overvoltage Waveform 0V 4 ns (Max) 4 ns (Max) 62.5 ns +3.6 V 7.1 V p-to-p (Min) Undervoltage Waveform -3.5 V Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling 2.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 3. Output Drive Capability Output Impedance () Supply Voltage Local bus interface utilities signals 42 OVDD = 3.3 V PCI signals (not including PCI output clocks) 25 PCI output clocks (including PCI_SYNC_OUT) 42 DDR signal 20 GVDD = 2.5 V DDR2 signal 16 32 (half strength mode) GVDD = 1.8 V TSEC/10/100 signals 42 LVDD = 2.5/3.3 V DUART, system control, I2C, JTAG 42 OVDD = 3.3 V GPIO signals 42 OVDD = 3.3 V, LVDD = 2.5/3.3 V Driver Type MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 9 Electrical Characteristics 2.2 Power Sequencing MPC8347EA does not require the core supply voltage and I/O supply voltages to be applied in any particular order. Note that during the power ramp up, before the power supplies are stable, there may be a period of time that I/O pins are actively driven. After the power is stable, as long as PORESET is asserted, most I/O pins are tri-stated. To minimize the time that I/O pins are actively driven, it is recommended to apply core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 10 Freescale Semiconductor Electrical Characteristics MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 11 Power Characteristics 3 Power Characteristics The estimated typical power dissipation for the MPC8347EA device is shown in Table 4. Table 4. MPC8347EA Power Dissipation 1 Core Frequency (MHz) CSB Frequency (MHz) Typical at TJ = 65 Typical 2, 3 Maximum 4 Unit 266 266 1.3 1.6 1.8 W 133 1.1 1.4 1.6 W 266 1.5 1.9 2.1 W 133 1.4 1.7 1.9 W 200 1.5 1.8 2.0 W 100 1.3 1.7 1.9 W 333 2.0 3.0 3.2 W 166 1.8 2.8 2.9 W 266 2.1 3.0 3.3 W 133 1.9 2.9 3.1 W 300 2.3 3.2 3.5 W 150 2.1 3.0 3.2 W 333 2.4 3.3 3.6 W 166 2.2 3.1 3.4 W 266 2.4 3.3 3.6 W 133 2.2 3.1 3.4 W 333 3.5 4.6 5 W 400 PBGA 400 333 400 450 TBGA 500 533 667 1 The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 5. Typical power is based on a voltage of Vdd = 1.2 V, a junction temperature of TJ = 105C, and a Dhrystone benchmark application. 3 Thermal solutions may need to design to a value higher than typical power based on the end application, T target, and I/O A power. 4 Maximum Power is based on a voltage of Vdd = 1.2 V, worst case process, a junction temperature of T = 105C, and an J artificial smoke test. 2 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 12 Freescale Semiconductor Power Characteristics Table 5 shows the estimated typical I/O power dissipation for MPC8347EA. Table 5. MPC8347EA Typical I/O Power Dissipation Interface DDR I/O 65% utilization 2.5 V Rs = 20 Rt = 50 2 pair of clocks Parameter GVDD (1.8v) GVDD (2.5 V) OVDD (3.3 V) LVDD (3.3 V) LVDD (2.5 V) Unit 200 MHz, 32 bits 0.42 W 200 MHz, 64 bits 0.55 W 266 MHz, 32 bits 0.5 W 266 MHz, 64 bits 0.66 W 300 MHz , 32 bits 0.54 W 300 MHz1, 64 bits 0.7 W 333 MHz1, 32 bits 0.58 W 333 MHz1, 64 bits 0.76 W 1 400MHz1, Comments 32b 400MHz1, 64b 33 MHz, 32 bits 0.04 W 66 MHz, 32 bits 0.07 W 167 Mhz, 32 bits 0.34 W 133 MHz, 32 bits 0.27 W 83 MHz, 32 bits 0.17 W 66 MHz, 32 bits 0.14 W 50 Mhz, 32 bits 0.11 W PCI I/O load = 30 pf Local Bus I/O Load = 25 pf TSEC I/O Load = 25 pf MII 0.01 W GMII or TBI 0.06 W RGMII or RTBI 0.04 W 12 MHz 0.01 W 480 MHz 0.2 W 0.01 W USB Other I/O 1 Multiply by number of interfaces used. Multiply by 2 if using 2 ports. MPC8347EA supports frequencies above 266 MHz only in the TBGA package. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 13 Clock Input Timing 4 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8347EA. 4.1 DC Electrical Characteristics Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8347EA. Table 6. CLKIN DC Electrical Characteristics Parameter Condition Symbol Min Max Unit Input high voltage -- VIH 2.7 OVDD+0.3 V Input low voltage -- VIL -0.3 0.4 V 0V VIN OVDD IIN -- 10 A PCI_SYNC_IN Input current 0V VIN 0.5 V or OVDD - 0.5 V VIN OVDD IIN -- 10 A PCI_SYNC_IN Input current 0.5 V VIN OVDD - 0.5 V IIN -- 50 A CLKIN Input current 4.2 AC Electrical Characteristics The primary clock source for the MPC8347EA can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input (CLKIN/PCI_CLK) AC timing specifications for the MPC8347EA. Table 7. CLKIN AC Timing Specifications Parameter/Condition Symbol Min Typical Max Unit Notes CLKIN/PCI_CLK frequency fCLKIN -- -- 66 MHz 1 CLKIN/PCI_CLK cycle time tCLKIN 15 -- -- ns -- CLKIN/PCI_CLK rise and fall time tKH, tKL 0.6 1.0 2.3 ns 2 tKHK/tCLKIN 40 -- 60 % 3 -- -- -- +/- 150 ps 4, 5 CLKIN/PCI_CLK duty cycle CLKIN/PCI_CLK jitter Notes: 1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating frequencies. 2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter--short term and long term--and is guaranteed by design. 5. The CLKIN/PCI_CLK driver's closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 14 Freescale Semiconductor Clock Input Timing MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 15 RESET Initialization 5 RESET Initialization This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8347EA. 5.1 RESET DC Electrical Characteristics Table 8 provides the DC electrical characteristics for the RESET pins of the MPC8347EA. Table 8. RESET Pins DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Input high voltage VIH 2.0 OVDD+0.3 V Input low voltage VIL -0.3 0.8 V Input current IIN 5 A Output high voltage VOH IOH = -8.0 mA 2.4 -- V Output low voltage VOL IOL = 8.0 mA -- 0.5 V Output low voltage VOL IOL = 3.2 mA -- 0.4 V Notes: 1. This table applies for pins PORESET, HRESET, SRESET and QUIESCE. 2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins. 5.2 RESET AC Electrical Characteristics Table 9 provides the reset initialization AC timing specifications of the MPC8347EA. Table 9. RESET Initialization Timing Specifications Parameter/Condition Min Max Unit Notes Required assertion time of HRESET or SRESET (input) to activate reset flow 32 -- tPCI_SYNC_IN 1 Required assertion time of PORESET with stable clock applied to CLKIN when the MPC8347EA is in PCI host mode 32 -- tCLKIN 2 Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN when the MPC8347EA is in PCI agent mode 32 -- tPCI_SYNC_IN 1 HRESET/SRESET assertion (output) 512 -- tPCI_SYNC_IN 1 HRESET negation to SRESET negation (output) 16 -- tPCI_SYNC_IN 1 Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347EA is in PCI host mode 4 -- tCLKIN 2 Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347EA is in PCI agent mode 4 -- tPCI_SYNC_IN 1 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 16 Freescale Semiconductor RESET Initialization Table 9. RESET Initialization Timing Specifications (continued) Input hold time for POR configuration signals with respect to negation of HRESET 0 -- ns Time for the MPC8347EA to turn off POR configuration signals with respect to the assertion of HRESET -- 4 ns 3 Time for the MPC8347EA to turn on POR configuration signals with respect to the negation of HRESET 1 -- tPCI_SYNC_IN 1, 3 Notes: 1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA Integrated Host Processor Reference Manual. 2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA Integrated Host Processor Reference Manual. 3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV. Table 10 lists the PLL and DLL lock times. Table 10. PLL and DLL Lock Times Parameter/Condition Min Max Unit PLL lock times -- 100 s DLL lock times 7680 122,880 csb_clk cycles Notes 1, 2 Notes: 1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, "Clocking." MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 17 RESET Initialization MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 18 Freescale Semiconductor DDR and DDR2 SDRAM 6 DDR and DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8347EA. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V. The AC electrical specifications are the same for DDR and DRR2 SDRAM. NOTE The information in this document is accurate for revision 3.0 silicon and later. For information on revision 1.1 silicon and earlier versions see the MPC8347E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications. See Section 23.1, "Part Numbers Fully Addressed by this Document," for silicon revision level determination. 6.1 DDR and DDR2 SDRAM DC Electrical Characteristics Table 11 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8347EA when GVDD(typ) = 1.8 V. Table 11. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V Parameter/Condition Symbol Min Max Unit Notes I/O supply voltage GVDD 1.71 1.89 V 1 I/O reference voltage MVREF 0.49 x GVDD 0.51 x GVDD V 2 I/O termination voltage VTT MVREF - 0.04 MVREF + 0.04 V 3 Input high voltage VIH MVREF+ 0.125 GVDD + 0.3 V Input low voltage VIL -0.3 MVREF - 0.125 V Output leakage current IOZ -9.9 9.9 A Output high current (VOUT = 1.420 V) IOH -13.4 -- mA Output low current (VOUT = 0.280 V) IOL 13.4 -- mA 4 Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MVREF is expected to equal 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF cannot exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 19 DDR and DDR2 SDRAM Table 12 provides the DDR2 capacitance when GVDD(typ) = 1.8 V. Table 12. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V Parameter/Condition Symbol Min Max Unit Notes Input/output capacitance: DQ, DQS, DQS CIO 6 8 pF 1 Delta input/output capacitance: DQ, DQS, DQS CDIO -- 0.5 pF 1 Note: 1. This parameter is sampled. GVDD = 1.8 V 0.090 V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V. Table 13 provides the recommended operating conditions for the DDR SDRAM component(s) when GVDD(typ) = 2.5 V. Table 13. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V Parameter/Condition Symbol Min Max Unit Notes I/O supply voltage GVDD 2.375 2.625 V 1 I/O reference voltage MVREF 0.49 x GVDD 0.51 x GVDD V 2 I/O termination voltage VTT MVREF - 0.04 MVREF + 0.04 V 3 Input high voltage VIH MVREF + 0.18 GVDD + 0.3 V Input low voltage VIL -0.3 MVREF- 0.18 V Output leakage current IOZ -9.9 -9.9 A Output high current (VOUT = 1.95 V) IOH -15.2 -- mA Output low current (VOUT = 0.35 V) IOL 15.2 -- mA 4 Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MVREF is expected to be equal to 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD. Table 14 provides the DDR capacitance when GVDD (typ)=2.5 V. Table 14. DDR SDRAM Capacitance for GVDD (typ) = 2.5 V Parameter/Condition Symbol Min Max Unit Notes Input/output capacitance: DQ, DQS CIO 6 8 pF 1 Delta input/output capacitance: DQ, DQS CDIO -- 0.5 pF 1 Note: 1. This parameter is sampled. GVDD = 2.5 V 0.125 V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 20 Freescale Semiconductor DDR and DDR2 SDRAM Table 15 provides the current draw characteristics for MVREF. Table 15. Current Draw Characteristics for MVREF Parameter / Condition Current draw for MVREF Symbol Min Max Unit Note IMVREF -- 500 A 1 1. The voltage regulator for MVREF must supply up to 500 A current. 6.2 DDR and DDR2 SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface. 6.2.1 DDR and DDR2 SDRAM Input AC Timing Specifications Table 16 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ)=1.8 V. Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface At recommended operating conditions with GVDD of 1.8 5%. Parameter Symbol Min Max Unit AC input low voltage VIL -- MVREF - 0.25 V AC input high voltage VIH MVREF + 0.25 -- V Notes Table 17 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ)=2.5 V. Table 17. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface At recommended operating conditions with GVDD of 2.5 5%. Parameter Symbol Min Max Unit AC input low voltage VIL -- MVREF - 0.31 V AC input high voltage VIH MVREF + 0.31 -- V Notes MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 21 DDR and DDR2 SDRAM Table 18 provides the input AC timing specifications for the DDR SDRAM interface. Table 18. DDR and DDR2 SDRAM Input AC Timing Specifications At recommended operating conditions with GVDD of (1.8 V or 2.5 V) 5%. Parameter Symbol Controller Skew for MDQS--MDQ/MECC/MDM Min Max tCISKEW Unit Notes ps 1 400 MHz -600 600 2 333 MHz -750 750 3 266 MHz -750 750 3 200 MHz -750 750 3 Note: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget. 2. This specification applies only to the DDR2 interface. 3. This specification applies only to the DDR interface. 6.2.2 DDR and DDR2 SDRAM Output AC Timing Specifications Table 19 shows the DDR and DDR2 output AC timing specifications. Table 19. DDR and DDR2 SDRAM Output AC Timing Specifications At recommended operating conditions with GVDD of (1.8 V or 2.5 V) 5%. Parameter MCK[n] cycle time, (MCK[n]/MCK[n] crossing) ADDR/CMD/MODT output setup with respect to MCK Symbol 1 Min Max Unit Notes tMCK 5 10 ns 2 ns 3 ns 3 ns 3 tDDKHAS 400 MHz 1.95 -- 333 MHz 2.40 -- 266 MHz 3.15 -- 200 MHz 4.20 -- ADDR/CMD/MODT output hold with respect to MCK tDDKHAX 400 MHz 1.95 -- 333 MHz 2.40 -- 266 MHz 3.15 -- 200 MHz 4.20 -- MCS(n) output setup with respect to MCK tDDKHCS 400 MHz 1.95 -- 333 MHz 2.40 -- 266 MHz 3.15 -- 200 MHz 4.20 -- MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 22 Freescale Semiconductor DDR and DDR2 SDRAM Table 19. DDR and DDR2 SDRAM Output AC Timing Specifications (continued) At recommended operating conditions with GVDD of (1.8 V or 2.5 V) 5%. Symbol 1 Parameter MCS(n) output hold with respect to MCK Max tDDKHCX 400 MHz 1.95 -- 333 MHz 2.40 -- 266 MHz 3.15 -- 200 MHz 4.20 -- -0.6 0.6 MCK to MDQS Skew tDDKHMH MDQ/MECC/MDM output setup with respect to MDQS tDDKHDS, tDDKLDS 400 MHz 700 -- 333 MHz 900 -- 266 MHz 1100 -- 200 MHz 1200 -- MDQ/MECC/MDM output hold with respect to MDQS MDQS preamble start Min tDDKHDX, tDDKLDX 400 MHz 700 -- 333 MHz 900 -- 266 MHz 1100 -- 200 MHz 1200 -- -0.5 x tMCK - 0.6 -0.5 x tMCK +0.6 tDDKHMP Unit Notes ns 3 ns 4 ps 5 ps 5 ns 6 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 23 DDR and DDR2 SDRAM Table 19. DDR and DDR2 SDRAM Output AC Timing Specifications (continued) At recommended operating conditions with GVDD of (1.8 V or 2.5 V) 5%. Parameter MDQS epilogue end Symbol 1 Min Max Unit Notes tDDKHME -0.6 0.6 ns 6 Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output goes invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are set up (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. 4. tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 registerand is typically set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two parameters are set to the same adjustment value. See the MPC8349EA PowerQUICC II Pro Integrated Processor Reference Manual for the timing modifications enabled by use of these bits. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the symbol conventions described in note 1. Figure 4 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK[n] MCK[n] tMCK tDDKHMHmax) = 0.6 ns MDQS tDDKHMH(min) = -0.6 ns MDQS Figure 4. Timing Diagram for tDDKHMH MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 24 Freescale Semiconductor DDR and DDR2 SDRAM Figure 5 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] tMCK tDDKHAS ,tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD/MODT Write A0 NOOP tDDKHMP tDDKHMH MDQS[n] tDDKHME tDDKHDS tDDKLDS MDQ[x] D0 D1 tDDKLDX tDDKHDX Figure 5. DDR SDRAM Output Timing Diagram Figure 6 provides the AC test load for the DDR bus. Output Z0 = 50 RL = 50 GVDD/2 Figure 6. DDR AC Test Load MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 25 DDR and DDR2 SDRAM MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 26 Freescale Semiconductor DUART 7 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8347EA. 7.1 DUART DC Electrical Characteristics Table 20 provides the DC electrical characteristics for the DUART interface of the MPC8347EA. Table 20. DUART DC Electrical Characteristics Parameter Symbol Min Max Unit High-level input voltage VIH 2 OVDD + 0.3 V Low-level input voltage VIL -0.3 0.8 V Input current (0.8 V VIN 2 V) IIN -- +/- 5 A High-level output voltage, IOH = -100 A VOH OVDD - 0.2 -- V Low-level output voltage, IOL = 100 A VOL -- 0.2 V Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. 7.2 DUART AC Electrical Specifications Table 21 provides the AC timing parameters for the DUART interface of the MPC8347EA. Table 21. DUART AC Timing Specifications Parameter Value Unit Minimum baud rate 256 baud Maximum baud rate > 1,000,000 baud 1 16 -- 2 Oversample rate Notes Notes: 1. Actual attainable baud rate will be limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 27 DUART MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 28 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management 8 Ethernet: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speeds (10/100/1000 Mbps) and MII management. 8.1 Three-Speed Ethernet Controller (TSEC) --GMII/MII/TBI/RGMII/RTBI Electrical Characteristics The electrical characteristics specified here apply to the gigabit media independent interface (GMII), the media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), and reduced ten-bit interface (RTBI) signals except management data input/output (MDIO) and management data clock (MDC). The MII, GMII, and TBI interfaces are defined for 3.3 V, and the RGMII and RTBI interfaces can operate at 3.3 or 2.5 V. The RGMII and RTBI interfaces follow the Hewlett-Packard Reduced Pin-Count Interface for Gigabit Ethernet Physical Layer Device Specification, Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in Section 8.3, "Ethernet Management Interface Electrical Characteristics." 8.1.1 TSEC DC Electrical Characteristics All GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes specified in Table 22 and Table 23. The potential applied to the input of a GMII, MII, TBI, RGMII, or RTBI receiver may exceed the potential of the receiver power supply (that is, a RGMII driver powered from a 3.6 V supply driving VOH into a RGMII receiver powered from a 2.5-V supply). Tolerance for dissimilar RGMII driver and receiver supply potentials is implicit in these specifications.The RGMII and RTBI signals are based on a 2.5 V CMOS interface voltage as defined by JEDEC EIA/JESD8-5. Table 22. GMII/TBI and MII DC Electrical Characteristics Parameter Symbol Conditions Min Max Unit Supply voltage 3.3 V LVDD 2 -- 2.97 3.63 V Output high voltage VOH IOH = -4.0 mA LVDD = Min 2.40 LVDD + 0.3 V Output low voltage VOL IOL = 4.0 mA LVDD = Min GND 0.50 V Input high voltage VIH -- -- 2.0 LVDD + 0.3 V Input low voltage VIL -- -- -0.3 0.90 V Input high current IIH -- 40 A -600 -- A Input low current IIL VIN 1 = LVDD 1 VIN = GND Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. 2. GMII/MII pins not needed for RGMII or RTBI operation are powered by the OVDD supply. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 29 Ethernet: Three-Speed Ethernet, MII Management Table 23. RGMII/RTBI (When Operating at 2.5 V), DC Electrical Characteristics Parameters Symbol Conditions Min Max Unit Supply voltage 2.5 V LVDD -- 2.37 2.63 V Output high voltage VOH IOH = -1.0 mA LVDD = Min 2.00 LVDD + 0.3 V Output low voltage VOL IOL = 1.0 mA LVDD = Min GND - 0.3 0.40 V Input high voltage VIH -- LVDD = Min 1.7 LVDD + 0.3 V Input low voltage VIL -- LVDD =Min -0.3 0.70 V Input high current IIH VIN 1 = LVDD -- 10 A Input low current IIL VIN 1 = GND -15 -- A Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 30 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management 8.2 GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section. 8.2.1 GMII Timing Specifications This section describes the GMII transmit and receive AC timing specifications. 8.2.1.1 GMII Transmit AC Timing Specifications Table 24 provides the GMII transmit AC timing specifications. Table 24. GMII Transmit AC Timing Specifications At recommended operating conditions with LVDD / OVDD of 3.3 V 10%. Symbol 1 Min Typ Max Unit tGTX -- 8.0 -- ns tGTXH/tGTX 43.75 -- 56.25 % tGTKHDX 0.5 -- 5.0 ns GTX_CLK clock rise time, VIL(min) to VIH(max) tGTXR -- -- 1.0 ns GTX_CLK clock fall time, VIH(max) to VIL(min) tGTXF -- -- 1.0 ns -- 8.0 -- ns 45 -- 55 % Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK125 clock period tG125 GTX_CLK125 reference clock duty cycle measured at LVDD/ 2 2 tG125H/tG125 Notes: 1. The symbols for timing specifications follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This symbol represents the external GTX_CLK125 signal and does not follow the original symbol naming convention. Figure 7 shows the GMII transmit AC timing diagram. tGTXR tGTX GTX_CLK tGTXH tGTXF TXD[7:0] TX_EN TX_ER tGTKHDX Figure 7. GMII Transmit AC Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 31 Ethernet: Three-Speed Ethernet, MII Management 8.2.1.2 GMII Receive AC Timing Specifications Table 25 provides the GMII receive AC timing specifications. Table 25. GMII Receive AC Timing Specifications At recommended operating conditions with LVDD / OVDD of 3.3 V 10%. Symbol 1 Min Typ Max Unit tGRX -- 8.0 -- ns tGRXH/tGRX 40 -- 60 % RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tGRDVKH 2.0 -- -- ns RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tGRDXKH 0.5 -- -- ns RX_CLK clock rise, VIL(min) to VIH(max) tGRXR -- -- 1.0 ns RX_CLK clock fall time, VIH(max) to VIL(min) tGRXF -- -- 1.0 ns Parameter/Condition RX_CLK clock period RX_CLK duty cycle Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 8 shows the GMII receive AC timing diagram. G tGRXR tGRX RX_CLK tGRXH tGRXF RXD[7:0] RX_DV RX_ER tGRDXKH tGRDVKH Figure 8. GMII Receive AC Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 32 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management 8.2.2 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 8.2.2.1 MII Transmit AC Timing Specifications Table 26 provides the MII transmit AC timing specifications. Table 26. MII Transmit AC Timing Specifications At recommended operating conditions with LVDD / OVDD of 3.3 V 10%. Symbol 1 Min Typ Max Unit TX_CLK clock period 10 Mbps tMTX -- 400 -- ns TX_CLK clock period 100 Mbps tMTX -- 40 -- ns tMTXH/tMTX 35 -- 65 % tMTKHDX 1 5 15 ns TX_CLK data clock rise VIL(min) to VIH(max) tMTXR 1.0 -- 4.0 ns TX_CLK data clock fall VIH(max) to VIL(min) tMTXF 1.0 -- 4.0 ns Parameter/Condition TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 9 shows the MII transmit AC timing diagram. tMTXR tMTX TX_CLK tMTXH tMTXF TXD[3:0] TX_EN TX_ER tMTKHDX Figure 9. MII Transmit AC Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 33 Ethernet: Three-Speed Ethernet, MII Management 8.2.2.2 MII Receive AC Timing Specifications Table 27 provides the MII receive AC timing specifications. Table 27. MII Receive AC Timing Specifications At recommended operating conditions with LVDD / OVDD of 3.3 V 10%. Symbol 1 Min Typ Max Unit RX_CLK clock period 10 Mbps tMRX -- 400 -- ns RX_CLK clock period 100 Mbps tMRX -- 40 -- ns tMRXH/tMRX 35 -- 65 % RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 -- -- ns RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 -- -- ns RX_CLK clock rise VIL(min) to VIH(max) tMRXR 1.0 -- 4.0 ns RX_CLK clock fall time VIH(max) to VIL(min) tMRXF 1.0 -- 4.0 ns Parameter/Condition RX_CLK duty cycle Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular functionl. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 10 provides the AC test load for TSEC. Z0 = 50 Output RL = 50 LVDD/2 Figure 10. TSEC AC Test Load Figure 11 shows the MII receive AC timing diagram. tMRXR tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRXF Valid Data tMRDVKH tMRDXKH Figure 11. MII Receive AC Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 34 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management 8.2.3 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. 8.2.3.1 TBI Transmit AC Timing Specifications Table 28 provides the TBI transmit AC timing specifications. Table 28. TBI Transmit AC Timing Specifications At recommended operating conditions with LVDD / OVDD of 3.3 V 10%. Symbol 1 Min Typ Max Unit tTTX -- 8.0 -- ns tTTXH/tTTX 40 -- 60 % tTTKHDX 1.0 -- 5.0 ns GTX_CLK clock rise, VIL(min) to VIH(max) tTTXR -- -- 1.0 ns GTX_CLK clock fall time, VIH(max) to VIL(min) tTTXF -- -- 1.0 ns -- 8.0 -- ns 45 -- 55 ns Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to TBI data TXD[7:0], TX_ER, TX_EN delay GTX_CLK125 reference clock period tG125 GTX_CLK125 reference clock duty cycle 2 tG125H/tG125 Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention Figure 12 shows the TBI transmit AC timing diagram. tTTXR tTTX GTX_CLK tTTXH tTTXF TXD[7:0] TX_EN TX_ER tTTKHDX Figure 12. TBI Transmit AC Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 35 Ethernet: Three-Speed Ethernet, MII Management 8.2.3.2 TBI Receive AC Timing Specifications Table 29 provides the TBI receive AC timing specifications. Table 29. TBI Receive AC Timing Specifications At recommended operating conditions with LVDD / OVDD of 3.3 V 10%. Symbol 1 Parameter/Condition PMA_RX_CLK clock period Min tTRX Typ Max 16.0 Unit ns PMA_RX_CLK skew tSKTRX 7.5 -- 8.5 ns RX_CLK duty cycle tTRXH/tTRX 40 -- 60 % RXD[7:0], RX_DV, RX_ER (RCG[9:0]) setup time to rising PMA_RX_CLK tTRDVKH 2 2.5 -- -- ns RXD[7:0], RX_DV, RX_ER (RCG[9:0]) hold time to rising PMA_RX_CLK tTRDXKH 2 1.5 -- -- ns RX_CLK clock rise time VIL(min) to VIH(max) tTRXR 0.7 -- 2.4 ns RX_CLK clock fall time VIH(max) to VIL(min) tTRXF 0.7 -- 2.4 ns Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript SK followed by the clock that is being skewed (TRX). 2. Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0. Figure 13 shows the TBI receive AC timing diagram. tTRXR tTRX PMA_RX_CLK1 tTRXH tTRXF Even RCG RCG[9:0] Odd RCG tTRDVKH tTRDXKH tSKTRX PMA_RX_CLK0 tTRDXKH tTRXH tTRDVKH Figure 13. TBI Receive AC Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 36 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management 8.2.4 RGMII and RTBI AC Timing Specifications Table 30 presents the RGMII and RTBI AC timing specifications. Table 30. RGMII and RTBI AC Timing Specifications At recommended operating conditions with LVDD of 2.5 V 5%. Symbol 1 Min Typ Max Unit tSKRGT -0.5 -- 0.5 ns tSKRGT 1.0 -- 2.8 ns tRGT 7.2 8.0 8.8 ns tRGTH/tRGT 45 50 55 % tRGTH/tRGT 40 50 60 % Rise time (20%-80%) tRGTR -- -- 0.75 ns Fall time (20%-80%) tRGTF -- -- 0.75 ns 6 -- 8.0 -- ns 47 -- 53 % Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock cycle duration 2 3 Duty cycle for 1000Base-T 4, 5 Duty cycle for 10BASE-T and 100BASE-TX GTX_CLK125 reference clock period GTX_CLK125 reference clock duty cycle 3, 5 tG12 tG125H/tG125 Notes: 1. In general, the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Also, the notation for rise (R) and fall (F) times follows the clock symbol. For symbols representing skews, the subscript is SK followed by the clock being skewed (RGT). 2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. 3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned. 5. Duty cycle reference is LVdd/2. 6. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 37 Ethernet: Three-Speed Ethernet, MII Management Figure 14 shows the RBMII and RTBI AC timing and multiplexing diagrams. tRGT tRGTH GTX_CLK (At Transmitter) tSKRGT TXD[8:5][3:0] TXD[7:4][3:0] TX_CTL TXD[3:0] TXD[8:5] TXD[7:4] TXD[4] TXEN TXD[9] TXERR tSKRGT TX_CLK (At PHY) RXD[8:5][3:0] RXD[7:4][3:0] RXD[8:5] RXD[3:0] RXD[7:4] tSKRGT RX_CTL RXD[4] RXDV RXD[9] RXERR tSKRGT RX_CLK (At PHY) Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 38 Freescale Semiconductor 8.3 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to the MII management interface signals management data input/output (MDIO) and management data clock (MDC). The electrical characteristics for GMII, RGMII, TBI and RTBI are specified in Section 8.1, "Three-Speed Ethernet Controller (TSEC) --GMII/MII/TBI/RGMII/RTBI Electrical Characteristics." 8.3.1 MII Management DC Electrical Characteristics The MDC and MDIO are defined to operate at a supply voltage of 2.5 V or 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 31 and Table 32. Table 31. MII Management DC Electrical Characteristics Powered at 2.5 V Parameter Symbol Conditions Min Max Unit Supply voltage (2.5 V) LVDD -- 2.37 2.63 V Output high voltage VOH IOH = -1.0 mA LVDD = Min 2.00 LVDD + 0.3 V Output low voltage VOL IOL = 1.0 mA LVDD = Min GND - 0.3 0.40 V Input high voltage VIH -- LVDD = Min 1.7 -- V Input low voltage VIL -- LVDD = Min -0.3 0.70 V -- 10 A -15 -- A Input high current IIH Input low current IIL VIN 1 = LVDD VIN = LVDD Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. Table 32. MII Management DC Electrical Characteristics Powered at 3.3 V Parameter Symbol Conditions Min Max Unit Supply voltage (3.3 V) LVDD -- 2.97 3.63 V Output high voltage VOH IOH = -1.0 mA LVDD = Min 2.10 LVDD + 0.3 V Output low voltage VOL IOL = 1.0 mA LVDD = Min GND 0.50 V Input high voltage VIH -- 2.00 -- V Input low voltage VIL -- -- 0.80 V Input high current IIH LVDD = Max VIN 1 = 2.1 V -- 40 A Input low current IIL LVDD = Max VIN = 0.5 V -600 -- A Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 39 8.3.2 MII Management AC Electrical Specifications Table 33 provides the MII management AC timing specifications. Table 33. MII Management AC Timing Specifications At recommended operating conditions with LVDD is 3.3 V 10% or 2.5 V 5% Symbol 1 Min Typ Max Unit Notes MDC frequency fMDC -- 2.5 -- MHz 2 MDC period tMDC -- 400 -- ns MDC clock pulse width high tMDCH 32 -- -- ns MDC to MDIO delay tMDKHDX 10 -- 170 ns MDIO to MDC setup time tMDDVKH 5 -- -- ns MDIO to MDC hold time tMDDXKH 0 -- -- ns MDC rise time tMDCR -- -- 10 ns MDC fall time tMDHF -- -- 10 ns Parameter/Condition 3 Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz). 3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a csb_clk of 333 MHz, the delay is 58 ns). Figure 15 shows the MII management AC timing diagram. tMDCR tMDC MDC tMDCF tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX Figure 15. MII Management Interface Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 40 Freescale Semiconductor MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 41 USB 9 USB This section provides the AC and DC electrical specifications for the USB interface of the MPC8347EA. 9.1 USB DC Electrical Characteristics Table 34 provides the DC electrical characteristics for the USB interface. Table 34. USB DC Electrical Characteristics Parameter Symbol Min Max Unit High-level input voltage VIH 2 OVDD + 0.3 V Low-level input voltage VIL -0.3 0.8 V Input current IIN -- 5 A High-level output voltage, IOH = -100 A VOH OVDD - 0.2 -- V Low-level output voltage, IOL = 100 A VOL -- 0.2 V Note: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. 9.2 USB AC Electrical Specifications Table 35 describes the general timing parameters of the USB interface of the MPC8347EA. Table 35. USB General Timing Parameters Symbol 1 Min Max Unit tUSCK 15 -- ns Input setup to usb clock - all inputs tUSIVKH 4 -- ns input hold to usb clock - all inputs tUSIXKH 1 -- ns usb clock to output valid - all outputs tUSKHOV -- 7 ns Output hold from usb clock - all outputs tUSKHOX 2 -- ns Parameter usb clock cycle time Notes Notes: 1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes usb timing (US) for the input (I) to go invalid (X) with respect to the time the usb clock reference (K) goes high (H). Also, tUSKHOX symbolizes USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to USB clock. 3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 x OVDD of the signal in question for 3.3 V signaling levels. 4. Input timings are measured at the pin. 5. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 42 Freescale Semiconductor USB Figure 16 and Figure 17 provide the AC test load and signals for the USB, respectively. Output Z0 = 50 RL = 50 OVDD/2 Figure 16. USB AC Test Load USB0_CLK/USB1_CLK/DR_CLK tUSIVKH tUSIXKH Input Signals tUSKHOV tUSKHOX Output Signals: Figure 17. USB Signals MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 43 USB MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 44 Freescale Semiconductor Local Bus 10 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8347EA. 10.1 Local Bus DC Electrical Characteristics Table 36 provides the DC electrical characteristics for the local bus interface. Table 36. Local Bus DC Electrical Characteristics Parameter 10.2 Symbol Min Max Unit High-level input voltage VIH 2 OVDD + 0.3 V Low-level input voltage VIL -0.3 0.8 V Input current IIN -- 5 A High-level output voltage, IOH = -100 A VOH OVDD - 0.2 -- V Low-level output voltage, IOL = 100 A VOL -- 0.2 V Local Bus AC Electrical Specification Table 37 and Table 38 describe the general timing parameters of the local bus interface of the MPC8347EA. Table 37. Local Bus General Timing Parameters--DLL on Symbol 1 Min Max Unit Notes tLBK 7.5 -- ns 2 Input setup to local bus clock (except LUPWAIT) tLBIVKH1 1.5 -- ns 3, 4 LUPWAIT input setup to local bus clock tLBIVKH2 2.2 -- ns 3, 4 Input hold from local bus clock (except LUPWAIT) tLBIXKH1 1.0 -- ns 3, 4 LUPWAIT Input hold from local bus clock tLBIXKH2 1.0 -- ns 3, 4 LALE output fall to LAD output transition (LATCH hold time) tLBOTOT1 1.5 -- ns 5 LALE output fall to LAD output transition (LATCH hold time) tLBOTOT2 3 -- ns 6 LALE output fall to LAD output transition (LATCH hold time) tLBOTOT3 2.5 -- ns 7 Local bus clock to LALE rise tLBKHLR -- 4.5 ns Local bus clock to output valid (except LAD/LDP and LALE) tLBKHOV1 -- 4.5 ns Local bus clock to data valid for LAD/LDP tLBKHOV2 -- 4.5 ns 3 Local bus clock to address valid for LAD tLBKHOV3 -- 4.5 ns 3 Output hold from local bus clock (except LAD/LDP and LALE) tLBKHOX1 1 -- ns 3 Output hold from local bus clock for LAD/LDP tLBKHOX2 1 -- ns 3 Parameter Local bus cycle time MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 45 Local Bus Table 37. Local Bus General Timing Parameters--DLL on (continued) Parameter Local bus clock to output high impedance for LAD/LDP Symbol 1 Min Max Unit tLBKHOZ -- 3.8 ns Notes Notes: 1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to the rising edge of LSYNC_IN. 3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN to 0.4 x OVDD of the signal in question for 3.3 V signaling levels. 4. Input timings are measured at the pin. 5.tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins. 6.tLBOTOT2 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins. 7.tLBOTOT3 should be used when RCWH[LALE] is set and when the load on the LALE output pin equals the load on the LAD output pins. 8. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 46 Freescale Semiconductor Local Bus Table 38. Local Bus General Timing Parameters--DLL Bypass Symbol 1 Min Max Unit Notes tLBK 15 -- ns 2 Input setup to local bus clock tLBIVKH 7 -- ns 3, 4 Input hold from local bus clock tLBIXKH 1.0 -- ns 3, 4 LALE output fall to LAD output transition (LATCH hold time) tLBOTOT1 1.5 -- ns 5 LALE output fall to LAD output transition (LATCH hold time) tLBOTOT2 3 -- ns 6 LALE output fall to LAD output transition (LATCH hold time) tLBOTOT3 2.5 -- ns 7 Local bus clock to output valid tLBKHOV -- 3 ns 3 Local bus clock to output high impedance for LAD/LDP tLBKHOZ -- 4 ns Parameter Local bus cycle time Notes: 1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to the falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or the rising edge of LCLK0 (for all other inputs). 3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 x OVDD of the signal in question for 3.3 V signaling levels. 4. Input timings are measured at the pin. 5.tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins. 6.tLBOTOT2 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins.the 7.tLBOTOT3 should be used when RCWH[LALE] is set and when the load on the LALE output pin equals to the load on the LAD output pins. 8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 9. DLL bypass mode is not recommended for use at frequencies above 66 MHz. Figure 18 provides the AC test load for the local bus. Output Z0 = 50 RL = 50 OVDD/2 Figure 18. Local Bus C Test Load MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 47 Local Bus Figure 19 through Figure 24 show the local bus signals. LSYNC_IN tLBIXKH tLBIVKH Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE/ tLBKHOV tLBKHOX tLBKHOV tLBKHOZ tLBKHOX Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV tLBKHOZ tLBKHOX Output (Address) Signal: LAD[0:31] tLBKHLR tLBOTOT LALE Figure 19. Local Bus Signals, Nonspecial Signals Only (DLL Enabled) MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 48 Freescale Semiconductor Local Bus LCLK[n] tLBIVKH Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH tLBIXKH tLBIVKH Input Signal: LGTA tLBIXKH Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE/ tLBKHOV tLBKHOV tLBKHOZ Output Signals: LAD[0:31]/LDP[0:3] tLBOTOT LALE Figure 20. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) LSYNC_IN T1 T3 tLBKHOV1 tLBKHOZ1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBIVKH2 tLBIXKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 tLBIXKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 tLBKHOZ1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled) MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 49 Local Bus LCLK T1 T3 tLBKHOV tLBKHOZ GPCM Mode Output Signals: LCS[0:7]/LWE tLBIVKH tLBIXKH UPM Mode Input Signal: LUPWAIT tLBIVKH Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) tLBKHOV tLBIXKH tLBKHOZ UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode) MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 50 Freescale Semiconductor Local Bus LCLK T1 T2 T3 T4 tLBKHOV tLBKHOZ GPCM Mode Output Signals: LCS[0:7]/LWE tLBIVKH tLBIXKH UPM Mode Input Signal: LUPWAIT tLBIVKH Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) tLBKHOV tLBIXKH tLBKHOZ UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode) MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 51 Local Bus LSYNC_IN T1 T2 T3 T4 tLBKHOV1 tLBKHOZ1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBIVKH2 tLBIXKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 tLBIXKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 tLBKHOZ1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled) MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 52 Freescale Semiconductor JTAG 11 JTAG This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the MPC8347EA 11.1 JTAG DC Electrical Characteristics Table 39 provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the MPC8347EA. Table 39. JTAG interface DC Electrical Characteristics Characteristic 11.2 Symbol Input high voltage VIH Input low voltage VIL Input current IIN Condition Min Max Unit OVDD - 0.3 OVDD + 0.3 -0.3 V 0.8 V 5 A Output high voltage VOH IOH = -8.0 mA 2.4 -- V Output low voltage VOL IOL = 8.0 mA -- 0.5 V Output low voltage VOL IOL = 3.2 mA -- 0.4 V JTAG AC Timing Specifications This section describes the AC electrical specifications for the IEEE Std. 1149.1TM (JTAG) interface of the MPC8347EA. Table 40 provides the JTAG AC timing specifications as defined in Figure 26 through Figure 29. Table 40. JTAG AC Timing Specifications (Independent of CLKIN) 1 At recommended operating conditions (see Table 2). Symbol 2 Min Max Unit JTAG external clock frequency of operation fJTG 0 33.3 MHz JTAG external clock cycle time t JTG 30 -- ns tJTKHKL 15 -- ns tJTGR & tJTGF 0 2 ns tTRST 25 -- ns Boundary-scan data TMS, TDI tJTDVKH tJTIVKH 4 4 -- -- Boundary-scan data TMS, TDI tJTDXKH tJTIXKH 10 10 -- -- Boundary-scan data TDO tJTKLDV tJTKLOV 2 2 11 11 Parameter JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Notes 3 ns 4 ns Input hold times: 4 ns Valid times: 5 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 53 JTAG Table 40. JTAG AC Timing Specifications (Independent of CLKIN) 1 (continued) At recommended operating conditions (see Table 2). Symbol 2 Min Max Boundary-scan data TDO tJTKLDX tJTKLOX 2 2 -- -- JTAG external clock to output high impedance: Boundary-scan data TDO tJTKLDZ tJTKLOZ 2 2 19 9 Parameter Output hold times: Unit Notes ns 5 ns 5, 6 Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 load (see Figure 25). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK. 6. Guaranteed by design and characterization. Figure 25 provides the AC test load for TDO and the boundary-scan outputs of the MPC8347EA. Z0 = 50 Output RL = 50 OVDD/2 Figure 25. AC Test Load for the JTAG Interface Figure 26 provides the JTAG clock input timing diagram. JTAG External Clock VM VM VM tJTGR tJTKHKL tJTG tJTGF VM = Midpoint Voltage (OVDD/2) Figure 26. JTAG Clock Input Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 54 Freescale Semiconductor JTAG Figure 27 provides the TRST timing diagram. TRST VM VM tTRST VM = Midpoint Voltage (OVDD/2) Figure 27. TRST Timing Diagram Figure 28 provides the boundary-scan timing diagram. JTAG External Clock VM VM tJTDVKH tJTDXKH Boundary Data Inputs Input Data Valid tJTKLDV tJTKLDX Boundary Data Outputs Output Data Valid tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OVDD/2) Figure 28. Boundary-Scan Timing Diagram Figure 29 provides the test access port timing diagram. JTAG External Clock VM VM tJTIVKH tJTIXKH Input Data Valid TDI, TMS tJTKLOV tJTKLOX Output Data Valid TDO tJTKLOZ TDO Output Data Valid VM = Midpoint Voltage (OVDD/2) Figure 29. Test Access Port Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 55 JTAG MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 56 Freescale Semiconductor I2 C 12 I2C This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8347EA. 12.1 I2C DC Electrical Characteristics Table 41 provides the DC electrical characteristics for the I2C interface of the MPC8347EA. Table 41. I2C DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V 10%. Parameter Symbol Min Max Unit Notes Input high voltage level VIH 0.7 x OVDD OVDD+ 0.3 V Input low voltage level VIL -0.3 0.3 x OVDD V Low level output voltage VOL 0 0.2 x OVDD V 1 Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10 to 400 pF tI2KLKV 20 + 0.1 x CB 250 ns 2 Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 3 Input current each I/O pin (input voltage is between 0.1 x OVDD and 0.9 x OVDD(max) II -10 10 A 4 Capacitance for each I/O pin CI -- 10 pF Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. CB = capacitance of one bus line in pF. 3. Refer to the MPC8349E Integrated Host Processor Reference Manual for information on the digital filter used. 4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off. 12.2 I2C AC Electrical Specifications Table 42 provides the AC timing parameters for the I2C interface of the MPC8347EA. Note that all values refer to VIH (min) and VIL (max) levels (see Table 41). Table 42. I2C AC Electrical Specifications Symbol 1 Min Max Unit SCL clock frequency fI2C 0 400 kHz Low period of the SCL clock tI2CL 1.3 -- s High period of the SCL clock tI2CH 0.6 -- s Setup time for a repeated START condition tI2SVKH 0.6 -- s Hold time (repeated) START condition (after this period, the first clock pulse is generated) tI2SXKL 0.6 -- s Data setup time tI2DVKH 100 -- ns Data hold time: tI2DXKL -- 02 -- 0.9 3 Parameter CBUS compatible masters I2C bus devices s MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 57 I2 C Table 42. I2C AC Electrical Specifications (continued) Symbol 1 Min Max Unit Rise time of both SDA and SCL signals tI2CR 20 + 0.1 Cb 4 300 ns Fall time of both SDA and SCL signals tI2CF 20 + 0.1 Cb 4 300 ns Set-up time for STOP condition tI2PVKH 0.6 -- s Bus free time between a STOP and START condition tI2KHDX 1.3 -- s Noise margin at the LOW level for each connected device (including hysteresis) VNL 0.1 x OVDD -- V Noise margin at the HIGH level for each connected device (including hysteresis) VNH 0.2 x OVDD -- V Parameter Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) goes invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaches the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. MPC8347EA provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tI2DVKH must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF. Figure 30 provides the AC test load for the I2C. Output Z0 = 50 RL = 50 OVDD/2 Figure 30. I2C AC Test Load Figure 31 shows the AC timing diagram for the I2C bus. SDA tI2CF tI2DVKH tI2CL tI2KHKL tI2SXKL tI2CF tI2CR SCL tI2SXKL S tI2CH tI2DXKL tI2SVKH Sr tI2PVKH P S Figure 31. I2C Bus AC Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 58 Freescale Semiconductor I2 C MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 59 PCI 13 PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8347EA. 13.1 PCI DC Electrical Characteristics Table 43 provides the DC electrical characteristics for the PCI interface of the MPC8347EA. Table 43. PCI DC Electrical Characteristics Parameter Symbol Test Condition Min Max Unit High-level input voltage VIH VOUT VOH (min) or 2 OVDD + 0.3 V Low-level input voltage VIL VOUT VOL (max) -0.3 0.8 V IIN 1 VIN = 0 V or VIN = OVDD -- 5 A High-level output voltage VOH OVDD = min, IOH = -100 A OVDD - 0.2 -- V Low-level output voltage VOL OVDD = min, IOL = 100 A -- 0.2 V Input current Notes: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1. 13.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus of the MPC8347EA. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8347EA is configured as a host or agent device. Table 44 provides the PCI AC timing specifications at 66 MHz. Table 44. PCI AC Timing Specifications at 66 MHz6 Symbol 1 Min Max Unit Notes Clock to output valid tPCKHOV -- 6.0 ns 2 Output hold from Clock tPCKHOX 1 -- ns 2 Clock to output high impedance tPCKHOZ -- 14 ns 2, 3 Input setup to Clock tPCIVKH 3.0 -- ns 2, 4 Input hold from Clock tPCIXKH 0 -- ns 2, 4 Parameter Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. 6. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a description of M66EN. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 60 Freescale Semiconductor PCI Table 45 provides the PCI AC timing specifications at 33 MHz. Table 45. PCI AC Timing Specifications at 33 MHz Symbol 1 Min Max Unit Notes Clock to output valid tPCKHOV -- 11 ns 2 Output hold from Clock tPCKHOX 2 -- ns 2 Clock to output high impedance tPCKHOZ -- 14 ns 2, 3 Input setup to Clock tPCIVKH 3.0 -- ns 2, 4 Input hold from Clock tPCIXKH 0 -- ns 2, 4 Parameter Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. Figure 32 provides the AC test load for PCI. Output Z0 = 50 RL = 50 OVDD/2 Figure 32. PCI AC Test Load Figure 33 shows the PCI input AC timing diagram. CLK tPCIVKH tPCIXKH Input Figure 33. PCI Input AC Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 61 PCI Figure 34 shows the PCI output AC timing diagram. CLK tPCKHOV tPCKHOX Output Delay tPCKHOZ High-Impedance Output Figure 34. PCI Output AC Timing Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 62 Freescale Semiconductor PCI MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 63 Timers 14 Timers This section describes the DC and AC electrical specifications for the timers. 14.1 Timer DC Electrical Characteristics Table 46 provides the DC electrical characteristics for the MPC8347EA timer pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 46. Timer DC Electrical Characteristics Characteristic 14.2 Symbol Condition Min Max Unit Input high voltage VIH 2.0 OVDD+0.3 V Input low voltage VIL -0.3 0.8 V Input current IIN 5 A Output high voltage VOH IOH = -8.0 mA 2.4 -- V Output low voltage VOL IOL = 8.0 mA -- 0.5 V Output low voltage VOL IOL = 3.2 mA -- 0.4 V Timer AC Timing Specifications Table 47 provides the timer input and output AC timing specifications. Table 47. Timers Input AC Timing Specifications 1 Characteristic Timers inputs--minimum pulse width Symbol 2 Min Unit tTIWID 20 ns Notes: 1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN. Timings are measured at the pin. 2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 64 Freescale Semiconductor GPIO 15 GPIO This section describes the DC and AC electrical specifications for the GPIO. 15.1 GPIO DC Electrical Characteristics Table 48 provides the DC electrical characteristics for the MPC8347EA GPIO. Table 48. GPIO DC Electrical Characteristics Characteristic 15.2 Symbol Condition Min Max Unit Input high voltage VIH 2.0 OVDD+0.3 V Input low voltage VIL -0.3 0.8 V Input current IIN 5 A Output high voltage VOH IOH = -8.0 mA 2.4 -- V Output low voltage VOL IOL = 8.0 mA -- 0.5 V Output low voltage VOL IOL = 3.2 mA -- 0.4 V GPIO AC Timing Specifications Table 49 provides the GPIO input and output AC timing specifications. Table 49. GPIO Input AC Timing Specifications 1 Characteristic GPIO inputs--minimum pulse width Symbol 2 Min Unit tPIWID 20 ns Notes: 1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN. Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external synchronous logic. GPIO inputs must be valid for at least tPIWID ns to ensure proper operation. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 65 IPIC 16 IPIC This section describes the DC and AC electrical specifications for the external interrupt pins. 16.1 IPIC DC Electrical Characteristics Table 50 provides the DC electrical characteristics for the external interrupt pins. Table 50. IPIC DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Input high voltage VIH 2.0 OVDD+0.3 V Input low voltage VIL -0.3 0.8 V Input current IIN 5 A Output low voltage VOL IOL = 8.0 mA -- 0.5 V Output low voltage VOL IOL = 3.2 mA -- 0.4 V Notes: 1. This table applies for pins IRQ[0:7], IRQ_OUT and MCP_OUT. 2. IRQ_OUT and MCP_OUT are open-drain pins; thus VOH is not relevant for those pins. 16.2 IPIC AC Timing Specifications Table 51 provides the IPIC input and output AC timing specifications. Table 51. IPIC Input AC Timing Specifications 1 Characteristic IPIC inputs--minimum pulse width Symbol 2 Min Unit tPICWID 20 ns Notes: 1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN. Timings are measured at the pin. 2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external synchronous logic. IPIC inputs must be valid for at least tPICWID ns to ensure proper operation in edge triggered mode. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 66 Freescale Semiconductor SPI 17 SPI This section describes the SPI DC and AC electrical specifications. 17.1 SPI DC Electrical Characteristics Table 52 provides the SPI DC electrical characteristics. Table 52. SPI DC Electrical Characteristics Characteristic 17.2 Symbol Condition Min Max Unit Input high voltage VIH 2.0 OVDD+0.3 V Input low voltage VIL -0.3 0.8 V Input current IIN 5 A Output high voltage VOH IOH = -8.0 mA 2.4 -- V Output low voltage VOL IOL = 8.0 mA -- 0.5 V Output low voltage VOL IOL = 3.2 mA -- 0.4 V SPI AC Timing Specifications Table 53 provides the SPI input and output AC timing specifications. Table 53. SPI AC Timing Specifications 1 Characteristic Symbol 2 Min Max Unit 6 ns SPI outputs valid--Master mode (internal clock) delay tNIKHOV SPI outputs hold--Master mode (internal clock) delay tNIKHOX SPI outputs valid--Slave mode (external clock) delay tNEKHOV SPI outputs hold--Slave mode (external clock) delay tNEKHOX 2 ns SPI inputs--Master mode (internal clock input setup time tNIIVKH 4 ns SPI inputs--Master mode (internal clock input hold time tNIIXKH 0 ns SPI inputs--Slave mode (external clock) input setup time tNEIVKH 4 ns SPI inputs--Slave mode (external clock) input hold time tNEIXKH 2 ns 0.5 ns 8 ns Notes: 1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal. Timings are measured at the pin. 2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 67 SPI Figure 35 provides the AC test load for the SPI. Z0 = 50 Output RL = 50 OVDD/2 Figure 35. SPI AC Test Load Figure 36 through Figure 37 represent the AC timings from Table 53. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 36 shows the SPI timings in slave mode (external clock). SPICLK (input) Input Signals: SPIMOSI (See Note) tNEIVKH tNEIXKH tNEKHOX Output Signals: SPIMISO (See Note) Note: The clock edge is selectable on SPI. Figure 36. SPI AC Timing in Slave Mode (External Clock) Diagram Figure 37 shows the SPI timings in master mode (internal clock). SPICLK (output) Input Signals: SPIMISO (See Note) tNIIVKH Output Signals: SPIMOSI (See Note) tNIIXKH tNIKHOX Note: The clock edge is selectable on SPI. Figure 37. SPI AC Timing in Master Mode (Internal Clock) Diagram MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 68 Freescale Semiconductor SPI MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 69 Package and Pin Listings 18 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8347EA is available in two packages a tape ball grid array (TBGA) and a plastic ball grid array (PBGA). See Section 18.1, "Package Parameters for the MPC8347EA TBGA," and Section 18.2, "Mechanical Dimensions of the MPC8347EA TBGA," and Section 18.3, "Package Parameters for the MPC8347EA PBGA" and Section 18.4, "Mechanical Dimensions of the MPC8347EA PBGA." 18.1 Package Parameters for the MPC8347EA TBGA The package parameters are provided in the following list. The package type is 35 mm x 35 mm, 672 tape ball grid array (TBGA). Package outline 35 mm x 35 mm Interconnects 672 Pitch 1.00 mm Module height (typical) 1.46 mm Solder Balls 62 Sn/36 Pb/2 Ag (ZU package) 95.5 Sn/0.5 Cu/4Ag (VV package) Ball diameter (typical) 0.64 mm MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 70 Freescale Semiconductor Package and Pin Listings 18.2 Mechanical Dimensions of the MPC8347EA TBGA Figure 38 shows the mechanical dimensions and bottom surface nomenclature of the MPC8347EA, 672-TBGA package. Figure 38. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8347EA TBGA NOTES 1. 2. 3. 4. 5. All dimensions are in millimeters. Dimensions and tolerances per ASME Y14.5M-1994. Maximum solder ball diameter measured parallel to datum A. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Parallelism measurement must exclude any effect of mark on top surface of package. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 71 Package and Pin Listings 18.3 Package Parameters for the MPC8347EA PBGA The package parameters are as provided in the following list. The package type is 29 mm x 29 mm, 620 Plastic ball grid array (PBGA). Package outline 29 mm x 29 mm Interconnects 620 Pitch 1.00 mm Module height (maximum) 2.46 mm Module height (typical) 2.23 mm Module height (minimum) 2.00 mm Solder Balls 62 Sn/36 Pb/2 Ag (ZQ package) 95.5 Sn/0.5 Cu/4Ag (VR package) Ball diameter (typical) 0.60 mm MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 72 Freescale Semiconductor Package and Pin Listings 18.4 Mechanical Dimensions of the MPC8347EA PBGA Figure 39 shows the mechanical dimensions and bottom surface nomenclature of theMPC8347EA , 620-PBGA package. Figure 39. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8347EA PBGA MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 73 Package and Pin Listings NOTE 1. 2. 3. 4. All dimensions in millimeters Dimensioning and tolerancing per ASME Y14. 5M-1994 Maximum solder ball diameter measured parallel to datum A Datum A, the seating plane, is determined by the spherical crowns of the solder balls. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 74 Freescale Semiconductor 18.5 Pinout Listings Table 51 provides the pin-out listing for the MPC8347EA, 672 TBGA package. Table 54. MPC8347EA (TBGA) Pinout Listing Signal Package Pin Number Pin Type Power Supply Notes 2 PCI PCI_INTA/IRQ_OUT B34 O OVDD PCI_RESET_OUT C33 O OVDD PCI_AD[31:0] G30, G32, G34, H31, H32, H33, H34, J29, J32, J33, L30, K31, K33, K34, L33, L34, P34, R29, R30, R33, R34, T31, T32, T33, U31, U34, V31, V32, V33, V34, W33, W34 I/O OVDD PCI_C/BE[3:0] J30, M31, P33, T34 I/O OVDD PCI_PAR P32 I/O OVDD PCI_FRAME M32 I/O OVDD 5 PCI_TRDY N29 I/O OVDD 5 PCI_IRDY M34 I/O OVDD 5 PCI_STOP N31 I/O OVDD 5 PCI_DEVSEL N30 I/O OVDD 5 PCI_IDSEL J31 I OVDD PCI_SERR N34 I/O OVDD 5 PCI_PERR N33 I/O OVDD 5 PCI_REQ[0] D32 I/O OVDD PCI_REQ[1]/CPCI1_HS_ES D34 I OVDD PCI_REQ[2:4] E34, F32, G29 I OVDD PCI_GNT0 C34 I/O OVDD PCI_GNT1/CPCI1_HS_LED D33 O OVDD PCI_GNT2/CPCI1_HS_ENUM E33 O OVDD PCI_GNT[3:4] F31, F33 O OVDD M66EN A19 I OVDD I/O GVDD DDR SDRAM Memory Interface MDQ[0:63] D5, A3, C3, D3, C4, B3, C2, D4, D2, E5, G2, H6, E4, F3, G4, G3, H1, J2, L6, M6, H2, K6, L2, M4, N2, P4, R2, T4, P6, P3, R1, T2, AB5, AA3, AD6, AE4, AB4, AC2, AD3, AE6, AE3, AG4, AK5, AK4, AE2, AG6, AK3, AK2, AL2, AL1, AM5, AP5, AM2, AN1, AP4, AN5, AJ7, AN7, AM8, AJ9, AP6, AL7, AL9, AN8 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 75 Table 54. MPC8347EA (TBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply Notes MECC[0:4]/MSRCID[0:4] W4, W3, Y3, AA6, T1 I/O GVDD MECC[5]/MDVAL U1 I/O GVDD MECC[6:7] Y1, Y6 I/O GVDD MDM[0:8] B1, F1, K1, R4, AD4, AJ1, AP3, AP7, Y4 O GVDD MDQS[0:8] B2, F5, J1, P2, AC1, AJ2, AN4, AL8, W2 I/O GVDD MBA[0:1] AD1, AA5 O GVDD MA[0:14] W1, U4, T3, R3, P1, M1, N1, L3, L1, K2, Y2, K3, J3, AP2, AN6 O GVDD MWE AF1 O GVDD MRAS AF4 O GVDD MCAS AG3 O GVDD MCS[0:3] AG2, AG1, AK1, AL4 O GVDD MCKE[0:1] H3, G1 O GVDD MCK[0:5] U2, F4, AM3, V3, F2, AN3 O GVDD MCK[0:5] U3, E3, AN2, V4, E1, AM4 O GVDD MODT[0:3] AH3, AJ5, AH1, AJ4 O GVDD MBA[2] H4 O GVDD MDIC0 AB1 I/O -- 10 MDIC1 AA1 I/O -- 10 3 Local Bus Controller Interface LAD[0:31] AM13, AP13, AL14, AM14, AN14, AP14, AK15, AJ15, AM15, AN15, AP15, AM16, AL16, AN16, AP16, AL17, AM17, AP17, AK17, AP18, AL18, AM18, AN18, AP19, AN19, AM19, AP20, AK19, AN20, AL20, AP21, AN21 I/O OVDD LDP[0]/CKSTOP_OUT AM21 I/O OVDD LDP[1]/CKSTOP_IN AP22 I/O OVDD LDP[2]/LCS[4] AN22 I/O OVDD LDP[3]/LCS[5] AM22 I/O OVDD LA[27:31] AK21, AP23, AN23, AP24, AK22 O OVDD LCS[0:3] AN24, AL23, AP25, AN25 O OVDD LWE[0:3]/LSDDQM[0:3]/ LBS[0:3] AK23, AP26, AL24, AM25 O OVDD LBCTL AN26 O OVDD MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 76 Freescale Semiconductor Table 54. MPC8347EA (TBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply LALE AK24 O OVDD LGPL0/LSDA10/ cfg_reset_source0 AP27 I/O OVDD LGPL1/LSDWE/ cfg_reset_source1 AL25 I/O OVDD LGPL2/ LSDRAS/LOE AJ24 O OVDD LGPL3/LSDCAS/ cfg_reset_source2 AN27 I/O OVDD LGPL4/LGTA/LUPWAIT/LPBSE AP28 I/O OVDD LGPL5/cfg_clkin_div AL26 I/O OVDD LCKE AM27 O OVDD LCLK[0:2] AN28, AK26, AP29 O OVDD LSYNC_OUT AM12 O OVDD LSYNC_IN AJ10 I OVDD Notes General Purpose I/O Timers GPIO1[0]/DMA_DREQ0/ GTM1_TIN1/ GTM2_TIN2 F24 I/O OVDD GPIO1[1]/DMA_DACK0/ GTM1_TGATE1/ GTM2_TGATE2 E24 I/O OVDD GPIO1[2]/DMA_DDONE0/ GTM1_TOUT1 B25 I/O OVDD GPIO1[3]/DMA_DREQ1/ GTM1_TIN2/ GTM2_TIN1 D24 I/O OVDD GPIO1[4]/DMA_DACK1/ GTM1_TGATE2/ GTM2_TGATE1 A25 I/O OVDD GPIO1[5]/DMA_DDONE1/ GTM1_TOUT2/ GTM2_TOUT1 B24 I/O OVDD GPIO1[6]/DMA_DREQ2/ GTM1_TIN3/ GTM2_TIN4 A24 I/O OVDD GPIO1[7]/DMA_DACK2/ GTM1_TGATE3/ GTM2_TGATE4 D23 I/O OVDD MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 77 Table 54. MPC8347EA (TBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply GPIO1[8]/DMA_DDONE2/ GTM1_TOUT3 B23 I/O OVDD GPIO1[9]/DMA_DREQ3/ GTM1_TIN4/ GTM2_TIN3 A23 I/O OVDD GPIO1[10]/DMA_DACK3/ GTM1_TGATE4/ GTM2_TGATE3 F22 I/O OVDD GPIO1[11]/DMA_DDONE3/ GTM1_TOUT4/ GTM2_TOUT3 E22 I/O OVDD MPH1_D0_ENABLEN/DR_D0_ENABLEN A26 I/O OVDD MPH1_D1_SER_TXD/DR_D1_SER_TXD B26 I/O OVDD MPH1_D2_VMO_SE0/DR_D2_VMO_SE0 D25 I/O OVDD MPH1_D3_SPEED/DR_D3_SPEED A27 I/O OVDD MPH1_D4_DP/DR_D4_DP B27 I/O OVDD MPH1_D5_DM/DR_D5_DM C27 I/O OVDD MPH1_D6_SER_RCV/DR_D6_SER_RCV D26 I/O OVDD MPH1_D7_DRVVBUS/DR_D7_DRVVBUS E26 I/O OVDD Notes USB Port 1 MPH1_NXT/DR_SESS_VLD_NXT D27 I OVDD MPH1_DIR_DPPULLUP/ DR_XCVR_SEL_DPPULLUP A28 I/O OVDD MPH1_STP_SUSPEND/ DR_STP_SUSPEND F26 O OVDD MPH1_PWRFAULT/ DR_RX_ERROR_PWRFAULT E27 I OVDD MPH1_PCTL0/DR_TX_VALID_PCTL0 A29 O OVDD MPH1_PCTL1/DR_TX_VALIDH_PCTL1 D28 O OVDD MPH1_CLK/DR_CLK B29 I OVDD USB Port 0 MPH0_D0_ENABLEN/ DR_D8_CHGVBUS C29 I/O OVDD MPH0_D1_SER_TXD/ DR_D9_DCHGVBUS A30 I/O OVDD MPH0_D2_VMO_SE0/ DR_D10_DPPD E28 I/O OVDD MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 78 Freescale Semiconductor Table 54. MPC8347EA (TBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply MPH0_D3_SPEED/ DR_D11_DMMD B30 I/O OVDD MPH0_D4_DP/ DR_D12_VBUS_VLD C30 I/O OVDD MPH0_D5_DM/ DR_D13_SESS_END A31 I/O OVDD MPH0_D6_SER_RCV/DR_D14 B31 I/O OVDD MPH0_D7_DRVVBUS/ DR_D15_IDPULLUP C31 I/O OVDD MPH0_NXT/ DR_RX_ACTIVE_ID B32 I OVDD MPH0_DIR_DPPULLUP/ DR_RESET A32 I/O OVDD MPH0_STP_SUSPEND/ DR_TX_READY A33 I/O OVDD MPH0_PWRFAULT/ DR_RX_VALIDH C32 I OVDD MPH0_PCTL0/ DR_LINE_STATE0 D31 I/O OVDD MPH0_PCTL1/ DR_LINE_STATE1 E30 I/O OVDD MPH0_CLK/DR_RX_VALID B33 I OVDD Notes Programmable Interrupt Controller MCP_OUT AN33 O OVDD IRQ0/MCP_IN/GPIO2[12] C19 I/O OVDD IRQ[1:5]/GPIO2[13:17] C22, A22, D21, C21, B21 I/O OVDD IRQ[6]/GPIO2[18]/ CKSTOP_OUT A21 I/O OVDD IRQ[7]/GPIO2[19]/ CKSTOP_IN C20 I/O OVDD 2 Ethernet Management Interface EC_MDC A7 O LVDD1 EC_MDIO E9 I/O LVDD1 I LVDD1 2 Gigabit Reference Clock EC_GTX_CLK125 C8 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 79 Table 54. MPC8347EA (TBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply Notes Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_COL/GPIO2[20] A17 I/O OVDD TSEC1_CRS/GPIO2[21] F12 I/O LVDD1 TSEC1_GTX_CLK D10 O LVDD1 TSEC1_RX_CLK A11 I LVDD1 TSEC1_RX_DV B11 I LVDD1 TSEC1_RX_ER/GPIO2[26] B17 I/O OVDD TSEC1_RXD[7:4]/ GPIO2[22:25] B16, D16, E16, F16 I/O OVDD TSEC1_RXD[3:0] E10, A8, F10, B8 I LVDD1 TSEC1_TX_CLK D17 I OVDD TSEC1_TXD[7:4]/GPIO2[27:30] A15, B15, A14, B14 I/O OVDD TSEC1_TXD[3:0] A10, E11, B10, A9 O LVDD1 TSEC1_TX_EN B9 O LVDD1 TSEC1_TX_ER/GPIO2[31] A16 I/O OVDD 3 Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_COL/GPIO1[21] C14 I/O OVDD TSEC2_CRS/GPIO1[22] D6 I/O LVDD2 TSEC2_GTX_CLK A4 O LVDD2 TSEC2_RX_CLK B4 I LVDD2 TSEC2_RX_DV/GPIO1[23] E6 I/O LVDD2 TSEC2_RXD[7:4]/GPIO1[26:29] A13, B13, C13, A12 I/O OVDD TSEC2_RXD[3:0]/GPIO1[13:16] D7, A6, E8, B7 I/O LVDD2 TSEC2_RX_ER/GPIO1[25] D14 I/O OVDD TSEC2_TXD[7]/GPIO1[31] B12 I/O OVDD TSEC2_TXD[6]/ DR_XCVR_TERM_SEL C12 O OVDD TSEC2_TXD[5]/ DR_UTMI_OPMODE1 D12 O OVDD TSEC2_TXD[4]/ DR_UTMI_OPMODE0 E12 O OVDD TSEC2_TXD[3:0]/GPIO1[17:20] B5, A5, F8, B6 I/O LVDD2 TSEC2_TX_ER/GPIO1[24] F14 I/O OVDD MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 80 Freescale Semiconductor Table 54. MPC8347EA (TBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply Notes 3 TSEC2_TX_EN/GPIO1[12] C5 I/O LVDD2 TSEC2_TX_CLK/GPIO1[30] E14 I/O OVDD DUART UART_SOUT[1:2]/ MSRCID[0:1]/LSRCID[0:1] AK27, AN29 O OVDD UART_SIN[1:2]/ MSRCID[2:3]/LSRCID[2:3] AL28, AM29 I/O OVDD UART_CTS[1]/ MSRCID4/LSRCID4 AP30 I/O OVDD UART_CTS[2]/ MDVAL/ LDVAL AN30 I/O OVDD UART_RTS[1:2] AP31, AM30 O OVDD I2C interface IIC1_SDA AK29 I/O OVDD 2 IIC1_SCL AP32 I/O OVDD 2 IIC2_SDA AN31 I/O OVDD 2 IIC2_SCL AM31 I/O OVDD 2 SPI SPIMOSI/LCS[6] AN32 I/O OVDD SPIMISO/LCS[7] AP33 I/O OVDD SPICLK AK30 I/O OVDD SPISEL AL31 I OVDD Clocks PCI_CLK_OUT[0:2] AN9, AP9, AM10 O OVDD PCI_CLK_OUT[3]/LCS[6] AN10 O OVDD PCI_CLK_OUT[4]/LCS[7] AJ11 O OVDD PCI_SYNC_IN/PCI_CLOCK AK12 I OVDD PCI_SYNC_OUT AP11 O OVDD RTC/PIT_CLOCK AM32 I OVDD CLKIN AM9 I OVDD 3 JTAG TCK E20 I OVDD TDI F20 I OVDD 4 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 81 Table 54. MPC8347EA (TBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply Notes TDO B20 O OVDD 3 TMS A20 I OVDD 4 TRST B19 I OVDD 4 Test TEST D22 I OVDD 6 TEST_SEL AL13 I OVDD 7 O OVDD PMC QUIESCE A18 System Control PORESET C18 I OVDD HRESET B18 I/O OVDD 1 SRESET D18 I/O OVDD 2 I -- 9 Power for e300 PLL (1.2 V) AVDD1 Thermal Management THERM0 K32 Power and Ground Signals AVDD1 L31 AVDD2 AP12 Power for system PLL (1.2 V) AVDD2 AVDD3 AE1 Power for DDR DLL (1.2 V) -- AVDD4 AJ13 Power for LBIU DLL (1.2 V) AVDD4 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 82 Freescale Semiconductor Table 54. MPC8347EA (TBGA) Pinout Listing (continued) Package Pin Number Pin Type Power Supply GND A1, A34, C1, C7, C10, C11, C15, C23, C25, C28, D1, D8, D20, D30, E7, E13, E15, E17, E18, E21, E23, E25, E32, F6, F19, F27, F30, F34, G31, H5, J4, J34, K30, L5, M2, M5, M30, M33, N3, N5, P30, R5, R32, T5, T30, U6, U29, U33, V2, V5, V30, W6, W30, Y30, AA2, AA30, AB2, AB6, AB30, AC3, AC6, AD31, AE5, AF2, AF5, AF31, AG30, AG31, AH4, AJ3, AJ19, AJ22, AK7, AK13, AK14, AK16, AK18, AK20, AK25, AK28, AL3, AL5, AL10, AL12, AL22, AL27, AM1, AM6, AM7, AN12, AN17, AN34, AP1, AP8, AP34 -- -- GVDD A2, E2, G5, G6, J5, K4, K5, L4, N4, P5, R6, T6, U5, V1, W5, Y5, AA4, AB3, AC4, AD5, AF3, AG5, AH2, AH5, AH6, AJ6, AK6, AK8, AK9, AL6 Power for DDR DRAM I/O Voltage (2.5 V) GVDD LVDD1 C9, D11 Power for Three Speed Ethernet #1 and for Ethernet Managemen t Interface I/O (2.5V, 3.3V) LVDD1 LVDD2 C6, D9 Power for Three Speed Ethernet #2 I/O (2.5V, 3.3V) LVDD2 VDD E19, E29, F7, F9, F11,F13, F15, F17, F18, F21, F23, F25, F29, H29, J6, K29, M29, N6, P29, T29, U30, V6, V29, W29, AB29, AC5, AD29, AF6, AF29, AH29, AJ8, AJ12, AJ14, AJ16, AJ18, AJ20, AJ21, AJ23, AJ25, AJ26, AJ27, AJ28, AJ29, AK10 Power for Core (1.2 V) VDD OVDD B22, B28, C16, C17, C24, C26, D13, D15, D19, D29, E31, F28, G33, H30, L29, L32, N32, P31, R31, U32, W31, Y29, AA29, AC30, AE31, AF30, AG29, AJ17, AJ30, AK11, AL15, AL19, AL21, AL29, AL30, AM20, AM23, AM24, AM26, AM28, AN11, AN13 PCI, 10/100 Ethernet, and other Standard (3.3 V) OVDD MVREF1 M3 I DDR Reference Voltage Signal Notes MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 83 Table 54. MPC8347EA (TBGA) Pinout Listing (continued) Signal MVREF2 Package Pin Number Pin Type AD2 Power Supply I DDR Reference Voltage -- -- Notes No Connection NC W32, AA31, AA32, AA33, AA34, AB31, AB32, AB33, AB34, AC29, AC31, AC33, AC34, AD30, AD32, AD33, AD34, AE29, AE30, AH32, AH33, AH34, AM33, AJ31, AJ32, AJ33, AJ34, AK32, AK33, AK34, AM34, AL33, AL34, AK31, AH30, AC32, AE32, AH31, AL32, AG34, AE33, AF32, AE34, AF34, AF33, AG33, AG32, AL11, AM11, AP10, Y32, Y34, Y31, Y33 Notes: 1. This pin is an open-drain signal. A weak pull-up resistor (1 k) should be placed on this pin to OVDD 2. This pin is an open-drain signal. A weak pull-up resistor (2-10 k) should be placed on this pin to OVDD. 3. During reset, this output is actively driven rather than three-stated. 4. These JTAG pins have weak internal pull-up P-FETs that are always enabled. 5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications. 6. This pin must always be tied to GND 7. This pin must always be pulled up to OVDD 8. This pin must always be left not connected. 9. Thermal sensitive resistor. 10. It is recommended that MDIC0 be tied to GRD using an 18 resistor and MDIC1 be tied to DDR power using an 18 resistor. Table 52 provides the pin-out listing for the MPC8347EA, 620 PBGA package. Table 55. MPC8347EA (PBGA) Pinout Listing Signal Package Pin Number Pin Type Power Supply Notes 2 PCI PCI1_INTA/IRQ_OUT D20 O OVDD PCI1_RESET_OUT B21 O OVDD PCI1_AD[31:0] E19, D17, A16, A18, B17, B16, D16, B18, E17, E16, A15, C16, D15, D14, C14, A12, D12, B11, C11, E12, A10, C10, A9, E11, E10, B9, B8, D9, A8, C9, D8, C8 I/O OVDD PCI1_C/BE[3:0] A17, A14, A11, B10 I/O OVDD PCI1_PAR D13 I/O OVDD PCI1_FRAME B14 I/O OVDD 5 PCI1_TRDY A13 I/O OVDD 5 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 84 Freescale Semiconductor Table 55. MPC8347EA (PBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply Notes PCI1_IRDY E13 I/O OVDD 5 PCI1_STOP C13 I/O OVDD 5 PCI1_DEVSEL B13 I/O OVDD 5 PCI1_IDSEL C17 I OVDD PCI1_SERR C12 I/O OVDD 5 PCI1_PERR B12 I/O OVDD 5 PCI1_REQ[0] A21 I/O OVDD PCI1_REQ[1]/ CPCI1_HS_ES C19 I OVDD PCI1_REQ[2:4] C18, A19, E20 I OVDD PCI1_GNT0 B20 I/O OVDD PCI1_GNT1/ CPCI1_HS_LED C20 O OVDD PCI1_GNT2/ CPCI1_HS_ENUM B19 O OVDD PCI1_GNT[3:4] A20, E18 O OVDD M66EN L26 I OVDD DDR SDRAM Memory Interface MDQ[0:63] AC25, AD27, AD25, AH27, AE28, AD26, AD24, AF27, AF25, AF28, AH24, AG26, AE25, AG25, AH26, AH25, AG22, AH22, AE21, AD19, AE22, AF23, AE19, AG20, AG19, AD17, AE16, AF16, AF18, AG18, AH17, AH16, AG9, AD12, AG7, AE8, AD11, AH9, AH8, AF6, AF8, AE6, AF1, AE4, AG8, AH3, AG3, AG4, AH2, AD7, AB4, AB3, AG1, AD5, AC2, AC1, AC4, AA3, Y4, AA4, AB1, AB2, Y5, Y3 I/O GVDD MECC[0:4]/MSRCID[0:4] AG13, AE14, AH12, AH10, AE15 I/O GVDD MECC[5]/MDVAL AH14 I/O GVDD MECC[6:7] AE13, AH11 I/O GVDD MDM[0:8] AG28, AG24, AF20, AG17, AE9, AH5, AD1, AA2, AG12 O GVDD MDQS[0:8] AE27, AE26, AE20, AH18, AG10, AF5, AC3, AA1, AH13 I/O GVDD MBA[0:1] AF10, AF11 O GVDD MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 85 Table 55. MPC8347EA (PBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply Notes MA[0:14] AF13, AF15, AG16, AD16, AF17, AH20, AH19, AH21, AD18, AG21, AD13, AF21, AF22, AE1, AA5 O GVDD MWE AD10 O GVDD MRAS AF7 O GVDD MCAS AG6 O GVDD MCS[0:3] AE7, AH7, AH4, AF2 O GVDD MCKE[0:1] AG23, AH23 O GVDD MCK[0:5] AH15, AE24, AE2, AF14, AE23, AD3 O GVDD MCK[0:5] AG15, AD23, AE3, AG14, AF24, AD2 O GVDD MODT[0:3] AG5, AD4, AH6, AF4 O GVDD MBA[2] AD22 O GVDD MDIC0 AG11 I/O -- 9 MDIC1 AF12 I/O -- 9 3 Local Bus Controller Interface LAD[0:31] T4, T5, T1, R2, R3, T2, R1, R4, P1, P2, P3, P4, N1, N4, N2, N3, M1, M2, M3, N5, M4, L1, L2, L3, K1, M5, K2, K3, J1, J2, L5, J3 I/O OVDD LDP[0]/CKSTOP_OUT H1 I/O OVDD LDP[1]/CKSTOP_IN K5 I/O OVDD LDP[2]/LCS[4] H2 I/O OVDD LDP[3]/LCS[5] G1 I/O OVDD LA[27:31] J4, H3, G2, F1, G3 O OVDD LCS[0:3] J5, H4, F2, E1 O OVDD LWE[0:3]/LSDDQM[0:3]/ LBS[0:3] F3, G4, D1, E2 O OVDD LBCTL H5 O OVDD LALE E3 O OVDD LGPL0/LSDA10/ cfg_reset_source0 F4 I/O OVDD LGPL1/LSDWE/ cfg_reset_source1 D2 I/O OVDD LGPL2/ LSDRAS/LOE C1 O OVDD MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 86 Freescale Semiconductor Table 55. MPC8347EA (PBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply LGPL3/LSDCAS/ cfg_reset_source2 C2 I/O OVDD LGPL4/LGTA/LUPWAIT/LPBSE C3 I/O OVDD LGPL5/cfg_clkin_div B3 I/O OVDD LCKE E4 O OVDD LCLK[0:2] D4, A3, C4 O OVDD LSYNC_OUT U3 O OVDD LSYNC_IN Y2 I OVDD Notes General Purpose I/O Timers GPIO1[0]/DMA_DREQ0/ GTM1_TIN1/ GTM2_TIN2 D27 I/O OVDD GPIO1[1]/DMA_DACK0/ GTM1_TGATE1/ GTM2_TGATE2 E26 I/O OVDD GPIO1[2]/DMA_DDONE0/ GTM1_TOUT1 D28 I/O OVDD GPIO1[3]/DMA_DREQ1/ GTM1_TIN2/ GTM2_TIN1 G25 I/O OVDD GPIO1[4]/DMA_DACK1/ GTM1_TGATE2/ GTM2_TGATE1 J24 I/O OVDD GPIO1[5]/DMA_DDONE1/ GTM1_TOUT2/ GTM2_TOUT1 F26 I/O OVDD GPIO1[6]/DMA_DREQ2/ GTM1_TIN3/ GTM2_TIN4 E27 I/O OVDD GPIO1[7]/DMA_DACK2/ GTM1_TGATE3/ GTM2_TGATE4 E28 I/O OVDD GPIO1[8]/DMA_DDONE2/ GTM1_TOUT3 H25 I/O OVDD GPIO1[9]/DMA_DREQ3/ GTM1_TIN4/ GTM2_TIN3 F27 I/O OVDD GPIO1[10]/DMA_DACK3/ GTM1_TGATE4/ GTM2_TGATE3 K24 I/O OVDD MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 87 Table 55. MPC8347EA (PBGA) Pinout Listing (continued) Pin Type Power Supply I/O OVDD MPH1_D0_ENABLEN/DR_D0_ENABLEN C28 I/O OVDD MPH1_D1_SER_TXD/DR_D1_SER_RXD F25 I/O OVDD MPH1_D2_VMO_SE0/DR_D2_VMO_SE0 B28 I/O OVDD MPH1_D3_SPEED/DR_D3_SPEED C27 I/O OVDD MPH1_D4_DP/DR_D4_DP D26 I/O OVDD MPH1_D5_DM/DR_D5_DM E25 I/O OVDD MPH1_D6_SER_RCV/DR_D6_SER_RCV C26 I/O OVDD MPH1_D7_DRVVBUS/DR_D7_DRVVBUS D25 I/O OVDD Signal GPIO1[11]/DMA_DDONE3/ GTM1_TOUT4/ GTM2_TOUT3 Package Pin Number G26 Notes USB Port 1 MPH1_NXT/DR_SESS_VLD_NXT B26 I OVDD MPH1_DIR_DPPULLUP/ DR_XCVR_SEL_DPPULLUP E24 I/O OVDD MPH1_STP_SUSPEND/ DR_STP_SUSPEND A27 O OVDD MPH1_PWRFAULT/ DR_RX_ERROR_PWRFAULT C25 I OVDD MPH1_PCTL0/DR_TX_VALID_PCTL0 A26 O OVDD MPH1_PCTL1/DR_TX_VALIDH_PCTL1 B25 O OVDD MPH1_CLK/DR_CLK A25 I OVDD USB Port 0 MPH0_D0_ENABLEN/ DR_D8_CHGVBUS D24 I/O OVDD MPH0_D1_SER_TXD/ DR_D9_DCHGVBUS C24 I/O OVDD MPH0_D2_VMO_SE0/ DR_D10_DPPD B24 I/O OVDD MPH0_D3_SPEED/ DR_D11_DMMD A24 I/O OVDD MPH0_D4_DP/ DR_D12_VBUS_VLD D23 I/O OVDD MPH0_D5_DM/ DR_D13_SESS_END C23 I/O OVDD MPH0_D6_SER_RCV/DR_D14 B23 I/O OVDD MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 88 Freescale Semiconductor Table 55. MPC8347EA (PBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply MPH0_D7_DRVVBUS/ DR_D15_IDPULLUP A23 I/O OVDD MPH0_NXT/ DR_RX_ACTIVE_ID D22 I OVDD MPH0_DIR_DPPULLUP/ DR_RESET C22 I/O OVDD MPH0_STP_SUSPEND/ DR_TX_READY B22 I/O OVDD MPH0_PWRFAULT/ DR_RX_VALIDH A22 I OVDD MPH0_PCTL0/ DR_LINE_STATE0 E21 I/O OVDD MPH0_PCTL1/ DR_LINE_STATE1 D21 I/O OVDD MPH0_CLK/DR_RX_VALID C21 I OVDD Notes Programmable Interrupt Controller MCP_OUT E8 O OVDD IRQ0/MCP_IN/GPIO2[12] J28 I/O OVDD IRQ[1:5]/GPIO2[13:17] K25, J25, H26, L24, G27 I/O OVDD IRQ[6]/GPIO2[18]/ CKSTOP_OUT G28 I/O OVDD IRQ[7]/GPIO2[19]/ CKSTOP_IN J26 I/O OVDD 2 Ethernet Management Interface EC_MDC Y24 O LVDD1 EC_MDIO Y25 I/O LVDD1 I LVDD1 2 Gigabit Reference Clock EC_GTX_CLK125 Y26 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_COL/GPIO2[20] M26 I/O OVDD TSEC1_CRS/GPIO2[21] U25 I/O LVDD1 TSEC1_GTX_CLK V24 O LVDD1 TSEC1_RX_CLK U26 I LVDD1 TSEC1_RX_DV U24 I LVDD1 3 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 89 Table 55. MPC8347EA (PBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply TSEC1_RX_ER/GPIO2[26] L28 I/O OVDD TSEC1_RXD[7:4]/GPIO2[22:25] M27, M28, N26, N27 I/O OVDD TSEC1_RXD[3:0] W26, W24, Y28, Y27 I LVDD1 TSEC1_TX_CLK N25 I OVDD TSEC1_TXD[7:4]/GPIO2[27:30] N28, P25, P26, P27 I/O OVDD TSEC1_TXD[3:0] V28, V27, V26, W28 O LVDD1 TSEC1_TX_EN W27 O LVDD1 TSEC1_TX_ER/GPIO2[31] N24 I/O OVDD Notes Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_COL/GPIO1[21] P28 I/O OVDD TSEC2_CRS/GPIO1[22] AC28 I/O LVDD2 TSEC2_GTX_CLK AC27 O LVDD2 TSEC2_RX_CLK AB25 I LVDD2 TSEC2_RX_DV/GPIO1[23] AC26 I/O LVDD2 TSEC2_RXD[7:4]/GPIO1[26:29] R28, T24, T25, T26 I/O OVDD TSEC2_RXD[3:0]/GPIO1[13:16] AA25, AA26, AA27, AA28 I/O LVDD2 TSEC2_RX_ER/GPIO1[25] R25 I/O OVDD TSEC2_TXD[7]/GPIO1[31] T27 I/O OVDD TSEC2_TXD[6]/DR_XCVR_TERM_SEL T28 O OVDD TSEC2_TXD[5]/DR_UTMI_OPMODE1 U28 O OVDD TSEC2_TXD[4]/DR_UTMI_OPMODE0 U27 O OVDD TSEC2_TXD[3:0]/GPIO1[17:20] AB26, AB27, AA24, AB28 I/O LVDD2 TSEC2_TX_ER/GPIO1[24] R27 I/O OVDD TSEC2_TX_EN/GPIO1[12] AD28 I/O LVDD2 TSEC2_TX_CLK/GPIO1[30] R26 I/O OVDD 3 DUART UART_SOUT[1:2]/ MSRCID[0:1]/LSRCID[0:1] B4, A4 O OVDD UART_SIN[1:2]/ MSRCID[2:3]/LSRCID[2:3] D5, C5 I/O OVDD UART_CTS[1]/ MSRCID4/LSRCID4 B5 I/O OVDD MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 90 Freescale Semiconductor Table 55. MPC8347EA (PBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply UART_CTS[2]/ MDVAL/ LDVAL A5 I/O OVDD UART_RTS[1:2] D6, C6 O OVDD Notes I2C interface IIC1_SDA E5 I/O OVDD 2 IIC1_SCL A6 I/O OVDD 2 IIC2_SDA B6 I/O OVDD 2 IIC2_SCL E7 I/O OVDD 2 SPI SPIMOSI/LCS[6] D7 I/O OVDD SPIMISO/LCS[7] C7 I/O OVDD SPICLK B7 I/O OVDD SPISEL A7 I OVDD Clocks PCI_CLK_OUT[0:2] Y1, W3, W2 O OVDD PCI_CLK_OUT[3]/LCS[6] W1 O OVDD PCI_CLK_OUT[4]/LCS[7] V3 O OVDD PCI_SYNC_IN/PCI_CLOCK U4 I OVDD PCI_SYNC_OUT U5 O OVDD RTC/PIT_CLOCK E9 I OVDD CLKIN W5 I OVDD 3 JTAG TCK H27 I OVDD TDI H28 I OVDD 4 TDO M24 O OVDD 3 TMS J27 I OVDD 4 TRST K26 I OVDD 4 Test TEST F28 I OVDD 6 TEST_SEL T3 I OVDD 6 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 91 Table 55. MPC8347EA (PBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply O OVDD Notes PMC QUIESCE K27 System Control PORESET K28 I OVDD HRESET M25 I/O OVDD 1 SRESET L27 I/O OVDD 2 I -- 8 Thermal Management THERM0 B15 Power and Ground Signals AVDD1 C15 Power for e300 PLL (1.2 V) AVDD1 AVDD2 U1 Power for system PLL (1.2 V) AVDD2 AVDD3 AF9 Power for DDR DLL (1.2 V) -- AVDD4 U2 Power for LBIU DLL (1.2 V) AVDD4 GND A2, B1, B2, D10, D18, E6, E14, E22, F9, F12, F15, F18, F21, F24, G5, H6, J23, L4, L6, L12, L13, L14, L15, L16, L17, M11, M12, M13, M14, M15, M16, M17, M18, M23, N11, N12, N13, N14, N15, N16, N17, N18, P6, P11, P12, P13, P14, P15, P16, P17, P18, P24, R5, R11, R12, R13, R14, R15, R16, R17, R18, R23, T11, T12, T13, T14, T15, T16, T17, T18, U6, U11, U12, U13, U14, U15, U16, U17, U18, V12, V13, V14, V15, V16, V17, V23, V25, W4, Y6, AA23, AB24, AC5, AC8, AC11, AC14, AC17, AC20, AD9, AD15, AD21, AE12, AE18, AF3, AF26 -- -- GVDD U9, V9, W10, W19, Y11, Y12, Y14, Y15, Y17, Y18, AA6, AB5, AC9, AC12, AC15, AC18, AC21, AC24, AD6, AD8, AD14, AD20, AE5, AE11, AE17, AG2, AG27 Power for DDR DRAM I/O Voltage (2.5 V) GVDD MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 92 Freescale Semiconductor Table 55. MPC8347EA (PBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply LVDD1 U20, W25 Power for Three Speed Ethernet #1 and for Ethernet Management Interface I/O (2.5V, 3.3V) LVDD1 LVDD2 V20, Y23 Power for Three Speed Ethernet #2 I/O (2.5V, 3.3V) LVDD2 VDD J11, J12, J15, K10, K11, K12, K13, K14, K15, K16, K17, K18, K19, L10, L11, L18, L19, M10, M19, N10, N19, P9, P10, P19, R10, R19, R20, T10, T19, U10, U19, V10, V11, V18, V19, W11, W12, W13, W14, W15, W16, W17, W18 Power for Core (1.2 V) VDD OVDD B27, D3, D11, D19, E15, E23, F5, F8, F11, PCI, 10/100 F14, F17, F20, G24, H23, H24, J6, J14, J17, Ethernet, and J18, K4, L9, L20, L23, L25, M6, M9, M20, other P5, P20, P23, R6, R9, R24, U23, V4, V6 Standard (3.3 V) MVREF1 AF19 I DDR Reference Voltage MVREF2 AE10 I DDR Reference Voltage Notes OVDD No Connection NC V1, V2, V5 Notes: 1. This pin is an open-drain signal. A weak pull-up resistor (1 k) should be placed on this pin to OVDD 2. This pin is an open-drain signal. A weak pull-up resistor (2-10 k) should be placed on this pin to OVDD. 3. During reset, this output is actively driven rather than three-stated. 4. These JTAG pins have weak internal pull-up P-FETs that are always enabled. 5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications. 6. .This pin must always be tied to GND 7. This pin must always be left not connected 8. Thermal sensitive resistor. 9. It is recommended that MDIC0 be tied to GRD using an 18 resistor and MDIC1 be tied to DDR power using an 18 resistor. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 93 Clocking 19 Clocking Figure 40 shows the internal distribution of the clocks. MPC8347EA e300 core Core PLL csb_clk to DDR memory controller ddr_clk System PLL Clock Unit lbiu_clk core_clk DDR Clock Div /2 6 6 /n MCK[0:5] MCK[0:5] DDR Memory Device LCLK[0:2] to local bus memory LBIU controller DLL LSYNC_OUT Local Bus Memory Device LSYNC_IN csb_clk to rest of the device PCI_CLK/ PCI_SYNC_IN CFG_CLKIN_DIV CLKIN PCI_SYNC_OUT PCI Clock Divider 5 PCI_CLK_OUT[0:4] Figure 40. MPC8347EA Clock Subsystem The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. When the MPC8347EA is configured as a PCI host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (/2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals. PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system, to allow the MPC8347EA to function. When the MPC8347EA is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal should be tied to GND. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 94 Freescale Semiconductor Clocking As shown in Figure 40, the primary clock input (frequency) is multiplied up by the system phase-locked loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk). The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = {PCI_SYNC_IN x (1 + CFG_CLKIN_DIV)} x SPMF In PCI host mode, PCI_SYNC_IN x (1 + CFG_CLKIN_DIV) is the CLKIN frequency. The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL), which is loaded at power-on reset or by one of the hard-coded reset options. See the chapter on reset, clocking, and initialization in the MPC8349EA Reference Manual for more information on the clock subsystem. The internal ddr_clk frequency is determined by the following equation: ddr_clk = csb_clk x (1 + RCWL[DDRCM]) ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (/2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk. The internal lbiu_clk frequency is determined by the following equation: lbiu_clk = csb_clk x (1 + RCWL[LBIUCM]) lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBIU clock divider ratio is controlled by LCCR[CLKDIV]. In addition, some of the internal units may have to be shut off or operate at lower frequency than the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory-mapped register after the device exits reset. Table 56 specifies which units have a configurable clock frequency. Table 56. Configurable Clock Units Unit Default Frequency Options csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 I2C1 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Security Core csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 USB DR, USB MPH csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 TSEC1 TSEC2, PCI and DMA complex csb_clk Off, csb_clk Table 57 provides the operating frequencies for the MPC8347EA TBGA under recommended operating conditions (see Table 2). MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 95 Clocking Table 57. Operating Frequencies for TBGA Characteristic 1 533 MHz 667 MHz Unit e300 core frequency (core_clk) 266-533 266-667 MHz Coherent system bus frequency (csb_clk) 100-266 100-333 MHz DDR and DDR2 memory bus frequency (MCLK) 2 100-200 100-200 MHz 16.67-133 16.67-133 MHz 25-66 25-66 MHz Security core maximum internal operating frequency 133 166 MHz USB_DR, USB_MPH maximum internal operating frequency 133 166 MHz Local bus frequency (LCLKn) 3 PCI input frequency (CLKIN or PCI_CLK) 1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting ccb_clk, MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of SCCR[ENCCM], SCCR[USBDRCM]and SCCR[USBMPHCM] must be programmed so that the maximum internal operating frequency of the Security core and USB modules does not exceed the respective values listed in this table. 2 The DDR data rate is 2x the DDR memory bus frequency. 3 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the ccb_clk frequency (depending on RCWL[LBIUCM]). Table 58 provides the operating frequencies for the MPC8347EA PBGA under recommended operating conditions. Table 58. Operating Frequencies for PBGA Characteristic 1 e300 core frequency (core_clk) 266 MHz 333 MHz 400 MHz Unit 200-266 200-333 200-400 MHz Coherent system bus frequency (csb_clk) 100-266 MHz DDR memory bus frequency (MCLK) 2 100-133 MHz 16.67-133 MHz 25-66 MHz Security core maximum internal operating frequency 133 MHz USB_DR, USB_MPH maximum internal operating frequency 133 MHz Local bus frequency (LCLKn) 3 PCI input frequency (CLKIN or PCI_CLK) 1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting ccb_clk, MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of SCCR[ENCCM], SCCR[USBDRCM]and SCCR[USBMPHCM] must be programmed so that the maximum internal operating frequency of the Security core and USB modules does not exceed the respective values listed in this table. 2 The DDR data rate is 2x the DDR memory bus frequency. 3 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the ccb_clk frequency (depending on RCWL[LBIUCM]). MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 96 Freescale Semiconductor Clocking 19.1 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. Table 59 shows the multiplication factor encodings for the system PLL. Table 59. System PLL Multiplication Factors RCWL[SPMF] System PLL Multiplication Factor 0000 x 16 0001 Reserved 0010 x2 0011 x3 0100 x4 0101 x5 0110 x6 0111 x7 1000 x8 1001 x9 1010 x 10 1011 x 11 1100 x 12 1101 x 13 1110 x 14 1111 x 15 As described in Section 19, "Clocking," The LBIUCM, DDRCM, and SPMF parameters in the reset configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 60 and Table 61 show the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN ratios. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 97 Clocking Table 60. CSB Frequency Options for Host Mode Input Clock Frequency (MHz)2 CFG_CLKIN_DIV at reset 1 SPMF csb_clk : Input Clock Ratio 2 16.67 25 33.33 66.67 csb_clk Frequency (MHz) 1 2 Low 0010 2:1 Low 0011 3:1 Low 0100 4:1 Low 0101 5:1 Low 0110 6:1 Low 0111 Low 133 100 200 100 133 266 125 166 333 100 150 200 7:1 116 175 233 1000 8:1 133 200 266 Low 1001 9:1 150 225 300 Low 1010 10 : 1 166 250 333 Low 1011 11 : 1 183 275 Low 1100 12 : 1 200 300 Low 1101 13 : 1 216 325 Low 1110 14 : 1 233 Low 1111 15 : 1 250 Low 0000 16 : 1 266 High 0010 2:1 High 0011 3:1 100 200 High 0100 4:1 133 266 High 0101 5:1 166 333 High 0110 6:1 200 High 0111 7:1 233 High 1000 8:1 133 CFG_CLKIN_DIV selects the ratio between CLKIN and PCI_SYNC_OUT. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 98 Freescale Semiconductor Clocking Table 61. CSB Frequency Options for Agent Mode Input Clock Frequency (MHz)2 CFG_CLKIN_DIV at reset 1 SPMF csb_clk : Input Clock Ratio 2 16.67 25 33.33 66.67 csb_clk Frequency (MHz) 1 2 19.2 Low 0010 2:1 Low 0011 3:1 Low 0100 4:1 Low 0101 5:1 Low 0110 6:1 Low 0111 Low 133 100 200 100 133 266 125 166 333 100 150 200 7:1 116 175 233 1000 8:1 133 200 266 Low 1001 9:1 150 225 300 Low 1010 10 : 1 166 250 333 Low 1011 11 : 1 183 275 Low 1100 12 : 1 200 300 Low 1101 13 : 1 216 325 Low 1110 14 : 1 233 Low 1111 15 : 1 250 Low 0000 16 : 1 266 high 0010 4:1 High 0011 6:1 High 0100 High 100 133 100 150 200 8:1 133 200 266 0101 10 : 1 166 250 333 High 0110 12 : 1 200 300 High 0111 14 : 1 233 High 1000 16 : 1 266 266 CFG_CLKIN_DIV doubles csb_clk if set high. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. Core PLL Configuration RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 62 shows the encodings for RCWL[COREPLL]. COREPLL values that are not listed in Table 62 should be considered as reserved. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 99 Clocking NOTE Core VCO frequency = Core frequency x VCO divider VCO divider must be set properly so that the core VCO frequency is in the range of 800-1800 MHz. Table 62. e300 Core PLL Configuration RCWL[COREPLL] 1 core_clk : csb_clk Ratio VCO divider 1 0-1 2-5 6 nn 0000 n PLL bypassed (PLL off, csb_clk clocks core directly) PLL bypassed (PLL off, csb_clk clocks core directly) 00 0001 0 1:1 2 01 0001 0 1:1 4 10 0001 0 1:1 8 11 0001 0 1:1 8 00 0001 1 1.5:1 2 01 0001 1 1.5:1 4 10 0001 1 1.5:1 8 11 0001 1 1.5:1 8 00 0010 0 2:1 2 01 0010 0 2:1 4 10 0010 0 2:1 8 11 0010 0 2:1 8 00 0010 1 2.5:1 2 01 0010 1 2.5:1 4 10 0010 1 2.5:1 8 11 0010 1 2.5:1 8 00 0011 0 3:1 2 01 0011 0 3:1 4 10 0011 0 3:1 8 11 0011 0 3:1 8 Core VCO frequency = Core frequency x VCO divider. The VCO divider must be set properly so that the core VCO frequency is in the range of 800-1800 MHz. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 100 Freescale Semiconductor Clocking 19.3 Suggested PLL Configurations Table 63 shows suggested PLL configurations for 33 MHz and 66 MHz input clocks. Table 63. Suggested PLL Configurations Ref No. 1 RCWL SPMF CORE PLL 400 MHz Device Input Clock Freq (MHz) 2 CSB Freq (MHz) 533 MHz Device Core Freq (MHz) Input Clock Freq (MHz)2 CSB Freq (MHz) 667 MHz Device Core Freq (MHz) Input Clock Freq (MHz)2 CSB Freq (MHz) Core Freq (MHz) 33 MHz CLKIN/PCI_CLK Options 922 1001 0100010 -- -- -- -- -- 300 33 300 300 723 0111 0100011 33 233 350 33 233 350 33 233 350 604 0110 0000100 33 200 400 33 200 400 33 200 400 624 0110 0100100 33 200 400 33 200 400 33 200 400 803 1000 0000011 33 266 400 33 266 400 33 266 400 823 1000 0100011 33 266 400 33 266 400 33 266 400 903 1001 0000011 -- -- 33 300 450 923 1001 0100011 -- -- 33 300 450 704 0111 0000011 -- 33 233 466 33 233 466 724 0111 0100011 -- 33 233 466 33 233 466 804 1000 0000100 -- 33 266 533 33 266 533 705 0111 0000101 -- -- 33 233 583 606 0110 0000110 -- -- 33 200 600 904 1001 0000100 -- -- 33 300 600 805 1000 0000101 -- -- 33 266 667 A04 1010 0000100 -- -- 33 333 667 66 MHz CLKIN/PCI_CLK Options 304 0011 0000100 66 200 400 66 200 400 66 200 400 324 0011 0100100 66 200 400 66 200 400 66 200 400 403 0100 0000011 66 266 400 66 266 400 66 266 400 423 0100 0100011 66 266 400 66 266 400 66 266 400 305 0011 0000101 -- 66 200 500 66 200 500 404 0100 0000100 -- 66 266 533 66 266 533 306 0011 0000100 -- -- 66 200 600 405 0100 0000101 -- -- 66 266 667 504 0101 0000100 -- -- 66 333 667 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 101 Clocking 1 The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4-15 associated with the SPMF and COREPLL settings given in the table. 2 The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 102 Freescale Semiconductor Thermal 20 Thermal This section describes the thermal specifications of the MPC8347EA. 20.1 Thermal Characteristics Table 64 provides the package thermal characteristics for the 672 35 x 35 mm TBGA of the MPC8347EA. Table 64. Package Thermal Characteristics for TBGA Characteristic Symbol Value Unit Notes Junction-to-ambient natural convection on single-layer board (1s) RJA 14 C/W 1, 2 Junction-to-ambient natural convection on four-layer board (2s2p) RJMA 11 C/W 1, 3 Junction-to-ambient (@200 ft/min) on single-layer board (1s) RJMA 11 C/W 1, 3 Junction-to-ambient (@ 200 ft/min) on four-layer board (2s2p) RJMA 8 *C/W 1, 3 Junction-to-ambient (@ 2 m/s) on single-layer board (1s) RJMA 9 *C/W 1, 3 Junction-to-ambient (@ 2 m/s) on four-layer board (2s2p) RJMA 7 *C/W 1, 3 Junction-to-board thermal RJB 3.8 *C/W 4 Junction-to-case thermal RJC 1.7 *C/W 5 Junction-to-package natural convection on top JT 1 *C/W 6 Notes 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal, 1 m/s is approximately equal to 200 linear feet per minute (LFM). 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Table 65 provides the package thermal characteristics for the 620 29 x 29 mm PBGA of the MPC8347EA. Table 65. Package Thermal Characteristics for PBGA Characteristic Symbol Value Unit Notes Junction-to-ambient natural convection on single layer board (1s) RJA 21 C/W 1, 2 Junction-to-ambient natural convection on four layer board (2s2p) RJMA 15 C/W 1, 3 Junction-to-ambient (@200 ft/min) on single layer board (1s) RJMA 17 C/W 1, 3 Junction-to-ambient (@ 200 ft/min) on four layer board (2s2p) RJMA 12 *C/W 1, 3 Junction-to-board thermal RJB 6 *C/W 4 Junction-to-case thermal RJC 5 *C/W 5 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 103 Thermal Table 65. Package Thermal Characteristics for PBGA (continued) Characteristic Junction-to-package natural convection on top Symbol Value Unit Notes JT 5 *C/W 6 Notes 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 20.2 Thermal Management Information For the following sections, PD = (VDD x IDD) + PI/O where PI/O is the power dissipation of the I/O drivers. See Table 5 for I/O power dissipation values. 20.2.1 Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA x PD) where: TJ = junction temperature (C) TA = ambient temperature for the package (C) RJA = junction to ambient thermal resistance (C/W) PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Generally, the value obtained on a single layer board is appropriate for a tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ - TA) are possible. 20.2.2 Estimation of Junction Temperature with Junction-to-Board Thermal Resistance The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 104 Freescale Semiconductor Thermal many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TA + (RJA x PD) where: TA = ambient temperature for the package (C) RJA = junction to ambient thermal resistance (C/W) PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. 20.2.3 Experimental Determination of Junction Temperature To determine the junction temperature of the device in the application after prototypes are available, use the thermal characterization parameter (JT) to determine the junction temperature and a measure of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TJ = junction temperature (C) TT = thermocouple temperature on top of package (C) JT = junction to ambient thermal resistance (C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 105 Thermal 20.2.4 Heat Sinks and Junction-to-Case Thermal Resistance Some application environments require a heat sink to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction to ambient thermal resistance (C/W) RJC = junction to case thermal resistance (C/W) RCA = case to ambient thermal resistance (C/W) RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. The thermal performance of devices with heat sinks has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. Table 66 and Table 67 show heat sink thermal resistance for TBGA and PBGA of the MPC8347EA. Table 66. Heat Sink and Thermal Resistance of MPC8347EA (TBGA) 35 x 35 mm TBGA Heat Sink Assuming Thermal Grease Air Flow Thermal Resistance AAVID 30 x 30 x 9.4 mm Pin Fin Natural Convection 10 AAVID 30 x 30 x 9.4 mm Pin Fin 1 m/s 6.5 AAVID 30 x 30 x 9.4 mm Pin Fin 2 m/s 5.6 AAVID 31 x 35 x 23 mm Pin Fin Natural Convection 8.4 AAVID 31 x 35 x 23 mm Pin Fin 1 m/s 4.7 AAVID 31 x 35 x 23 mm Pin Fin 2 m/s 4 Wakefield, 53 x 53 x 25 mm Pin Fin Natural Convection 5.7 Wakefield, 53 x 53 x 25 mm Pin Fin 1 m/s 3.5 Wakefield, 53 x 53 x 25 mm Pin Fin 2 m/s 2.7 MEI, 75 x 85 x 12 no adjacent board, extrusion Natural Convection 6.7 MEI, 75 x 85 x 12 no adjacent board, extrusion 1 m/s 4.1 MEI, 75 x 85 x 12 no adjacent board, extrusion 2 m/s 2.8 MEI, 75 x 85 x 12 mm, adjacent board, 40 mm Side bypass 1 m/s 3.1 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 106 Freescale Semiconductor Thermal f Table 67. Heat Sink and Thermal Resistance of MPC8347EA (PBGA) 29 x 29 mm PBGA Heat Sink Assuming Thermal Grease Air Flow Thermal Resistance AAVID 30 x 30 x 9.4 mm Pin Fin Natural Convection 13.5 AAVID 30 x 30 x 9.4 mm Pin Fin 1 m/s 9.6 AAVID 30 x 30 x 9.4 mm Pin Fin 2 m/s 8.8 AAVID 31 x 35 x 23 mm Pin Fin Natural Convection 11.3 AAVID 31 x 35 x 23 mm Pin Fin 1 m/s 8.1 AAVID 31 x 35 x 23 mm Pin Fin 2 m/s 7.5 Wakefield, 53 x 53 x 25 mm Pin Fin Natural Convection 9.1 Wakefield, 53 x 53 x 25 mm Pin Fin 1 m/s 7.1 Wakefield, 53 x 53 x 25 mm Pin Fin 2 m/s 6.5 MEI, 75 x 85 x 12 no adjacent board, extrusion Natural Convection 10.1 MEI, 75 x 85 x 12 no adjacent board, extrusion 1 m/s 7.7 MEI, 75 x 85 x 12 no adjacent board, extrusion 2 m/s 6.6 MEI, 75 x 85 x 12 mm, adjacent board, 40 mm Side bypass 1 m/s 6.9 Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling and the convection cooling of the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. Heat sink vendors include the following list: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com 603-224-9988 Alpha Novatech 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com 408-567-8082 International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com 818-842-7277 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 107 Thermal Millennium Electronics (MEI) Loroco Sites 671 East Brokaw Road San Jose, CA 95112 Internet: www.mei-thermal.com 408-436-8770 Tyco Electronics Chip CoolersTM P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com 800-522-2800 Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com 603-635-5102 Interface material vendors include the following: 20.3 Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com 781-935-4850 Dow-Corning Corporation Dow-Corning Electronic Materials P.O. Box 994 Midland, MI 48686-0997 Internet: www.dowcorning.com 800-248-2481 Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com 888-642-7674 The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com 800-347-4572 Heat Sink Attachment When heat sinks are attached, an interface material is required, preferably thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces that can lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint lifetime of the package. The recommended maximum force on the top of the package is 10 lb force (4.5 kg force). Any adhesive attachment should attach to painted or plastic surfaces, and its performance should be verified under the application requirements. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 108 Freescale Semiconductor Thermal 20.3.1 Experimental Determination of the Junction Temperature with a Heat Sink When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimize the size of the clearance to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction to case thermal resistance. TJ = TC + (RJC x PD) where: TJ = junction temperature (C) TC = case temperature of the package (C) RJC = junction to case thermal resistance (C/W) PD = power dissipation (W) MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 109 Thermal MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 110 Freescale Semiconductor System Design Information 21 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8347EA. 21.1 System Clocking The MPC8347EA includes two PLLs. 1. The platform PLL (AVDD1) generates the platform clock from the externally supplied CLKIN input. The frequency ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in Section 19.1, "System PLL Configuration." 2. The e300 Core PLL (AVDD2) generates the core clock as a slave to the platform clock. The frequency ratio between the e300 core clock and the platform clock is selected using the e300 PLL ratio configuration bits as described in Section 19.2, "Core PLL Configuration." 21.2 PLL Power Supply Filtering Each PLL gets power through independent power supply pins (AVDD1, AVDD2 respectively). The AVDD level should always equal to VDD, and preferably these voltages are derived directly from VDD through a low frequency filter scheme. There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to provide five independent filter circuits as illustrated in Figure 41, one to each of the five AVDD pins. Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other. The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the specific AVDD pin being supplied. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of package, without the inductance of vias. Figure 41 shows the PLL power supply filter circuit. 10 VDD AVDD (or L2AVDD) 2.2 F 2.2 F GND Low ESL Surface Mount Capacitors Figure 41. PLL Power Supply Filter Circuit MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 111 System Design Information 21.3 Decoupling Recommendations Due to large address and data buses and high operating frequencies, the MPC8347EA can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8347EA system, and the MPC8347EA itself requires a clean, tightly regulated source of power. Therefore, the system designer should place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pin of the MPC8347EA. These capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND power planes in the PCB, with short traces to minimize inductance. Capacitors can be placed directly under the device using a standard escape pattern. Others can surround the part. These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, distribute several bulk storage capacitors around the PCB, feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors are 100-330 F (AVX TPS tantalum or Sanyo OSCON). 21.4 Connection Recommendations To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of the MPC8347EA. 21.5 Output Buffer DC Impedance The MPC8347EA drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 42). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 112 Freescale Semiconductor System Design Information OVDD RN SW2 Pad Data SW1 RP OGND Figure 42. Driver Impedance Measurement Two measurements give the value of this resistance and the strength of the driver current source. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V1 = Rsource x Isource. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value Rterm. The measured voltage is V2 = (1/(1/R1 + 1/R2)) x Isource. Solving for the output impedance gives Rsource = Rterm x (V1/V2 - 1). The drive current is then Isource = V1/Rsource. Table 68 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal OVDD, 105C. Table 68. Impedance Characteristics Impedance Local Bus, Ethernet, DUART, Control, Configuration, Power Management PCI Signals (not including PCI output clocks) PCI Output Clocks (including PCI_SYNC_OUT) DDR DRAM Symbol Unit RN 42 Target 25 Target 42 Target 20 Target Z0 RP 42 Target 25 Target 42 Target 20 Target Z0 Differential NA NA NA NA ZDIFF Note: Nominal supply voltages. See Table 1, Tj = 105C. 21.6 Configuration Pin Multiplexing The MPC8347EA power-on configuration options can be set through external pull-up or pull-down resistors of 4.7 k on certain output pins (see the customer-visible configuration pins). These pins are used as output only pins in normal operation. However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 113 System Design Information the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for the output pins. 21.7 Pull-Up Resistor Requirements The MPC8347EA requires high resistance pull-up resistors (10 k is recommended) on open-drain pins, including I2C pins, the Ethernet Management MDIO pin, and EPIC interrupt pins. Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 43. Take care to ensure that these pins are maintained at a valid deasserted state under normal operating conditions because most have asynchronous behavior, and spurious assertion yields unpredictable results. Refer to the PCI 2.3 specification for all pull-ups required for PCI. 21.8 JTAG Configuration Signals Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE Std. 1149.1 specification, but it is provided on all processors that implement the PowerPC architecture. The MPC8347EA requires TRST to be asserted during reset conditions to ensure that the JTAG boundary logic does not interfere with normal chip operation. While the TAP controller may be forced to the reset state using only the TCK and TMS signals, systems typically assert TRST during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to PORESET is not practical. The PowerPC COP function allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to assert TRST independently without causing PORESET. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 43 allows the COP to assert HRESET or TRST independently, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header are not used, TRST should be tied to PORESET so that it is asserted when the system reset signal (PORESET) is asserted. The COP header shown in Figure 43 adds many benefits--breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. It requires no more effort than adding an unpopulated footprint for a header when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). There is no standardized way to number the header, shown in Figure 43, so emulator vendors use different pin numbering schemes. Some headers are numbered top-to-bottom then left-to-right, others use left-to-right then top-to-bottom, and still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering scheme, the signal placement recommended in Figure 43 is common to all known emulators. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 114 Freescale Semiconductor System Design Information PORESET PORESET From Target Board Sources (if any) SRESET SRESET HRESET HRESET 13 11 10 k HRESET OVDD SRESET OVDD 10 k OVDD 10 k OVDD 1 2 3 4 5 6 7 8 9 10 11 12 4 61 5 15 10 k TRST VDD_SENSE TRST 2 k OVDD NC CHKSTP_OUT CHKSTP_OUT 10 k OVDD 14 KEY 13 No pin 16 COP Connector Physical Pin Out OVDD CHKSTP_IN COP Header 15 10 k 2 CHKSTP_IN 8 TMS 9 1 3 TMS TDO TDI TDO TDI TCK 7 TCK 2 NC 10 NC 12 NC 16 Notes: 1. Some systems require power to be fed from the application board into the debugger repeater card via the COP header. The resistor value for VDD_SENSE should be around 20 . 2. Key location; pin 14 is not physically present on the COP header. Figure 43. JTAG Interface Connection MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 115 System Design Information MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 116 Freescale Semiconductor Document Revision History 22 Document Revision History Table 66 provides a revision history of this document. Table 69. Document Revision History Revision Date Substantive Change(s) 2 8/2006 Changed all references to revision 2.0 silicon to revision 3.0 silicon. Changed VIH minimum value in Table 36, "JTAG Interface DC Electrical Characteristics," to OVDD - 0.3. In Table 60, "Suggested PLL Configurations," deleted reference-number rows 902 and 703. In Table 40, "PCI DC Electrical Characteristics," changed higl-level input voltage values to min = 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (-0.3) and max = 0.8. In Table 44, "PCI DC Electrical Characteristics," changed higl-level input voltage values to min = 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (-0.3) and max = 0.8. Updated DDR2 I/O power values in Table 9, "MPC8347EA Typical I/O Power Dissipation." 1 4/2006 Removed Table 20, "Timing Parameters for DDR2-400." Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, "DDR and DDR2 SDRAM Output AC Timing Specifications," rows 2 and 3, and in Figure 2, "DDR SDRAM Output Timing Diagram. Changed Min and Max values for VIH and VIL in Table 40,"PCI DC Electrical Characteristics." In Table 51, "MPC8347EA (TBGA) Pinout Listing," and Table 52, "MPC8347EA (PBGA) Pinout Listing," modified rows for MDICO and MDIC1 signals and added note "It is recommended that MDICO be tied to GRD using an 18 resistor and MCIC1 be tied to DDR power using an 18 resistor." In Table 51, "MPC8347EA (TBGA) Pinout Listing," and Table 52, "MPC8347EA (PBGA) Pinout Listing," in row AVDD3 changed power supply from "AVDD3" to "--." 0 3/2006 Initial Release 23 Ordering Information This section presents ordering information for the device discussed in this document, and it shows an example of how the parts are marked. 23.1 Part Numbers Fully Addressed by this Document Table 67 shows an analysis of the Freescale part numbering nomenclature for the MPC8347EA. The individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. Also the part numbering scheme includes an application modifier to specify special application conditions. Each part number also contains a revision code that refers to the die mask revision number. MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 117 Ordering Information Table 70. Part Numbering Nomenclature MPC nnnn e t pp aa a r Product Part Code Identifier Encryption Acceleration Temperature1 Range Package 2 Processor Frequency 3 Platform Frequency Revision Level Blank = Not included E = included Blank = 0 to 105C C= -40 to 105C ZU =TBGA VV = PB free TBGA ZQ = PBGA VR = PB Free PBGA e300 core speed AD =266 AG = 400 AJ = 533 AL = 667 D = 266 F = 333 A = 3.0 MPC 8347 Notes: 1. For temperature range = C, processor frequency is limited to 400 with a platform frequency of 266. 2. See Section 17, "Package and Pin Listings" for more information on available package types. 3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core frequencies. Table 68 shows the SVR settings by device and package type. Table 71. SVR Settings Device Package SVR (Rev. 3.0) MPC8347EA TBGA 8052_0030 MPC8347A TBGA 8053_0030 MPC8347EA PBGA 8054_0030 MPC8347A PBGA 8055_0030 MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 118 Freescale Semiconductor Ordering Information 23.2 Part Marking Parts are marked as in the example shown in Figure 44. MPCnnnnetppaaar core/platform MHZ ATWLYYWW CCCCC *MMMMM Notes: YWWLAZ TBGA/PBGA ATWLYYWW is the traceability code. CCCCC is the country code. MMMMM is the mask number. YWWLAZ is the assembly traceability code. Figure 44. Freescale Part Marking for TBGA or PBGA Devices MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 119 How to Reach Us: Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 1-800-521-6274 480-768-2130 support@freescale.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Freescale Semiconductor reserves the right to make changes without further notice to Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064, Japan 0120 191014 +81 3 5437 9125 support.japan@freescale.com parameters, including "Typicals" must be validated for each customer application by Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. Document Number: MPC8347EAEC Rev. 2 8/2006 any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. (c) Freescale Semiconductor, Inc., 2005.