IDT72T51346L7-5BBI - Integrated Device Technology, Inc.

2001 Integrated Device Technology, Inc.

OCTOBER 2, 2001

2.5V MULTI-QUEUE FIFO (8 QUEUES)

36 BIT WIDE CONFIGURATION

589,824 bits, 1,179,648 bits and

2,359,296 bits

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

ADVANCE INFORMATION

IDT72T51336

IDT72T51346

IDT72T51356

FEATURES:

••

•Choose from among the following memory density options:

IDT72T51336 



Total Available Memory = 589,824 bits

IDT72T51346 



Total Available Memory = 1,179,648 bits

IDT72T51356 



Total Available Memory = 2,359,296 bits

••

•Configurable from 1 to 8 Queues

••

•Queues may be configured at master reset from the pool of

Total Available Memory in blocks of 256 x 36

••

•Independent Read and Write access per queue

••

•User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL

••

•User programmable via serial port

••

•Default Multi-Queue device configurations

-IDT72T51336: 2,048 x 36 x 8Q

-IDT72T51346: 4,096 x 36 x 8Q

-IDT72T51356: 8,192 x 36 x 8Q

••

•100% Bus Utilization, Read and Write on every clock cycle

••

•200 MHz High speed operation (5ns cycle time)

••

•3.6ns access time

••

•Echo Read Enable & Echo Read Clock Outputs

••

•Individual, Active queue flags (OV, FF, PAE, PAF, PR)

••

•8 bit parallel flag status on both read and write ports

••

•Provides continuous PAE and PAF status of up to 8 Queues

••

•Global Bus Matching - (All Queues have same Input Bus Width

and Output Bus Width)

••

•User Selectable Bus Matching Options:

- x36in to x36out

- x18in to x36out

- x9in to x36out

- x36in to x18out

- x36in to x9out

••

•FWFT mode of operation on read port

••

•Packet Ready mode of operation

••

•Partial Reset, clears data in single Queue

••

•Expansion of up to 8 Multi-Queue devices in parallel is available

••

•Power Down Input provides additional power savings in HSTL

and eHSTL modes.

••

•JTAG Functionality (Boundary Scan)

••

•Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm

••

•HIGH Performance submicron CMOS technology

••

•Industrial temperature range (-40°C to +85°C) is available

Qmax

MULTI-QUEUE FIFO

FSTR

WEN

PAF

WRADD

WCLK

PAFn

x9, x18, x36

DATA IN

PAE

PAEn

x9, x18, x36

DATA OUT

WRITE CONTROL

Din Qout

PRn

READ CONTROL

WRITE FLAGS

READ FLAGS

6114 drw01

WADEN ESTR

EREN

RDADD

RADEN

ERCLK

REN

RCLK

DATA PATH FLOW DIAGRAM

IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FIFO (8 QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION:

The IDT72T51336/72T51346/72T51356 Multi-Queue FIFO device is a

single chip within which anywhere between 1 and 8 discrete FIFO queues

can be setup. All queues within the device have a common data input bus,

(write port) and a common data output bus, (read port). Data written into the

write port is directed to a respective queue via an internal de-multiplex

operation, addressed by the user. Data read from the read port is accessed

from a respective queue via an internal multiplex operation, addressed by

the user. Data writes and reads can be performed at high speeds up to

200MHz, with access times of 3.6ns. Data write and read operations are totally

independent of each other, a queue maybe selected on the write port and

a different queue on the read port or both ports may select the same queue

simultaneously.

The device provides Full flag and Output Valid flag status for the queue

selected for write and read operations respectively. Also a Programmable

Almost Full and Programmable Almost Empty flag for each queue is provided.

Two 8 bit programmable flag busses are available, providing status of all

queues, including queues not selected for write or read operations, these flag

busses provide an individual flag per queue.

Bus Matching is available on this device, either port can be 9 bits, 18 bits

or 36 bits wide provided that at least one port is 36 bits wide. When Bus

Matching is used the device ensures the logical transfer of data throughput

in a Little Endian manner.

A packet ready mode of operation is also provided when the device is

configured for 36 bit input and 36 bit output port sizes. The Packet Ready mode

provides the user with a flag output indicating when at least one (or more)

packets of data within a queue is available for reading. The Packet Ready

provides the user with a means by which to mark the start and end of packets

of data being passed through the FIFO queues. The Multi-Queue device then

provides the user with an internally generated packet ready status per queue.

The user has full flexibility configuring queues within the device, being able

to program the total number of queues between 1 and 8, the individual queue

depths being independent of each other. The programmable flag positions are

also user programmable. All programming is done via a dedicated serial port.

If the user does not wish to program the Multi-Queue device, a default option is

available that configures the device in a predetermined manner.

Both Master Reset and Partial Reset pins are provided on this device. A Master

Reset latches in all configuration setup pins and must be performed before

programming of the device can take place. A Partial Reset will reset the read and

write pointers of an individual FIFO queue, provided that the queue is selected

on both the write port and read port at the time of partial reset.

Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are

provided. These are outputs from the read port of the FIFO that are required for

high speed data communication, to provide tighter synchronization between the

data being transmitted from the Qn outputs and the data being received by the

input device. Data read from the read port is available on the output bus with

respect to EREN and ERCLK, this is very useful when data is being read at high

speed.

The Multi-Queue FIFO has the capability of operating its IO in either 2.5V

LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected via the

IOSEL input. The core supply voltage (VCC) to the Multi-Queue is always 2.5V,

however the output levels can be set independently via a separate supply, VDDQ.

The devices also provide additional power savings via a Power Down Input.

This input disables the write port data inputs when no write operations are

required.

A JTAG test port is provided, here the Multi-Queue FIFO has a fully functional

Boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port

and Boundary Scan Architecture.

See Figure 1, Multi-Queue FIFO Block Diagram for an outline of the functional

blocks within the device.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FIFO (8 QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

x9, x18, x36

Qout

OUTPUT

Q0 - Q 35

WRADD

WADEN

INPUT

DEMUX

WCLK WEN

Write Control

Logic

Din

Write Pointers

Active Q

Flags

PAF

General Flag

Monitor

FSTR

PAFn

FSYNC

PAF

Reset

Logic

Serial

Multi-Queue

Programming

PAE/ PAF

Offset

TMS

TDI

TDO

TCK

TRST

PRS

MRS

SCLK

SENI

RCLK

REN

Read Control

Logic

Read Pointers

Active Q

Flags

PAE

General Flag

Monitor ESTR

ESYNC

RDADD

RADEN

FXO

FXI

EXI

EXO

6114 drw02

x9, x18, x36

ID0

ID1

ID2

Device ID

3 Bit

PKT

Packet Mode

Logic

JTAG

Logic

D35 = TEOP

D34 = TSOP

Q35 = REOP

Q34 = RSOP

PRn/PAEn

SENO

DFM

MAST

PAE

Upto 8

FIFO

Queues

0.5 Mbit

1.1 Mbit

2.3 Mbit

Dual Port

Memory

OUTPUT

MUX

D0 - D35

NULL-Q

ERCLK

EREN

IO Level Control

Power Down

IOSEL

Vref

Figure 1. Multi-Queue Block Diagram

IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FIFO (8 QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PRELIMINARY

D14

D13 D12 D10 Q9D7 Q6D4 Q3D1 ID1TCK TDO Q12 Q14 Q15

D15

D16 D11 D9 Q8

D6 Q5D3 Q2D0 ID0

TMS TDI Q11 Q13 Q19

D17

D18 D19 D8 Q7D5 Q4D2 Q1

TRST Q0

IOSEL ID2 Q10 Q17 Q18

D20

D21 D22 VDDQ VDDQ

VDDQ VDDQVDDQ VDDQVDD VDDVDD VDD Q16 Q21 Q20

D23

D24 D25 VDDQ VDDQVDDQ VDDQVDD VDD

VDD VDD

GND GND Q24 Q23 Q22

D26

D27 D28 VDDQ VDDQVDD VDDGND GNDGND GNDGND GND Q27 Q26 Q25

D29

D30 D31 VDD VDDVDD VDDGND GNDGND GNDGND GND Q30 Q29 Q28

D32

D33 D34 VDD VDDGND GNDGND GNDGND GNDGND GND Q33 Q32 Q31

GND

Null Q D35 VDD VDDGND GNDGND GNDGND GNDGND GND PKT Q35 Q34

GND VREF VDD VDDVDD VDD

GND GNDGND GNDGND GND GND MASTER FM

DFM DF VDDQ VDDQVDD VDDGND GNDGND GNDGND GND BM IW OW

SENO

SENI SO VDDQ VDDQVDDQ VDDQVDD VDDVDD VDDGND GND OE RDADD0 RDADD1

WRADD1

WRADD0 SCLK VDDQ VDDQVDDQ VDDQVDDQ VDDQVDD VDDVDD VDD RDADD2 RDADD3 GND

GND

WRADD3 WRADD2 WADEN PAE3

PAF3PAE6PAF6PAE7PAF7PAE

FF OV RDADD5 RDADD6 RDADD7

WRADD6

WRADD5 FSYNC FSTR PAE2

PAF2PAE5PAF5EREN

PAF4 ERCLK

PAF PR RADEN ESTR ESYNC

WRADD7

FXI FXO PAF0PAE1PAF1PAE4

WEN REN

WCLK RCLK

PRS MRS PAE0

12 3 4 135126117108 9 14 15 16

6114 drw03

A1 BALL PAD CORNER

EXO EXI

PIN CONFIGURATION

PBGA (BB256-1, order code: BB)

TOP VIEW

NOTE:

1. DNC - Do Not Connect.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FIFO (8 QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

DETAILED DESCRIPTION

MULTI-QUEUE STRUCTURE

The IDT Multi-Queue FIFO has a single data input port and single data output

port with up to 8 FIFO queues in parallel buffering between the two ports. The

user can setup between 1 and 8 FIFO Queues within the device. These queues

can be configured to utilize the total available memory, providing the user with

full flexibility and ability to configure the queues to be various depths, indepen-

dent of one another.

MEMORY ORGANIZATION/ ALLOCATION

The memory is organized into what is known as “blocks”, each block being

256 x36 bits. When the user is configuring the number of queues and individual

queue sizes the user must allocate the memory to respective queues, in units

of blocks, that is, a single queue can be made up from 0 to m blocks, where m

is the total number of blocks available within a device. Also the total size of any

given queue must be in increments of 256 x36. For the IDT72T51336/

72T51346 and IDT72T51356 the Total Available Memory is 64, 128 and 256

blocks respectively (a block being 256 x36). Queues can be built from these

blocks to make any size queue desired and any number of queues desired.

BUS WIDTHS

The input port is common to all FIFO queues within the device, as is the output

port. The device provides the user with Bus Matching options such that the input

port and output port can be either x9, x18 or x36 bits wide provided that at least

one of the ports is x36 bits wide, the read and write port widths being set

independently of one another. Because the ports are common to all queues the

width of the queues is not individually set, so that the input width of all queues

are equal and the output width of all queues are equal.

WRITING TO & READING FROM THE MULTI-QUEUE

Data being written into the device via the input port is directed to a discrete

FIFO queue via the write queue select address inputs. Conversely, data being

read from the device read port is read from a queue selected via the read queue

select address inputs. Data can be simultaneously written into and read from the

same FIFO queue or different FIFO queues. Once a queue is selected for data

writes or reads, the writing and reading operation is performed in the same

manner as conventional IDT synchronous FIFO’s, utilizing clocks and enables,

there is a single clock and enable per port. When a specific queue is addressed

on the write port, data placed on the data inputs is written to that queue

sequentially based on the rising edge of a write clock provided setup and hold

times are met. Conversely, data is read on to the output port after an access time

from a rising edge on a read clock.

The operation of the write port is comparable to the function of a conventional

FIFO operating in standard IDT mode. Write operations can be performed on

the write port provided that the queue currently selected is not full, a full flag output

provides status of the selected queue. The operation of the read port is

comparable to the function of a conventional FIFO operating in FWFT mode.

When a FIFO queue is selected on the output port, the next word in that queue

will automatically fall through to the output register. All subsequent words from

that queue require an enabled read cycle. Data cannot be read from a selected

queue if that queue is empty, the read port provides an Output Valid flag indicating

when data read out is valid. If the user switches to a queue that is empty, the

last word from the previous queue will remain on the output register.

As mentioned, the write port has a full flag, providing full status of the selected

queue. Along with the full flag a dedicated almost full flag is provided, this almost

full flag is similar to the almost full flag of a conventional IDT FIFO. The device

provides a user programmable almost full flag for all 8 FIFO queues and when

a respective queue is selected on the write port, the almost full flag provides status

for that queue. Conversely, the read port has an output valid flag, providing

status of the data being read from the queue selected on the read port. As well

as the output valid flag the device provides a dedicated almost empty flag. This

almost empty flag is similar to the almost empty flag of a conventional IDT FIFO.

The device provides a user programmable almost empty flag for all 4 FIFO

queues and when a respective queue is selected on the read port, the almost

empty flag provides status for that queue.

PROGRAMMABLE FLAG BUSSES

In addition to these dedicated flags, full & almost full on the write port and output

valid & almost empty on the read port, there are two flag status busses. An almost

full flag status bus is provided, this bus is 8 bits wide. Also, an almost empty flag

status bus is provided, again this bus is 8 bits wide. The purpose of these flag

busses is to provide the user with a means by which to monitor the data levels

within FIFO queues that may not be selected on the write or read port. As

mentioned, the device provides almost full and almost empty registers (program-

mable by the user) for each of the 8 FIFO queues in the device.

The 4 bit PAEn and 4 bit PAFn busses provide a discrete status of the Almost

Empty and Almost Full conditions of all 8 queue's. If the device is programmed

for less than 8 queue's, then there will be a corresponding number of active

outputs on the PAEn and PAFn busses.

The flag busses can provide a continuous status of all queues. If devices are

connected in expansion mode the individual flag busses can be left in a discrete

form, providing constant status of all queues, or the busses of individual devices

can be connected together to produce a single bus of 8 bits. The device can

then operate in a "Polled" or "Direct" mode.

When operating in polled mode the flag bus provides status of each device

sequentially, that is, on each rising edge of a clock the flag bus is updated to show

the status of each device in order. The rising edge of the write clock will update

the Almost Full bus and a rising edge on the read clock will update the Almost

Empty bus.

When operating in direct mode the device driving the flag bus is selected by

the user. The user addresses the device that will take control of a respective

flag bus, these PAFn and PAEn flag busses operating independently of one

another. Addressing of the Almost Full flag bus is done via the write port and

addressing of the Almost Empty flag bus is done via the read port.

PACKET READY

The 36 bit Multi-Queue FIFO also offers a ”Packet Ready” mode of operation,

this is user selectable and requires that the device be configured with both write

and read ports as 36 bits wide. The packet mode of operation provides

monitoring of “user marked” locations, when the user is writing data into a FIFO

queue a word being written in can be marked as a “Start of Packet” or “End of

Packet”. Internally as words are being written into the device with markers

attached, the device monitors these markers and provides a packet ready status

flag, which indicates when at least one full packet is available in a queue. The

read port therefore includes an additional status flag, “Packet Ready”, this flag

providing packet ready status for the queue currently selected on the read port

for read operations, indicating when at least one (or more) packets of data are

available to be read. When in packet ready mode the almost empty flag status

bus no longer provides almost empty status for individual quadrants, but instead

provides packet ready flag status for individual quadrants. (A packet is regarded

as any number of words written between a start of packet and end of packet

marker, packet sizes are user defined and sizes are not controlled or limited by

the device).

IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FIFO (8 QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

EXPANSION

Expansion of Multi-Queue devices is also possible, up to 8 devices can be

connected in a parallel fashion providing the possibility of both depth expansion

or queue expansion. Depth Expansion means expanding the depths of

individual queues. Queue expansion means increasing the total number of

queues available. Depth expansion is possible by virtue of the fact that more

memory blocks within a Multi-Queue device can be allocated to increase the

depth of a queue. For example, depth expansion of 8 devices provides the

possibility of 8 queues of 64K x36 deep, each queue being setup within a single

device utilizing all memory blocks available to produce a single queue. This is

the deepest FIFO queue that can setup within a device.

For queue expansion of the 8 queue device, a maximum number of 64 (8 x 8)

queues may be setup, each queue being 2K x36 deep, if less queues are setup,

then more memory blocks will be available to increase queue depths if desired.

When connecting Multi-Queue devices in expansion mode all respective input

pins (data & control) and output pins (data & flags), should be “connected”

together between individual devices.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FIFO (8 QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

BM Bus Matching LVTTL This pin is setup before Master Reset and must not toggle during any device operation. This pin is used

INPUT along with IW and OW to setup the FIFO bus width. Please refer to Table 3 for details.

D[35:0] Data Input Bus LVTTL These are the 36 data input pins. Data is written into the device via these input pins on the rising edge

Din INPUT of WCLK provided that WEN is LOW. Note, that in Packet Ready mode D32-D35 may be used as packet

markers, please see packet ready functional discussion for more detail. Due to bus matching not all inputs

may be used, any unused inputs should be tied LOW.

DF(1) Default Flag LVTTL If the user requires default programming of the Multi-Queue device, this pin must be setup before Master

INPUT Reset and must not toggle during any device operation. The state of this input at master reset determines

the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.

DFM(1) Default Mode LVTTL The Multi-Queue device requires programming after master reset. The user can do this serially via the

INPUT serial port, or the user can use the default method. If DFM is LOW at master reset then serial mode will be

selected, if HIGH then default mode is selected.

ERCLK RCLK Echo HSTL-LVTTL Read Clock Echo output, this output generates a clock based on the read clock input, this is used for

OUTPUT Source Synchronous clocking where the receiving devices utilizes the ERCLK to clock data output from

the FIFO.

EREN REN Echo HSTL-LVTTL Read Enable Echo output, can be used in conjunction with the ERCLK output to load data output from the

OUTPUT FIFO into the receiving device.

ESTR PAEn Flag Bus LVTTL If direct operation of the PAEn bus has been selected, the ESTR input is used in conjunction with RCLK

Strobe INPUT and the RDADD bus to select a device for its queues to be placed on to the PAEn bus outputs. A device

addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If

Polled operations has been selected, ESTR should be tied inactive, LOW.

ESYNC PAEn Bus Sync LVTTL ESYNC is an output from the Multi-Queue device that provides a synchronizing pulse for the PAEn bus

OUTPUT during Polled operation of the PAEn bus. During Polled operation each devices queue status flags are

loaded on to the PAEn bus outputs sequentially based on RCLK. The first RCLK rising edge loads device 1

on to PAEn, the second RCLK rising edge loads device 2 and so on. During the RCLK cycle that a selected

device is placed on to the PAEn bus, the ESYNC output will be HIGH.

EXI PAEn/PRn Bus LVTTL The EXI input is used when Multi-Queue devices are connected in expansion mode and Polled PAEn/

Expansion In INPUT PRn bus operation has been selected . EXI of device ‘N’ connects directly to EXO of device ‘N-1’. The

EXI receives a token from the previous device in a chain. In single device mode the EXI input should be

tied LOW if the PAEn/PRn bus is operated in direct mode. If the PAEn/PRn bus is operated in polled mode

the EXI input should be connected to the EXO output of the same device. In expansion mode the EXI of

the first device should be tied LOW, when direct mode is selected.

EXO PAEn/PRn Bus LVTTL EXO is an output that is used when Multi-Queue devices are connected in expansion mode and Polled

Expansion Out OUTPUT PAEn/PRn bus operation has been selected . EXO of device ‘N’ connects directly to EXI of device ‘N+1’.

This pin pulses HIGH when device N places its PAE status on to the PAEn/PRn bus with respect to RCLK.

This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising

edge the first quadrant of device N+1 will be loaded on to the PAEn/PRn bus. This continues through the

chain and EXO of the last device is then looped back to EXI of the first device. The ESYNC output of each

device in the chain provides synchronization to the user of this looping event.

FF Full Flag LVTTL This pin provides the full flag output for the active FIFO queue, that is, the queue selected on the input

OUTPUT port for write operations, (selected via WCLK, WRADD bus and WADEN). On the WCLK cycle after a

queue selection, this flag will show the status of the newly selected queue. Data can be written to this queue

on the next cycle provided FF is HIGH. This flag has High-Impedance capability, this is important during

expansion of devices, when the FF flag output of up to 8 devices may be connected together on a common

line. The device with a queue selected takes control of the FF bus, all other devices place their FF output

into High-Impedance. When a queue selection is made on the write port this output will switch from

High-Impedance control on the next WCLK cycle. This flag is synchronized to WCLK.

FM(1) Flag Mode LVTTL This pin is setup before a master reset and must not toggle during any device operation. The state of the

INPUT FM pin during Master Reset will determine whether the PAFn and PAEn flag busses operate in either Polled

or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct.

PIN DESCRIPTIONS

Symbol Name I/O TYPE Description

IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FIFO (8 QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTIONS (CONTINUED)

FSTR PAFn Flag Bus LVTTL If direct operation of the PAFn bus has been selected, the FSTR input is used in conjunction with WCLK

Strobe INPUT and the WRADD bus to select a device for its queues to be placed on to the PAFn bus outputs. A device

addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If

Polled operations has been selected, FSTR should be tied inactive, LOW.

FSYNC PAFn Bus Sync LVTTL FSYNC is an output from the Multi-Queue device that provides a synchronizing pulse for the PAFn bus

OUTPUT during Polled operation of the PAFn bus. During Polled operation each quadrant of queue status flags

is loaded on to the PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads

device1on to the PAFn bus outputs, the second WCLK rising edge loads device 2 and so on. During the

WCLK cycle that a selected device is placed on to the PAFn bus, the FSYNC output will be HIGH.

FXI PAFn Bus LVTTL The FXI input is used when Multi-Queue devices are connected in expansion mode and Polled PAFn

Expansion In INPUT bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI

receives a token from the previous device in a chain. In single device mode the FXI input should be tied

LOW if the PAEn bus is operated in direct mode. If the PAEn bus is operated in polled mode the FXI input

should be connected to the FXO output of the same device. In expansion mode the FXI of the first device

should be tied LOW, when direct mode is selected.

FXO PAFn Bus LVTTL FXO is an output that is used when Multi-Queue devices are connected in expansion mode and Polled

Expansion Out OUTPUT PAFn bus operation has been selected . FXO of device ‘N’ connects directly to FXI of device ‘N+1’. This

pin pulses HIGH when device N places its PAF status on to the PAFn bus with respect to WCLK. This pulse

(token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK rising edge the first

quadrant of device N+1 will be loaded on to the PAFn bus. This continues through the chain and FXO

of the last device is then looped back to FXI of the first device. The FSYNC output of each device in the

chain provides synchronization to the user of this looping event.

ID[2:0](1) Device ID Pins LVTTL For the 4Q Multi-Queue device the WRADD address bus is 5 bits and RDADD address bus is 6 bits wide.

INPUT When a queue selection takes place the 3 MSB’s of this address bus are used to address the specific device

(the LSB’s are used to address the queue within that device). During write/read operations the 3 MSB’s

of the address are compared to the device ID pins. The first device in a chain of Multi-Queue’s (connected

in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which is

‘111’, however the ID does not have to match the device order. In single device mode these pins should

be setup as ‘000’ and the 3 MSB’s of the WRADD and RDADD address busses should be tied LOW. The

ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during

any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.

IOSEL IO Select LVTTL This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are

INPUT required then IOSEL should be tied LOW. If LVTTL I/O are required then it should be tied HIGH.

IW(1) Input Width LVTTL This pin is used in conjunction with OW and BM to setup the input and output bus widths to be a combination

INPUT of x9, x18 or x36, (providing that one port is x36).

MAST(1) Master Device LVTTL The state of this input at Master Reset determines whether a given device (within a chain of devices), is

INPUT the Master device or a Slave. If this pin is HIGH, the device is the master, if it is LOW then it is a Slave.

The master device is the first to take control of all outputs after a master reset, all slave devices go to High-

Impedance, preventing bus contention. If a Multi-Queue device is being used in single device mode, this

pin must be set HIGH.

MRS Master Reset LVTTL A master reset is performed by taking MRS from HIGH to LOW, to HIGH. Device programming is required

INPUT after master reset.

NULL-Q Null Queue Select HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with th e RDADD

INPUT address bus to address the Null-Q.

OE Output Enable LVTTL The Output enable signal is an Asynchronous signal used to providethree-state control of the Multi-Queue

INPUT data output bus, Qout. If a devicehas been configured as a “Master” device, the Qout data outputs will be

in aLow Impedance condition if the OE input is LOW. If OE is HIGH then the Qout data outputs will be in

High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be in

High Impedance until that device has been selected on the Read Port, at which point OE provides three-

state of that respective device.

Symbol Name I/O TYPE Description

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FIFO (8 QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

OV Output Valid Flag LVTTL This output flag provides output valid status for the data word present on the Multi-Queue FIFO data output

OUTPUT port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That is, there is

a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time the OV flag represents

the data in that respective queue. When a selected queue on the read port is read to empty, the OV flag

will go HIGH, indicating that data on the output bus is not valid. The OV flag also has High-Impedance

capability, required when multiple devices are used and the OV flags are tied together.

OW(1) Output Width LVTTL This pin is setup during Master Reset and must not toggle during any device operation. This pin is used

INPUT in conjunction with IW and BM to setup the data input and output bus widths to be a combination of x9,

x18 or x36, (providing that one port is x36).

PAE Programmable LVTTL This pin provides the Almost-Empty flag status for the FIFO queue that has been selected on the output

Almost-Empty Flag OUTPUT port for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected

FIFO queue almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag

is synchronized to RCLK.

PAEn/PRn Programmable LVTTL On the 8Q device the PAEn/ PRn bus is 8 bits wide. During a Master Reset this bus is setup for either

Almost-Empty Flag OUTPUT Almost Empty mode or Packet Ready mode. This output bus provides PAE/ PRn status of all 8 queues,

Bus/Packet Ready within a selected device. During FIFO read/write operations these outputs provide programmable empty

Flag Bus flag status or packet ready status, in either director polled mode. The mode of flag operation is determined

during master reset via the state of the FM input. This flag bus is capable of High-Impedance state, this

is important during expansion of Multi-Queue devices. During direct operation the PAEn/ PRn bus is

to show the PAE/PR status of queues within a selected device. Selection is made using RCLK, ESTR and

RDADD. During Polled operation the PAEn/ PRn bus is loaded with the PAE/ PRn status of Multi-Queue

FIFO devices sequentially based on the rising edge of RCLK. PAE or PR operation is determined by the

state of PKT during master reset.

PAF Programmable LVTTL This pin provides the Almost-Full flag status for the FIFO queue that has been selected on the input

Almost-Full Flag OUTPUT port for write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected

FIFO queue is almost-full. This flag output may be duplicated on one of the PAFn bus lines. This flag is

synchronized to WCLK.

PAFn Programmable LVTTL On the 8Q device the PAFn bus is 8 bits wide. This output bus provides PAF status of all 8 queues, within

Almost-Full Flag Bus OUTPUT a selected device. During FIFO read/write operations these outputs provide programmable full flag status,

in either direct or polled mode. The mode of flag operation is determined during master reset via the state

of the FM input. This flag bus is capable of High-Impedance state, this is important during expansion of

Multi-Queue devices. During direct operation the PAFn bus is updated to show the PAF status of a queues

within a selected device. Selection is made using WCLK, FSTR, WRADD and WADEN. During Polled

operation the PAFn bus is loaded with the PAF status of Multi-Queue FIFO devices sequentially based

on the rising edge of WCLK.

PD Power Down HSTL This input is used to provide additional power savings. When the device I/O is setup for HSTL/eHSTL

INPUT mode a HIGH on the PD input disables the data inputs on the write port only, providing significant power

savings. In LVTTL mode this pin has no operation

PKT(1) Packet Mode LVTTL The state of this pin during a Master Reset will determine whether the part is operating in Packet Ready

INPUT mode providing both a Packet Ready (PR) output and a Programmable Almost Empty (PAE) discrete

output, or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part

will operate in packet ready mode, if it is LOW then almost empty mode. If packet mode has been selected

the read port flag bus becomes packet ready flag bus, PRn and the discrete packet ready flag, PR is

functional. If almost empty operation has been selected then the flag bus provides almost empty status, PAEn

and the discrete almost empty flag, PAE is functional, the PR flag is inactive and should not be connected.

Packet Ready utilizes user marked locations to identify start and end of packets being written into the device.

Packet Mode can only be selected if both the input port width and output port width are 36 bits.

PR Packet Ready Flag LVTTL If packet ready mode has been selected this flag output provides Packet Ready status of the FIFO queue

OUTPUT selected for read operations. During a master reset the state of the PKT input determines whether Packet

mode of operation will be used. If Packet mode is selected, then the PR flag becomes a valid output, from

which the user can determine if a selected FIFO queue has a “complete” packet of data available for reading.

The user must mark the start of a packet and the end of a packet when writing data into a queue. Using

PIN DESCRIPTIONS (CONTINUED)

Symbol Name I/O TYPE Description

IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FIFO (8 QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTIONS (CONTINUED)

Symbol Name I/O TYPE Description

PR Packet Ready Flag LVTTL these Start Of Packet (SOP) and End Of Packet (EOP) markers, the Multi-Queue device sets PR LOW

(Conitnued) OUTPUT if one or more “complete” packets are available in the queue.

PRS Partial Reset LVTTL A Partial Reset can be performed on a single queue selected within the Multi-Queue device. Before a Partial

INPUT Reset can be performed on a queue, that queue must be selected on both the write port and read port

2 clock cycles before the reset is performed. A Partial Reset is then performed by taking PRS LOW for

one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to

the first memory location, none of the devices configuration will be changed.

Q[35:0] Data Output Bus LVTTL These are the 36 data output pins. Data is read out of the device via these output pins on the rising edge

Qout OUTPUT of RCLK provided that REN is LOW, OE is LOW and the FIFO queue is selected. Note, that in Packet Ready

mode Q32-Q35 may be used as packet markers, please see packet ready functional discussion for more

detail. Due to bus matching not all outputs may be used, any unused outputs should not be connected.

RADEN Read Address Enable LVTTL The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to

INPUT be read from. A FIFO queue addressed via the RDADD bus is selected on the rising edge of RCLK

provided that RADEN is HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR.

RCLK Read Clock LVTTL When enabled by REN, the rising edge of RCLK reads data from the selected FIFO queue via the output

INPUT bus Qout. The FIFO queue to be read is selected via the RDADD address bus and a rising edge of RCLK

while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the

device to be placed on the PAEn/PRn bus during direct flag operation. During polled flag operation the

PAEn/PRn bus is cycled with respect to RCLK and the ESYNC signal is synchronized to RCLK. The PAE,

PR and OV outputs are all synchronized to RCLK. During device expansion the EXO and EXI signals

are based on RCLK. RCLK must be continuous and free-running.

RDADD Read Address Bus LVTTL For the 8Q device the RDADD bus is 7 bits. The RDADD bus is a dual purpose address bus. The first

[6:0] INPUT function of RDADD is to select a FIFO queue to be read from. The least significant 3 bits of the bus,

RDADD[2:0] are used to address 1 of 8 possible queues within a Multi-Queue device. Address pin,

RDADD[3] provides the user with a Null-Q address. If the user does not wish to address one of the 8 queues,

a Null-Q can be addressed using this pin. The Null-Q operation is discussed in more detail later. The most

significant 3 bits, RDADD[6:4] are used to select 1 of 8 possible Multi-Queue devices that may be connected

in expansion mode. These 3 MSB’s will address a device with the matching ID code. The address present

on the RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that

data can be placed on to the Qout bus, read from the previously selected FIFO queue on this RCLK edge).

On the next rising RCLK edge after a read queue select, a data word from the previous queue will be

placed onto the outputs, Qout, regardless of the REN input. Two RCLK rising edges after read queue select,

data will be placed on to the Qout outputs from the newly selected queue, regardless of REN due to the

first word fall through effect.

The second function of the RDADD bus is to select the device of FIFO queues to be loaded on to the

PAEn/PRn bus during strobed flag mode. The most significant 3 bits, RDADD[6:4] are again used to select 1

of 8 possible Multi-Queue devices that may be connected in expansion mode. Address bits RDADD[3:0]

are don’t care during device selection. The device address present on the RDADD bus will be selected

on the rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout

bus, read from the previously selected FIFO Q on this RCLK edge). Please refer to Table 2 for details

on RDADD bus.

REN Read Enable LVTTL The REN input enables read operations from a selected FIFO queue based on a rising edge of RCLK.

INPUT A queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless

of the state of REN. Data from a newly selected queue will be available on the Qout output bus on the second

RCLK cycle after queue selection regardless of REN due to the FWFT operation. A read enable is not

required to cycle the PAEn/PRn bus (in polled mode) or to select the device , (in direct mode).

SCLK Serial Clock LVTTL If serial programming of the Multi-Queue device has been selected during master reset, the SCLK input

INPUT clocks the serial data through the Multi-Queue device. Data setup on the SI input is loaded into the device

on the rising edge of SCLK provided that SENI is enabled, LOW. When expansion of devices is performed

the SCLK of all devices should be connected to the same source.

SENI Serial Input Enable LVTTL During serial programming of a Multi-Queue device, data loaded onto the SI input will be clocked into the

INPUT part (via a rising edge of SCLK), provided the SENI input of that device is LOW. If multiple devices are

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FIFO (8 QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

PIN DESCRIPTIONS (CONTINUED)

Symbol Name I/O TYPE Description

SENI Serial Input Enable LVTTL cascaded, the SENI input should be connected to the SENO output of the previous device. So when serial

(Continued) INPUT loading of a given device is complete, its SENO output goes LOW, allowing the next device in the chain

to be programmed (SENO will follow SENI of a given device once that device is programmed). The SENI

input of the master device (or single device), should be controlled by the user.

SENO Serial Output Enable LVTTL This output is used to indicate that serial programming or default programming of the Multi-Queue device

OUTPUT has been completed. SENO follows SENI once programming of a device is complete. Therefore, SENO

will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENO will also

go HIGH. When the SENO output goes LOW, the device is ready to begin normal read/write operations.

If multiple devices are cascaded and serial programming of the devices will be used, the SENO output

should be connected to the SENI input of the next device in the chain. When serial programming of the

first device is complete, SENO will go LOW, thereby taking the SENI input of the next device LOW and

so on throughout the chain. When a given device in the chain is fully programmed the SENO output

essentially follows the SENI input. The user should monitor the SENO output of the final device in the chain.

When this output goes LOW, serial loading of all devices has been completed.

SI Serial In LVTTL During serial programming this pin is loaded with the serial data that will configure the Multi-Queue devices.

INPUT Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion

mode the serial data input is loaded into the first device in a chain. When that device is loaded and its SENO

has gone LOW, the data present on SI will be directly output to the SO output. The SO pin of the first device

connects to the SI pin of the second and so on. The Multi-Queue device setup registers are shift registers.

SO Serial Out LVTTL This output is used in expansion mode and allows serial data to be passed through devices in the chain

OUTPUT to complete programming of all devices. The SI of a device connects to SO of the previous device in the

chain. The SO of the final device in a chain should not be connected.

TCK JTAG Clock LVTTL Clock input for JTAG function. TMS and TDI are sampled on the rising edge of TCK. TDO is output on

INPUT the falling edge of TCK.

TDI Test Data Input LVTTL During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK.

INPUT This is also the data for the Instruction Register, JTAG ID Register and Bypass Register.

TDO Test Data Output LVTTL During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK.

INPUT This output is in High-Impedance except when shifting data while in SHIFT-DR and SHIFT-IR controller

states.

TMS JTAG Mode Select LVTTL TMS is a serial input pin. Bits are serially loaded on the rising edge of TCK, which selects 1 of 5 modes

INPUT of operation for the JTAG boundary scan.

TRST JTAG Reset LVTTL TRST is the asynchronous reset pin for the JTAG controller.If the JTAG port is not utilized, TRST should

INPUT be tied to GND.

WADEN Write Address Enable LVTTL The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to

INPUT be written in to. A FIFO queue addressed via the WRADD bus is selected on the rising edge of WCLK

provided that WADEN is HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR.

WCLK Write Clock LVTTL When enabled by WEN, the rising edge of WCLK writes data into the selected FIFO queue via the input

INPUT bus, Din. The FIFO queue to be written to is selected via the WRADD address bus and a rising edge

of WCLK while WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also

select the device to be placed on the PAFn bus during direct flag operation. During polled flag operation

the PAFn bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK. The PAFn,

PAF and FF outputs are all synchronized to WCLK. During device expansion the FXO and FXI signals

are based on WCLK. The WCLK must be continuous and free-running.

WEN Write Enable LVTTL The WEN input enables write operations to a selected FIFO queue based on a rising edge of WCLK.

INPUT A queue to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless

of the state of WEN. Data present on Din can be written to a newly selected queue on the second WCLK

cycle after queue selection provided that WEN is LOW. A write enable is not required to cycle the PAFn

bus (in polled mode) or to select the device , (in direct mode).

WRADD Write Address Bus LVTTL For the 8Q device the WRADD bus is 6 bits. The WRADD bus is a dual purpose address bus. The first

[5:0] INPUT function of WRADD is to select a FIFO queue to be written to. The least significant 3 bits of the bus,

IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FIFO (8 QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WRADD Write Address Bus LVTTL WRADD[2:0] are used to address 1 of 8 possible queues within a Multi-Queue device. The most significant

[5:0] INPUT 3 bits, WRADD[5:3] are used to select 1 of 8 possible Multi-Queue devices that may be connected in

(Continued) expansion mode. These 3 MSB’s will address a device with the matching ID code. The address present

on the WRADD bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that

data present on the Din bus can be written into the previously selected FIFO queue on this WCLK edge

and on the next rising WCLK also, providing that WEN is LOW). Two WCLK rising edges after write queue

elect, data can be written into the newly selected queue.

The second function of the WRADD bus is to select the device of FIFO queues to be loaded on to the

PAFn bus during strobed flag mode. The most significant 3 bits, WRADD[5:3] are again used to select

1 of 8 possible Multi-Queue devices that may be connected in expansion mode. Address bits WRADD[2:0]

are don’t care during device selection. The device address present on the WRADD bus will be selected

on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be written into the previously

selected FIFO queue on this WCLK edge). Please refer to Table 1 for details on the WRADD bus.

VCC +2.5V Supply Power These are VCC power supply pins and must all be connected to a +2.5V supply rail.

VDDQ O/P Rail Voltage Power These pins must be tied to the desired output rail voltage. For LVTTL I/O these pins must be connected

to +2.5V, for HSTL these pins must be connected to +1.5V and for eHSTL these pins must be connected

to +1.8V.

GND Ground Pin Power These are Ground pins and must all be connected to the GND supply rail.

Vref Reference Voltage HSTL This is a Voltage Reference input and must be connected to a voltage level determined from the table

INPUT "Recommended DC Operating Conditions". The input provides the reference level for HSTL/eHSTL

inputs. For LVTTL I/O mode this input should be tied to GND.

PIN DESCRIPTIONS (CONTINUED)

NOTE:

1. Inputs should not change after Master Reset.

Symbol Name I/O TYPE Description

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 408-330-1753

Santa Clara, CA 95054 fax: 408-492-8674 email: FIFOhelp@idt.com

www.idt.com

ORDERING INFORMATION

NOTE:

1. Industrial temperature range product for 6ns and 7-5ns speed grades are available as a standard device. All other speed grades available by special order.

Plastic Ball Grid Array (PBGA, BB256-1)

Commercial (0°C to +70°C)

lndustrial (-40°C to +85°C)

Low Power

6114 drw35

IDT XXXXX

Device Type

Power

Speed

Package

Process /

Temperature

Range

BLANK

(1)

72T51336 589,824 bits  2.5V Multi-Queue FIFO

72T51346 1,179,648 bits  2.5V Multi-Queue FIFO

72T51356 2,359,296 bits  2.5V Multi-Queue FIFO

Commercial Only

Commercial & Industrial

Commercial & Industrial Clock Cycle Time (t

CLK

)

Speed in Nanoseconds

7-5