TC500ACPEG - Microchip Technology

TC500/A/510/514

Features:

• Precision (up to 17 bits) A/D Converter “Front

End”

• 3-Pin Control Interface to Microprocessor

• Flexible: User Can Trade-off Conversion Speed

for Resolution

• Single-Supply Operation (TC510/TC514)

• 4 Input, Differential Analog MU X (TC514)

• Automatic Input Voltage Polarity Detection

• Low Power Dissipation:

- (TC 500/TC500A): 10 mW

- (TC 510/TC514): 18 mW

• Wide Analog Input Range:

- ±4.2V (TC500A/TC510)

• Direct ly Accep t s Bipo lar and Differenti al

Input Signals

Applications:

• Precision Analog Signal Processor

• Precision Sensor Interface

• High Accurac y DC Me as urem en t s

General Description:

TheTC500/A/510/514 family are precision analog front

ends that implement dual slope A/D converters having

a maximum resolution of 17 bits plus sign. As a

minimum, each device contains the integrator, zero

crossi ng comp arator and processor interface logic. Th e

TC500 is the base (16-bit max) device and requires

both positive and negative power supplies. The

TC500A is identical to the TC500 with the exception

that it has improved linearity, allowing it to operate to a

maxim um resolutio n of 17 bits. T he TC510 adds an o n-

board negative power supply converter for single-

supply operation. The TC514 adds both a negative

power supply converter and a 4-input differential

analog multiplexer.

Each device has the same processor control interface

consis ting of 3 wires: contr ol inputs (A and B) and zero-

crossing comparator output (CMPTR). The processor

manipu late s A, B to s eq uen ce the TC5XX throug h fo ur

phases of conversion: auto-zero, integrate, de-inte-

grate and integrator zero. During the auto-zero phase,

of fset v ol tages in t he TC5XX are c orrec te d by a clo se d

loop fee dback m echanis m. The i nput vol tag e is app lied

to the integrator during the integrate phase. This

causes an integrator output dv/dt directly proportional

to the magnitude of the input voltage. The higher the

input voltage, the greater the magnitude of the voltage

stored on the integrator during this phase. At the start

of the de-integrate phase, an external voltage

refe renc e is app lie d t o the int egra tor and, at the same

time, the external host processor starts its on-board

timer. The processor maintains this state until a

transition occurs on the CMPTR output, at which time

the processor halts its timer. The resulting timer count

is the conv erted a nalog data. In tegr ator zero ( the fi nal

phase of conversion) removes any residue remaining

in the integrator in preparation for the next conversion.

The TC500/A/510/514 offer high resolution (up to 17

bits), superior 50/60 Hz noise rejection, low-power

operation, minimum I/O connections, low input bias

currents and lower cost compared to other converter

technologies having similar conversion speeds.

Precision Analog Front Ends

TC500/A/510/514

Package Types

Typical Application

CMPTR OUT

DGND

VDD

VIN+

VIN–

VREF+

BUF

VSS

CINT

ACOM

VREF−

CREF+

CREF–

CAZ

TC500/

TC500A

16-Pin PDIP/SOIC/CERDIP

VOUT–1

CAP–

DGND

CREF–

CINT

CAZ

BUF

ACOM

CH4–

CH3–

CH2–

TC514

CREF+

VREF–

VREF+

VDD

OSC

CMPTR OUT

CAP+

CH1–

N/C

CH1+

CH2+

CH3+

CH4+

28-Pin PDIP/SOIC

24-Pin PDIP/SOIC

TC510

CAP–

DGND

VDD

OSC

CMPTR OUT

VIN+

VIN–

N/C

CAP+

CREF–

CINT

CAZ

BUF

ACOM

N/C

VOUT–

CREF+

VREF–

VREF+

Level

Shift

Control Logic

Analog

Switch

Control

Signals

ACOM

VREF+BUF

CAZ

Buffer Integrator

SWR

SWIZ

CMPTR 1 CMPTR 2

CMPTR

Output

DGND

Control Logic

SW1

TC500

TC500A

TC510

TC514

CREF

CREF+

SWR

CREF-CAZ

RINT CINT

CINT

SWRI-SWRI-

SWRI+SWRI-

SWZ

SWI

SWZ

VSS

OSC

Phase

Decoding

Logic

Polarity

Detection

DC-TO-DC

Converter

(TC510 & TC514)

A B

0 0 Zero Integrator Output

0 1 Auto-Zero

1 0 Signal Integrate

1 1 De-integrate

VREF-

VOUT-

COUT-

1.0 μF1.0 μFVSS

SWI

A0 A1

DIF.

MUX

(TC514)

CH1+

CH2+

CH3+

CH4+

CH1-

CH2-

CH3-

CH4-

CAP- CAP+

(TC500

TC500A)

Converter Sate

TC500/A/510/514

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings†

TC510/TC514 Positive Supply Voltage

(VDD to GND) .........................................+10.5V

TC500/TC500A Supply Voltage

(VDD to VSS)..............................................+18V

TC500/TC500A Positive Supply Voltage

(VDD to GND) ............................................+12V

TC500/TC500A Negative Supply Voltage

(VSS to GND)............... ...... ...... ..... ...... ..........-8V

Analog Input Voltage (VIN+ or VIN-) ............VDD to VSS

Logic Input Voltage...............VDD +0.3V to GND - 0.3V

Voltage on OSC:

........................... -0.3V to (VDD +0.3V) for VDD < 5.5V

Ambient Operating Temperature Range:

................................................................0°C to +70°C

Storage Temperature Range:.............-65°C to +150°C

† Stresses above those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the

device. These are stress ratings only and functional

operatio n of the devic e at these or an y other con ditions

above those indicated in the operation sections of the

specifications is not implied. Exposure to Absolute

Maximum Rating conditions for extended periods may

affect device reliability.

DC CHARACTERISTICS

Electrical Specifications: Unless otherwise specified, TC510/TC514: VDD = +5V, TC500/TC500A: VSS = ±5V.

CAZ = CREF = 0.47 μF.

Parameters Sym TA = +25°C TA = 0°C to 70°C Units Conditions

Min. Typ. Max. Min. Typ. Max.

Analog

Resolution 60 — — — — — μVNote 1

Zero-scale Er ror with

Auto-zero Phase ZSE — — 0.005 — 0.005 0.012 % F.S. TC500/TC510/TC514

— — 0.003 — 0.003 0.009 TC500A

End Point Linearity ENL — 0.005 0.015 — 0.015 0.060 % F.S. TC500/TC510/TC514

— — 0.010 — 0.010 0.045 % F.S. Note 1, Note 2,

TC500A

Best-Case Straight

Line Linearity NL — 0.003 0.008 — — — % F.S. TC500/TC510/TC514,

Note 1, Note 2

— — 0.005 — — — % F.S. TC500A

Zero-scale Temp.

Coefficient ZSTC ——— —1 2μV/°C Over Operating

Temperature Range

Full-scale Symmetry

Error (Rollover Error) SYE — 0.01 — — 0.03 — % F. S. Note 1

Full-scale

Temperature

Coefficient

FSTC — — — — 10 — ppm/°C Over Operating

Temperature Range;

External Reference

TC = 0 ppm/°C

Input Current IIN —6— ——— pAV

IN = 0V

Common Mode

Voltage Range VCMR VSS + 1.5 — V DD – 1.5 VSS + 1.5 — VDD – 1.5 V

Integrator Output

Swing VSS + 0.9 — VDD – 0.9 VSS + 0.9 — VSS + 0.9 V

Analog Input Signal

Range VSS + 1.5 — VDD – 1.5 VSS + 1.5 — VSS + 1.5 V ACOM = GND = 0V

Note 1: Integrate time ≥ 66 msec, auto-zero time ≥ 66 msec, VINT (peak) ≈ 4V.

2: End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment.

3: Rollover error is related to CINT, CREF, CAZ characteristics.

TC500/A/510/514

Voltage Reference

Range VREF VSS +1 — VDD – 1 VSS +1 — VDD – 1 V VREF- VREF+

Digital

Comparator Logic 1,

Output High VOH 4—— 4 — — VI

SOURCE = 400 μA

Comparator Logic 0,

Output Low VOL — — 0.4 — — 0.4 V ISINK = 2.1 mA

Logic 1, Input High

Voltage VIH 3.5 — — 3.5 — — V

Logic 0, Input Low

Voltage VIL —— 1 — — 1 V

Logic Input Current IL—— — — 0.3 μA Logic ‘1’ or ‘0’

Comparator Delay tD—2 — — 3—μsec

Multiplexer (TC514 Only)

Maximum Input

Voltage -2.5 — 2.5 -2 .5 — 2.5 V VDD = 5V

Drain/Source ON

Resistance RDSON — 6 10 — — — kΩVDD = 5V

Power (TC510/TC514 Only)

Supply Current IS— 1.8 2.4 — — 3.5 mA VDD = 5V, A = 1, B = 1

Power Dissipation PD—18— — — —mWV

DD = 5V

Positive Supply

Operating Voltage

Range

VDD 4.5 — 5.5 4.5 — 5.5 V

Operating Source

Resistance ROUT — 60 85 — — 100 ΩIOUT = 10 mA

Oscillator Frequency — 100 — — — — kHz Note 1

Maximum Current

Out IOUT — — -10 — — -10 mA VDD = 5V

Power (TC500/TC500A Only)

Supply Current IS— 1 1.5 — — 2.5 mA VS = ±5V, A = B = 1

Power Dissipation PD—10— — — —mWV

DD = 5V, VSS = -5V

Positive Supply

Operating Range VDD 4.5 — 7.5 4.5 — 7.5 V

Negative Supply

Operating Range VSS -4.5 — -7.5 - 4.5 — -7.5 V

DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, TC510/TC514: VDD = +5V, TC500/TC500A: VSS = ±5V.

CAZ = CREF = 0.47 μF.

Parameters Sym TA = +25°C TA = 0°C to 70°C Units Conditions

Min. Typ. Max. Min. Typ. Max.

Note 1: Integrate time ≥ 66 msec, auto-zero time ≥ 66 msec, VINT (peak) ≈ 4V.

2: End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment.

3: Rollover error is related to CINT, CREF, CAZ characteristics.

TC500/A/510/514

2.0 TYPICAL PERFORMANCE CURVES

FIGURE 2-1: Output Voltage vs. Load

Current.

FIGURE 2-2: Output Ripple vs. Load

Current.

FIGURE 2-3: Oscillator Frequency vs.

Capacitance.

FIGURE 2-4: Output Voltage vs. Output

Current.

FIGURE 2-5: Output Source Resistance

vs. Temperature.

FIGURE 2-6: Oscillator Frequency vs.

Temperature.

Note: The g r ap hs and t ables prov id ed followi ng thi s n ote are a sta tis tic al s umm ar y b as ed on a limite d n um ber of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Load Current (mA)

-5

-4

-3

-2

-1

010 20 30 40 50 60 70 80

Output Voltage (V)

= +25°C

V+ = 5V

Slope 60Ω

Load Current (mA)

0 3 45612 78 910

100

125

150

175

200

Output Ripple (mV PK-PK)

V+ = 5V, TA = +25°C

Osc. Freq. = 100 kHz

CAP = 1 µF

CAP = 10 µF

Oscillator Capacitance (pF)

100

110 100 1000

Oscillator Frequency (kHz)

TA = +25°C

V+ = 5V

Output Current (mA)

068104214161812 20

-0

-1

-3

-2

-4

-5

-7

-6

-8

Output Voltage (V)

TA = +25°C

Temperature (°C)

100

-50 025

-25 50 75 100

Output Source Resistance (Ω)

V+ = 5V

OUT

= 10 mA

Temperature (°C)

125

150

100

-50 025-25 50 75 125100

Oscillator Frequency (kHz)

V+ = 5V

TC500/A/510/514

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

Pin No.

Symbol Function

TC500,

TC500A TC510 TC514

12 2C

INT Integrator output. Integrator capacitor connection.

2 Not Used Not Used VSS Negative power supply input (TC500/TC500A only).

33 3C

AZ Auto-zero input. The auto-zero capacitor connection.

4 4 4 BUF Buffer output. The Integrator capacitor connection.

5 5 5 ACOM This pin is grounded in most applications. It is recommended that ACOM and the

input common pin (V en- o r CHn-) be within the analog Common Mode Range (CMR).

66 6C

REF- Input. Negative reference capacitor connection.

77 7C

REF+ Input. Positive reference capacitor connection.

88 8V

REF- Input . External voltage reference (-) connection.

99 9V

REF+ Input. External voltage reference (+) connection.

10 15 Not Used VIN- Negative analog input.

11 16 Not Used VIN+ Positive analog input.

12 18 22 A Input. Converter phase cont rol MSB. (See input B.)

13 17 21 B Input. Converter phase control LSB. The states of A, B place the TC5XX in one of

four required phases. A conversion is complete when all four phases have been

executed:

Phase control input pins: AB = 00: Integrator zero

01: Auto-zero

10: Integrate

11: De-integrate

14 19 23 CMPTR

OUT Zero crossing comparator output. CMPTR is high during the integration phase when

a positive input voltage is being integrated and is low when a negative input voltage

is being integrated. A high-to-low transition on CMPTR signals the processor that the

De-integrate phase is completed. CMPTR is undefined during the auto-zero phase. It

should be monitored to time the integrator zero phase.

15 23 27 DGND Input. Digital ground.

16 21 25 VDD Input. Power supply positive connection.

— 22 26 CAP+ Input. Negative power supply converter capacitor (+) connection.

— 24 28 CAP- Input. Negative power supply converter capacitor (-) connection.

—1 1V

OUT- Output. Negative power supply converter output and reservoir capacitor connection.

This output can be used to power other devices in the circuit requiring a negative

bias voltage.

— 20 24 OSC Oscillator control input. The negative power supply converter normally runs at a

frequency of 100 kHz. The converter oscillator frequency can be slowed down (to

reduce quiescent current) by connecting an external capacit or between this pin and

VDD (see Section 2.0 “Typical Performance Curves”).

— — 18 CH1+ Positive analog input pin. MUX channel 1.

— — 13 CH1- Negative analog input pin. MUX channel 1.

— — 17 CH2+ Positive analog input pin. MUX channel 2.

— — 12 CH2- Negative analog input pin. MUX channel 2.

— — 16 CH3+ Positive analog input pin. MUX channel 3.

— — 11 CH3- Negative analog input pin. MUX channel 3.

— — 15 CH4+ Positive analog input pin. MUX channel 4.

— — 10 CH4- Negative analog input pin. MUX channel 4

— — 20 A0 Multiplexer input channel select input LSB (see A1).

— — 19 A1 Multiplexer input channel select input MSB.

Phase control input pins: A1, A0 = 00 = Channel 1

01 = Channel 2

10 = Channel 3

11 = Channel 4

TC500/A/510/514

4.0 DETAILED DESCRIPTION

4.1 Dual Slope Conversion Principles

Actual data conversion is accomplished in two

phas es: inp ut s ign al int egra tio n and refe rence vol ta ge

de-integration.

The integrator output is initialized to 0V prior to the start

of integration. During integration, analog switch S1 con-

nects VIN to the integrat or input where it is maintaine d

for a fixed time period (TINT). The application of VIN

causes the integrator output to depart 0V at a rate deter-

mined by the magnitude of VIN and a direction deter-

mined by the polarity of VIN. The de-integration phase is

initiated immediately at the expiration of TINT.

During de-int egratio n, S1 c onnec ts a refe rence volt age

(having a pola rity opp os ite th at of VIN) to the integra tor

input. At the same time, an external precision timer is

started. The de-integration phase is maintained until

the comparator output changes state, indicating the

integrator has returned to its starting point of 0V. When

this occurs, the precision timer is stopped. The de-

integration time period (TDEINT), as measured by the

precisi on timer , is directly pro portional to the magn itude

of the applied input voltage (see Figure 4-3).

A simple mathematical equation relates the input

signal, reference voltage and integration time:

EQUATION 4-1:

For a constant VIN:

EQUATION 4-2:

The dual slope conv erter accuracy is unrelated to the

integrating resistor and capacitor values as long as

they are stable during a measurement cycle.

An inherent benefit is noise immunity. Input noise

spikes are integrated (averaged to zero) during the

integration periods. Integrating ADCs are immune to

the large conversion errors that plague successive

approximation converters in high noise environments.

Integrating converters provide inherent noise rejection

with at least a 20dB/decade attenuation rate.

Interference signals with frequencies at integral

multiples of the integration period are, theoretically,

comple tel y re mo ved , s inc e th e av erage value of a s in e

wave of frequency (1/T) averaged over a period (T) is

zero.

Integrating converters often establish the integration

period to reject 50/60 Hz line frequency interference

signal s. The abi li ty t o re jec t s uc h s ig nal s is sh ow n by a

normal mode rejection plot (Figure 4-1). Normal mode

rejection is limited in practice to 50 to 65 dB, since the

line freq uency can de via t e by a f ew te nth s o f a pe rce nt

(Figure 4-2).

FIGURE 4-1: Integrati ng Conv erte r

Normal Mode Rejection.

FIGURE 4-2: Line Frequency Deviation.

Where:

VREF = Reference Vo ltage

TINT = Signal Inte gra tion time (fixed)

tDEINT = Reference V olt age In tegration t ime (variabl e

)

RINTCINT

------------------------VIN T()DT

TINT

∫VREFCDEINT

RINTCINT

--------------------------------

VIN VREFTDEINT

TINT

------------------

0.1/T 1/T 10/T

Input Frequency

Normal Mode Rejection (dB)

T = Measurment

Period

0.01 0.1 1.0

Normal Mode Rejeciton (dB)

t = 0.1 sec

Line Frequency Deviation from 60 Hz (%)

Normal Mode

REJECTION

= 20 LOG

DEV = Deviation from 60 Hz

t = Integration Period

SIN 60 t (1 ± )

DEV

100

DEV

100

60 t (1 ± )

TC500/A/510/514

FIGURE 4-3: Basic Dual Slope Converter.

Phase

Control

Comparator

Integrator

Output

Integrator

CINT

Analog

Input (VIN)

Switch Driver

Ref

Voltage Control

Logic

Polarity Control

I/O

Timer

Counter

ROM

RAM

Microcomputer

CMPTR Out

VSUPPLY

TINT

TC510

VINT

VIN ≈ VREF

VIN ≈ 1/2 VREF

TDEINT

–

RINT VINT

–

TC500/A/510/514

5.0 TC500/A/510/514 CONVERTER

OPERATION

The TC500/A/510/514 incorporates an auto-zero and

Integr ator phase in addition to t he input signal Integrate

and reference De-integrate phases. The addition of

these phases reduce system errors, calibration steps

and shorten overrange recovery time. A typical

measurement cycle uses all four phases in the

following order:

1. Auto-zero.

2. Input signal integration.

3. Reference de-integration.

4. Integrator output zero.

The internal analog switch status for each of these

phases is summarized in Table 5-1. This table

reference s the Typical Applic ati on.

TABLE 5-1: INTERNAL ANALOG GATE STATUS

5.1 Auto-zero Phase (AZ)

During this phase, errors due to buffer, integrator and

comparator offset voltages are nulled out by charging

CAZ (auto-zero capacitor) with a compensating error

voltage.

The external input signal is disconnected from the

inter nal ci rcu itry by ope nin g th e two SWI switches. The

internal input points connect to analog common. The

reference capacitor is charged to the reference voltage

potential through SWR. A feedback l oop, closed aroun d

the integrator and comparator, charges the capacitor

(CAZ) wit h a v oltage to c ompensate for buf fer am pl ifie r,

integrator and comparator offset voltages.

5.2 Analog Input Signal Integration

Phase (INT)

The TC5XX integrates the differential voltage between

the VIN+ and VIN– inputs. The differential voltage must

be wi thin the dev ice’s C ommon mode ra nge VCMR. The

input si gnal pola rity is no rmally c hecked v ia softw are at

the end of this phase: CMPTR = 1 for positive polarity;

CMPTR = 0 for negative polarity.

5.3 Reference Volt age De-integration

Phase (DINT)

The previously charged reference capacitor is

connected with the proper polarity to ramp the

integrator output back to zero. An externally-provided,

precision timer is used to measure the duration of this

phase. Th e resul ting ti me measu remen t is prop ortiona l

to the magnitude of the applied input voltage.

5.4 Integrator Output Zero Phase (IZ)

This phase ensures the integrator output is at 0V when

the auto-zero phase is entered, and that only system

of fset volt ages are comp ensated. This pha se is used at

the end of the reference voltage de-integration phase

and MUST be use d for ALL TC5XX applicati ons having

resoluti ons of 12-bit s or more . If this phase i s not u sed,

the value of the auto-zero capacitor (CAZ) must be

about 2 to 3 times the value of the integration capacitor

(CINT) to reduc e the effec ts of char ge sharing. The inte-

grator output zero phase should be programmed to

operate until the ou tpu t of th e c omparato r re turns h ig h.

The overall timing system is shown in Figure 5-1.

Conversion Phase SWISWR+SW

R-SW

ZSWRSW1SWIZ

Auto-zero (A = 0, B = 1) — — — Closed Closed Closed —

Input Signal Integration (A = 1, B = 0) Closed — — — — — —

Reference Voltage De-integration

(A =1, B = 1) — *

Closed — — — Closed —

Integrator Output Zero (A = 0, B = 0) — — — — Closed Closed Close d

* Assumes a positive polarity input signal. SW–RI would be closed for a negative input signal.

TC500/A/510/514

FIGURE 5-1: Typical Dual Slope A/D Converter System Timing.

Auto-zero Integrate

Full-scale Input Reference

De-integrate Overshoot Integrator

Output

Zero

Converter Status

TTIME

Integrator

Voltage VINT

Comparator

Output

AB Inputs

Controller

Operation

Notes:

Comparator Delay

Begin Co nver sion with

Auto-Zero Phase

(Pos itive Input Shown)

Sample Input Pola rity

The length of this phase is chosen almost arbitrarily

but needs to be long enough to null out worst case errors

(see text ).

Minimizing

Overshoot

will Minimize

I.O.Z. Time

Ready for Next

Conversion

(Auto-Zero is

Idle State)

Time Input

Integration

Phase

Capture

De-integration

Time

Integrator

Output

Zero Phase

Complete

Undefined

A = 0

B = 1

A = 1

0 For Negative Input

1 For Positive Input

B = 0 B = 1B = 0

A = 1A = 0

Typically = TINT TINT

Comparator Delay +

Proces sor Lat ency

TC500/A/510/514

6.0 ANALOG SECTION

6.1 Differential Inputs (VIN+, VIN–)

The TC5XX operates with differential voltages within

the input am plifi er Commo n mode ra nge. The am plifi er

Common mode range extends from 1.5V below

positive supply to 1.5V above negative supply. Within

this Common mode voltage range, Common mode

rejection is typically 80 dB. Full accuracy is maintained,

however, when the inputs are no less than 1.5V from

either supply.

The integrator output also follows the Common mode

voltage. The integrator output must not be allowed to

saturate. A worst-case condition exists, for example,

when a large, positive Common mode voltage, with a

near full-scale negative differential input voltage, is

applied. The negative input signal drives the integrator

positive when most of its swing has been used up by

the positive Common mode voltage. For these critical

applications, the integrator swing can be reduced. The

integr ator ou tput ca n sw ing with in 0.9V o f ei ther su pply

without loss of linearity.

6.2 Analog Common

Analog common is used as VIN return during system

zero and reference de -integrate. If VIN– is different from

analog common , a Com mon mod e volt age exi sts i n the

system . This signal is re jected by the ex cell ent CM R of

the conv erter. In most appl ications, VIN– will be se t at a

fixed known voltage (i.e., power supply common). A

Common mode voltage will exist when VIN– is not

connected to analog common.

6.3 Differential Reference

(VREF+, VREF–)

The reference voltage can be anywhere within 1V of

the power supply voltage of the converter. Rollover

error is caused by the reference capacitor losing or

gaining charge due to stray capacitance on its nodes.

The difference in reference for (+) or (-) input voltages

will cause a rollover error. This error can be minimized

by using a large reference capacitor in comparison to

the stray capacitanc e.

6.4 Phase Control I nputs (A, B)

The A, B unlatched logic inputs select the TC5XX

operating phase. The A, B inputs are normally driven

by a microprocessor I/O port or external logic.

6.5 Comparator Output

By monitoring the comparator output during the fixed

signal integrate time, the input signal polarity can be

determined by the microprocessor controlling the

conversion. The comparator output is high for positive

signals and low for negative signals during the signal

integrate phase (see Figure 6-1).

During the reference de-integrate phase, the

comp ara tor output wi ll make a h igh -to-l ow transit ion a s

the integra t or out put ram p cr oss es zero. T he tra nsi tio n

is used to signal the processor that the conversion is

complete.

The internal comparator delay is 2 μsec, typically.

Figure 6-1 shows the comparator output for large

positiv e and ne gative signa l input s. Fo r signal input s at

or near ze ro volts, howev er , the integra tor swing is ver y

small. If Common mode noise is present, the

comparator can switch several times during the

beginni ng of the si gn al i nte grat e pe riod. To ensure that

the polarity reading is correct, the comparator output

should be read and stored at the end of the signal

integrate phase.

The comparator output is undefined during the auto-

zero phase and is used to time the integrator output

zero phase. (See Section 8.6 “Integrator Output Zero

Phase”).

FIGURE 6-1: Comparator Output.

Integrator

Output Zero

Crossing

Comparator

Output

Reference

Signal

Integrate

Integrator

Output Zero

Crossing

Comparator

Output

Reference

Deintegrate

Signal

Integrate

B. Negative Input SignalA. Positive Input Signal

De-integrate

TC500/A/510/514

7.0 TYPICAL APPLICATIONS

7.1 Component Value Selection

The procedure outlined below allows the user to arrive

at values for the following TC5XX design variables:

1. Integr ati on Phas e Timi ng.

2. Integr ator Timing Components (R INT, CINT).

3. Auto- z ero and Reference Capac itors.

4. Voltage Refere nc e.

7.2 Select In tegration Ti me

Integration time must be picked as a multiple of the

period of th e line frequen cy. For examp le, TINT tim es of

33 msec, 66 msec and 132 msec maximize 60 Hz line

rejection.

7.3 DINT and IZ Phase Timing

The duration of the DINT phase is a function of the

amount of voltage stored on the integrator during TINT

and the value o f VREF. The DINT phase must be initiated

immediately fol lowi ng INT and terminate d w hen a n inte-

grator output zero-crossing is detected. In general, the

maximum number of counts chosen for DINT is twice

that of INT (with VREF chosen at VIN(MAX) /2).

7.4 Calcula te Integrating Resistor

(RINT)

The desired full-sca le input voltage and amplifier output

current capability determine the value of RINT. The

buffer and integrator amplifiers each have a full-scale

current of 20 μA.

The valu e of RINT is, therefore, directly calculated in the

following equation:

EQUATION 7-1:

7.5 Select Refe rence (CREF) and Auto-

zero (CAZ) Capacitors

CREF and CAZ must be low leakag e capaci tors (such a s

polypropylene). The slower the conversion rate, the

larger the value CREF must be. Recommended

capacitors for CREF and CAZ are shown in Table 7-1.

Larger values for CAZ and CREF may also be used to

limit rollover errors.

TABLE 7-1: CREF AND CAZ SELECTION

7.6 Calculate Integrating Capacitor

(CINT)

The integrating capacitor must be selected to maximize

integrator output voltage swing. The integrator output

voltage swing is defined as the absolute value of VDD

(or VSS) less 0.9V (i.e., IVDD - 0.9VI or IVSS + 0.9VI).

Using the 20 μA buffer maximum output current, the

value of the integra ting capacitor is calculated using the

following equation.

EQUATION 7-2:

It is critical that the integrating capacitor has a very low

dielectric absorption. Polypropylene capacitors are an

example of one such dialectic. Polyester and poly-

bicarbo nate cap acitors may a lso be used in less c ritical

applications. Table 7-2 summarizes recommended

capacitors for CINT.

TABLE 7-2: RECOMMENDED CAPACITOR

FOR CINT

7.7 Calculate VREF

The reference de-integration voltage is calculated

using the following equation:

EQUATION 7-3:

Where:

VIN(MAX) = Maximu m input volt age (full cou nt voltag e

)

RINT = Integrating Resistor (in MΩ)

For loop stability, RINT should be ≥ 50 kΩ.

RINT in MΩ()

VIN MAX()

-----------------------

Conversions

Per Second Typical Value of

CREF, CAZ (μF) Sug gested* Part

Number

>7 0.1 SMR5 104K50 J01L4

2 to 7 0.22 SMR5 224K50 J02L4

2 or less 0.47 SMR5 474K50J04L4

* Manufactured by Evox Rifa, Inc.

Value Suggested

Part Number*

0.1 SMR5 104K50J01L4

0.22 SMR5 224K50J02L4

0.33 SMR5 334K50J03L4

0.47 SMR5 474K50J04L4

* Manufactured by Evox Rifa, Inc.

Where:

TINT = Integrat ion Period

VS = IVDDI or IVSSI, whichever is less (TC500/A)

VS = IVDDI (TC510, TC514)

CINT TINT

()20 10 6–

×()

VS0.9–()

---------------------------------------------

VREF VS0.9–()CINT

()RINT

()

INT

()

-----------------------------------------------------------V=

TC500/A/510/514

8.0 DESIGN CONSIDERATIONS

8.1 Noise

The threshold noise (NTH) is the algebraic sum of the

integrator and comparator noise and is typically 30 μV.

Figure 8-1 illustrates how the value of the reference

voltage can affect the final count. Such errors can be

reduced by increased integration times, in the same

way that 50/60 Hz noise is rejected. The signal-to-

noise ratio is related to the integration time (TINT) and

the integration time constant (RINT, CINT) as follows:

EQUATION 8-1:

8.2 System Timing

To ob tai n maxi mu m p erf o rma nc e f ro m t he TC 5X X, the

overshoot at the end of the de-integration phase must

be minimized. Also, the integrator output zero phase

must be terminated as soon as the comparator output

returns high (see Figure 5-1).

Figure 5- 1 shows the overall ti ming for a typical sys tem

in which a TC5XX is interfaced to a microcontroller. The

microc ontroll er drives the A, B input s wit h I/O lines an d

monitors the comparator output (CMPTR) using an I/O

line or dedicated timer capture control pin. It may be

necess ary to mo nitor the st at e of the CMPTR outpu t in

addition to having it control a timer directly for the

Reference de-integration phase (this is further

explained below.)

The timi ng di ag ram in Fi gure 5-1 is not to scale, as th e

timing in a real system depends on many system

parameters and component value selections. There

are four cr itica l timing events (as sh own in Figure 5-1):

sampli ng the inp ut polarit y , c apturing th e de-integr ation

time, mini mizi ng ov ersh oot and pro perl y exec uti ng t he

integrator output zero phase.

8.3 Auto-zero Phase

The leng th of this ph ase is usu ally set to be equal to th e

input signal integration time. This decision is virtually

arbitrary since the magnitudes of the various system

errors are not known. Setting the auto-zero time equal

to the Input Integrate time should be more than

adequate to null out system errors. The system may

remain in this phase indefinitely (i.e., auto-zero is the

appropriate Idle state for a TC5XX device).

8.4 Input Sign al Integrate Phase

The length of this phase is constant from one

conversion to the next and depends on system

parameters and component value selections. The

calculation of TINT is shown elsewhere in this data

sheet. At some point near the end of this phase, the

microcontroller should sample CMPTR to determine

the input signal polari ty . This v alue is, in ef fect, the Sign

Bit for the overall conversion result. Optimally, CMPTR

should be sampl ed just bef ore this ph ase is termin ated

by changing AB from 10 to 11. The consideration here

is that, du ring the initial st a ge o f inp ut in tegration whe n

the integrator voltage is low, the comparator may be

affected by noise and its output unreliable. Once

integrati on is w ell und erway, the c ompa rator will b e in a

defined state.

8.5 Reference De-integration

The length of this phase must be precisely measured

from the transition of AB from 10 to 11 to the falling-

edge of CMPTR. The comparator delay contributes

some error in timing this phase. The typical delay is

specif ied to be 2 μsec. This should be considered in the

context of the length of a single count when

determining overall system performance and possible

single count e rrors. Ad dition ally, overs hoot wi ll resu lt in

charge accumulating on the integrator once its output

crosses zero. This charge must be nulled during the

integrator output zero phase.

S/N (dB) 20 log VIN

30 10 6–

-----------------------tINT

RINT

()CINT

()•

---------------------------------------

•

⎝⎠

⎜⎟

⎛⎞

TC500/A/510/514

FIGURE 8-1: Noise Threshold.

8.6 Integrator Output Zero Phase

The comparator delay and the controller’s response

latency may result in overshoot, causing charge

buildup on the integrator at the end of a conversion.

This charge must be removed or performance will

degrade. The integrator output zero phase should be

activated (AB = 00) until CMPTR goes high. It is

absolutely critical that this phase be terminated

immediately so that overshoot is not allowed to occur in

the opposite direction. At this point, it can be assured

that the integrator is near zero. Auto-zero should be

entered (AB = 01) and the TC5XX held in this state until

the next cycle is begun (see Figure 8-2).

FIGURE 8-2: Overshoot.

8.7 Using the TC510/TC514

8.7.1 NEGATIVE SUPPLY VOLTAGE

CONVERTER (TC510, TC514)

A capacitive charge pump is employed to invert the

voltage on VDD for negative bias within the TC510/

TC514. T his voltage is al so available on t he VOUT- pin

to provide neg ative bias elsewher e in the system. Two

external capacitors are required to perform the

conversion.

T iming is generat ed by an internal st ate machine driven

from an on-board oscillator. During the first phase,

capacit or CF is switched across the power supply and

charged to VS+. This charge is transferred to capacitor

COUT- during the second phase. The oscillator normally

runs at 100 kHz to ensure minimum output ripple. This

freq uen cy ca n b e red uced by pla cing a c apacit or f rom

OSC to VDD. The relationship between the capacitor

value is shown in Section 2.0 “Typical Performance

Curves”.

8.7.2 ANALOG INPUT MULTIPLEXER

(TC514)

The TC514 is equipped with a four-input differential

analog multiplexer. Input channels are selected using

select inputs (A1, A0). These are high-true control

signal s (i .e., channel 0 is selec ted when (A1, A 0 = 00).

Low VREF Normal VREF High VREF

NTH

30V

NTH

Slope (S) = NTH = Noise Threshold

VREF

RINT CINT

Integrator

Output

Comparator

Output Comp

Integrate

Phase

De-integrate PhaseIntegrator

Zero Phase

Zero

Crossing

Overshoot

TC500/A/510/514

9.0 DESIGN EXAMPLES

Refer to Figures 9-1 to 9-4.

EQUATION 9-1:

Given: Required Resolution: 16 bits (65,536

counts).

Maximum VIN: ±2V

Power Supply Voltage: +5V

60 Hz System

Step 1. Pick integration time (tINT) as a multipl e

of the line frequency:

1/60 Hz = 16.6 msec. Use 4x line

frequency.

= 66 msec

Step 2. Calculate RINT:

RINT = VIN(MAX) /20 μA 2 /20 μA

= 100 kΩ

Step 3. Calculate CINT for maximum (4V)

integrat or outp ut swin g.

CINT = (tINT) (20 x 10 –6) / (VS - 0.9)

= (.066) (20 x 10 –6) / (4.1)

= 0.32 μF (use closest value: 0.33 μF)

Note: Microchip recommended capacitor:

Evox Rifa p/n: 5MR5 334K50J03L4.

Step 4. Choose CREF and CAZ based on

conversion rate.

Conversions/sec:

= 1/(TAZ + TINT + 2 TINT + 2 mse c)

= 1/(66 msec +66 ms ec

+132 msec +2 msec)

= 3.7 conversions/sec

From which CAZ = CREF = 0.22 μF

(see Table 7-1)

Note: Microchip recommended capacitor:

Evox Rifa p/n: 5MR5 224K50J02L4

Step 5. Calculate VREF:

VREF VS0.9–()CINT

()RINT

()

INT

()

-----------------------------------------------------------

4.1()0.33 1 6–

×()105

()=20.66()

--------------------------------------------------------------

1.025=

TC500/A/510/514

FIGURE 9-1: TC510 Design Sample.

FIGURE 9-2: TC514 Design Example.

INPUT+

INPUT-

+5V

Pin 2

Pin 19

Pin 2

Pin 19

CINT

0.33 μF

VIN+

Typical Waveform

1μF1μF

CAZ

0.22 μF

CREF

VIN-

RINT

100 kΩ

CAP-

DGND

VREF+

VOUT-

CREF-

CINT

CAZ

BUF

ACOM

TC510

VREF-VIN+

VIN-

CAP+

VDD

CMPTR

0.22 μF

0.01 μF

10 kΩ

+5V

R3, 10 kΩ

MCP1525

1μF

CREF+

Microcontroller

PICmicro®

+5V

PIN 2

PIN 23

PIN 2

PIN 23

VIN+

Typical Waveforms

1μF

VIN-

CAP-

DGND

TC514 CAP+

VDD

CMPTR

Analog

Mux Logic

INPUT 1+

INPUT 1-

INPUT 2+

INPUT 2-

INPUT 3+

INPUT 3-

INPUT4+

INPUT4-

CH1+

CH2+

CH2-

CH3+

CH3-

CH4+

CH4-

CH1-

CINT

0.33 μF

1μF

CAZ

0.22 μF

CREF

RINT

100 kΩ

VREF+

VOUT-

CREF-

CINT

CAZ

BUF

ACOM

VREF-

0.22 μF

0.01 μF

10 kΩ

+5V

R3, 10 kΩ

MCP1525

1μF

CREF+

Microcontroller

PICmicro®

TC500/A/510/514

FIGURE 9-3: TC510 To IBM® Compatible Printer Port.

Printer

Port

PORT

0378

Hex

Input

+5V

10 kΩ

100 kΩ

1μF

121

CAP-

DGND

VOUT-VDD

B CINT

CAZ

BUF

ACOM

TC510

CREF+

VIN+

CAP+

CMPTR

0.22 μF

0.01 μF

1μF

0.33 μF

MCP1525

CREF-

VREF+

VREF-

VIN-–

TC500/A/510/514

FIGURE 9-4: TC514 To IBM® Compatible Printer Port.

IBM®

Printer Port

Port

0378

Hex

+5V

10 kΩ

100 kΩ

1μF

CAP–

DGND

VOUT

VDD

CREF+

TC514

BUF

0.22 μF10 kΩ

10 kΩ

0.22 μF

0.01 μF

0.33 μF

CH1+

Input 1

+18

–13

Input 2

+17

–12

Input 3

+16

–11

Input 4

+15

–10

CAP+

CREF-

VREF+

VREF-

CAZ

CINT

ACOM

CH1–

CH2+

CH2–

CH3+

CH3–

CH4+

CH4–

CMPTR

Analog

Mux Contro l Logi c

MCP1525

TC500/A/510/514

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

16-Lead PDIP (300 mil) Example:

16-Lead SOIC (300 mil) Example:

XXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXXXX

YYWWNNN

TC500CPE

0441256

XXXXXXXXXXXXX TC500ACOE

0441256

Legend: XX...X Customer specific information*

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanum eri c trac eab ili ty code

Note: In th e event the full Microchi p part number cannot be marked on one l ine, it wi ll

be carried over to the next line thus limiting the number of available characters for cus-

tomer specific information.

*Standard marking consists of Microchip part number, year code, week code, traceability code.

For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.

16-Lead CERDIP (300 mil) Example:

XXXXXXXXXXXXXX

YYWWNNN

TC500AIJE

0441256

TC500/A/510/514

Package Marking Information (Continued)

28-Lead PD IP (300 mil) Example:

28-Lead SOIC (300 mil) Example:

XXXXXXXXXXXXXX

YYWWNNN

TC514CPJ

0441256

XXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXXXX

0441256

TC514COI

24-Lead PDIP (300 mil) Example:

24-Lead SOIC (300 mil) Example:

YYWWNNN

XXXXXXXXXXXXX

0441256

TC510CPF

XXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXXXX

0441256

TC510COG

TC500/A/510/514

16-Lead Ceramic Dual In-line (JE) – 300 mil (CERDIP)

10.419.148.25.410.360.325

Overall Row Spacing

0.530.460.38.021.018.015BLower Lead Width

1.651.401.14.065.055.045

Upper Lead Width

0.360.300.20.014.012.008

Lead Thickness

5.084.14

3.18.200.163.125LTip to Seating Plane

19.8119.3019.10.780.760.752DOverall Length

7.527.327.11.296.288.280

Ceramic Pkg. Width

8.257.757.37.325.305.290EShoulder to Shoulder Width

1.020.760.38.040.030.015

Standoff §

5.084.574.06.200.180.160ATop to Seating Plane

2.54.100

Pitch

1818

Number of Pins

MAX

NOM

MINMAX

NOM

MINDimension Limits

MILLIMETERSINCHES*Units

JEDEC Equivalent: MS-030

Drawing No. C04-003

*Controlling Parameter

TC500/A/510/514

16-Lead Plastic Dual In-line (PE) – 300 mil (PDIP)

1510515105

Mold D r a ft Angle Botto m 1510515105

Mold Draft Angle Top 10.929.407.87.430.370.310eBOverall Row Spacing 0.560.46.036.022.018.014BLower Lead Width 1.781.461.14.070.058.045B1Upper Lead Wi dth 0.380.290.20.015.012.008

Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 19.3019.0518.80.760.750.740DOverall Length 6.606.356.10.260.250.240E1Molded Package W idth 8.267.947.62.325.313.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.683.302.92.145.130.115A2Molded Package Thickness 4.323.943.56.170.155.140ATop to Seating Plane 2.54.100

Pitch 1616

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS

INCHES

Units

Dimensions D and E1 do not include mol d flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

Notes

JEDEC Equiv alent: MS-001 Revised 07-21-05

Controlling Parameter

Drawing No. C04-017

TC500/A/510/514

16-Lead Plasti c Small Outline (OE) – Wide, 300 mil (SOIC)

Foot Angle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009

Lead Thickness

1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 10.4910.3010.10.413.406.398DOverall Len gth 7.597.497.39.299.295.291E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004

Standoff §2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27

.050

Pitch 1616

Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-102

§ Significant Characteristic

TC500/A/510/514

24-Lead Skinny Plasti c Dual In-line (PF) – 300 mil (PDIP)

1510515105

Mold D r a ft Angle Botto m 1510515105

Mold Draft Angle Top 10.929.407.87.430.370.310eBOverall Row Spacing 0.560.460.36.022.018.014BLower Lead Width 1.521.331.14.060.053.045B1Upper Lead Width 0.380.290.20.015.012.008

Lead Thickness 3.303.183.05.130.125.120LTip to Seating Plane 31.8831.7531.621.2551.2501.245DOverall Length 6.606.356.10.260.250.240E1Molded Package Width 8.267.877.49.325.310.295EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.683.302.92.145.130.115A2Molded Package Thickness 4.063.813.56.160.150.140ATop to Seating Plane 2.54.100

Pitch 2424

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS

INCHES

Units

Dimensions D and E 1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

Notes:

JEDEC Equivalent: MS-001 AF

Drawing No. C04-043

Controlling Parameter

Revised 09-14-05

TC500/A/510/514

24-Lead Plastic Small Outline (OG) – Wide, 300 mil (SOIC)

Foot Angle

0° 8° 0° 8°

15°5°15°5°

Mold D r a ft Angle Botto m 15°5°15°5°

Mold Draft Angle Top 0.510.31.020.012BLead Width 0.330.20.013.008

Lead Thickness

1.270.40.050.016LFoot Length 0.750.25.030.010hChamfer Distance 15.40 BSC.607 BSCDOverall Length 7.50 BSC.295 BSCE1Molded Package Width 10.30 BSC.406 BSCEOverall Width 0.300.10.012.004A1Standoff 2.552.05.100.081A2Molded Package Thickness 2.652.35.104.093AOverall Height 1.27 BSC.050 BSC

Pitch 2424

Number of Pins MAXNOMMINMAXNOMMINDimens ion Limits MILLIMETERS

INCHESUnits

Dimensions D and E1 do not include mol d flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

Notes:

JEDEC Equiv alent: MS-013 A D Revised 07-19-05

Controlling Parameter per JEDE C M S -103 Revision C.

-- --

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

See ASME Y14.5M

Drawing No. C04-025

TC500/A/510/514

28-Lead Skinny Plasti c Dual In-line (PJ) – 300 mil (PDIP)

1510515105

Mold Draft Angle Bottom 1510515105

Mold Draft Angle Top 10.928.898.13.430.350.320

Overall Row Spacing §0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008

Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Len gth 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to S houlder Wi dth 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125A2Mol ded Package Thickness 4.063.813.56.160.150.140ATop to Seating Plane 2.54.100

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units

Notes:

JEDEC Equivalent: MO-095

Drawing No. C04-070

* Controlling Parameter

Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

§ Significant Characteristic

TC500/A/510/514

28-Lead Plastic Small Outline (OI) – Wide, 300 mil (SOIC)

Foot Angle Top φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009

Lead Thickness

1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff §2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27

.050

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

§ Significant Characteristic

TC500/A/510/514

10.2 Product Tape and Reel Specifications

Component Taping Orientation for 16-Pin SOIC (Wide) Devices

Pin 1

User Direction of Feed

Standard Reel Component Orientation

for 713 Suffix Device

Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size

16-Pin SOIC (W) 16 mm 12 mm 1000 13 in

Carrier Tape, Number of Components Per Reel and Reel Size

Component Taping Orientation for 24-Pin SOIC (Wide) Devices

Pin 1

User Direction of Feed

Standard Reel Component Orientation

for 713 Suffix Device

Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size

24-Pin SOIC (W) 24 mm 12 mm 1000 13 in

Carrier Tape, Number of Components Per Reel and Reel Size

TC500/A/510/514

Product Tape and Reel Specifications (Continued)

Component Taping Orientation for 28-Pin SOIC (Wide) Devices

Pin 1

User Direction of Feed

Standard Reel Component Orientation

for 713 Suffix Device

Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size

28-Pin SOIC (W) 24 mm 12 mm 1000 13 in

Carrier Tape, Number of Components Per Reel and Reel Size

TC500/A/510/514

NOTES:

TC500/A/510/514

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

PART NO. X/XX

PackageTemperature

Range

Device

Device TC500 16 Bit Analog Processor

TC500A 16 Bit Analog P rocessor

TC510 Pr ecision Analog Front End

TC514 Pr ecision Analog Front End

Temperature Range C = 0°C to +70°C (Commercial)

I = -25°C to +85°C (Industrial)

Package: JE = Ceramic Dual In-line, (3 00 mil Body), 16-lead

PE = Plastic DIP, (300 mil Body), 16-lead

OE = Plastic SOIC, (300 mil Body), 16-lead

OE713 = Plastic SOIC, (300 mil Body), 16-lead

(Tape and Ree l)

PF = Plastic DIP, (300 mil Body), 24-lead

OG = Plastic SOIC, (300 mil Body), 24-lead

OG713 = Plastic SOIC, (300 mil Body), 24-lead

(Tape and Ree l)

PJ = Plastic DIP, (300 mil Body), 28-lead

OI = Plastic SOIC, (300 mil Body), 28-lead

OI713 = Plastic SOIC, (300 mil Body), 28-lead

(Tape and Ree l)

Examples:

a) TC500ACOE: Commercial Temp.,

16LD SOIC package.

b) TC500 AC OE 713 : Comme rcia l Temp.,

16LD SOIC package,

Tape and Reel.

c) TC500ACPE: Commercial Temp.,

16LD PDIP package.

d) TC500AIJE: Industrial Temp.,

16LD CERDIP package.

a) TC5 00 C OE: Commercia l Temp.,

16LD SOIC package.

b) TC500COE713: Commercial Temp.,

16LD SOIC package,

Tape and Reel.

c) TC500CPE: Commercial Temp.,

16LD PDIP package.

d) TC500IJE: Industrial Temp.,

16LD CERDIP package.

a) TC510COG: Commercial Temp.,

24LD PDIP package.

b) TC510COG713: Commercial Temp.,

24LD PDIP package,

Tape and Reel.

c) TC510CPF: Commercial Temp.,

24LD PDIP package.

a) TC514COI: Commercial Temp.,

28LD PDIP package.

b) TC514COI713: Commercial Temp.,

28LD PDIP package,

Tape and Reel.

c) TC514CPJ: Commercial Temp.,

28LD PDIP package.

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.c om)

Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.

Customer Notification System

TC500/A/510/514

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIN D WHETHER EXPRESS OR IMPLIED ,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. U se of Microc hip’s products as critical com ponents in

life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Linear Active Thermistor,

MPASM , MPLIB, MPLINK, MPSIM, PIC kit, PICDE M,

PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,

PowerMate, Powe rTool, Real ICE, rfLAB, rfPICDEM, Select

Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

WiperLock and Zena are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in t he

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving the c ode prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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WORLDWIDE SALES AND SERVICE

10/31/05