2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Features DDR2 SDRAM SOCDIMM MT18HTS25672CHY - 2GB MT18HTS51272CHY - 4GB Features Figure 1: 200-Pin SOCDIMM (MO-274 R/C C) * 200-pin, small-outline clocked dual in-line memory module (SOCDIMM) * Fast data transfer rates: PC2-4200 or PC2-5300 * 2GB (256 Meg x 72) or 4GB (512 Meg x 72) * Supports ECC error detection and correction * VDD = VDDQ = 1.8V * VDDSPD = 3.0-3.6V * JEDEC-standard 1.8V I/O (SSTL_18-compatible) * Differential data strobe (DQS, DQS#) option * 4n-bit prefetch architecture * Multiple internal device banks for concurrent operation * Programmable CAS latency (CL) * Posted CAS additive latency (AL) * WRITE latency = READ latency - 1 tCK * Programmable burst lengths (BL): 4 or 8 * Adjustable data-output drive strength * 64ms, 8192-cycle refresh * On-die termination (ODT) * Serial presence detect (SPD) with EEPROM * Phase-lock loop (PLL) to reduce system clock line loading * Gold edge contacts * Dual rank, TwinDieTM (2COB) DRAM devices * I2C temperature sensor Module height 30.0mm (1.18in) Options * Operating temperature - Commercial (0C TA +70C) - Industrial (-40C TA +85C)1 * Package - 200-pin DIMM (lead-free) * Frequency/CL2 - 3.0ns @ CL = 5 (DDR2-667) - 3.75ns @ CL = 4 (DDR2-533) Notes: Marking None I Y -667 -53E 1. Contact Micron for industrial temperature module offerings 2. CL = CAS (READ) latency. Table 1: Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 5 CL = 4 CL = 3 (ns) tRP (ns) tRC (ns) -667 PC2-5300 667 553 400 15 15 55 -53E PC2-4200 - 553 400 15 15 55 PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 1 tRCD Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Features Table 2: Addressing Parameter Refresh count Row address 2GB 4GB 8K 8K 16K A[13:0] 32K A[14:0] Device bank address 8 BA[2:0] 8 BA[2:0] Device configuration 2Gb TwinDie (256 Meg x 8) 4Gb TwinDie (512 Meg x 8) Column address 1K A[9:0] 1K A[9:0] Module rank address 2 S#[1:0] 2 S#[1:0] Table 3: Part Numbers and Timing Parameters - 2GB Modules Base device: MT47H256M8THN,1 2Gb TwinDie DDR2 SDRAM Module Part Number2 Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT18HTS25672CH(I)Y-667__ 2GB 256 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 MT18HTS25672CH(I)Y-53E__ 2GB 256 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4 Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) Table 4: Part Numbers and Timing Parameters - 4GB Modules Base device: MT47H512M8THM,1 4Gb TwinDie DDR2 SDRAM Module Part Number2 Density Configuration MT18HTS51272CH(I)Y-667__ 4GB 512 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 MT18HTS51272CH(I)Y-53E__ 4GB 512 Meg x 72 4.3 GB/s 3.75ns/553 MT/s 4-4-4 Notes: 1. The data sheet for the base device can be found on Micron's Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18HTS51272CHY-53EA1. PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Pin Assignments Pin Assignments Table 5: Pin Assignments 200-Pin SOCDIMM Front 200-Pin SOCDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREF 51 DQ18 101 VDD 151 VSS 2 VSS 52 VSS 102 A6 152 VSS 3 DQ0 53 DQ19 103 A5 153 DQS5# 4 DQ4 54 DQ28 104 A4 154 DM5 5 VSS 55 VSS 105 A3 155 DQS5 6 DQ5 56 DQ29 106 VDD 156 VSS 7 DQ1 57 DQ24 107 A2 157 VSS 8 VSS 58 VSS 108 A1 158 DQ46 9 DQS0# 59 DQ25 109 VDD 159 DQ42 10 DM0 60 DM3 110 A0 160 DQ47 11 DQS0 61 VSS 111 A10 161 DQ43 12 VSS 62 VSS 112 BA1 162 VSS 13 VSS 63 DQS3# 113 BA0 163 VSS 14 DQ6 64 DQ30 114 VDD 164 DQ52 15 DQ2 65 DQS3 115 RAS# 165 DQ48 16 DQ7 66 DQ31 116 WE# 166 DQ53 17 DQ3 67 VSS 117 VDD 167 DQ49 18 VSS 68 VSS 118 S0# 168 VSS 19 VSS 69 DQ26 119 CAS# 169 VSS 20 DQ12 70 CB4 120 ODT0 170 DM6 21 DQ8 71 DQ27 121 S1# 171 DQS6# 22 DQ13 72 CB5 122 A13 172 VSS 23 DQ9 73 VSS 123 VDD 173 DQS6 24 VSS 74 VSS 124 VDD 174 DQ54 25 VSS 75 CB0 125 ODT1 175 VSS 26 DM1 76 DM8 126 CK0 176 DQ55 27 DQS1# 77 CB1 127 NC 177 DQ50 28 VSS 78 VSS 128 CK0# 178 VSS 29 DQS1 79 VSS 129 DQ32 179 DQ51 30 DQ14 80 CB6 130 VSS 180 DQ60 31 VSS 81 DQS8# 131 VSS 181 VSS 32 DQ15 82 CB7 132 DQ36 182 DQ61 33 DQ10 83 DQS8 133 DQ33 183 DQ56 34 VSS 84 VSS 134 DQ37 184 VSS 35 DQ11 85 VSS 135 DQS4# 185 DQ57 36 DQ20 86 CB2 136 VSS 186 DM7 37 VSS 87 CKE0 137 DQS4 187 VSS 38 DQ21 88 CB3 138 DM4 188 DQ62 39 DQ16 89 CKE1 139 VSS 189 DQS7# 40 VSS 90 VSS 140 VSS 190 VSS 41 DQ17 91 EVENT# 141 DQ34 191 DQS7 42 RESET# 92 BA2 142 DQ38 192 DQ63 43 VSS 93 VDD 143 DQ35 193 DQ58 44 DM2 94 NC/A141 144 DQ39 194 SDA 45 DQS2# 95 A12 145 VSS 195 VSS 46 VSS 96 A11 146 VSS 196 SCL 47 DQS2 97 A9 147 DQ40 197 DQ59 48 DQ22 98 VDD 148 DQ44 198 SA1 49 VSS 99 A7 149 DQ41 199 VDDSPD 50 DQ23 100 A8 150 DQ45 200 SA0 Note: PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 1. Pin 94 is NC for 2GB or A14 for 4GB. 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Pin Descriptions Pin Descriptions The pin description table below is a comprehensive list of all possible pins for all DDR2 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Table 6: Pin Descriptions Symbol Type Description Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. CKx, CK#x Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DDR2 SDRAM. DMx, Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z. S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C bus. SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the SPD EEPROM on the I2C bus. CBx I/O Check bits. Used for system error detection and correction. DQx I/O Data input/output: Bidirectional data bus. DQSx, DQS#x I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the controller. Output with read data; input with write data for source synchronous operation. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Pin Descriptions Table 6: Pin Descriptions (Continued) Symbol Type SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on the I2C bus. RDQSx, RDQS#x Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS is output with read data only and is ignored during write data. When RDQS is disabled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled and differential data strobe mode is enabled. Err_Out# Output (open drain) Parity error output: Parity error found on the command and address bus. EVENT# Output (open drain) Temperature event: The EVENT# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. VDD/VDDQ Supply Power supply: 1.8V 0.1V. The component VDD and VDDQ are connected to the module VDD. VDDSPD Supply SPD EEPROM power supply: 1.7-3.6V. VREF Supply Reference voltage: VDD/2. VSS Supply Ground. NC - No connect: These pins are not connected on the module. NF - No function: These pins are connected within the module, but provide no functionality. NU - Not used: These pins are not used in specific module configurations/operations. RFU - Reserved for future use. PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN Description 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S1# S0# DQS0# DQS0 DM0 DQS4# DQS4 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U1b CS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1t DQS1# DQS1 DM1 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U13b CS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U13t DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U2b CS# DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U7t DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U10b CS# DQS DQS# U10t DM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U2t CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U8b CS# DQS DQS# U8t DQS7# DQS7 DM7 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U12b CS# DM DQS DQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U12t CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS U6 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U11b DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# CK0 CK0# U4 SPD EEPROM WP A0 SCL CS# DQS DQS# U9t U1, U13 U2, U12 U11 U7, U10 U8, U9 SDA A2 VSS SA0 SA1 VSS U3 Rank 0 = U1b, U2b, U7b-U13b Rank 1 = U1t, U2t, U7t-U13t BA[2:0] A[14/13:0] A1 DM DQ DQ DQ DQ DQ DQ DQ DQ CLK0/CLK0# CLK1/CLK1# CLK2/CLK2# CLK3/CLK3# CLK4/CLK4# PLL U11t DQS# U9b DQS8# DQS8 DM8 PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DQS3# DQS3 DM3 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQS# DQS6# DQS6 DM6 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS U7b DM DQS DQS# DQS2# DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS5# DQS5 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM DQS DQS# Temp Sensor EVT A0 BA[2:0]: DDR2 SDRAM A[14/13:0]: DDR2 SDRAM A1 SDA A2 SA0 SA1 VSS EVENT# RAS# CAS# WE# CKE0 RAS#: DDR2 SDRAM CAS#: DDR2 SDRAM WE#: DDR2 SDRAM CKE0: DDR2 SDRAM Rank 0 VDDSPD DDR2 SDRAM CKE1 ODT0 ODT1 CKE1: DDR2 SDRAM Rank 1 ODT0: DDR2 SDRAM Rank 0 ODT1: DDR2 SDRAM Rank 1 VDD VREF DDR2 SDRAM VSS DDR2 SDRAM 6 SPD EEPROM, Temp Sensor Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM General Description General Description DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM modules use DDR architecture to achieve high-speed operation. DDR2 architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect EEPROM Operation DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM's SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to VSS, permanently disabling hardware write protection. Register and PLL Operation DDR2 SDRAM modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock signals (CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize system and clock loading. PLL clock timing is defined by JEDEC specifications and ensured by use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL. Register and PLL Operation An on-board temperature sensor provides the ability to monitor the module temperature along with monitoring alarms. Programmable registers can be used to specify temperature events and critical boundaries. An EVENT# pin is used to signal when different conditions occur based on how the registers are defined. PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in the device data sheet are not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 7: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD VDD supply voltage relative to VSS -1.0 2.3 V VIN, VOUT Voltage on any pin relative to VSS -0.5 2.3 V Input leakage current; Any input 0V VIN Address inputs, RAS#, CAS#, VDD; VREF input 0V VIN 0.95V; (All other WE#, ODT pins not under test = 0V) S#, CKE -90 90 A II IOZ IVREF TA -45 45 CK0, CK0# -250 250 DM -10 10 Output leakage current; 0V VOUT VDDQ; DQ, DQS, DQS# DQ and ODT are disabled -10 10 A VREF leakage current; VREF = valid VREF level -36 36 A Module ambient operating temperature Commercial Industrial 1 TC DDR2 SDRAM component operating temperature2 Notes: PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN Commercial Industrial 0 70 C -40 85 C 0 85 C -40 95 C 1. The refresh rate is required to double when TC exceeds 85C. 2. For further information, refer to technical note TN-00-08: "Thermal Applications," available on Micron's Web site. 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades. Table 8: Module and Component Speed Grades DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Component Speed Grade -1GA -187E -80E -25E -800 -25 -667 -3 -53E -37E -40E -5E Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM IDD Specifications IDD Specifications Table 9: DDR2 IDD Specifications and Conditions - 2GB Values shown for MT47H256M8THN DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (256 Meg x 8) component data sheet Combined Parameter Symbol -667 -53E Units Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (I ); CKE is HIGH, S# is HIGH between valid commands; Address DD bus inputs are switching; Data bus inputs are switching ICDD0 873 738 mA Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W ICDD1 1008 963 mA Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating ICDD2P 126 126 mA Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating ICDD2Q 423 423 mA Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching ICDD2N 468 468 mA Fast PDN exit Active power-down current: All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; MR[12] = 0 Data bus inputs are floating Slow PDN exit MR[12] = 1 ICDD3P 333 333 mA 153 153 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching ICDD3N 603 513 mA Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD4W 1323 1233 mA Operating burst read current: All device banks open; Continuous burst read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD4R 1323 1233 mA Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching ICDD5 2043 1998 mA Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating ICDD6 126 126 mA Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (I ), tRRD = tRRD (I ), tRCD = tRCD (I ); CKE is HIGH, S# is HIGH between valid DD DD DD commands; Address bus inputs are stable during deselects; Data bus inputs are switching ICDD7 2628 2538 mA PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM IDD Specifications Table 10: DDR2 IDD Specifications and Conditions - 4GB Values shown for MT47H512M8THM DDR2 SDRAM only and are computed from values specified in the 4Gb TwinDie (512 Meg x 8) component data sheet Combined Parameter Symbol -667 -53E Units Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (I ); CKE is HIGH, S# is HIGH between valid commands; Address DD bus inputs are switching; Data bus inputs are switching ICDD0 1017 927 mA Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W ICDD1 1422 1062 mA Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating ICDD2P 144 144 mA Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating ICDD2Q 567 477 mA Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching ICDD2N 657 567 mA Fast PDN exit Active power-down current: All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; MR[12] = 0 Data bus inputs are floating Slow PDN exit MR[12] = 1 ICDD3P 432 387 mA 162 162 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching ICDD3N 612 522 mA Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD4W 1467 1287 mA Operating burst read current: All device banks open; Continuous burst read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD4R 1647 1467 mA Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching ICDD5 2637 2457 mA Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating ICDD6 144 144 mA Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (I ), tRRD = tRRD (I ), tRCD = tRCD (I ); CKE is HIGH, S# is HIGH between valid DD DD DD commands; Address bus inputs are stable during deselects; Data bus inputs are switching ICDD7 3177 2772 mA PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM PLL Specifications PLL Specifications Table 11: PLL Specifications CUA845 device or JESD82-21 equivalent Parameter Symbol Pins Condition Min Max Units DC high-level input voltage VIH OE, OS, CK, CK# LVCMOS 0.65 x VDD - V DC low-level input voltage VIL OE, OS, CK, CK# LVCMOS - 0.35 x VDD V Input voltage (limits) VIN -0.3 VDD + 0.3 V Input differential-pair cross voltage VIX Differential input (VDD/2) - 0.15 (VDD/2) + 0.15 V Input differential voltage VID(DC) Differential input 0.3 VDD + 0.4 V Input differential voltage VID(AC) Differential input 0.6 VDD + 0.4 V OE, OS, FBIN, FBIN# VI = VDD or VSS -10 10 A CK, CK# VI = VDD or VSS -250 250 A Input current II Output disabled current IODL OE = L, VODL = 100mV 100 - A Static supply current IDDLD CL = 0pf - 500 A Dynamic supply IDD N/A CK and CK# = 410 MHz, all outputs open (not connected to PCB) - 300 mA Input capacitance CIN Each input VI = VDD or VSS 2 3 pF Table 12: PLL Clock Driver Timing Requirements and Switching Characteristics Parameter Symbol Min Max Units tL - 6 s slr(i) 1.0 4.0 V/ns Stabilization time Input clock slew rate SSC modulation frequency 30 33 kHz SSC clock input frequency deviation 0.0 -0.5 % PLL loop bandwidth (-3dB from unity gain) 2.0 - MHz Note: PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM. This is a subset of parameters for the specific PLL used. 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor with Serial Presence-Detect EEPROM Temperature Sensor with Serial Presence-Detect EEPROM The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I2C bus shared with the SPD EEPROM. Programming and configuration details comply with JEDEC standard No. 21-C page 4.7-1, "Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor." Table 13: Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions All voltages referenced to VSS Parameter/Condition Supply voltage Symbol Min Max Units VDDSPD 3.0 3.6 V - 500 A Average operating supply current Input high voltage: logic 1; All inputs VIH 2.1 - V Input low voltage: logic 0; All inputs VIL - 0.8 V Output low voltage: IOUT = 3mA VOL - 0.4 V Logic input current IIH -5.0 5.0 A IIL -5.0 5.0 A -40 125 C Symbol Min Max Units tBUF 4.7 - s SDA and SCL fall time tF - 300 ns SDA and SCL rise time tR - 1 ns Data hold time tHD:DAT 300 - ns Start condition hold time tHD:STA 4.0 - s Clock HIGH period tHIGH 4.0 50 s Clock LOW period tLOW Temperature sensing range Table 14: Sensor and EEPROM Serial Interface Timing Parameter/Condition Time bus must be free before a new transition can start 4.7 - s tSCL - 400 kHz Data setup time tSU:DAT 250 - ns Start condition setup time tSU:STA 4.7 - s Stop condition setup time tSU:STO 4.0 - s fCK 10 100 kHz SCL clock frequency Clock frequency EVENT# Pin The temperature sensor also adds the EVENT# pin (open drain). Not used by the SPD EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be set up in the sensor's configuration register. EVENT# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. The open-drain output of EVENT# under the three separate operating modes is illustrated below. Event thresholds are programmed in the 0x01 register using a hysteresis. The alarm window provides a comparison window, with upper PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor with Serial Presence-Detect EEPROM and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user. The interrupt mode enables software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window. The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by the user and only returns to the logic HIGH state when the temperature falls below the programmed thresholds. Critical temperature mode triggers EVENT# only when the temperature has exceeded the programmed critical trip point. When the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical EVENT# cannot be cleared through software. SMBus Slave Subaddress Decoding The temperature sensor's physical address differs from the SPD EEPROM's physical address: binary 0011 for A0, A1, A2, and RW#, where A2, A1, and A0 are the three slave subaddress pins and the RW# bit is the READ/WRITE flag. If the slave base address is fixed for the temperature sensor/SPD EEPROM, then the pins set the subaddress bits of the slave address, enabling the devices to be located anywhere within the eight slave address locations. For example, they could be set from 30h to 3Eh. PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor with Serial Presence-Detect EEPROM Figure 3: EVENT# Pin Functionality Temperature Critical Hysteresis affects these trip points Alarm window (MAX) Alarm window (MIN) Clears event Time EVENT# interrupt mode EVENT# comparator mode EVENT# critical temperature only mode Table 15: Temperature Sensor Registers Name Pointer register Address Power-On Default Not applicable Undefined Capability register 0x00 0x0001 Configuration register 0x01 0x0000 Alarm temperature upper boundary register 0x02 0x0000 Alarm temperature lower boundary register 0x03 0x0000 Critical temperature register 0x04 0x0000 Temperature register 0x05 Undefined Pointer Register The pointer register selects which of the 16-bit registers is being accessed in subsequent READ and WRITE operations. This register is a write-only register. PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor with Serial Presence-Detect EEPROM Table 16: Pointer Register Bits 0-7 Bit 7 6 5 4 3 2 1 0 0 0 0 0 Register select Register select Register select Register select Table 17: Pointer Register Bits 0-2 Descriptions Bit 2 1 0 Register 0 0 0 Capability register 0 0 1 Configuration register 0 1 0 Alarm temperature upper boundary register 0 1 1 Alarm temperature lower boundary register 1 0 0 Critical temperature register 1 0 1 Temperature register Capability Register The capability register indicates the features and functionality supported by the temperature sensor. This register is a read-only register. Table 18: Capability Register Bits 0-15 RFU = reserved for future use. Bit 15 14 13 12 RFU RFU RFU RFU 11 10 9 8 RFU RFU RFU RFU Bit 7 6 5 4 3 2 1 0 RFU RFU RFU TRES1 TRES0 Wider range Precision Has alarm and critical temperature Table 19: Capability Register Bit Descriptions Bit Description 0 Basic capability 1: Has alarm and critical trip point capabilities 1 Accuracy 0: 2C over the active range and 3C over the monitor range 1: 1C over the active range and 2C over the monitor range PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor with Serial Presence-Detect EEPROM Table 19: Capability Register Bit Descriptions (Continued) Bit 2 Description Wider range 0: Temperatures lower than 0C are clamped to a binary value of 0 1: Temperatures below 0C can be read 4:3 Temperature resolution 00: 0.5C LSB 01: 0.25C LSB 10: 0.125C LSB 11: 0.0625C LSB 15:5 0: Must be set to zero Configuration Register Table 20: Configuration Register Bits 0-15 Bit 15 14 13 12 11 10 RFU RFU RFU RFU RFU 9 Hysteresis 8 Shutdown mode Bit 7 6 5 4 3 2 Critical lock bit Alarm lock bit Clear event Event output status Event output control 1 Critical event Event polarity only 0 Event mode Table 21: Configuration Register Bit Descriptions Bit Description Notes 0 Event mode 0: Comparator mode 1: Interrupt mode Event mode cannot be changed if either of the lock bits is set. 1 EVENT# polarity 0: Active LOW 1: Active HIGH EVENT# polarity cannot be changed if either of the lock bits is set. 2 Critical event only 0: EVENT# trips on alarm or critical temperature event 1: EVENT# trips only if critical temperature is reached 3 Event output control 0: Event output disabled 1: Event output enabled 4 Event status This is a read-only field in the register. The event caus0: EVENT# has not been asserted by this device ing the event can be determined from the read tem1: EVENT# is being asserted due to an alarm window perature register. or critical temperature condition PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor with Serial Presence-Detect EEPROM Table 21: Configuration Register Bit Descriptions (Continued) Bit Description Notes 5 Clear event This is a write-only field in the register and is self clear0: No effect ing 1: Clears the event when the temperature sensor is in the interrupt mode 6 Alarm window lock bit 0: Alarm trips are not locked and can be changed 1: Alarm trips are locked and cannot be changed 7 Critical trip lock bit 0: Critical trip is not locked and can be changed 1: Critical trip is locked and cannot be changed 8 Shutdown mode 0: Enabled 1: Shutdown The shutdown mode is a power-saving mode that disables the temperature sensor. Hysteresis enable 00: Disable 01: Enable at 1.5C 10: Enable at 3C 11: Enable at 6C When enabled, a hysteresis is applied to temperature movement around the trip points. As an example, if the hysteresis register is enabled to a delta of 6C, the preset trip points will toggle when the temperature reaches the programmed value. These values will reset when the temperature drops below the trip points minus the set hysteresis level. In this case, this would be critical temperature minus 6C. 10:9 The hysteresis is applied to both the above alarm window and the below alarm window bits found in the read-only temperature register. EVENT# is also affected by this register. PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor with Serial Presence-Detect EEPROM Figure 4: Hysteresis Applied to Temperature Around Trip Points TH1 TH - Hyst3 TL2 TL - Hyst Below window bit Above window bit 1. TH is the value set in the alarm temperature upper boundary trip register. 2. TL is the value set in the alarm temperature lower boundary trip register. 3. Hyst is the value set in the hysteresis bits of the configuration register. Notes: Table 22: Hysteresis Applied to Alarm Window Bits in the Temperature Register Below Alarm Window Bit Condition Temperature Gradient Sets Clears Above Alarm Window Bit Critical Temperature Temperature Gradient Critical Temperature Falling TL - Hyst Rising TH Rising TL Falling TH - Hyst Temperature Format The temperature trip point registers and temperature readout register use a 2's complement format to enable negative numbers. The least significant bit (LSB) is equal to 0.0625C or 0.25C, depending on which register is referenced. For example, assuming an LSB of 0.0625C: * A value of 0x018C would equal 24.75C * A value of 0x06C0 would equal 108C * A value of 0x1E74 would equal -24.75C PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor with Serial Presence-Detect EEPROM Temperature Trip Point Registers The upper and lower temperature boundary registers are used to set the maximum and minimum values of the alarm window. LSB for these registers is 0.25C. All RFU bits in the register will always report zero. Table 23: Alarm Temperature Upper Boundary Register Bits Bit 15 14 13 12 11 0 0 0 MSB 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU 2 1 0 LSB RFU RFU Alarm window upper boundary temperature Table 24: Alarm Temperature Lower Boundary Register Bit 15 14 13 12 11 0 0 0 MSB 10 9 8 7 6 5 4 3 Alarm window lower boundary temperature Critical Temperature Register The critical temperature register is used to set the maximum temperature above the alarm window. The LSB for this register is 0.25C. All RFU bits in the register will always report zero. Table 25: Critical Temperature Register Bits Bit 15 14 13 12 11 0 0 0 MSB 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Critical temperature trip point Temperature Register The temperature register is a read-only register that provides the current temperature detected by the temperature sensor. The LSB for this register is 0.0625C with a resolution of 0.0625C. The most significant bit (MSB) is 128C in the readout section of this register. The upper three bits of the register are used to monitor the trip points that are set in the previous three registers. PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Temperature Sensor with Serial Presence-Detect EEPROM Table 26: Temperature Register Bits Bit 15 14 13 12 Above critical trip Above alarm window Below alarm window MSB 11 10 9 8 7 6 5 4 3 2 1 0 LSB Temperature Table 27: Temperature Register Bit Descriptions Bit Description 13 Below alarm window 0: Temperature is equal to or above the lower boundary 1: Temperature is below alarm window 14 Above alarm window 0: Temperature is equal to or below the upper boundary 1: Temperature is above alarm window 15 Above critical trip point 0: Temperature is below critical trip point 1: Temperature is above critical trip point Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron's SPD page: www.micron.com/SPD. PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Serial Presence-Detect (SPD) Serial Presence-Detect (SPD) For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD. Table 28: SPD EEPROM Operating Conditions Parameter/Condition Symbol Min Max Units VDDSPD 3.0 3.6 V Input high voltage: logic 1; All inputs VIH 2.1 VDDSPD + 0.5 V Input low voltage: logic 0; All inputs VIL -0.6 0.8 V Output low voltage: IOUT = 3mA Supply voltage with temperature sensor option VOL - 0.4 V Input leakage current: VIN = GND to VDD ILI 0.1 3 A Output leakage current: VOUT = GND to VDD ILO 0.05 3 A Standby current ISB 1.6 4 A Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA Table 29: SPD EEPROM AC Operating Conditions Symbol Min Max Units Notes SCL LOW to SDA data-out valid Parameter/Condition tAA 0.2 0.9 s 1 Time bus must be free before a new transition can start tBUF 1.3 - s Data-out hold time tDH 200 - ns SDA and SCL fall time tF - 300 ns 2 SDA and SCL rise time tR - 300 ns 2 Data-in hold time tHD:DAT 0 - s Start condition hold time tHD:STA 0.6 - s tHIGH 0.6 - s tI - 50 s tLOW 1.3 - s tSCL - 400 kHz Data-in setup time tSU:DAT 100 - ns Start condition setup time tSU:STA 0.6 - s Stop condition setup time tSU:STO 0.6 - s tWRC - 10 ms Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SCL clock frequency WRITE cycle time Notes: PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pullup resistance, and the EEPROM does not respond to its slave address. 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM Module Dimensions Module Dimensions Figure 5: 200-Pin DDR2 SOCDIMM Front view 3.80 (0.150) MAX 67.75 (2.667) 67.75 (2.667) U3 2.0 (0.079) R (2X) U5 1.0 (0.039) R (2X) 1.80 (0.071) (2X) U1 U2 U7 U8 30.15 (1.187) 29.85 (1.175) 20.0 (0.787) TYP U6 6.0 (0.236) TYP 0.50 (0.0197) R 2.00 (0.079) TYP 0.45 (0.018) TYP Pin 1 0.60 (0.024) TYP 1.10 (0.043) 0.90 (0.035) Pin 199 63.60 (2.504) TYP Back view U9 U10 U11 U12 U13 10.00 (0.394) TYP 3.50 (0.138) TYP Pin 200 1.0 (0.039) TYP 47.4 (1.87) TYP 4.2 (0.165) TYP Pin 2 11.4 (0.45) TYP 16.26 (0.64) TYP Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef8253e3ea hts18c256_512x72ch.pdf - Rev. D 3/10 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved.