PRELIMINARY
128K x 36 Synchronous Flow-Through 3.3V Cache RAM
CY7C1345B
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
April 5, 2000
Features
• Supports 117-MHz microprocessor cache systems with
zero wait states
• 128K by 36 com m on I/ O
• Fast clock-to-output times
—7.5 ns (117-MHz version)
• Two- bit wrap-aroun d counter supporting ei ther
interleaved or linear burst seque nce
• Separate processor and controller address strobes pro-
vide direct interf ace w it h the processor and external
cache controller
• Synchronous self-timed write
• Asy nchronous output enable
•3.3V I/Os
• JEDEC-standard pinout
• 100-pi n TQFP packaging
• ZZ “sleep” mode
Functional Descri pti on
The CY7C1345B is a 3.3V, 128K by 36 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MH z version). A 2-bit on- chip counter cap-
tures the fir st address in a burst and i ncrements the addr ess
automatic ally for the rest of the burst access.
The CY7C1345B allows ei ther interleaved or linear burst se-
quences, selected b y the MODE input pin. A HIGH selects an
interlea ved bu rst sequence , while a LO W sele cts a linear burst
sequence. Burst accesses can be initi ated with the Processor
Address Strobe (ADSP) or the cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the Address Advancement (ADV) input.
A synchr onous self -timed write mechanism is provi ded to si m-
plify the wri te inter face. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three- state contr ol.
Selec tion Guide
7C1345B-117 7C1345B-100 7C1345B-90 7C1345B-50
Maximum Access Time (ns) 7.5 8.0 8.5 11.0
Maximum Operatin g Current (mA) 350 325 300 250
Maxim um Standby Current (mA) 2.0 2.0 2.0 2.0
Intel and Pentium are registered trademarks of Intel Corporation.
CLK
ADV
ADSC
A[16:0]
GW
BWE
BWS0
CE1
CE3
CE2
OE
ZZ
BURST
COUNTER
DQ[31:24],DP3
BYTEWRITE
REGISTERS
ADDRESS
REGISTER
DQ
INPUT
REGISTERS
128K X 36
MEMORY
ARRAY
CLK
Q0
Q1
Q
D
CE
CE
CLR
SLEEP
CONTROL
DQ[23:16],DP2
BYTEWRITE
REGISTERS
D Q
DQ
DQ[15:8],DP1
BYTEWRITE
REGISTERS
DQ[7:0],DP0
BYTEWRITE
REGISTERS
D Q
ENABLE
REGISTER
DQ
CE
CLK
36 36
17
15
15
17
(A0,A1)2
MODE
ADSP
Logic Block Diagram
DQ[31:0]
BWS1
BWS2
BWS3
DP[3:0]
CY7C1345B
PRELIMINARY
2
Pin Configurations
A5
A4
A3
A2
A1
A0
DNU
DNU
VSS
VDD
DNU
A10
A11
A12
A13
A14
A16
DP1
DQ14
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
DQ8
VSS
NC
VDD
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
DP0
DP2
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
VSSQ
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
DP3
A6
A7
CE1
CE2
BWS3
BWS2
BWS1
BWS0
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSP
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BYTE0
BYTE2
A15
ADV
ADSC
ZZ
MODE
DNU
BYTE1
DQ15
BYTE3
VSS
100-Pin TQFP
CY7C1345B
CY7C1345B
PRELIMINARY
3
Functional Description
Single Write Accesses Init iated by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
count er/con trol logic and deli ver ed t o the RAM cor e. The wri te
inputs (GW, BWE, and BW[3:0]) are ignored during this first
clock cycle. If the write inputs are asserted active ( see W rite
Cycle Descr iptions table for appropr iate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW0 controls DQ[7:0], BW1 controls
DQ[15:8], BW2 controls DQ[23:16], and BW3 control s DQ[31:24].
All I/Os are three-stated during a byte write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasser ted and the I/Os must be three-stated pri or to the
presentation of data to DQ[31:0]. As a safety precaution, the
data lines ar e three-stated once a write cycle i s detected, re-
gardless of the state of OE .
Single Wri te Accesses Initiated by ADSC
This writ e acc ess is i nitiat ed when the f oll owing c ondit ions ar e
satisfied at clock rise: (1) CE1, CE 2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BW E, and BW[3:0])
indi cate a write access. ADSC is ignored if ADS P is active LOW.
The addr ess es presen ted are loa ded int o th e address regist er
and the burst counter/cont rol logic and delivered to the RAM
core. The informatio n presented to DQ[31:0] will be written into
the speci fied address locat ion. Byte writ es are allowed. During
b y te wri tes, BW0 c ontrols DQ[7:0], BW1 c ontrols DQ[15:8], BW 2
controls DQ[23:16], and BWS3 controls DQ[31:24]. All I/Os are
three- stat ed when a wri te is detect ed, e v en a byt e write . Si nce
this is a c ommon I/O de vi ce, the asynchronous O E input si gnal
must be dea sserted an d the I/ Os must be three -stat ed prior to
the pr esentation of da ta to DQ[31:0]. As a safet y precauti on, the
data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Single Read Acces ses
A singl e read access is initiated when the following conditions
ar e satisfied at clock rise: (1) CE1, CE 2, and CE3 are all as-
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the wri te input s must be deassert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the address register and the burst
counter/control lo gic and presented to the m em ory core. If the
OE input is asserted LO W , the request ed data will be av ailabl e
at the data outputs a maximum to tCDV after clock rise. ADSP
is ignored if CE1 is HIGH.
Burst Se quences
The CY7C1338 provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LO W on MODE wi ll se lect a line ar bu rst se quenc e. A HI GH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence .
Pin Configurations (conti nued)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC DQPc
DQc
DQd
DQc
DQd
AA AAADSP VDDQ
CE2A
DQc
VDDQ
DQc
VDDQ
VDDQ
VDDQ
DQd
DQd
NC
NC VDDQ
VDD
CLK
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
VSS
NCNCNCNC NCNC NC
VDDQ
VDDQ
VDDQ
AAAA
CE3
AA
A
AA
AA0
A1
DQa
DQc
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQa
DQa
DQa
DQa
DQb
VDD
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
ADSC
NC
CE1
OE
ADV
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS DQPa
MODE
DQPd
DQPb
BWb
BWc
NC VDD NC
BWa
NC
BWE
BWd
ZZ
119-Ball BGA
A
CY7C1345B
PRELIMINARY
4
Sleep Mode
The ZZ input pin is an asynchronous i nput. Asserting ZZ HIGH
places t he SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac-
cesses pending when entering the “sleep” mode are not con-
sidered valid nor is the completion of the operation guaran-
teed. The device must be deselected prior to entering the
“sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LO W. Leaving ZZ unconnected defaults the device int o an ac-
tive st ate.
Table 1. Counter Implementation for the Intel®
Pentium®/80486 Processor’s Sequence
First
Address Second
Address Third
Address Fourth
Address
AX + 1 , AxAX + 1, AxAX + 1, AxAX + 1, Ax
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Table 2. Counter Implementati on for a Linear Sequence
First
Address Second
Address Third
Address Fourth
Address
AX + 1 , AxAX + 1, AxAX + 1, A xAX + 1, Ax
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
CY7C1345B
PRELIMINARY
5
Cycle Description Table[1, 2, 3]
Cycle Description ADD
Used CE1CE3CE2ZZ ADSP ADSP ADV WE OE CLK DQ
Deselected Cyc le, Power- down None H X X L X L X X X L-H High-Z
Deselected Cyc le, Power- down None L X L L L X X X X L-H High-Z
Deselected Cyc le, Power- down None L H X L L X X X X L-H High-Z
Deselected Cyc le, Power- down None L X L L H L X X X L-H High-Z
Deselected Cyc le, Power- down None X X X L H L X X X L-H High-Z
Snooze M ode, P ower-down None X X X H X X X X X X High-Z
Read Cycle, Begin Burst External L L H L L X X X L L -H Q
Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z
Write Cycl e, Begin Burst External L L H L H L X L X L-H D
Read Cycle, Begin Burst External L L H L H L X H L L -H Q
Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z
Write Cycl e, Continue Bur st Next X X X L H H L L X L-H D
Write Cycl e, Continue Bur st Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z
Write Cycl e, Suspend Burst Current X X X L H H H L X L-H D
Write Cycl e, Suspend Burst Current H X X L X H H L X L-H D
Notes:
1. X= “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a “Don't Care” for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.
CY7C1345B
PRELIMINARY
6
Maximum Ratings
(Above which the usefu l l ife ma y be impaired. For use r gui de-
li nes, not tested .)
Storage Temperature ... ..... .............. .. ........ .–65°C to +150°C
Ambient Temperat ure with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC Vol tage Applied t o Outputs
in High Z State[5]....................................–0.5V to VDD + 0.5V
DC Input Vo ltage[5]................................ –0. 5V to VDD + 0.5V
Cu r re n t in to Outp ut s (L OW ) ..... ..... ....... ..... ..... ..... ....... .. 20 mA
Static Discharge Voltage ...... ..... ...... ............. .. .. ..... ... >2001V
(per MIL- STD-883, Method 3015)
Latch-Up Current... ......... ..... ..... ..... ............ ..... .. ...... >200 mA
Notes:
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
6. TA is the ca se temper atu re.
Wr i te C ycl e D escri p t i o n s[1, 2, 3, 4]
Function GW BWE BW3BW2BW1BW0
Read 11XXXX
Read 101111
Write Byte 0, DP0101110
Write Byte 1, DP1101101
Write Byt es 1, 0, DP0, DP1101100
Write Byte 2, DP2101011
Write Byt es 2, 0, DP2, DP0101010
Write Byt es 2, 1, DP2, DP1101001
Write Byt es 2, 1, 0, DP2, DP 1, DP0101000
Write Byte 3, DP3100111
Write Byt es 3, 0, DP3, DP0100110
Write Byt es 3, 1, DP3, DP0100101
Write Byt es 3, 1, 0, DP3, DP 1, DP0100100
Write Byt es 3, 2, DP3, DP2100011
Write Byt es 3, 2, 0, DP3, DP 2, DP0100010
Write Byt es 3, 2, 1, DP3, DP 2, DP1100001
Write All Bytes 100000
Write All Bytes 0 XXXXX
ZZ Mode Elec trical Characteristics
Parameter Description Test Conditions Min Max Unit
ICCZZ Snooze mode
standby current ZZ > VDD − 0.2V 3 mA
tZZS Device operation to
ZZ ZZ > VDD − 0.2V 2tCYC ns
tZZREC ZZ re c ove ry time ZZ < 0.2 V 2t CYC ns
Operating Range
Range Ambient
Temperature[6] VDD VDDQ
Com’l 0°C to +70°C 3.135V to 3.6V 2.375V to VDD
CY7C1345B
PRELIMINARY
7
Electrical Characteristics Over the Operating Range
P arameter Des cri ption Test Conditi ons Min. Max. Unit
VOH Output HIGH Vol tage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V
VDDQ = 2.5V, VDD = M in., IOH = –2.0 mA 1.7 V
VOL Output LOW Vo ltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V
VDDQ = 2.5V, VDD = M in., IOL = 2.0 mA 0.7 V
VIH Input HIGH Voltage 1.7 VDD +
0.3V V
VIL Input LOW Voltage[5] –0.3 0.8 V
IXInput Load Current
(except ZZ and MODE) GND ≤ VI ≤ VDDQ −11µA
Input Current of MODE Input = VSS –30 µA
Input = VDDQ 5µA
Input Current of ZZ Input = VSS –5µA
Input = VDDQ 30 µA
IOZ Output Leakage Current GND ≤ VI ≤ V DD, Output Disabled –55µA
IOS Output Short Circuit Current[7] VDD = Max ., V OUT = GND –300 mA
IDD VDD Operating Supply Current VDD = Max ., IOU T = 0 mA,
f = fMAX = 1/ tCYC 8.5-ns cycle, 117 MHz 350 mA
10-ns cycl e, 100 MHz 32 5 mA
11-ns cycle, 90 MHz 300 mA
20-ns cycle, 50 MHz 250 mA
ISB1 Automatic CE Power-Down
Current—TTL In puts Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC, inputs switch-
ing
8.5-ns cycle, 117 MHz 35 mA
10-ns cycl e, 100 MHz 30 mA
11-ns cycle, 90 MHz 25 mA
20-ns cycle, 50 MHz 20 mA
ISB2 Automatic CE Power-Down
Current—CMOS Inputs Ma x. VDD, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0, in puts s ta t ic
All spee ds 10 mA
Max. VDD, Device Deselected,
VIN ≥ VDDQ– 0.3V or VIN ≤ 0.3V,
f = fMAX, inputs switchin g
ISB3 Automatic CE Power-Down
Current—CMOS Inputs 8.5-ns cycle, 117 MHz 10 mA
10-ns cycl e, 100 MHz 10 mA
11-ns cycle, 90 MHz 10 mA
20-ns cycle, 50 MHz 10 mA
ISB4 Automatic CE Power-Down
Current—TTL In puts Max. VDD, Device Deselected,
VIN ≥ VDD –0.3V or VIN ≤ 0.3V, f = 0,
inputs static
18 mA
Note:
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C1345B
PRELIMINARY
8
Capacitance[8]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 5.0V 4.0 pF
CI/O I/O Capacitance 4.0 pF
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range[9]
Parameter Description
-117 -100 -90 -50
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC Clo ck Cy cle Tim e 8. 5 10 1 1 2 0 ns
tCH Clock HIGH 3.0 4.0 4.5 4.5 ns
tCL Clock LOW 3.0 4.0 4.5 4.5 ns
tAS Address Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tAH Address Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tCDV Data Output Valid After CLK Rise 7.5 8.0 8.5 11.0 ns
tDOH Data Output Hold After CLK Rise 2.0 2.0 2.0 2 .0 ns
tADS ADSP, ADSC Set-Up Before CLK Rise 2.0 2.0 2.0 2 .0 ns
tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 n s
tWES BWS[1:0], GW,BWE Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tWEH BWS[1:0], GW,BWE Ho ld After CL K Rise 0.5 0.5 0.5 0 .5 n s
tADVS ADV Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tADVH ADV Hold Af ter CLK Rise 0 .5 0.5 0.5 0.5 ns
tDS Data Input Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tCES Chip Enable Set-Up 2.0 2.0 2.0 2.0 ns
tCEH Ch ip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tCHZ Clock to H i g h-Z [10, 11] 3.5 3.5 3.5 3.5 ns
tCLZ Clock to Low-Z[10, 11] 0000ns
tEOHZ OE HIGH to Output High- Z[10, 12] 3.5 3.5 3.5 3.5 ns
tEOLZ OE LOW to Outp ut Low-Z[10, 12] 0000ns
tEOV OE LOW to Outp ut Valid 3.5 3. 5 3.5 3.5 ns
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and loa d capaci tance. Show n in ( a) and ( b) of AC Test Load s.
10. tCHZ, tCLZ, tEOHZ, a nd tEOLZ are specified wi th a l oad capacit ance of 5 pF as in part (b) of A C Test Loads. Transiti on is meas ured ±200 mV from ste ady-state v olta ge.
11. At any given voltage and temperature, tCHZ (max.) is l ess tha n tCLZ (mi n.) .
12. This parameter is sampled and not 100% tested.
3.0V
GND
90%
10% 90%
10%
OUTPUT
R1=317Ω
R2=351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
ALL INPUT PULSES
OUTPUT
RL=50Ω
Z0=50Ω
VL=1.5V
3.3V
Ri se Tim e: 1 V/ns Fall Time: 1 V/ns
CY7C1345B
PRELIMINARY
9
Timing Diagrams
Write Cy cl e Tim ing [13, 14]
Notes:
13. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Descriptions table).
14. WDx stands for Write Data to Address X.
ADSP
CLK
ADSC
ADV
ADD
CE
1
OE
GW
WE
CE
2
CE
3
1a
Data-
In
tCYC
tCH
tCL
tADS
tADH
tADS tADH
tADVS tADVH
WD1 WD2 WD3
tAH
tAS
tWS tWH tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
2b 3a
1a
Single W rite Burst Write
Unselected
ADSP ignored with CE1 inactive
CE1 masks ADSP
= DON’T CARE
= UNDEFINED
Pipe li ned Write
2a 2c 2d
tDH
tDS
High-Z
High-Z
Unselected with CE2
ADV Must Be Inactive for ADSP Write
ADSC initiated write
CY7C1345B
PRELIMINARY
10
Read Cycle Timing[13, 15]
Note:
15. RDx stands for Read Data from Address X.
Timing Diagrams (c ontinued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
2a 2c
1a
Data Out
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 RD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tCDV
tEOV
2b 2c 2d 3a
1a
tOEHZ tDOH
tCLZ tCHZ
Singl e Read Burst Read Unselected
ADSP ignored with CE1 i nactive
Suspend Burst
CE1 masks ADSP
= DON’T CARE = UNDEFINED
Pipel ined Read
ADSC initiated read
Uns elected with CE2
CY7C1345B
PRELIMINARY
11
Timing Diagrams (c ontinued)
In/Out
A
tAH
tAS
= DON’T CARE = UNDEFINED
WE is th e combination of BWE, BW S [1:0], and GW to define a wri te cycle (see Write Cycle Descriptions tabl e).
tCLZ
tCHZ
CE is the co mb ination of CE2 and CE3. All chip selects need t o be active in order to select
the device. RAx stands for Read Address X, W Ax stands for Write Address X, Dx stands for Data-in X,
tDOH
CLK
ADD
WE
CE1
Data
BCD
ADSP
ADSC
ADV
CE
OE
Q(A) Q(B) Q
(B+1) Q
(B+2) Q
(B+3) Q(B) D(C) D
(C+1) D
(C+2) D
(C+3) Q(D)
tCYC
tCH tCL
tADS tADH
tADS tADH
tADVH
tADVS
tCEH
tCEH
tCES
tCES
tWEH
tWES
tCDV
Read/Writ e Timing
Device originally
deselected
ADSP ignored
with CE1 HIGH
tEOHZ
Qx stands for Data-out X.
CY7C1345B
PRELIMINARY
12
Timing Diagrams (c ontinued)
Pipeline Timing
tAS
= DON’T CARE = UNDEFINED
tCLZ
tCHZ
tDOH
CLK
ADD
WE
CE1
Data In /O u t
ADSC
ADSP
ADV
CE
OE
D(C)
tCYC
tCH tCL
tADS tADH
tCEH
tCES
tWEH
tWES
tCDV
ADSP ignored
with CE1 HIGH
RD1 RD2 RD3 RD4 WD1WD2WD3WD4
1a
Out 2a
Out 3a
Out 4a
Out 1a
In 2a
In 3a
In 4a
In
Back to Bac k Reads
ADSP ini tiate d Rea ds
ADSC initiated Reads
Back to Back Writes
CY7C1345B
PRELIMINARY
13
Timing Diagrams (c ontinued)
OE
three-state
I/Os
tEOHZ tEOV
tEOLZ
OE Switching Waveforms
CY7C1345B
PRELIMINARY
14
Notes:
16. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device.
17. I/Os are in three-state when exiting ZZ sleep mode.
Timing Diagrams (c ontinued)
ADSP
CLK
ADSC
CE1
CE3
LOW
HIGH
ZZ tZZS
tZZREC
ICC ICC(active)
Three-state
I/Os
ZZ Mode Timing [16, 17]
CE2
ICCZZ
HIGH
CY7C1345B
PRELIMINARY
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document #: 38-00953-*A
Orde ring Information
Speed
(MHz) Ordering Code Package
Name Package Typ e Operating
Range
117 CY7C1345B-117AC A1 01 100-Lead Thin Quad Fl at Pac k Commer cial
100 CY7C1345B-100AC A1 01 100-Lead Thin Quad Fl at Pac k
90 CY7C1345B-90AC A1 01 100-Lead Thin Quad Fl at Pac k
50 CY7C1345B-50AC A1 01 100-Lead Thin Quad Fl at Pac k
Package D i ag ra m
100-Pin Thin Plasti c Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
